JPH05347478A - Printed wiring board - Google Patents

Printed wiring board

Info

Publication number
JPH05347478A
JPH05347478A JP4179394A JP17939492A JPH05347478A JP H05347478 A JPH05347478 A JP H05347478A JP 4179394 A JP4179394 A JP 4179394A JP 17939492 A JP17939492 A JP 17939492A JP H05347478 A JPH05347478 A JP H05347478A
Authority
JP
Japan
Prior art keywords
wiring board
printed wiring
insulating layer
laminated
double
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4179394A
Other languages
Japanese (ja)
Inventor
Masayuki Yasuda
誠之 安田
Toshio Tamura
俊夫 田村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP4179394A priority Critical patent/JPH05347478A/en
Publication of JPH05347478A publication Critical patent/JPH05347478A/en
Pending legal-status Critical Current

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  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

PURPOSE:To prevent warp by making contraction coefficient of an intermediate insulation layer of a printed wiring board wherein three insulation layers are laminated larger than that of its outer insulation layer. CONSTITUTION:An insulation layer 34 of large contraction coefficient such as an aramid resin layer is used for an intermidiate in thickness direction of three insulation layers of a printed wiring board 30 and an insulation substrate 17 laminated in its outer side is formed of ordinary glass epoxy of small contraction coefficient, for example. Therefore, in a manufacturing process of the printed wiring board 30, a central insulation layer 34 among insulation layers 17, 34, 17 contracts most and a stress is generated as shown by an arrow 31. The stress becomes larger as shown by an arrow 31' when warp is going to be generated. As a result, if the printed wiring board 30 is about to generate warp, a stress 31' to resist it is generated, thereby making warp hard to be generated and flatness of the printed wiring substrate 30 can be kept good.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、プリント配線板に関す
るものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a printed wiring board.

【0002】[0002]

【従来の技術】従来、プリント配線板としての多層印刷
配線板は、表面側及び裏面側に導電回路を有する複数の
両面配線板をプリプレグ(ガラス繊維強化樹脂)によっ
て接着して積層した構成からなっている。
2. Description of the Related Art Conventionally, a multilayer printed wiring board as a printed wiring board has a structure in which a plurality of double-sided wiring boards having conductive circuits on the front surface side and the back surface side are adhered and laminated by a prepreg (glass fiber reinforced resin). ing.

【0003】図9には、従来の多層印刷配線板20の構成
例を示した。この配線板では、絶縁基板17の両面に銅箔
18、19を接着した両面配線板11にブラインドバイアホー
ル15が形成され、このブラインドバイアホール15を含め
て全面に施された銅メッキ22及び銅箔19が裏面側(即ち
内層側)において同一パターンにエッチングされ、導電
回路が形成されている。
FIG. 9 shows an example of the structure of a conventional multilayer printed wiring board 20. In this wiring board, the copper foil
A blind via hole 15 is formed in the double-sided wiring board 11 to which 18 and 19 are adhered, and the copper plating 22 and the copper foil 19 applied to the entire surface including the blind via hole 15 have the same pattern on the back surface side (that is, the inner layer side). The conductive circuit is formed by etching.

【0004】そして、両面配線板11は同様に加工された
他方の両面配線板12と回路パターンのある面同士でプリ
プレグ14(例えばガラスエポキシ:ガラス繊維強化エポ
キシ樹脂)によって熱圧着されて多層印刷配線板20に形
成される。
The double-sided wiring board 11 and the other double-sided wiring board 12 processed in the same manner are thermocompression-bonded to each other on a surface having a circuit pattern by a prepreg 14 (for example, glass epoxy: glass fiber reinforced epoxy resin) to form a multilayer printed wiring. Formed on the plate 20.

【0005】この多層印刷配線板20の所定箇所には、貫
通したスルーホール23が形成され、このスルーホール23
を含む全面に施された銅メッキ21及びその下層22、18が
同一パターンにエッチングされ、導電回路パターンに夫
々加工されている。
A through hole 23 is formed at a predetermined position of the multilayer printed wiring board 20, and the through hole 23 is formed.
The copper plating 21 and the lower layers 22 and 18 provided on the entire surface including are etched into the same pattern and processed into conductive circuit patterns, respectively.

【0006】このように、積層された両面配線板11及び
12の外層の回路同士がスルーホール23を通して接続さ
れ、かつ各両面配線板11及び12の各両面の回路同士がブ
ラインドバイアホール15を通して接続されている多層印
刷配線板20が構成されている。
In this way, the double-sided wiring boards 11 and
A multilayer printed wiring board (20) is formed in which twelve outer layer circuits are connected to each other through through holes (23) and circuits on both sides of each double-sided wiring board (11, 12) are connected to each other through blind via holes (15).

【0007】しかし、上記した従来の多層印刷配線板に
おいては、次の如き問題点が存在することが判明した。
これを図10について説明すると、この図では理解容易の
ために上記のプリプレグ14及び絶縁基板17を簡略に図示
したが、このような多層板はプリント配線板としての製
造工程中に様々な処理工程を経る際に、同図に示す如く
に反りを生じることがある。
However, it has been found that the above-mentioned conventional multilayer printed wiring board has the following problems.
Referring to FIG. 10, the prepreg 14 and the insulating substrate 17 are illustrated in a simplified manner for easy understanding in this figure.However, such a multilayer board has various processing steps during a manufacturing step as a printed wiring board. When passing through, a warp may occur as shown in the figure.

【0008】このように反りが生じる傾向は、多層板の
軽薄短小化の要求に伴う薄板化のために生じ易くなって
いる。即ち、一般に、銅箔18、19及び22のある絶縁基板
17の熱膨張係数は、プリプレグ14の熱膨張係数よりも小
さく、加熱工程においてはプリプレグ14の方が熱膨張し
易い。
Such a tendency for the warp to occur tends to occur due to the thinning of the multi-layered plate due to the demand for lighter, thinner, shorter and smaller plates. That is, generally an insulating substrate with copper foils 18, 19 and 22.
The coefficient of thermal expansion of 17 is smaller than the coefficient of thermal expansion of the prepreg 14, and the prepreg 14 is more susceptible to thermal expansion in the heating process.

【0009】このため、図10に示した如くに、多層板20
が変形して反りを生じることとなる。しかもこの場合、
各層での銅箔等の導電パターン(導体層のパターン)が
層毎に異なるために、多層板の厚み方向でパターンの対
称性が失われ易いことも、上記の反りを助長する一因と
なっている。
For this reason, as shown in FIG.
Will be deformed and warped. And in this case,
Since the conductive pattern (pattern of the conductor layer) such as copper foil in each layer is different for each layer, it is easy to lose the symmetry of the pattern in the thickness direction of the multilayer board, which is also a factor contributing to the above warpage. ing.

【0010】多層板20が上記のように反りを生じると、
その実装工程上、及び実装部品の接続信頼性において、
はんだ等による接続を良好に行えなくなるから、重大な
問題となる。例えば、反りによって、はんだ接続部分に
ストレスが生じ、剥離等を生じることがある。
When the multilayer board 20 warps as described above,
In terms of the mounting process and connection reliability of mounted parts,
This is a serious problem because the connection using solder or the like cannot be performed well. For example, the warp may cause stress in the solder connection portion, resulting in peeling or the like.

【0011】[0011]

【発明が解決しようとする課題】本発明の目的は、上記
した多層板のごとく少なくとも3つの絶縁層が積層され
ているプリント配線板について、その反りを低減若しく
はなくし、これによって実装工程でのトラブルを回避し
て生産性を向上させ、実装後の接続信頼性を向上させる
ことにある。
SUMMARY OF THE INVENTION An object of the present invention is to reduce or eliminate the warp in a printed wiring board in which at least three insulating layers are laminated like the above-mentioned multi-layer board, which causes troubles in the mounting process. It is to avoid the above, improve productivity, and improve connection reliability after mounting.

【0012】[0012]

【課題を解決するための手段】本出願の第1の発明は、
少なくとも3つの絶縁層が積層されているプリント配線
板において、中間の絶縁層の収縮率がその外側の絶縁層
の収縮率よりも大きいことを特徴とするプリント配線板
に係るものである。
The first invention of the present application is
In a printed wiring board in which at least three insulating layers are laminated, the shrinkage rate of the intermediate insulating layer is larger than the shrinkage rate of the outer insulating layer, which relates to the printed wiring board.

【0013】本出願の第2の発明は、少なくとも3つの
絶縁層が積層されているプリント配線板において、中間
の絶縁層の熱膨張係数がその外側の絶縁層の熱膨張係数
よりも小さいことを特徴とするプリント配線板に係るも
のである。
The second invention of the present application is that in a printed wiring board in which at least three insulating layers are laminated, the coefficient of thermal expansion of the intermediate insulating layer is smaller than the coefficient of thermal expansion of the outer insulating layer. The present invention relates to a characteristic printed wiring board.

【0014】上記において、少なくとも3つの絶縁層が
積層され、これらの各絶縁層の両面側に導体層が設けら
れていて、中間の絶縁層がプリント配線板の厚み方向に
おける中心位置に存在していることが望ましい。
In the above, at least three insulating layers are laminated, conductor layers are provided on both sides of each of these insulating layers, and an intermediate insulating layer exists at the center position in the thickness direction of the printed wiring board. Is desirable.

【0015】また、本発明は、表面側及び裏面側に導電
回路を有する第1及び第2の両面配線板が絶縁層を介し
て互いに積層され、前記両面配線板に形成されたブライ
ンドバイアホールを通して両面の導電回路間が接続さ
れ、かつ、前記第1及び第2の両面配線板及び前記絶縁
層を貫通してスルーホールが形成され、このスルーホー
ルを通して少なくとも前記第1及び第2の両面配線板の
外面側の導電回路同士が接続されているプリント配線板
に適用することができる。
Further, according to the present invention, the first and second double-sided wiring boards having conductive circuits on the front surface side and the back surface side are laminated on each other with an insulating layer interposed therebetween, and the blind via holes formed in the double-sided wiring board are passed through. Conductive circuits on both sides are connected to each other, a through hole is formed through the first and second double-sided wiring boards and the insulating layer, and at least the first and second double-sided wiring boards are formed through the through holes. It can be applied to a printed wiring board in which conductive circuits on the outer surface side are connected.

【0016】[0016]

【実施例】以下、本発明の実施例を説明する。EXAMPLES Examples of the present invention will be described below.

【0017】まず、本発明に基づくプリント配線板の一
例(多層印刷配線板)を図1について説明する。この例
によれば、図9に示したと同様に両面配線板11、12を一
対使用し、これらを収縮率の大きい絶縁層34を介して積
層していることが特徴的である。但し、銅箔又は銅層1
8、19、22は単純化のためにそれぞれ単層として示して
いる。
First, an example of a printed wiring board (multilayer printed wiring board) according to the present invention will be described with reference to FIG. This example is characterized in that a pair of double-sided wiring boards 11 and 12 are used as in the case shown in FIG. 9, and these are laminated via an insulating layer 34 having a large shrinkage ratio. However, copper foil or copper layer 1
8, 19, and 22 are shown as single layers for simplicity.

【0018】即ち、このプリント配線板30は、3つの絶
縁層のうち、厚み方向での中心位置(中間)には収縮率
の大きい絶縁層34、例えばアラミド樹脂層を使用し、そ
の外側に積層される絶縁基板17を例えば通常のガラスエ
ポキシによって形成しているので、図2に示す如くに、
プリント配線板の製造工程において各絶縁層間では中心
の絶縁層34が最も大きく収縮し、応力が矢印31で示すよ
うに生じる。この応力は、反りを生じようとする場合に
は更に31' のように大きくなる。
That is, in this printed wiring board 30, an insulating layer 34 having a large shrinkage ratio, for example, an aramid resin layer, is used at the central position (middle) in the thickness direction among the three insulating layers and is laminated on the outer side thereof. Since the insulating substrate 17 to be formed is formed of, for example, ordinary glass epoxy, as shown in FIG.
In the manufacturing process of the printed wiring board, the central insulating layer 34 contracts most among the insulating layers, and stress is generated as shown by an arrow 31. This stress becomes larger like 31 'when warping is attempted.

【0019】この結果、プリント配線板(多層板)が反
りを生じようとすると、これに抵抗する如くに応力31’
が生じるため、反りが生じ難くなっているのである。従
って、プリント配線板の平坦性を良好に保持でき、実装
工程でのトラブルや、実装部品の接続部分の剥離等をな
くし、生産性及び接続信頼性を大きく向上させることが
できる。
As a result, when the printed wiring board (multilayer board) is going to warp, stress 31 'is applied so as to resist it.
As a result, warpage is less likely to occur. Therefore, the flatness of the printed wiring board can be maintained satisfactorily, troubles in the mounting process, peeling of the connection parts of the mounted components, etc. can be eliminated, and productivity and connection reliability can be greatly improved.

【0020】上記の場合は、プリント配線板30として、
絶縁層が3つ(17−34−17)又は導体層を4層若しくは
それ以上(18−19−19−18、更には22も)としたが、図
3のように、絶縁層を5つ又は導体層を6層若しくはそ
れ以上としてもよい。
In the above case, as the printed wiring board 30,
Three insulating layers (17-34-17) or four or more conductor layers (18-19-19-18, and even 22) were used, but as shown in Fig. 3, five insulating layers were used. Alternatively, the number of conductor layers may be six or more.

【0021】即ち、図3の例によれば、図1の構造に加
えて、その上、下にプリプレグ又はガラスエポキシ板37
をそれぞれ重ね、更に最上面、最下面に導体層(銅箔又
は銅メッキ層)28を設けている。
That is, according to the example of FIG. 3, in addition to the structure of FIG.
And a conductor layer (copper foil or copper plating layer) 28 on the uppermost and lowermost surfaces.

【0022】この場合、プリント配線板30の厚み方向の
中心層、即ち絶縁層34として、その上、下の絶縁層17や
37よりも熱膨張率の小さい材料を使用することによっ
て、図2に示したように高温時に反りが生じようとして
も中心の絶縁層34が膨張しにくい(従って、伸びにく
い)ために、プリント配線板30の反りが生じ難くなる。
In this case, as the center layer in the thickness direction of the printed wiring board 30, that is, the insulating layer 34, the upper and lower insulating layers 17 and
By using a material having a smaller coefficient of thermal expansion than 37, the center insulating layer 34 is less likely to expand (and therefore less likely to expand) even when warping occurs at high temperatures as shown in FIG. The plate 30 is less likely to warp.

【0023】従って、図1の例と同様にプリント配線板
の平坦性を保持でき、同様の効果を得ることができる。
このためには、絶縁層34の材質として低熱膨張率のアラ
ミド樹脂や、ガラス繊維の多いガラスエポキシ等を使用
する。
Therefore, the flatness of the printed wiring board can be maintained as in the example of FIG. 1, and the same effect can be obtained.
For this purpose, an aramid resin having a low coefficient of thermal expansion, glass epoxy containing a large amount of glass fiber, or the like is used as the material of the insulating layer 34.

【0024】次に、図1の例を具体化した構造例を図4
〜図8について説明する。即ち、プリント配線板を製造
するに際し、図4のようにして絶縁基板17の両面に銅箔
18、19を接着した両面配線板材11Aにブラインドバイア
ホール15が形成され、このブラインドバイアホール15を
含めて全面に施された銅メッキ22及び銅箔19が裏面側
(即ち内層側)において同一パターンにエッチングさ
れ、導電回路が形成される。
Next, an example of a structure embodying the example of FIG. 1 is shown in FIG.
8 will be described. That is, when manufacturing a printed wiring board, copper foil is formed on both surfaces of the insulating substrate 17 as shown in FIG.
A blind via hole 15 is formed on the double-sided wiring board material 11A to which 18 and 19 are adhered, and the copper plating 22 and the copper foil 19 applied to the entire surface including the blind via hole 15 have the same pattern on the back surface side (that is, the inner layer side). To form a conductive circuit.

【0025】そして、図5のように、両面配線板材11A
は同様に加工された他方の両面配線板材12Aと回路パタ
ーンのある面同士でアラミド樹脂34によって熱圧着され
て多層印刷配線板材30Aに成形される。
Then, as shown in FIG. 5, double-sided wiring board material 11A
Is heat-pressed with the aramid resin 34 on the other side double-sided wiring board material 12A processed in the same manner and on the surface having the circuit pattern to form a multilayer printed wiring board material 30A.

【0026】この多層印刷配線板材30Aの所定箇所に
は、図6のように貫通したスルーホール23が形成され、
更に図7のようにこのスルーホール23を含む全面に施さ
れた銅メッキ21及びその下層22、18が図8のように同一
パターンにエッチングされ、導電回路パターンに夫々加
工される。
A through hole 23 is formed at a predetermined position of the multilayer printed wiring board material 30A as shown in FIG.
Further, as shown in FIG. 7, the copper plating 21 and the lower layers 22 and 18 provided on the entire surface including the through hole 23 are etched into the same pattern as shown in FIG. 8 and processed into conductive circuit patterns, respectively.

【0027】このように、積層された両面配線板11及び
12の外層の回路同士がスルーホール23を通して接続さ
れ、かつ各両面配線板11及び12の各両面の回路同士がブ
ラインドバイアホール15を通して接続されている多層印
刷配線板30が構成される。
The laminated double-sided wiring boards 11 and
A multilayer printed wiring board (30) is formed in which twelve outer layer circuits are connected to each other through through holes (23) and circuits on both sides of each double-sided wiring board (11, 12) are connected to each other through blind via holes (15).

【0028】以上、本発明の実施例を説明したが、上述
の実施例は本発明の技術的思想に基づいて更に変形が可
能である。
Although the embodiments of the present invention have been described above, the above embodiments can be further modified based on the technical idea of the present invention.

【0029】例えば、上述した中心層としての絶縁層34
や17、37の材質は様々にかつ相対的に選択することがで
き、上述した収縮率又は熱膨張係数を考慮して決めるこ
とができる。図1の例の絶縁層34として、熱膨張係数の
小さい材料を使用したり、或いは図3の例の絶縁層34と
して、収縮率の大きい材料を使用することもできる。
For example, the insulating layer 34 as the above-mentioned central layer
The materials of the materials 17, 17 and 37 can be variously and relatively selected, and can be determined in consideration of the above-mentioned shrinkage rate or thermal expansion coefficient. A material having a small thermal expansion coefficient may be used as the insulating layer 34 in the example of FIG. 1, or a material having a large shrinkage rate may be used as the insulating layer 34 in the example of FIG.

【0030】また、多層板の層構成として、絶縁層の数
を4或いは6つ等とすることができる。導体層も単層、
複数を問わないし、その材質も変更してよい。また、絶
縁層34の位置は厚み方向の中心であることが望ましい
が、必ずしもそのようにしなくても中間に存在していれ
ばよい。
Further, the number of insulating layers can be set to 4 or 6 as the layer structure of the multilayer board. The conductor layer is also a single layer,
A plurality of materials may be used, and the material thereof may be changed. Further, the position of the insulating layer 34 is preferably at the center in the thickness direction, but it does not necessarily have to be so and may be in the middle.

【0031】[0031]

【発明の作用効果】本発明は上述した如く、中間の絶縁
層の収縮率をその外側の絶縁層よりも大きくし、或いは
前者の熱膨張係数を後者よりも小さくしているので、反
りが生じ難くなり、従って、プリント配線板の平坦性を
良好に保持でき、実装工程でのトラブルや、実装部品の
接続部分の剥離等をなくし、生産性及び接続信頼性を大
きく向上させることができる。
As described above, according to the present invention, the shrinkage rate of the intermediate insulating layer is made larger than that of the outer insulating layer, or the coefficient of thermal expansion of the former is made smaller than that of the latter, so that warpage occurs. Therefore, the flatness of the printed wiring board can be maintained well, troubles in the mounting process, peeling of the connecting portion of the mounted components, etc. can be eliminated, and productivity and connection reliability can be greatly improved.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の実施例による多層印刷配線板の要部断
面図である。
FIG. 1 is a sectional view of an essential part of a multilayer printed wiring board according to an embodiment of the present invention.

【図2】同配線板の反りを防ぐ応力が生じる状況を説明
するための概略図である。
FIG. 2 is a schematic diagram for explaining a situation in which stress that prevents warpage of the wiring board occurs.

【図3】本発明の他の実施例による多層印刷配線板の要
部断面図である。
FIG. 3 is a cross-sectional view of an essential part of a multilayer printed wiring board according to another embodiment of the present invention.

【図4】図1の配線板の製造方法の一工程を示す断面図
である。
FIG. 4 is a cross-sectional view showing a step in the method of manufacturing the wiring board shown in FIG.

【図5】同配線板の製造方法の一工程を示す断面図であ
る。
FIG. 5 is a cross-sectional view showing one step in a method for manufacturing the same wiring board.

【図6】同配線板の製造方法の一工程を示す断面図であ
る。
FIG. 6 is a cross-sectional view showing one step in a method for manufacturing the same wiring board.

【図7】同配線板の製造方法の一工程を示す断面図であ
る。
FIG. 7 is a cross-sectional view showing one step in a method for manufacturing the same wiring board.

【図8】同配線板の製造方法の一工程を示す断面図であ
る。
FIG. 8 is a cross-sectional view showing one step in a method for manufacturing the same wiring board.

【図9】従来例による多層印刷配線板の断面図である。FIG. 9 is a cross-sectional view of a conventional multilayer printed wiring board.

【図10】同配線板に反りが生じる状況を説明するための
概略図である。
FIG. 10 is a schematic diagram for explaining a situation in which the wiring board is warped.

【符号の説明】[Explanation of symbols]

11、12・・・両面配線板 14・・・プリプレグ 15・・・ブラインドバイアホール 17、37・・・絶縁基板 18、19・・・銅箔 20、30・・・プリント配線板(多層印刷配線板) 21、22・・・銅メッキ層 23・・・貫通スルーホール 31、31' ・・・応力 34・・・高収縮率又は低熱膨張率の絶縁層 11, 12 ・ ・ ・ Double-sided wiring board 14 ・ ・ ・ Prepreg 15 ・ ・ ・ Blind via hole 17,37 ・ ・ ・ Insulating substrate 18, 19 ・ ・ ・ Copper foil 20, 30 ・ ・ ・ Printed wiring board (multilayer printed wiring) Plate) 21,22 ・ ・ ・ Copper plating layer 23 ・ ・ ・ Through through hole 31, 31 '・ ・ ・ Stress 34 ・ ・ ・ Insulation layer with high shrinkage or low thermal expansion

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】 少なくとも3つの絶縁層が積層されてい
るプリント配線板において、中間の絶縁層の収縮率がそ
の外側の絶縁層の収縮率よりも大きいことを特徴とする
プリント配線板。
1. A printed wiring board in which at least three insulating layers are laminated, wherein the shrinkage rate of the intermediate insulating layer is larger than that of the outer insulating layer.
【請求項2】 少なくとも3つの絶縁層が積層されてい
るプリント配線板において、中間の絶縁層の熱膨張係数
がその外側の絶縁層の熱膨張係数よりも小さいことを特
徴とするプリント配線板。
2. A printed wiring board in which at least three insulating layers are laminated, wherein a coefficient of thermal expansion of an intermediate insulating layer is smaller than a coefficient of thermal expansion of an insulating layer outside thereof.
【請求項3】 少なくとも3つの絶縁層が積層され、こ
れらの各絶縁層の両面側に導体層が設けられていて、中
間の絶縁層がプリント配線板の厚み方向における中心位
置に存在している、請求項1又は2に記載したプリント
配線板。
3. At least three insulating layers are laminated, conductor layers are provided on both sides of each of these insulating layers, and an intermediate insulating layer is present at a central position in the thickness direction of the printed wiring board. The printed wiring board according to claim 1 or 2.
【請求項4】 表面側及び裏面側に導電回路を有する第
1及び第2の両面配線板が絶縁層を介して互いに積層さ
れ、前記両面配線板に形成されたブラインドバイアホー
ルを通して両面の導電回路間が接続され、かつ、前記第
1及び第2の両面配線板及び前記絶縁層を貫通してスル
ーホールが形成され、このスルーホールを通して少なく
とも前記第1及び第2の両面配線板の外面側の導電回路
同士が接続されている、請求項1〜3のいずれかに記載
したプリント配線板。
4. The first and second double-sided wiring boards having conductive circuits on the front surface side and the back surface side are laminated on each other with an insulating layer interposed therebetween, and conductive circuits on both surfaces are passed through blind via holes formed in the double-sided wiring board. Between the first and second double-sided wiring boards and at least the outer surface side of the first and second double-sided wiring boards through which the through holes are formed. The printed wiring board according to claim 1, wherein the conductive circuits are connected to each other.
JP4179394A 1992-06-12 1992-06-12 Printed wiring board Pending JPH05347478A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4179394A JPH05347478A (en) 1992-06-12 1992-06-12 Printed wiring board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4179394A JPH05347478A (en) 1992-06-12 1992-06-12 Printed wiring board

Publications (1)

Publication Number Publication Date
JPH05347478A true JPH05347478A (en) 1993-12-27

Family

ID=16065103

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4179394A Pending JPH05347478A (en) 1992-06-12 1992-06-12 Printed wiring board

Country Status (1)

Country Link
JP (1) JPH05347478A (en)

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