JPH10135640A - Structure of printed wiring board and its manufacture - Google Patents

Structure of printed wiring board and its manufacture

Info

Publication number
JPH10135640A
JPH10135640A JP28859996A JP28859996A JPH10135640A JP H10135640 A JPH10135640 A JP H10135640A JP 28859996 A JP28859996 A JP 28859996A JP 28859996 A JP28859996 A JP 28859996A JP H10135640 A JPH10135640 A JP H10135640A
Authority
JP
Japan
Prior art keywords
hole
layer
printed wiring
wiring board
signal pattern
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP28859996A
Other languages
Japanese (ja)
Inventor
Shigeyuki Ogata
繁行 尾形
Kyoko Okura
共子 大倉
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Priority to JP28859996A priority Critical patent/JPH10135640A/en
Publication of JPH10135640A publication Critical patent/JPH10135640A/en
Withdrawn legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0213Electrical arrangements not otherwise provided for
    • H05K1/0216Reduction of cross-talk, noise or electromagnetic interference
    • H05K1/0218Reduction of cross-talk, noise or electromagnetic interference by printed shielding conductors, ground planes or power plane
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/11Printed elements for providing electric connections to or between printed circuits
    • H05K1/115Via connections; Lands around holes or via connections
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/11Printed elements for providing electric connections to or between printed circuits
    • H05K1/115Via connections; Lands around holes or via connections
    • H05K1/116Lands, clearance holes or other lay-out details concerning the surrounding of a via
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/40Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42Plated through-holes or plated via connections
    • H05K3/429Plated through-holes specially for multilayer circuits, e.g. having connections to inner circuit layers

Landscapes

  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)

Abstract

PROBLEM TO BE SOLVED: To increase the degree of freedom in designing and make the structure suitable for high density mounting of electronic components by concentrating at one place signal patterns for connecting one layer to the other layers. SOLUTION: A cutout 5a is formed in an outside through hole 5. In an upper layer, a signal pattern 3 is so located inside the outside through hole 5 that it may be connected to an inside through hole 4. Signal patterns for connecting one layer to the other layers can be collected at one place in an upper layer, and therefore, the degree of freedom in designing can be increased and the structure of a printed wiring board can be made suitable for high density mounting of electronic components.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、電子機器等に使用
するプリント配線板の構造及びその製造方法に関し、特
に、多層のプリント配線板の各層の信号パターン同士を
接続するのに有用なものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure of a printed wiring board used for electronic equipment and the like and a method of manufacturing the same, and more particularly, to a method useful for connecting signal patterns of each layer of a multilayer printed wiring board. is there.

【0002】[0002]

【従来の技術】一般に、多層のプリント配線板の各層の
信号パターンの接続は、スルーホールにめっきを施し、
このめっきにより各層間の信号パターンを接続するよう
にしている。従来のスルーホールは、各信号パターン同
士の接続に応じて複数設けていた。例えば、プリント配
線板に4層の信号パターンを設けた場合に、その4層を
上からa,b,c,d層と呼び、c層の信号パターンと
b層の信号パターンを接続し、かつ、d層の信号パター
ンとb層の信号パターンを接続し、c層の信号パターン
とd層の信号パターンを接続しないときには、各信号パ
ターン同士を接続するめっきしたスルーホールを別々に
設けていた。つまり、c層の信号パターンとb層の信号
パターンを接続するめっきしたスルーホールと、d層の
信号パターンとb層の信号パターンを接続するめっきし
たスルーホールとを別々に設けていた。
2. Description of the Related Art In general, connection of signal patterns of each layer of a multilayer printed wiring board is performed by plating through holes.
The plating connects the signal patterns between the layers. Conventionally, a plurality of through holes are provided in accordance with the connection between the signal patterns. For example, when a printed wiring board is provided with four signal patterns, the four layers are called a, b, c, and d layers from above, and the signal pattern of the c layer is connected to the signal pattern of the b layer, and When the signal pattern of the d-layer and the signal pattern of the b-layer were connected and the signal pattern of the c-layer and the signal pattern of the d-layer were not connected, plated through holes for connecting the respective signal patterns were separately provided. That is, a plated through hole that connects the signal pattern of the c layer and the signal pattern of the b layer and a plated through hole that connects the signal pattern of the d layer and the signal pattern of the b layer are separately provided.

【0003】[0003]

【発明が解決しようとする課題】しかしながら、上述し
た従来のプリント配線板の構造では、複数の層から別々
に信号パターンを同一層に接続する場合には、その接続
数分だけ別々にスルーホールを配設しなければならない
ため、それぞれのスルーホールに接続するための信号パ
ターンを長くしなければならず、プリント配線板のスル
ーホールに接続するために必要な面積が大きくなり、プ
リント配線板への電子部品の実装密度の向上には適さな
い問題があった。
However, in the above-described conventional printed wiring board structure, when signal patterns are separately connected to the same layer from a plurality of layers, through holes are separately formed by the number of connections. Therefore, the signal pattern for connecting to each through-hole must be lengthened, and the area required for connecting to the through-hole of the printed wiring board increases, and There is a problem that is not suitable for improving the mounting density of electronic components.

【0004】[0004]

【課題を解決するための手段】そこで本発明は、配線パ
ターンを形成した導体層と絶縁層とが交互に積層され、
任意の導体層の任意の信号パターンをスルーホールめっ
きにより接続するようにしたプリント配線板の構造にお
いて、一の層から二の層に接続するためのめっきを施し
た外側スルーホールの中に、三の層から二の層に接続す
るためのめっきを施した内側スルーホールを配置し、前
記外側スルーホールの二の層の一部に切り欠きを設け、
この切り欠きから内側スルーホールの二の層へ配線を接
続するようにした。なお、二の層はプリント配線板の表
層してもよい。また、二の層はプリント配線板の中層と
なるように、二の層に絶縁層を重ねるようにしてもよ
い。
SUMMARY OF THE INVENTION Accordingly, the present invention provides a method of manufacturing a semiconductor device comprising the steps of: alternately laminating conductor layers having a wiring pattern and insulating layers;
In the structure of a printed wiring board in which an arbitrary signal pattern of an arbitrary conductor layer is connected by through-hole plating, three through-holes are formed in plated outer through-holes for connecting from one layer to two layers. Placing an inner through-hole plated for connecting to the two layers from the layer of the, the notch is provided in a part of the two layers of the outer through-hole,
A wire was connected from the notch to the two layers of the inner through hole. The second layer may be a surface layer of a printed wiring board. Further, an insulating layer may be superimposed on the two layers so that the two layers are intermediate layers of the printed wiring board.

【0005】一方、上述のプリント配線板において、絶
縁体の両側に導体を積層した両側導体基材に対して一の
スルーホールを形成してめっきを施し、前記両側導体基
材の各面にスルーホールめっきに接続する信号パターン
を形成し、前記一のスルーホールに絶縁体を充填し、絶
縁体の両側又は片側に導体を積層した導体基材を前記両
側導体基材の両側に順次積層して多層板を形成し、この
多層板に対して前記一のスルーホールめっきが露出する
ように穴をあけ、その穴の一部をマスクしてその穴にめ
っきを施した後にマスクを取り除いて、めっきの一部を
切り欠いた外側スルーホールを形成し、この外側スルー
ホールに絶縁体を充填した後に、この外側スルーホール
を貫通する穴をあけて、その穴にめっきを施して内側ス
ルーホールとし、前記外側スルーホールの切り欠きから
前記内側スルーホールに信号パターンを接続するように
信号パターンを形成するようにした。なお、前記外側ス
ルーホールの切り欠きから前記内側スルーホールに信号
パターンを接続するように信号パターンを形成した後
に、更に絶縁層と導体層とを積層し、多層のプリント配
線板となるようにしてもよい。
On the other hand, in the above-mentioned printed wiring board, one through hole is formed in a conductor substrate on both sides in which conductors are laminated on both sides of an insulator, and plating is performed. Forming a signal pattern to be connected to the hole plating, filling the one through-hole with an insulator, sequentially laminating a conductor substrate having a conductor laminated on both sides or one side of the insulator on both sides of the both-side conductor substrate. A multilayer board is formed, a hole is formed in the multilayer board so that the one through-hole plating is exposed, a part of the hole is masked, the mask is plated, and then the mask is removed. After forming a part of the outside through hole cut out, filling the outside through hole with an insulator, making a hole penetrating this outside through hole, plating the hole and making it an inside through hole, And to form a signal pattern to connect the signal pattern to the inner through-hole from the notches in the Kisotogawa through hole. After forming a signal pattern so as to connect a signal pattern from the cutout of the outer through hole to the inner through hole, an insulating layer and a conductor layer are further laminated to form a multilayer printed wiring board. Is also good.

【0006】[0006]

【発明の実施の形態】以下に、図面を参照して、本発明
の実施の形態を説明する。図1は要部断面図、図2は要
部斜視図、図3は要部平面図である。このプリント配線
板1は、絶縁樹脂2の間及び表裏面に信号パターン3を
形成して層M1〜M4の4層のものとしてある。なお、
4層以外の場合でも適宜積層することができる。また、
ここでは、ここでは、層M1と層M4とを接続するよう
に、めっきを施した内側スルーホールと、層M2及び層
M3と層M1を接続するめっきを施した外側スルーホー
ルとを形成する場合を想定している。
Embodiments of the present invention will be described below with reference to the drawings. 1 is a sectional view of a main part, FIG. 2 is a perspective view of a main part, and FIG. 3 is a plan view of a main part. The printed wiring board 1 has four layers M1 to M4 with signal patterns 3 formed between the insulating resins 2 and on the front and back surfaces. In addition,
Even in the case of other than four layers, the layers can be appropriately laminated. Also,
Here, a case where a plated inner through-hole and a plated outer through-hole connecting the layers M2 and M3 and the layer M1 are formed so as to connect the layer M1 and the layer M4 is formed. Is assumed.

【0007】また、前記内側スルーホール4及び前記外
側スルーホール5の配置関係は、次のようである。すな
わち、図2及び図3に示すように、前記外側スルーホー
ル5には切り欠き5aを設けてあり、層M1では切り欠
き5aから信号パターン3を外側スルーホール5の内側
に配線して内側スルーホール4に接続するように配置し
てある。層M1では、他層への接続配線のための信号パ
ターンを1箇所に集中することができるため、設計の自
由度が増し、電子部品の実装の高密度化に適した構造と
することができる。
The positional relationship between the inner through hole 4 and the outer through hole 5 is as follows. That is, as shown in FIGS. 2 and 3, the outer through hole 5 is provided with a notch 5a, and in the layer M1, the signal pattern 3 is routed from the notch 5a to the inside of the outer through hole 5 to form an inner through hole. It is arranged so as to be connected to the hole 4. In the layer M1, a signal pattern for connection wiring to another layer can be concentrated at one place, so that the degree of design freedom is increased and a structure suitable for high-density mounting of electronic components can be achieved. .

【0008】次に、本実施の形態のプリント配線板の製
造方法を説明する。図4は製造工程のフローチャート、
図5及び図6は製造工程の説明図である。 S1:図5の(1)に示すように、樹脂層6の両側に導
体層7を積層した基材を製造する。 S2:図5の(2)に示すように、前記基材に対し、穴
8を空ける。 S3:以下、S6までは図5の(3)に示すように、前
記穴8にめっき9を施す。 S4:前記導体層7に信号パターンを形成するためにレ
ジストを塗布する。 S5:前記導体層7をエッチングし、図示しない信号パ
ターンを形成する。 S6:レジストを除去し、図5の(3)に示すように、
図示しない信号パターン及びめっき9を形成した構造と
する。 S7:図5の(4)に示すように、前記めっき9を施し
た穴8に樹脂10を充填する。 S8:図5の(5)に示すように、前記導体層7に樹脂
等の絶縁層11,12及び導体層13,14を積層す
る。この際には、例えば、プリプレグを介して積層す
る。このプリプレグは、ガラス繊維等に絶縁層の材質と
同種又は異種の樹脂をしみ込ませたものである。 S9:図5の(6)に示すように、前記めっき9の内壁
が表れるように前記絶縁層6,11,12を貫通する穴
15を形成する。 S10:図5の(7)に示すように、前記絶縁層6の穴
15の一部と前記絶縁層12の穴15の内壁にマスク1
6をマスキングする。 S11:図6の(8)に示すように、穴15の内壁にめ
っき17を施す。 S12:図6の(9)に示すように、穴15の内壁のマ
スク16を除去し、めっき17を残す。このときのめっ
き17が前記外側スルーホール5となる。 S13:図6の(10)に示すように、穴15に樹脂1
8を充填する。 S14:図6の(11)に示すように、樹脂18の部分
に絶縁層6,11,12を貫通し、前記17よりが表れ
ないように穴19を形成する。 S15:図6の(12)に示すように、穴19にめっき
を施して、前記内側スルーホール4とし、前記導体層1
3,14にレジスト、エッチングを施して信号パターン
を形成し、本実施の形態のプリント配線板1を製造す
る。なお、この後に、さらに絶縁層及び導体層を積層し
ていき多層のプリント配線板とすることもできる。
Next, a method for manufacturing a printed wiring board according to the present embodiment will be described. FIG. 4 is a flowchart of a manufacturing process,
5 and 6 are explanatory diagrams of the manufacturing process. S1: As shown in (1) of FIG. 5, a base material having a conductor layer 7 laminated on both sides of a resin layer 6 is manufactured. S2: As shown in (2) of FIG. 5, holes 8 are formed in the base material. S3: Hereinafter, as shown in (3) of FIG. 5, plating 9 is applied to the hole 8 up to S6. S4: A resist is applied to the conductor layer 7 to form a signal pattern. S5: The conductor layer 7 is etched to form a signal pattern (not shown). S6: The resist is removed, and as shown in FIG.
It has a structure in which a signal pattern (not shown) and plating 9 are formed. S7: As shown in (4) of FIG. 5, a resin 10 is filled in the hole 8 provided with the plating 9. S8: As shown in FIG. 5 (5), insulating layers 11 and 12 made of resin or the like and conductive layers 13 and 14 are laminated on the conductive layer 7. In this case, for example, lamination is performed via a prepreg. This prepreg is made by impregnating glass fiber or the like with a resin of the same type or a different type as the material of the insulating layer. S9: As shown in (6) of FIG. 5, a hole 15 penetrating the insulating layers 6, 11, 12 is formed so that the inner wall of the plating 9 is exposed. S10: As shown in (7) of FIG. 5, a mask 1 is formed on a part of the hole 15 of the insulating layer 6 and the inner wall of the hole 15 of the insulating layer 12.
Mask 6 S11: Plating 17 is applied to the inner wall of the hole 15 as shown in FIG. S12: As shown in FIG. 6 (9), the mask 16 on the inner wall of the hole 15 is removed, and the plating 17 is left. The plating 17 at this time becomes the outer through hole 5. S13: As shown in (10) of FIG.
Fill 8. S14: As shown in FIG. 6 (11), holes 19 are formed in the resin 18 so as to penetrate the insulating layers 6, 11, and 12 so that the resin 17 does not appear. S15: As shown in FIG. 6 (12), the holes 19 are plated to form the inner through holes 4 and the conductor layer 1
A signal pattern is formed by applying resist and etching to the substrates 3 and 14 to manufacture the printed wiring board 1 of the present embodiment. After that, an insulating layer and a conductor layer may be further laminated to form a multilayer printed wiring board.

【0009】上記実施の形態によると、他層から同一の
層に接続するための信号パターンを1箇所に集中するこ
とができるため、設計の自由度が増し、電子部品の実装
の高密度化に適した構造とすることができる効果が得ら
れる。
According to the above-described embodiment, since a signal pattern for connecting from the other layer to the same layer can be concentrated at one place, the degree of freedom in design is increased, and the mounting density of electronic components is increased. The effect that a suitable structure can be obtained is obtained.

【0010】[0010]

【発明の効果】以上説明したように本発明によると、他
層から同一の層に接続するための信号パターンを1箇所
に集中することができるため、設計の自由度が増し、電
子部品の実装の高密度化に適した構造とすることができ
る効果が得られる。
As described above, according to the present invention, the signal pattern for connecting from the other layer to the same layer can be concentrated at one place, so that the degree of freedom of design is increased and the mounting of electronic parts is achieved. The effect that can be set as the structure suitable for high density of this is obtained.

【図面の簡単な説明】[Brief description of the drawings]

【図1】実施の形態の要部断面図FIG. 1 is a sectional view of a main part of an embodiment.

【図2】実施の形態の要部斜視図FIG. 2 is a perspective view of a main part of the embodiment.

【図3】実施の形態の要部平面図FIG. 3 is a plan view of a main part of the embodiment.

【図4】実施の形態の製造工程のフローチャートFIG. 4 is a flowchart of a manufacturing process according to the embodiment;

【図5】実施の形態の製造工程の説明図FIG. 5 is an explanatory diagram of a manufacturing process according to the embodiment.

【図6】実施の形態の製造工程の説明図FIG. 6 is an explanatory diagram of a manufacturing process according to the embodiment.

【符号の説明】[Explanation of symbols]

1 プリント配線板 2 絶縁樹脂 3 信号パターン 4 内側スルーホール 5 外側スルーホール DESCRIPTION OF SYMBOLS 1 Printed wiring board 2 Insulating resin 3 Signal pattern 4 Inside through hole 5 Outside through hole

Claims (5)

【特許請求の範囲】[Claims] 【請求項1】 配線パターンを形成した導体層と絶縁
層とが交互に積層され、任意の導体層の任意の信号パタ
ーンをスルーホールめっきにより接続するようにしたプ
リント配線板の構造において、 一の層から二の層に接続するためのめっきを施した外側
スルーホールの中に、三の層から二の層に接続するため
のめっきを施した内側スルーホールを配置し、前記外側
スルーホールの二の層の一部に切り欠きを設け、この切
り欠きから内側スルーホールの二の層へ配線を接続した
ことを特徴とするプリント配線板の構造。
1. A printed wiring board structure in which conductive layers and insulating layers on which a wiring pattern is formed are alternately laminated, and an arbitrary signal pattern on an arbitrary conductive layer is connected by through-hole plating. A plated inner through hole for connecting the third layer to the second layer is disposed in the outer through hole plated for connecting the second layer to the second layer, and a second through hole for the outer through hole is provided. Wherein a notch is provided in a part of the layer and a wiring is connected to the second layer of the inner through hole from the notch.
【請求項2】 請求項1において、二の層はプリント配
線板の表層としたことを特徴とするプリント配線板の構
造。
2. The structure of a printed wiring board according to claim 1, wherein the second layer is a surface layer of the printed wiring board.
【請求項3】 請求項1において、二の層はプリント配
線板の中層となるように、二の層に絶縁層を重ねたこと
を特徴とするプリント配線板の構造。
3. The structure of a printed wiring board according to claim 1, wherein an insulating layer is superposed on the two layers so that the two layers are intermediate layers of the printed wiring board.
【請求項4】 請求項1に記載のプリント配線板におい
て、 絶縁体の両側に導体を積層した両側導体基材に対して一
のスルーホールを形成してめっきを施し、前記両側導体
基材の各面にスルーホールめっきに接続する信号パター
ンを形成し、 前記一のスルーホールに絶縁体を充填し、 絶縁体の両側又は片側に導体を積層した導体基材を前記
両側導体基材の両側に順次積層して多層板を形成し、 この多層板に対して前記一のスルーホールめっきが露出
するように穴をあけ、その穴の一部をマスクしてその穴
にめっきを施した後にマスクを取り除いて、めっきの一
部を切り欠いた外側スルーホールを形成し、この外側ス
ルーホールに絶縁体を充填した後に、この外側スルーホ
ールを貫通する穴をあけて、その穴にめっきを施して内
側スルーホールとし、 前記外側スルーホールの切り欠きから前記内側スルーホ
ールに信号パターンを接続するように信号パターンを形
成するようにしたことを特徴とするプリント配線板の製
造方法。
4. The printed wiring board according to claim 1, wherein one through-hole is formed and plated on both side conductor bases having conductors laminated on both sides of an insulator. Forming a signal pattern to be connected to through-hole plating on each surface, filling the one through-hole with an insulator, and laminating a conductor on both sides or one side of the insulator on both sides of the conductor base on both sides A multilayer board is formed by sequentially laminating, and a hole is formed in the multilayer board so that the one through-hole plating is exposed, a part of the hole is masked, and the hole is plated. Remove and form an outer through hole with a part of the plating cut out, fill this outer through hole with an insulator, make a hole through this outer through hole, apply plating to the hole, Through Ho And then, the manufacturing method of the printed wiring board, characterized in that so as to form a signal pattern to connect the signal pattern to the inner through-hole from the notches of the outer through-hole.
【請求項5】 請求項4に記載のプリント配線板の製造
方法において、前記外側スルーホールの切り欠きから前
記内側スルーホールに信号パターンを接続するように信
号パターンを形成した後に、更に絶縁層と導体層とを積
層し、多層のプリント配線板となるようにしたことを特
徴とするプリント配線板の製造方法。
5. The method of manufacturing a printed wiring board according to claim 4, further comprising: forming a signal pattern so as to connect the signal pattern from the cutout of the outer through hole to the inner through hole; A method for manufacturing a printed wiring board, comprising laminating a conductive layer to form a multilayer printed wiring board.
JP28859996A 1996-10-30 1996-10-30 Structure of printed wiring board and its manufacture Withdrawn JPH10135640A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP28859996A JPH10135640A (en) 1996-10-30 1996-10-30 Structure of printed wiring board and its manufacture

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP28859996A JPH10135640A (en) 1996-10-30 1996-10-30 Structure of printed wiring board and its manufacture

Publications (1)

Publication Number Publication Date
JPH10135640A true JPH10135640A (en) 1998-05-22

Family

ID=17732336

Family Applications (1)

Application Number Title Priority Date Filing Date
JP28859996A Withdrawn JPH10135640A (en) 1996-10-30 1996-10-30 Structure of printed wiring board and its manufacture

Country Status (1)

Country Link
JP (1) JPH10135640A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130189812A1 (en) * 2008-12-31 2013-07-25 Mihir Roy Coaxial plated through holes (pth) for robust electrical performance
US8502085B2 (en) 2007-01-11 2013-08-06 Samsung Electronics Co., Ltd. Multi-layer substrate with a via hole and electronic device having the same
JP2016066770A (en) * 2014-09-25 2016-04-28 京セラサーキットソリューションズ株式会社 Wiring board and method of manufacturing the same
CN110867431A (en) * 2019-11-27 2020-03-06 西安电子科技大学 TSV through hole supporting multi-path electric connection

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8502085B2 (en) 2007-01-11 2013-08-06 Samsung Electronics Co., Ltd. Multi-layer substrate with a via hole and electronic device having the same
KR101335987B1 (en) * 2007-01-11 2013-12-04 삼성전자주식회사 Multi-layer substrate
US20130189812A1 (en) * 2008-12-31 2013-07-25 Mihir Roy Coaxial plated through holes (pth) for robust electrical performance
JP2016066770A (en) * 2014-09-25 2016-04-28 京セラサーキットソリューションズ株式会社 Wiring board and method of manufacturing the same
CN110867431A (en) * 2019-11-27 2020-03-06 西安电子科技大学 TSV through hole supporting multi-path electric connection
CN110867431B (en) * 2019-11-27 2021-04-02 西安电子科技大学 TSV through hole supporting multi-path electric connection

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