JP2001024322A - Printed wiring board and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a highly reliable printed wiring board, in which delay or noise does not occur in a power supply or an electric signal, etc., which is to be transmitted through a pad for forming a solder bump and a solder bump and no crack or peeling off occurs in the solder bump. SOLUTION: This printed wiring board is made by forming on an insulative substrate a conductor circuit, composed of a plurality of layers pinching interlayer insulation layers 2a and 2b therein, providing a solder resist layer 14 on the uppermost conductor circuit, and forming a solder bump 17 in the solder resist layer 14. The solder bump 17 has Sn content of 1 to 70 wt.%, at least one kind of to a total of 0.001 to 0.1 wt.% to be selected from among a group including Al, As, Ag, Cu, and Zn, and a Pb as the remaining component.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention has a solder bump forming pad and a solder bump which has no delay in a power supply or an electric signal transmitted through the solder bump and which is unlikely to crack or peel off the solder bump. The present invention relates to a printed wiring board and a method for manufacturing the same.

[0002]

2. Description of the Related Art A multilayer printed wiring board called a so-called multilayer build-up wiring board is manufactured by a semi-additive method or the like.
m on a resin substrate reinforced with glass cloth, etc.
It is manufactured by alternately laminating a conductor circuit made of copper or the like and an interlayer resin insulating layer. The connection between the conductor circuits via the interlayer resin insulation layer of the multilayer printed wiring board is performed by via holes.

Conventionally, build-up multilayer printed wiring boards have been manufactured by a method disclosed in, for example, Japanese Patent Application Laid-Open No. 9-130050. That is, first, a through-hole is formed in the copper-clad laminate on which the copper foil is stuck, and then a through-hole is formed by performing an electroless copper plating process. Subsequently, the surface of the substrate is etched into a conductor pattern using a photolithography technique to form a conductor circuit. Next, on the surface of the formed conductor circuit,
A roughened surface is formed by electroless plating or etching, and an interlayer insulating resin is applied and formed on a conductor circuit having the roughened surface by a roll coater or printing, and then exposed and developed to perform a via hole opening. Is formed, and then an interlayer resin insulating layer is formed through UV curing and main curing.

Further, after a roughening treatment is performed on the interlayer resin insulating layer with an acid or an oxidizing agent, a catalyst such as palladium is adhered to the formed roughened surface to form a thin electroless plating film. After a plating resist is formed on the electroless plating film, a thickening is performed by electrolytic plating, and etching is performed after the plating resist is stripped to form a conductor circuit connected to the lower conductor circuit by a via hole.

After repeating this, a solder resist layer for protecting the conductor circuit is formed as the outermost layer,
After plating is applied to the portion where the opening is exposed for connection with electronic components such as chips and motherboard, etc., to form solder bump forming pads, solder paste is printed on the side where electronic components such as IC chips are mounted Then, a build-up multilayer printed wiring board is manufactured by forming solder bumps. Also, if necessary, solder bumps are formed on the side connected to the motherboard.

[0006]

At present, electronic components such as IC chips have been increased in density and integration, and have been increased in capacity and speed. Therefore, the solder bumps of these electronic components have a narrow pitch. , Are being refined.

As a result, printed wiring boards on which these electronic components are mounted have been increased in capacity and speed, and due to the increase in capacity and speed, impurities such as solder constituting solder bumps are contained. In this case, a delay is likely to occur in a power supply or an electric signal transmitted from an electronic component such as an IC chip to a conductor circuit via a solder bump and a corrosion-resistant metal layer. In recent years, since the speed of electric signals and the like has been increased (increased in frequency), even a small delay tends to cause malfunction of an IC chip or the like.

Further, although the cross-sectional area of the circuit has been reduced due to high integration and large capacity, the same current as in the prior art is applied to the circuit having the small cross-sectional area, and the density of the solder bumps and the conductor circuit is reduced. Therefore, these circuit portions easily generate heat. In particular, the temperature tends to be high at the interface between the solder bump and the corrosion-resistant metal layer.

As described above, when the temperature of the solder bumps becomes high, noise is apt to be generated in electric signals and the like, and therefore, IC chips and the like may malfunction and their original functions cannot be sufficiently exhibited. Further, peeling and cracking are likely to occur between the solder bump and the corrosion-resistant metal layer or between the corrosion-resistant metal layer and the conductor circuit due to the heat described above.

When a reliability test is performed in a state where a bias voltage is applied under high temperature and high humidity, migration of metal in a solder bump portion or the like proceeds at an accelerated rate. Are likely to occur, which is a factor that lowers reliability.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and does not cause delay or noise in a power supply or an electric signal transmitted through a solder bump forming pad and a solder bump, and a solder bump portion is provided. An object of the present invention is to provide a printed wiring board free from cracks, peeling, and the like, and a method for manufacturing the same.

[0012]

Means for Solving the Problems The inventors of the present invention have made intensive studies in view of the above-mentioned problems, and as a result, by controlling the content of metals other than Sn and Pb with respect to the components of the solder used in the solder paste, the solder bump components have To prevent power supply or electrical signal delay and noise caused by
The present invention has been achieved which has the following content as a gist configuration.

That is, in the printed wiring board of the present invention, a conductor circuit composed of a plurality of layers sandwiching an interlayer insulating layer is formed on an insulating substrate, and a solder resist layer is provided on the uppermost conductor circuit. In a printed wiring board in which solder bumps are formed on a resist layer, the solder bumps are S
n, 1 to 70% by weight and Al, As, A
At least one selected from the group consisting of g, Cu and Zn is contained in a total amount of 0.001 to 0.1% by weight, and the remaining component is Pb.

In the printed wiring board, the solder bumps may be made of Sn, Al, As, Ag, Cu, Zn, and P.
It is desirable that a metal other than b is contained at 0.0001% by weight or less.

In the method of manufacturing a printed wiring board according to the present invention, the step of forming an interlayer insulating layer on the formed conductive circuit is repeated to form a conductive circuit comprising a plurality of layers with an interlayer insulating layer interposed on an insulating substrate. Is formed, a solder resist layer is provided on the uppermost conductive circuit, a part of the solder resist layer is opened to form a plurality of solder bump forming pads, and a solder paste is applied to the solder bump forming pads. A method of manufacturing a printed wiring board, wherein a solder bump is formed by applying the solder paste, wherein the solder paste contains Sn in a range of 1 to 70% by weight and is made of a group consisting of Al, As, Ag, Cu, and Zn. The total content of at least one selected from 0.001 to 0.1% by weight, and the remaining component is Pb
Characterized by using solder consisting of

[0016]

BEST MODE FOR CARRYING OUT THE INVENTION In a printed wiring board of the present invention, a conductor circuit composed of a plurality of layers sandwiching an interlayer insulating layer is formed on an insulating substrate, and a solder resist layer is provided on the uppermost conductor circuit. In the printed wiring board having solder bumps formed on the solder resist layer, the solder bumps are
While containing 1 to 70% by weight of Sn, Al, As,
At least one selected from the group consisting of Ag, Cu and Zn is contained in a total amount of 0.001 to 0.1% by weight, and the remaining component is Pb.

According to the above printed wiring board, at least one metal selected from the group consisting of Al, As, Ag, Cu and Zn (hereinafter referred to as metal such as As, Cu) ) Is controlled to be 0.001 to 0.1% by weight, so that no delay occurs in the power supply or the electric signal transmitted through the solder bump. Further, when the IC chip or the like is operated for a long time, even if the solder bump and its surroundings are heated to a high temperature, no noise is generated in the solder bump portion.
Furthermore, even when a reliability test is performed in a state where a bias voltage is applied, the metal content of As, Cu, and the like is small.
The rate of progress of metal migration and corrosion is slow, and cracks and peeling do not occur in the solder bumps.

Al, As, Ag, C in the above solder bumps
It is practically difficult to make the total content of at least one selected from the group consisting of u and Zn less than 0.001, while the content of metals such as As and Cu is 0.1% by weight. When the value exceeds, the delay of the electric signal is apt to occur, and the frequency of occurrence of migration increases under severe conditions such as high temperature and high humidity.

Among these metals such as As and Cu, it is particularly desirable that the content of As, Cu and Zn is small. When these metal concentrations are high, power supply and electric signal delays are likely to occur, and the frequency of occurrence of migration increases. Further, the α dose in the solder also increases, which affects the electrical characteristics and the like.

In the printed wiring board of the present invention, the solder bump has a content of a metal other than Sn, Al, As, Ag, Cu, Zn and Pb (hereinafter also referred to as a metal other than Sn, Al, etc.) It is desirably 0.0001% by weight or less. As metals other than these Sn, Al, etc.,
Examples thereof include alkali metals such as Na and K, and the content of these metals is desirably 0.0001% by weight or less.

The above-mentioned determination of the metal can be performed by using the energy dispersion method (EDS). That is, first, an electron beam, which is an excitation source of a scanning electron microscope (SEM) or a transmission electron microscope (TEM), is irradiated on the surface of a sample, and the generated characteristic X-ray is detected by a Si (Li) semiconductor detector. . In this detector, a number of electron-hole pairs is generated in the semiconductor in proportion to the characteristic X-ray energy. Next, an electron signal due to these electron-hole pairs is generated, and then amplified. Performs analog and digital conversion,
An X-ray spectrum can be obtained by performing identification using a multi-channel analyzer. Then, the element is identified from the peak energy of the X-ray spectrum, and the amount of the element is calculated from the peak area, whereby the quantitative analysis of the trace element in the solder can be performed.

Next, a method of manufacturing a printed wiring board having solder bumps according to the present invention will be described. In the present invention, after various processes, a solder resist layer is formed on a conductor circuit, and a portion serving as a pad for forming a solder bump is opened. The opening of the pad for forming a solder bump is formed by a method using photolithography, a method using laser, a punching method, or the like. The shape of the opening in a plan view is not particularly limited, and includes, for example, a circle, an oval, a square, a rectangle, and the like.
A circular shape is desirable from the viewpoint of increasing the degree of freedom in designing when performing wiring and the like, the stability of the solder bump shape, and the like.

A roughened surface is formed on the conductor circuit, and the roughened surface ensures the close contact between the solder resist layer and the conductor circuit. The roughness of the roughened surface is preferably 0.5 to 10 μm in average roughness, and 1 to 5 μm.
m is more desirable. The roughened surface is desirably formed by electroless plating, etching, oxidation-reduction treatment, polishing treatment, or the like. Further, the thickness of the solder resist layer is desirably 5 to 70 μm. If the thickness is less than 5 μm, the solder resist layer will be peeled off or cracks will occur, and if it is more than 70 μm, it will be difficult to form openings.

The conductor circuit portion exposed by the opening is usually covered with a corrosion-resistant metal such as nickel, palladium, gold, silver, and platinum. Specifically, nickel-gold, nickel-
The coating layer is formed of a metal such as silver, nickel-palladium, and nickel-palladium-gold. The coating layer is formed by, for example, a plating method, a vapor deposition method, an electrodeposition method, and the like. Among these, the plating method is preferable from the viewpoint of film uniformity.

There are two types of pads for forming solder bumps having a corrosion-resistant metal layer formed on their surface. That is, one formed by opening the upper part of the flat conductor circuit, and one formed above the via hole and having a depression at the center. The diameter of this depression is generally 10 to 120 μm.

Next, in the present invention, Sn is contained in an amount of 1 to 70% by weight.
Containing, Al, As, Ag, Cu and Zn
At least one member selected from the group consisting of 0.
A solder paste containing 001 to 0.1% by weight and using a solder containing Pb as the remaining component is applied to a solder bump forming pad to form a solder bump. It is desirable that the solder in the solder paste contains 0.0001% by weight or less of metals other than Sn, Al, As, Ag, Cu, Zn and Pb.

As a method of applying the solder paste, for example, a printing method, a potting method, a solder plating method and the like can be cited, but a solder paste layer can be formed on all the solder bump forming pads at one time. The printing method is desirable because the filling amount of the solder paste can be easily controlled.

When the printing method is adopted, it is desirable to use a mask such as a metal mask and fill a solder bump forming pad with a solder paste through an opening of the mask.

The solder paste used for printing is not particularly limited, and any paste generally used in the manufacture of printed wiring boards can be used. In particular,
For example, a tin-lead alloy having a weight ratio of 63:37 can be used. The solder particle diameter is preferably 5 to 40 μm, and the viscosity of the solder paste is 50 μm at 23 ° C.
~ 400 Pa. s is desirable. The viscosity of the solder paste is 5
0 Pa. s, the shape of the solder bump cannot be maintained, and 400 Pa.s. If the length exceeds s, the solder paste layer cannot be satisfactorily formed on the solder bump forming pad portion.

When printing the solder paste, a printing squeegee is usually used. The material of the squeegee for forming a print is not particularly limited, for example, rubber such as polyethylene;
Metals such as iron and stainless steel; and materials generally used for printing on printed wiring boards such as ceramics can be used. The reflow is performed under an inert atmosphere such as nitrogen under 150 atmospheres.
It is desirable to carry out in a temperature range of -300 ° C. The reflow temperature is set according to the solder composition.

The shape of the solder bump formed by the method of forming a solder bump of the present invention is a semi-spherical shape, and its height is 5 to 50 μm.
m, and a solder bump having a uniform height and shape can be formed. Also, the formed solder bumps are A
The total content of at least one metal selected from the group consisting of l, As, Ag, Cu and Zn is 0.001 to
Since it is controlled to 0.1% by weight, no delay occurs in the power supply or the electric signal transmitted through the solder bump. Further, when the IC chip or the like is operated for a long time, even if the solder bump and its surroundings generate heat and become high temperature, no noise is generated in the solder bump portion. Furthermore, even when a reliability test is performed in a state where a bias voltage is applied, since the metal content of the above-mentioned As, Cu, etc. is small, the rate of progress of metal migration and corrosion becomes slow, and cracks and peeling occur on solder bumps. Nothing to do.

Next, the method for manufacturing a printed wiring board of the present invention will be briefly described. (1) In the method for manufacturing a printed wiring board of the present invention, first, a substrate having a conductive circuit formed on a surface of an insulating substrate is prepared.

As the insulating substrate, a resin substrate is desirable, and specific examples thereof include a glass epoxy substrate, a polyimide substrate, a bismaleimide-triazine resin substrate, a fluororesin substrate, a ceramic substrate, and a copper-clad laminate. . In the present invention, a through hole is formed in the insulating substrate by a drill or the like, and the wall surface of the through hole and the surface of the copper foil are subjected to electroless plating to form a surface conductive film and a through hole. Copper plating is preferred as the electroless plating.

After the electroless plating, a roughening treatment is usually performed on the inner wall of the through hole and the surface of the electrolytic plating film.
Examples of the roughening forming treatment method include blackening (oxidation) -reduction treatment, spray treatment with a mixed aqueous solution of an organic acid and a cupric complex, treatment with Cu-Ni-P needle-like alloy plating, and the like.

(2) Next, a conductive circuit-shaped etching resist is formed on the substrate on which the electroless plating has been performed, and the conductive circuit is formed by performing etching. Next, a resin filler is applied to the surface of the substrate on which the conductive circuit is formed, dried to a semi-cured state, then polished, the resin filler layer is ground, and the upper part of the conductive circuit is also ground. Then, both main surfaces of the substrate are flattened. Thereafter, the layer of the resin filler is completely cured.

(3) Next, a roughened layer is formed on the conductor circuit. Examples of the roughening treatment method include a blackening (oxidation) -reduction treatment, a spray treatment with a mixed aqueous solution of an organic acid and a cupric complex, and a treatment with Cu-Ni-P alloy plating.

(4) Next, a coating layer made of tin, zinc, copper, nickel, cobalt, thallium, lead or the like is formed on the surface of the formed roughened layer by electroless plating, vapor deposition, or the like. By depositing the coating layer in the range of 0.01 to 2 μm, the conductor circuit exposed from the interlayer insulating layer can be protected from a roughening solution or an etching solution, and discoloration and dissolution of the inner layer pattern can be reliably prevented. Because.

(5) Thereafter, an interlayer resin insulating layer is provided on the conductor circuit on which the roughened layer has been formed. As a material of the interlayer resin insulating layer, a thermosetting resin, a thermoplastic resin, a resin obtained by sensitizing a part of the thermosetting resin, or a composite resin thereof can be used. The interlayer insulating layer may be formed by applying an uncured resin, or may be formed by thermocompression bonding an uncured resin film. Further, a resin film in which a metal layer such as a copper foil is formed on one surface of an uncured resin film may be attached. When such a resin film is used, an opening is formed by irradiating a laser beam after etching a metal layer in a via hole forming portion. As the resin film having the metal layer formed thereon, a resin-coated copper foil or the like can be used.

In forming the interlayer insulating layer, an adhesive layer for electroless plating can be used. The most suitable adhesive for electroless plating is one in which heat-resistant resin particles soluble in a cured acid or oxidizing agent are dispersed in an uncured heat-resistant resin hardly soluble in an acid or oxidizing agent. is there. By treating with an acid or an oxidizing agent, the heat-resistant resin particles are dissolved and removed, and a roughened surface composed of an octopus pot-shaped anchor can be formed on the surface.

In the above-mentioned adhesive for electroless plating, particularly as the heat-resistant resin particles cured, (a) a heat-resistant resin powder having an average particle diameter of 10 μm or less, and (b) an average particle diameter of 2 μm or less. Aggregated particles obtained by aggregating heat-resistant resin powder,
(c) a mixture of a heat-resistant resin powder having an average particle diameter of 2 to 10 μm and a heat-resistant resin powder having an average particle diameter of 2 μm or less, (d)
Pseudo particles obtained by adhering at least one of a heat-resistant resin powder or an inorganic powder having an average particle diameter of 2 μm or less to the surface of a heat-resistant resin powder having an average particle diameter of 2 to 10 μm, A mixture of 0.1 to 0.8 μm heat-resistant powder resin powder and a heat-resistant resin powder having an average particle diameter of more than 0.8 μm and less than 2 μm, (f) an average particle diameter of 0.1 to 1.0 μm It is desirable to use heat-resistant resin powder. They are,
This is because a more complicated anchor can be formed.

Examples of the heat-resistant resin hardly soluble in an acid or an oxidizing agent include a “resin composite composed of a thermosetting resin and a thermoplastic resin” and a “resin composite composed of a photosensitive resin and a thermoplastic resin”. desirable. This is because the former has high heat resistance, and the latter can form an opening for a via hole by photolithography.

As the thermosetting resin, for example, epoxy resin, phenol resin, polyimide resin and the like can be used. Examples of the photosensitized resin include those obtained by subjecting a thermosetting group to methacrylic acid or acrylic acid to undergo an acrylation reaction. In particular, an acrylated epoxy resin is most suitable. As the epoxy resin, a novolak type epoxy resin such as a phenol novolak type and a cresol novolak type, and an alicyclic epoxy resin modified with dicyclopentadiene can be used.

As the thermoplastic resin, polyether sulfone (PES), polysulfone (PSF), polyphenylene sulfone (PPS), polyphenylene sulfide (PPES), polyphenyl ether (PP
E), polyetherimide (PI), fluororesin and the like can be used. The mixing ratio of the thermosetting resin (photosensitive resin) and the thermoplastic resin is preferably thermosetting resin (photosensitive resin) / thermoplastic resin = 95/5 to 50/50. This is because a high toughness value can be secured without impairing the heat resistance.

The mixing weight ratio of the heat-resistant resin particles is preferably 5 to 50% by weight, more preferably 10 to 40% by weight, based on the solid content of the heat-resistant resin matrix. As the heat-resistant resin particles, an amino resin (a melamine resin, a urea resin, a guanamine resin), an epoxy resin or the like is desirable.

(6) Next, while the interlayer insulating resin layer is cured, an opening for forming a via hole is provided in the interlayer resin layer. Opening of the interlayer insulating resin layer is performed using laser light or oxygen plasma when the resin matrix of the adhesive for electroless plating is a thermosetting resin, and exposed when the resin matrix is a photosensitive resin. Performed by development processing. In the exposure and development process, a photomask (preferably a glass substrate) on which a circular pattern for forming a via hole is drawn is brought into close contact with the photosensitive interlayer resin insulating layer on the circular pattern side. After mounting, the substrate is exposed and immersed in a developing solution or sprayed with the developing solution. By curing the interlayer resin insulating layer formed on the conductor circuit having a roughened surface with a sufficient unevenness, an interlayer resin insulating layer having excellent adhesion to the conductor circuit can be formed.

(7) Next, the surface of the interlayer resin insulating layer (the adhesive layer for electroless plating) having the via hole opening is roughened. Usually, the roughening is performed by dissolving and removing the heat-resistant resin particles present on the surface of the adhesive layer for electroless plating with an acid or an oxidizing agent. The height of the roughened surface formed by acid treatment or the like is desirably Rmax = 0.01 to 20 μm. This is for ensuring adhesion to the conductor circuit. In particular, in the semi-additive method, 0.1 to 5 μm is desirable. This is because the electroless plating film can be removed while ensuring adhesion.

When performing the above acid treatment, phosphoric acid, hydrochloric acid,
Sulfuric acid or an organic acid such as formic acid or acetic acid can be used, and it is particularly preferable to use an organic acid. This is because the metal conductor layer exposed from the via hole is hardly corroded when the roughening treatment is performed. The oxidation treatment is performed using chromic acid,
It is desirable to use permanganate (such as potassium permanganate).

(8) Next, a thin electroless plating film is formed on the entire surface of the roughened interlayer insulating resin. The electroless plating film is preferably formed by electroless copper plating, and has a thickness of 1 to 3.
5 μm is desirable, and 2-3 μm is more desirable.

(9) Further, a plating resist is provided thereon. As the plating resist, a commercially available photosensitive dry film or liquid resist can be used. Then, after applying a photosensitive dry film or applying a liquid resist, an ultraviolet exposure process is performed, and a developing process is performed with an alkaline aqueous solution.

(10) Next, after the substrate subjected to the above treatment is immersed in an electroplating solution, direct current electroplating is performed using the electroless plating layer as a cathode and the metal to be plated as an anode, and plating the openings for via holes. While filling
An upper conductor circuit is formed. As the electrolytic plating, electrolytic copper plating is preferable, and its thickness is preferably 10 to 20 μm.

(11) Next, the plating resist is peeled off with a strong aqueous alkali solution and then etched to remove the electroless plating layer, thereby forming the upper conductor circuit and the via hole into independent patterns. As the etching solution, a sulfuric acid / hydrogen peroxide aqueous solution, an aqueous solution of a persulfate such as ferric chloride, cupric chloride, or ammonium persulfate is used. The palladium catalyst nuclei exposed on the non-conductor circuit portion are dissolved and removed with chromic acid, sulfuric acid, hydrogen peroxide or the like.

(12) Thereafter, if necessary, the steps (3) to (11) are repeated, and the uppermost conductive circuit is subjected to electroless plating under the same conditions as in the above step (3). A roughening layer is formed on the conductor circuit.

Next, a solder resist layer is formed on the substrate surface including the uppermost conductive circuit, and solder bumps are formed by the above-described method, thereby completing the manufacture of the printed wiring board. In addition, a plasma treatment with oxygen, carbon tetrachloride, or the like may be performed as needed for a character printing process for forming a product recognition character or the like or for modifying a solder resist layer. Although the above method is based on the semi-additive method, a full additive method may be employed.

[0054]

The present invention will be described in more detail below. Example 1 A. Preparation of adhesive for electroless plating (adhesive for upper layer) (i) 25% acrylate of cresol novolac type epoxy resin (manufactured by Nippon Kayaku Co., Ltd., molecular weight: 2500) at a concentration of 80% by weight of diethylene glycol dimethyl ether (DMDG) 35 parts by weight of a resin solution dissolved in water, photosensitive monomer (Aronix M315, manufactured by Toa Gosei Co., Ltd.) 3.1
5 parts by weight, antifoaming agent (S-65, manufactured by San Nopco) 0.5
Parts by weight and 3.6 parts by weight of N-methylpyrrolidone (NMP) were placed in a container and mixed by stirring to prepare a mixed composition.

(Ii) Polyether sulfone (PES) 1
2 parts by weight, 7.2 parts by weight of an epoxy resin particle (manufactured by Sanyo Kasei Co., polymer pole) having an average particle diameter of 1.0 μm and 3.09 parts by weight of an epoxy resin particle having an average particle diameter of 0.5 μm were placed in another container, After stirring and mixing, 30 parts by weight of NMP was further added and stirred and mixed with a bead mill to prepare another mixed composition.

(Iii) 2 parts by weight of an imidazole curing agent (2E4MZ-CN, manufactured by Shikoku Chemicals), a photopolymerization initiator (Irgacure, manufactured by Ciba Specialty Chemicals)
I-907) 2 parts by weight, photosensitizer (manufactured by Nippon Kayaku Co., Ltd., DE
TX-S) 0.2 part by weight and 1.5 parts by weight of NMP were further placed in another container, and mixed by stirring to prepare a mixed composition. Then, an adhesive for electroless plating was obtained by mixing the mixed compositions prepared in (i), (ii) and (iii).

B. Preparation of adhesive for electroless plating (adhesive for lower layer) (i) 25% acrylate of cresol novolac type epoxy resin (manufactured by Nippon Kayaku Co., Ltd., molecular weight: 2500) at a concentration of 80% by weight of diethylene glycol dimethyl ether (DMDG) 35 parts by weight of a resin solution, 4 parts by weight of a photosensitive monomer (manufactured by Toagosei Co., Aronix M315), 0.5 parts by weight of an antifoaming agent (S-65 manufactured by Sannopco) and N-methylpyrrolidone (NMP) 3.6 parts by weight were placed in a container and mixed by stirring to prepare a mixed composition.

(Ii) Polyether sulfone (PES) 1
2 parts by weight and epoxy resin particles (manufactured by Sanyo Chemical Industries,
14.4 having an average particle size of 0.5 μm
9 parts by weight were placed in another container and mixed with stirring.
30 parts by weight of MP was added and mixed by stirring with a bead mill to prepare another mixed composition.

(Iii) 2 parts by weight of an imidazole curing agent (2E4MZ-CN manufactured by Shikoku Chemicals) and a photopolymerization initiator (Irgacure manufactured by Ciba Specialty Chemicals)
I-907) 2 parts by weight, photosensitizer (manufactured by Nippon Kayaku Co., Ltd., DE
TX-S) 0.2 part by weight and 1.5 parts by weight of NMP were further placed in another container, and mixed by stirring to prepare a mixed composition. Then, an adhesive for electroless plating was obtained by mixing the mixed compositions prepared in (i), (ii) and (iii).

C. Preparation of resin filler (i) 100 parts by weight of bisphenol F type epoxy monomer (manufactured by Yuka Shell Co., molecular weight: 310, YL983U),
SiO ₂ spherical particles having an average particle diameter of 1.6 μm and a maximum particle diameter of 15 μm or less (CRS 1101 manufactured by Adtec Co., Ltd.) having a surface coated with a silane coupling agent.
-CE) 170 parts by weight and 1.5 parts by weight of a leveling agent (Perenol S4 manufactured by San Nopco Co.) are placed in a container, and the mixture is stirred and mixed to have a viscosity of 40 to 40 at 23 ± 1 ° C.
A resin filler of 50 Pa · s was prepared. As the curing agent, an imidazole curing agent (2E4MZ manufactured by Shikoku Chemicals Co., Ltd.)
-CN) 6.5 parts by weight.

D. Manufacturing method of printed wiring board (1) 1 mm thick glass epoxy resin or BT (bismaleimide triazine) resin
A copper-clad laminate on which an 8 μm copper foil 8 was laminated was used as a starting material (see FIG. 1A). First, the copper-clad laminate was drilled, subjected to electroless plating, and etched in a pattern to form a lower conductor circuit 4 and through holes 9 on both surfaces of the substrate 1.

(2) Through-hole 9 and lower conductor circuit 4
After the substrate on which was formed was washed with water and dried, NaOH (1
0 g / l), NaClO ₂ (40 g / l), Na ₃ PO
₄ A blackening treatment using an aqueous solution containing (6 g / l) as a blackening bath (oxidizing bath), NaOH (10 g / l), NaBH
₄ A reduction treatment was performed using an aqueous solution containing (6 g / l) as a reduction bath, and roughened surfaces 4a and 9a were formed on the entire surface of the lower conductor circuit 4 including the through holes 9 (see FIG. 1 (b)). .

(3) After preparing the resin filler described in the above C, within 24 hours after the preparation by the following method, the resin filler 1 in the through hole 9 and between the lower conductor circuits 4 is prepared.
0 (see FIG. 1 (c)).
At this time, as a coating method, a printing method using a squeegee was adopted. In the first printing coating, the through holes 9 were mainly filled and dried at 100 ° C. for 20 minutes. Also,
In the second printing application, the recesses mainly formed by the formation of the lower conductive circuit 4 were filled and dried at 100 ° C. for 20 minutes.

(4) One surface of the substrate after the treatment of the above (3) is subjected to belt sander polishing using # 600 belt polishing paper (manufactured by Sankyo Rikagaku Co., Ltd.) to form the surface of the lower conductor circuit 4 and the through holes 9. Was polished so that the resin filler did not remain on the land surface, and then buffed to remove the scratches caused by the belt sander polishing. Such a series of polishing was similarly performed on the other surface of the substrate. Thereafter, a heat treatment was performed at 100 ° C. for 1 hour and at 150 ° C. for 1 hour to completely cure the resin filler layer.

In this way, the surface portion of the resin filler 10 formed in the through hole 9 and the portion where the conductor circuit is not formed and the surface of the lower conductor circuit 4 are flattened, and the resin filler 10 and the side surfaces of the lower conductor circuit 4 are flattened. 4a is firmly adhered through the roughened surface, and the inner wall surface 9a of the through hole 9 and the resin filler 10
Was obtained, thereby obtaining an insulating substrate firmly adhered through the roughened surface (see FIG. 1D). That is, by this step, the surface of the resin filler and the surface of the inner layer copper pattern become the same surface.

(5) Next, the insulating substrate on which the conductor circuit has been formed by the above process is subjected to alkali degreasing and soft etching, and then treated with a catalyst solution comprising palladium chloride and an organic acid to remove the Pd catalyst. To activate the catalyst.

Next, copper sulfate (3.9 × 10 ^-2 mol /
l), nickel sulfate (3.8 × 10 ^-3 mol / l), sodium citrate (7.8 × 10 ^-3 mol / l), sodium hypophosphite (2.3 × 10 ^-1 mol / l) ), Surfactant (Sufinol 465, manufactured by Nissin Chemical Industry Co., Ltd.)
(1.1 × 10 ⁻⁴ mol / l)
The substrate was immersed in an electroless copper plating bath of H = 9, and one minute after the immersion, the substrate was vibrated in the vertical and horizontal directions at a rate of once every 4 seconds, so that A roughened layer of a needle-like alloy made of Cu-Ni-P was provided.

(6) Further, tin borofluoride (0.1 mol
1 / l), temperature 3 containing thiourea (1.0 mol / l)
Using a tin-substituted plating solution at 5 ° C. and pH = 1.2, a Cu—Sn substitution reaction was performed for 10 minutes in an immersion time to provide a 0.3 μm-thick Sn layer on the surface of the roughened layer (FIG. )reference). However, this Sn layer is not shown.

(7) Adhesive for lower layer electroless plating described in B above (viscosity: 1.5 Pa ·
s) was applied using a roll coater within 24 hours after preparation, allowed to stand in a horizontal state for 20 minutes, and then dried at 60 ° C. for 30 minutes. Next, the adhesive for electroless plating (viscosity: 7 Pa · s) for the upper layer described in the above A was applied using a roll coater within 24 hours after preparation, and similarly left for 20 minutes in a horizontal state, After drying at 60 ° C. for 30 minutes, a 35 μm-thick electroless plating adhesive layer 2
a and 2b were formed (see FIG. 2B).

(8) A photomask film on which a black circle having a diameter of 85 μm is printed is brought into close contact with both surfaces of the substrate on which the layer of the adhesive for electroless plating is formed in the above (7), and is 500 mJ / cm by an ultrahigh pressure mercury lamp. After exposure at ^two intensities, it was spray-developed with a DMDG solution. Thereafter, the substrate was further exposed at 3000 mJ / cm ² intensity using an ultra-high pressure mercury lamp,
A heat treatment at 100 ° C. for 1 hour, 120 ° C. for 1 hour, and 150 ° C. for 3 hours is performed.
(See FIG. 2 (c)). Note that the tin plating layer was partially exposed in the opening serving as the via hole.

(9) The substrate on which the via hole openings 6 are formed is immersed in a chromic acid aqueous solution (7500 g / l) for 19 minutes to dissolve and remove the epoxy resin particles present on the surface of the interlayer resin insulating layer. Was roughened to obtain a roughened surface. Then, it was immersed in a neutralizing solution (manufactured by Shipley) and washed with water (see FIG. 2D). Further, by applying a palladium catalyst (manufactured by Atotech) to the surface of the substrate that has been subjected to the surface roughening treatment (roughening depth: 6 μm), the catalyst is applied to the surface of the interlayer insulating material layer and the inner wall surface of the via hole opening. Nuclei were attached.

(10) Next, the substrate was immersed in an electroless copper plating aqueous solution having the following composition, and the thickness of the substrate was reduced to 0.6 to 1.
An electroless copper plating film 12 of 2 μm was formed (FIG. 3A)
reference). [Electroless plating aqueous solution] EDTA 0.08 mol / l Copper sulfate 0.03 mol / l HCHO 0.05 mol / l NaOH 0.05 mol / l α, α'-bipyridyl 80 mg / l PEG 0.10 g / L (polyethylene glycol) [Electroless plating conditions] 20 minutes at a liquid temperature of 65 ° C

(11) A commercially available photosensitive dry film is affixed to the electroless copper plating film 12, a mask is placed, and
Exposure at mJ / cm ² and development with a 0.8% aqueous sodium carbonate solution provided a plating resist 3 having a thickness of 15 μm (see FIG. 3B).

(12) Next, the copper-free copper plating film 13 having a thickness of 15 μm was formed on the non-resist-formed portion under the following conditions (see FIG. 3C). [Electroplating aqueous solution] sulfuric acid 2.24 mol / l copper sulfate 0.26 mol / l additive 19.5 ml / l (manufactured by Atotech Japan, capparaside HL) [electroplating conditions] current density 1 A / dm ² hours 65 minutes Temperature 22 ± 2 ℃

(13) Further, after the plating resist is stripped and removed with a 5% KOH aqueous solution, the electroless plating film under the plating resist is dissolved and removed by etching with a mixed solution of sulfuric acid and hydrogen peroxide. The upper conductor circuit 5 (including the via hole 7) having a thickness of 18 μm and comprising a plating film and an electrolytic copper plating film was formed (see FIG. 3D).

(14) With respect to the substrate on which the conductor circuit is formed,
Perform the same treatment as in (5), and apply a 2 μm thick
The alloy roughened layer 11 made of Cu—Ni—P was formed (see FIG. 4A). However, the roughened surface has Sn
No substitution was made. (15) Subsequently, the above steps (6) to (14) were repeated to form a further upper layer conductive circuit. (FIG. 4 (b)
To FIG. 5 (b)).

(16) Next, a cresol novolak type epoxy resin (manufactured by Nippon Kayaku Co., Ltd.) dissolved in diethylene glycol dimethyl ether (DMDG) so as to have a concentration of 60% by weight was used. 46.67 parts by weight of an oligomer for imparting property (molecular weight: 4000), 15 parts by weight of a bisphenol A type epoxy resin (trade name: Epicoat 1001 manufactured by Yuka Shell Co., Ltd.) dissolved in methyl ethyl ketone, and 15 parts by weight of an imidazole curing agent ( (Shikoku Chemicals, trade name: 2E4MZ-CN)
6 parts by weight, 3 parts by weight of polyfunctional acrylic monomer (trade name: R604, manufactured by Nippon Kayaku Co., Ltd.), which is a photosensitive monomer, and polyvalent acrylic monomer (trade name: DP, manufactured by Kyoei Chemical Co., Ltd.)
E6A) 1.5 parts by weight and 0.71 part by weight of a dispersion antifoaming agent (manufactured by San Nopco, trade name: S-65) in a container,
A mixed composition was prepared by stirring and mixing, and 2.0 parts by weight of benzophenone (manufactured by Kanto Kagaku) as a photopolymerization initiator and Michler's ketone (manufactured by Kanto Kagaku) as a photosensitizer were added to the mixed composition. Add 0.2 parts by weight and adjust viscosity to 25 ° C
To obtain a solder resist composition (organic resin insulating material) adjusted to 2.0 Pa · s. The viscosity was measured with a B-type viscometer (DVL-B type, manufactured by Tokyo Keiki Co., Ltd.) when the rotor No. was 60 rpm. Rotor N at 4,6 rpm
o. According to 3.

(17) Next, the above-mentioned solder resist composition is applied on both surfaces of the multilayer wiring board in a thickness of 20 μm.
After performing a drying process under the conditions of 20 ° C. for 20 minutes and 70 ° C. for 30 minutes, a 5 mm-thick photomask on which a pattern of the opening of the solder resist is drawn is brought into close contact with the solder resist layer, and an ultraviolet ray of 1000 mJ / cm ² is applied. Exposure with DM
Development was performed with a TG solution to form an opening having a diameter of 200 μm. Then, at 80 ° C. for 1 hour, and at 100 ° C. for 1 hour.
The solder resist layer is cured by heating for 120 hours at 120 ° C. for 1 hour and 150 ° C. for 3 hours to form a solder bump forming pad portion (the pitch of which is 25 μm).
A solder resist layer 14 having a diameter of 130 μm and a thickness of 20 μm was formed.

(18) Next, a solder resist layer (organic resin
The substrate on which the insulating layer (14) was formed was coated with nickel chloride (2.3).
× 10^-1mol / l), sodium hypophosphite (2.8
× 10 ^-1mol / l), sodium citrate (1.6 ×
10^-1mol / l) and pH = 4.5
Immersion in a plating solution for 20 minutes, and a 5 μm thick
A nickel plating layer 15 was formed. In addition, the board
Potassium gold cyanide (7.6 × 10^-3mol / l), salt
Ammonium iodide (1.9 × 10^-1mol / l), quenched
Sodium acid (1.2 × 10^-1mol / l), phosphorus hypophosphite
Sodium acid (1.7 × 10^-1mol / l)
Immerse in a plating solution at 80 ° C for 7.5 minutes,
0.03 μm thick gold plating layer on the Kell plating layer 15
No. 16 was formed.

(19) Next, solder paste was printed on the pads for forming the solder bumps. First, openings (opening diameter: 170) are formed in portions facing all solder bump forming pads.
μm) was formed, the mask was placed on the solder resist layer 14, the solder bump forming pad was filled with solder paste, and then reflowed at 200 ° C. to form a solder bump. (FIG. 5 (c))

The solder paste used was composed mainly of Sn / Pb in a weight ratio of 55:45 and having a particle size of 5 to 20 μm.
And the viscosity is 250 Pa. s. In addition, Cu, Zn, As in solder
Was 0.04% by weight, and the other metals were 0.001% by weight or less.

(20) Next, the substrate is flux-cleaned, and the substrate is divided into pieces of an appropriate size using a device having a router. I got (21) A plurality of printed wiring boards were manufactured by the above method, and the other part of the manufactured printed wiring boards was joined to an IC chip. That is, using a predetermined mounting device, after the flux cleaning, the solder bumps of the printed wiring board are aligned with the bumps provided on the IC chip with reference to the target mark, and the solder is reflowed. The solder bump and the bump of the IC chip were joined. Then, flux washing was performed, and an underfill was filled between the IC chip and the multilayer printed wiring board, thereby obtaining a printed wiring board to which the IC chip was connected.

Comparative Example 1 A solder paste was used in the same manner as in Example 1 except that a solder containing a total of 0.2% by weight of Al, As, Ag, Cu and Zn was used. A printed wiring board was manufactured.

For the printed wiring boards manufactured in Example 1 and Comparative Example 1, first, the content of impurities in the solder bumps was measured by an energy dispersion method. As a result, in the solder bump according to Example 1, As was 0.02% by weight, Cu was 0.01% by weight, Zn was 0.01% by weight, and the total was 0.04% by weight. Was 0.001% by weight or less. On the other hand, in the solder bump according to Comparative Example 1, Al was 0.1% by weight and As was 0.1% by weight.
02% by weight, Ag is 0.04% by weight, Cu is 0.01% by weight, Zn is 0.03% by weight, and the total is 0.2% by weight.
And the content of other metals was 0.001% by weight or less.

Next, the printed wiring boards manufactured in Example 1 and Comparative Example 1 were subjected to high temperature and high humidity conditions (temperature: 85 ° C.,
(Relative humidity: 85%), a bias voltage (5 V) is applied,
After being left in this state for 500 hours, the operation of the printed wiring board on which the IC chip was mounted was confirmed. Further, the printed wiring board was cut so as to include the solder bump portions, and the solder bump portions were observed with a microscope (× 100).

As a result, in the printed wiring board according to the first embodiment, even after 500 hours, the transmitted power supply and electric signal did not show any delay, and the IC chip and the printed wiring board operated normally. did. No cracks or peeling were observed on the solder bump forming pad and the solder bump, and no peeling between the solder bump and the corrosion-resistant metal layer was observed. Furthermore, no melting of the solder bumps occurred.

On the other hand, in the printed wiring board according to Comparative Example 1, a delay was confirmed in the power supply and the electric signal. That is, the power supply and the electric signal were transmitted to the solder ball portion on the opposite side only about 10% of the frequency transmitted from the IC chip. In addition, cracks were observed in the solder bump portions, and dissolution of the solder bumps was also observed.

[0088]

As described above, according to the printed wiring board of the present invention, delay or noise is not generated in a power supply or an electric signal transmitted through the solder bump forming pad and the solder bump. In addition, it is possible to manufacture a highly reliable printed wiring board that does not cause cracks or peeling at the solder bump portions.

[Brief description of the drawings]

FIGS. 1A to 1D are cross-sectional views illustrating a part of a manufacturing process of a printed wiring board according to the present invention.

FIGS. 2A to 2D are cross-sectional views showing a part of the manufacturing process of the printed wiring board of the present invention.

FIGS. 3A to 3D are cross-sectional views showing a part of the manufacturing process of the printed wiring board of the present invention.

FIGS. 4A to 4C are cross-sectional views showing a part of the manufacturing process of the printed wiring board of the present invention.

FIGS. 5A to 5C are cross-sectional views showing a part of the manufacturing process of the printed wiring board of the present invention.

[Explanation of symbols]

Reference Signs List 1 substrate 2 (2a, 2b) interlayer resin insulating layer (adhesive layer for electroless plating) 3 plating resist 4 lower conductive circuit 4a roughened surface 5 upper conductive circuit 7 via hole 8 copper foil 9 through hole 9a roughened surface 10 Resin filler 11 Roughened layer 12 Electroless plating layer 13 Electroplating layer 14 Solder resist layer (organic resin insulating layer) 15 Nickel plating film 16 Gold plating film 17 Solder bump

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H05K 1/09 H05K 1/09 A

Claims (3)

[Claims] 1. A conductive circuit comprising a plurality of layers with an interlayer insulating layer interposed therebetween is formed on an insulating substrate, a solder resist layer is provided on an uppermost conductive circuit, and a solder bump is formed on the solder resist layer. Printed wiring board
The solder bump contains 1 to 70% by weight of Sn and at least one selected from the group consisting of Al, As, Ag, Cu and Zn in a total amount of 0.001 to 0.
A printed wiring board containing 1% by weight and the remaining component being Pb. 2. The method according to claim 1, wherein the solder bumps include Sn, Al, As,
0.0001 of metals other than Ag, Cu, Zn and Pb
The printed wiring board according to claim 1, wherein the content of the printed wiring board is not more than weight%. 3. A process of forming an interlayer insulating layer on the formed conductive circuit is repeated to form a conductive circuit having a plurality of layers with an interlayer insulating layer interposed therebetween on an insulating substrate, and then on the uppermost conductive circuit. A printed wiring board, wherein a solder resist layer is provided on the substrate, a part of the solder resist layer is opened to form a plurality of solder bump forming pads, and a solder paste is applied to the solder bump forming pads to form solder bumps The method according to claim 1, wherein the solder paste has a Sn content of 1 to 70.
%, Al, As, Ag,
At least one selected from the group consisting of Cu and Zn
A method for producing a printed wiring board, wherein a solder containing 0.001 to 0.1% by weight of seeds in total and the remaining component being Pb is used.