JP2008088543A - Copper surface treatment liquid set, surface treatment method for copper using the same, copper, wiring board and semiconductor package - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a copper surface treatment liquid set with which fine ruggedness with the Rz of ≤1 μm can be densely and uniformly formed on the surface of copper in a short time, to provide a surface treatment method for copper using the treatment liquid set, to provide copper surface-treated applying the surface treatment method, to provide a wiring board having copper wiring surface-treated applying the surface treatment method, and to provide a semiconductor package obtained by using the board. <P>SOLUTION: The copper surface treatment liquid set is provided with: an acidic noble metal treatment liquid comprising the salt of a metal nobler than copper and discretely forming a metal nobler than copper on the surface of copper; and an alkaline oxidation treatment liquid comprising a phosphate and an oxidizer and oxidizing the surface of copper. Upon its use, a metal nobler than copper is discretely formed on the surface of copper using the noble metal treatment liquid, and thereafter, the copper surface is subjected to oxidation treatment using the oxidation treatment liquid, thus fine ruggedness by the dense and uniform crystals of copper oxide can be formed on the copper surface. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention applies a copper surface treatment liquid set for forming fine irregularities excellent in adhesion to an insulating resin on a copper surface, a copper surface treatment method using the treatment liquid set, and the surface treatment method. The present invention relates to a surface-treated copper, a wiring substrate having a copper wiring surface-treated by applying the surface treatment method, and a semiconductor package using the substrate.

  The development of the information society in recent years has been remarkable, and consumer devices have been reduced in size, weight, performance, and functionality, such as personal computers and mobile phones. Industrial equipment includes wireless base stations, optical communication devices, and servers. In addition, there is a demand for improvement in functions in the same way regardless of whether it is large or small, such as routers and other network-related devices. In addition, with the increase in the amount of information transmitted, the frequency of signals handled tends to increase year by year, and high-speed processing and high-speed transmission technology are being developed. With regard to mounting relations, the development of system-on-chip (SoC), system-in-package (SiP), etc., as new high-density mounting technologies, as well as higher-speed and higher-performance LSIs such as CPUs, DSPs, and various types of memory are actively developed. Has been done. For this reason, build-up type multilayer wiring boards have come to be used for semiconductor chip mounting boards and motherboards in order to cope with high frequency, high density wiring, and high functionality.

  A build-up multilayer wiring board is manufactured by repeating an interlayer insulating layer forming step and a wiring forming step. In this manufacturing method, it is important to ensure the adhesive strength between the wiring and the interlayer insulating layer and the insulation reliability between the wiring. In order to satisfy these requirements, surface treatment (roughening treatment) of wiring has been conventionally performed by the method described below.

  The first prior art is a method in which a roughened shape on the order of microns is given to the surface of the wiring, and an adhesive force between the wiring and the insulating material is obtained by an anchor effect. For example, a method of imparting a micron-order roughened shape to a copper surface using an aqueous solution containing a main agent composed of an inorganic acid and a copper oxidizing agent and an auxiliary composed of at least one azole and at least one etching inhibitor. (Patent Document 1), a method of performing chromate treatment and coupling agent treatment (Patent Document 2) after forming continuous irregularities having a height of 1.5 to 5.0 μm by microetching.

  The second prior art is a method in which fine copper oxide needle crystals are provided on the surface of the wiring, and an adhesive force between the wiring and the insulating layer is obtained by an anchor effect. For example, there is a method of imparting fine copper oxide needle-like crystals by dipping for several minutes at around 80 ° C. using an alkaline aqueous solution containing an oxidizing agent such as sodium chlorite.

The third prior art is a method in which fine metallic copper needle crystals are provided on the surface of the wiring to obtain an adhesive force between the wiring and the insulating layer by an anchor effect. For example, by using an alkaline aqueous solution containing an oxidizing agent such as sodium chlorite, immersion is performed at around 80 ° C. for several minutes to give fine acicular crystals of copper oxide, and then at least one kind of amine boranes. For example, there is a method (Patent Document 3) for imparting fine metallic copper needle-like crystals by performing a reduction treatment with an acidic solution in which a boron-based chemical is mixed.
JP 2000-282265 A Japanese Patent Laid-Open No. 9-246720 Japanese Patent No. 2656622

  The first conventional technique that imparts the above-mentioned micron-order roughened shape and improves the adhesive strength between the wiring and the interlayer insulating layer has a Rz (10-point average surface roughness, the same applies hereinafter) 2 to 2 on the surface of the wiring. Concavities and convexities of 3 μm were formed, and the adhesive strength was secured by the anchor effect. However, when a high-speed electrical signal is applied to a wiring having an Rz exceeding 1 μm, the electrical signal is concentrated and flows near the surface of the wiring due to the skin effect, and there is a problem that transmission loss increases. In addition, when the wiring has a fine wiring width / space (L / S) = less than 25 μm / 25 μm, when the surface of the wiring is roughened by a conventional method, the wiring becomes thin or the variation in the wiring width increases. There is a problem that.

  The second conventional technique for imparting fine copper oxide needle-like crystals to the wiring surface and improving the adhesive strength between the wiring and the interlayer insulating layer is such that the Rz of the wiring surface is 0.1 to 1.5 μm. Although unevenness can be formed, the unevenness of the unevenness is large, and there is a problem that the reliability of adhesion at high temperature and high humidity test is lowered at a location where Rz <1.0 μm, and at a location where Rz> 1.0 μm Similar to the first prior art, there is a problem that transmission loss increases. In addition, the copper oxide needle crystals are dissolved in the plating process for through-hole connection, and the insulation reliability is easily lowered and the wiring and the insulating layer are likely to be peeled off at a portion where the distance between the wirings is short.

  A third conventional technique for imparting fine metallic copper needle crystals to the wiring surface to improve the adhesive strength between the wiring and the interlayer insulating layer is that the metallic copper needle crystals dissolve in the through-hole plating process. Since there is no problem, there is no decrease in insulation reliability or separation between the wiring and the insulating layer at the short part of the insulation distance between the wirings. However, as in the case of the second conventional technology, the reliability is lowered during the high temperature / high humidity test. There is a problem of transmission loss.

  An object of the present invention is to improve the above-mentioned problems of the prior art, and fine unevenness on the surface of copper, which is excellent in adhesiveness with an insulating resin and the like and whose Rz is 1 μm or less, is densely formed. Copper surface treatment liquid set that can be formed uniformly and in a short time, copper surface treatment method using the treatment liquid set, copper surface treated by applying the surface treatment method, surface treatment method The present invention provides a wiring board having a copper wiring that has been surface-treated by applying, and a semiconductor package using the board.

  The present invention is characterized by the following items (1) to (15).

  (1) A copper surface treatment liquid set for roughening the copper surface, including a salt of a metal nobler than copper, and an acidic solution for discretely forming a metal nobler than copper on the copper surface A copper surface treatment liquid set comprising: a noble metal treatment liquid; and an alkaline oxidation treatment liquid containing a phosphate and an oxidizing agent for oxidizing the copper surface treated with the noble metal treatment liquid.

  (2) The above-mentioned (1), wherein the salt of the metal nobler than copper is a salt containing at least one metal selected from the group consisting of gold, silver, platinum, palladium, rhodium, rhenium, ruthenium, osmium and iridium. ) Copper surface treatment solution set.

  (3) The copper according to (1) or (2), wherein the noble metal treatment liquid further contains one or more compounds selected from the group consisting of ammonium salts, amino acids, hydroxycarboxylic acids, and hydroxycarboxylates. Surface treatment liquid set.

  (4) The oxidizing agent is one or more selected from the group consisting of chlorate, chlorite, hypochlorite, perchlorate and peroxodisulfate, (1) to (1) to (4) above The copper surface treatment liquid set according to any one of (3).

  (5) The phosphate according to any one of (1) to (4), wherein the phosphate is one or more selected from the group consisting of trisodium phosphate, tripotassium phosphate, and trilithium phosphate. Copper surface treatment solution set.

  (6) The copper surface treatment liquid set according to any one of (1) to (5), wherein the noble metal treatment liquid contains 0.1 to 10 mmol / L of a salt of a metal nobler than the copper.

  (7) The copper surface treatment liquid according to any one of (1) to (6), wherein the oxidation treatment liquid contains 1 to 40 g / L of the phosphate and 1 to 100 g / L of the oxidizing agent. set.

  (8) The copper surface treatment liquid used after the treatment with the oxidation treatment liquid further includes one or more treatment liquids selected from the group consisting of a reduction treatment liquid, a coupling treatment liquid, and a corrosion inhibition treatment liquid (1) )-(7) The copper surface treatment liquid set in any one of.

  (9) The copper surface treatment liquid set according to any one of the above (1) to (8), for roughening the copper surface so that the Rz is 1 nm or more and 1000 nm or less.

  (10) A copper surface treatment method in which the copper surface is roughened by sequentially using at least a noble metal treatment solution and an oxidation treatment solution of the copper surface treatment solution set according to any one of (1) to (9) above.

(11) The copper according to the above (10), wherein the amount of the noble metal formed on the copper surface by the noble metal treatment liquid is 0.001 μmol / dm ² or more and 40 μmol / dm ² or less. Surface treatment method.

  (12) The copper surface treatment method according to the above (10) or (11), wherein the roughness of the copper surface after treatment is 1 nm to 1000 nm in terms of Rz.

  (13) Copper surface-treated by the copper surface treatment method according to any one of (10) to (12) above.

  (14) A wiring board having a copper wiring surface-treated by the copper surface treatment method according to any one of (10) to (12).

  (15) A semiconductor package in which a semiconductor chip is mounted at a predetermined position of the wiring board according to (14).

  According to the present invention, since it is possible to form fine irregularities having a Rz of 1 μm or less densely and uniformly on a copper surface in a short time, for example, the adhesive strength between the wiring and the insulating layer and the fine wiring It becomes possible to manufacture a wiring board (multilayer wiring board) excellent in inter-insulation reliability and a semiconductor package excellent in reliability using the board with high productivity.

  The copper surface treatment liquid set of the present invention includes a salt of a metal nobler than copper, an acidic noble metal treatment (giving) liquid for discretely forming a metal nobler than copper on the copper surface, and phosphate And an oxidant, and an alkaline oxidation treatment liquid for oxidizing the copper surface treated with the noble metal treatment liquid.

  Further, the copper surface treatment liquid set of the present invention includes a reduction treatment liquid, a coupling treatment liquid, and a corrosion inhibition treatment as a copper surface treatment liquid used after the treatment with the oxidation treatment liquid in addition to the noble metal treatment liquid and the oxidation treatment liquid. You may further provide the at least 1 or more process liquid among liquids. In particular, the reduction treatment liquid can reduce fine irregularities due to the fine and uniform copper oxide needle crystals formed on the copper surface by the noble metal treatment and the oxidation treatment to fine irregularities due to the metallic copper needle crystals, preferable.

  In the copper surface treatment method of the present invention, at least a step of discretely forming a noble metal from copper on the copper surface with the noble metal treatment liquid, and then the copper surface is oxidized with the oxidation treatment liquid. The copper surface is treated with at least one treatment liquid among a reduction treatment liquid, a coupling treatment liquid, and a corrosion inhibition treatment liquid as necessary. You may have a process. Moreover, as pre-processing of each process, it is preferable to perform the degreasing process which cleans the copper surface, a pickling process, or combining these suitably.

  In addition, after the oxidation treatment or after performing at least one of the reduction treatment, the coupling treatment, and the corrosion inhibition treatment, the copper surface roughness generated by the surface treatment of these copper is Rz. It is preferable that it is 1 nm or more and 1,000 nm or less. Further, Rz is more preferably 1 nm or more and 100 nm or less, and further preferably 1 nm or more and 50 nm or less. If Rz is less than 1 nm, the adhesive strength with a resist or an insulating resin tends to be reduced, and if Rz exceeds 1,000 nm, problems of the prior art tend to occur. “Dense and uniform” means that the shape of the copper surface is processed with a scanning electron microscope (SEM) or with a focused ion beam processing observation device (FIB) and observed with a scanning ion microscope (SIM) image. In this case, the size and height of the copper oxide or metal copper crystals are 1 nm or more and 1,000 nm or less, and the formed crystals are densely packed.

  Hereinafter, each treatment liquid of the copper surface treatment liquid set of the present invention and a treatment method using the same will be described in detail.

(Precious metal treatment liquid and treatment using it)
The noble metal treatment liquid for discretely forming a metal nobler than copper on the copper surface is an acidic solution containing a salt of a metal nobler than copper, and further includes ammonium salt, amino acid, hydroxycarboxylic acid, hydroxycarboxylic acid. It is preferable to include additives such as acid salts. The salt of a metal nobler than copper is preferably a salt containing at least one metal selected from the group consisting of gold, silver, platinum, palladium, rhodium, rhenium, ruthenium, osmium, iridium, for example. In particular, a palladium salt is preferred. As the palladium salt, for example, palladium chloride, palladium sulfate, palladium nitrate and the like can be used. More specifically, for example, ammonium chloride, ammonium sulfate, or ammonium nitrate is preferably used as the ammonium salt. More specifically, the amino acid is, for example, alanine, arginine, asparagine, aspartic acid, cysteine, glutamine, glutamic acid, glycine, histidine, isoleucine, leucine, lysine, methionine, phenylalanine, proline, serine, threonine, tryptophan. , Tyrosine, valine, etc. are preferably used. More specifically, the hydroxycarboxylic acid or hydroxycarboxylate is, for example, glycolic acid or glycolate, lactic acid or lactate, glyceric acid or glycerate, malic acid or malate, tartaric acid or tartaric acid. Salt, citric acid or citrate, isocitric acid or isocitrate, salicylic acid or salicylate, mandelic acid or mandelate, gallic acid or gallate, mevalonic acid or mevalonate, quinic acid or quinate, shikimi It is preferable to use acid or shikimate.

  The noble metal treatment liquid is prepared by adding a salt of a metal nobler than copper or the above additive to an acidic aqueous solution obtained by diluting an inorganic acid such as hydrochloric acid, sulfuric acid or nitric acid with water. Can do. The concentration of the noble metal salt in the noble metal treatment liquid is not particularly limited, but is preferably 0.1 to 10 mmol / L. Moreover, the pH of the said noble metal processing liquid should just be a value which shows acidity, Although it does not specifically limit, It is preferable that it is 1-3. The pH can be adjusted appropriately using an aqueous solution of hydrochloric acid, sulfuric acid, nitric acid, sodium hydroxide, potassium hydroxide, or the like.

  Further, the method for treating the copper surface with the noble metal treatment liquid, that is, the method for discretely forming a noble metal from copper on the copper surface is not particularly limited. For example, the noble metal treatment liquid by a spray method or a dip method is used. Can be carried out by displacement plating in which a metal noble than copper is deposited on the copper surface. Displacement plating uses the difference in ionization tendency between copper and a metal nobler than copper, and according to this, a metal nobler than copper can be easily and inexpensively formed on the copper surface. . Moreover, the temperature of the noble metal treatment solution during the treatment is not particularly limited, but is preferably 20 to 80 ° C, more preferably 30 to 70 ° C, and particularly preferably 40 to 50 ° C. Further, the treatment time with the noble metal treatment liquid may be appropriately determined in consideration of the noble metal salt concentration of the noble metal treatment liquid, the liquid temperature, and the like so that the copper surface is not completely covered with the noble metal.

In addition, the amount of the metal noble than copper formed discretely on the copper surface by the treatment with the noble metal treatment liquid is not particularly limited, but is 0.001 μmol / dm ² or more and 40 μmol / dm ² or less. it is preferred, more preferably 0.01μmol / dm ² or more and 10 .mu.mol / dm ² or less, more preferably 0.1 [mu] mol / dm ² or more and is 4μmol / dm ² or less. If the formation amount is less than 0.001 μmol / dm ² , it tends to be difficult to form dense and uniform fine irregularities, and if it exceeds 40 μmol / dm ² , the adhesive strength tends to decrease. That is, in the present invention, “discrete” means that the copper surface is not completely covered with the noble metal, and preferably the noble metal is uniformly on the copper surface in an amount of 0.001 μmol / dm ² or more and 40 μmol / dm ² or less. It means a state of being distributed. In addition, the amount of discretely formed noble metal on the copper surface is determined by dissolving the noble metal on the copper surface with aqua regia and then quantitatively analyzing the solution with an atomic absorption photometer. Can be sought.

(Oxidation treatment liquid and treatment using it)
The oxidation treatment liquid for oxidizing the copper surface treated with the noble metal treatment liquid is an alkaline solution containing a phosphate and an oxidizing agent. As the phosphate, for example, trisodium phosphate, tripotassium phosphate, trilithium phosphate and the like are preferably used. Further, as the oxidizing agent, for example, one or more compounds selected from the group consisting of chlorate, chlorite, hypochlorite, perchlorate, and peroxodisulfate may be used. More specifically, sodium hypochlorite, sodium chlorite, sodium chlorate, sodium perchlorate, potassium hypochlorite, potassium chlorite, potassium chlorate, potassium perchlorate, peroxodioxide Ammonium sulfate, potassium peroxodisulfate, sodium peroxodisulfate, and the like are preferably used, and sodium chlorite is particularly preferable from the viewpoints of handleability such as storage stability and safety and price. Furthermore, you may add a well-known organic acid and a chelating agent to the said oxidation treatment liquid.

  In addition, the oxidation treatment liquid is prepared by adding, for example, the phosphate and the oxidizing agent to an alkaline aqueous solution in which an alkali (earth) metal compound such as sodium hydroxide, potassium hydroxide, or sodium carbonate is dissolved in water. It can prepare by adding the additive etc. which are added according to it. Moreover, although the density | concentration of each component in an oxidation treatment liquid is not specifically limited, It is preferable that a phosphate concentration is 1-40 g / L, and it is preferable that an oxidizing agent density | concentration is 1-100 g / L. The pH of the oxidation treatment solution is not particularly limited as long as it is a value indicating alkalinity, but is preferably 11 to 13. The pH can be adjusted appropriately using an aqueous solution of hydrochloric acid, sulfuric acid, nitric acid, sodium hydroxide, potassium hydroxide, or the like.

  The method for oxidizing the copper surface with the oxidation treatment liquid is not particularly limited. For example, the oxidation treatment liquid can be supplied to the copper surface by a spray method or a dipping method. In addition, the temperature of the oxidation treatment solution during the treatment is not particularly limited, but it is preferably 20 to 95 ° C in consideration of sufficient oxidation treatment and damage to the substrate given by the alkaline solution, and preferably 30 to 80 ° C. More preferably, it is 40-60 degreeC. Further, the treatment time with the oxidation treatment liquid may be appropriately determined so that a desired amount of copper oxide crystals is formed in consideration of the concentration of the oxidation treatment liquid, the liquid temperature, and the like. In addition, in the oxidation treatment of the copper surface with the above-described oxidation treatment liquid, the copper surface is covered with copper oxide needle crystals in a short time, and the oxidation reaction is stopped, so that the treatment time can be shortened compared to the prior art. is there.

The amount of crystal of copper oxide formed on the copper surface by the treatment with the oxidation treatment liquid is not particularly limited, but is preferably 0.001 mg / cm ² or more and 0.3 mg / cm ² or less. more preferably 01mg / cm ² or more and is 0.2 mg / cm ² or less, particularly preferably 0.03 mg / cm ² or more and is 0.1 mg / cm ² or less. If the copper oxide crystal amount is less than 0.001 mg / cm ² , the resist peels off or the adhesive strength with the insulating resin or the like tends to decrease, and if it exceeds 0.3 mg / cm ² , the transmission loss increases. It tends to occur easily. The amount of copper oxide crystals formed on the copper surface can be examined by measuring the amount of electrolytic reduction. For example, using oxidized copper as a working electrode (cathode), a constant amount of electricity of 0.5 mA / cm ² is passed, and the surface potential of copper completely changes from the potential of copper oxide to the potential of metallic copper. The amount of copper oxide crystals can be determined from the amount of electrolytic reduction by measuring the time until a stable potential of −1.0 V or less is obtained.

(Reduction treatment liquid and treatment using it)
The unevenness due to the copper oxide crystals formed on the copper surface by the oxidation treatment is preferably made into an unevenness of metal copper by reduction treatment. Examples of the reduction treatment solution used for this reduction treatment include an aqueous solution in which formaldehyde, paraformaldehyde, an aromatic aldehyde compound, etc. are added to an alkaline solution adjusted to pH 9.0 to 13.5, hypophosphorous acid or hypochlorous acid. It is preferable to use an aqueous solution to which a phosphate or the like is added, an aqueous solution to which dimethylamine borane or a compound containing it is added, an aqueous solution to which a boron hydride salt or a compound containing it is added, or the like. As what is marketed, for example, HIST-100 (manufactured by Hitachi Chemical Co., Ltd., trade names, including HIST-100B and HIST-100D) is preferably used as the reduction treatment liquid. In addition, the alkaline solution shown here is not particularly limited, but for example, an alkaline solution containing an alkali metal or an alkaline earth metal is preferable. More specifically, for example, those obtained by adding an alkali metal compound such as sodium hydroxide, potassium hydroxide or sodium carbonate or an alkaline earth metal compound to a solvent such as water or water treated with an ion exchange resin are more preferable.

  Further, the treatment with the reduction treatment liquid is preferably performed by a method such as immersing copper to be treated in the reduction treatment liquid, or spraying or applying the reduction treatment liquid to copper, such as the liquid temperature and treatment time. The treatment conditions may be appropriately determined according to the type and concentration of the reduction treatment solution, and are not particularly limited.

(Coupling solution and treatment using this)
After the oxidation treatment, a coupling treatment is preferably performed in order to improve the adhesive strength between the copper surface and the insulating layer (build-up layer, etc.). The coupling treatment is performed after the reduction treatment or the corrosion inhibition treatment. More preferably, it is performed later. Thereby, adhesiveness can be improved. The coupling treatment liquid used for the coupling treatment includes solvents such as water, alcohol, ketones, coupling agents such as silane coupling agents, aluminum coupling agents, titanium coupling agents, and zirconium. It can be obtained by adding a system coupling agent or two or more of these coupling agents. Among them, it is preferable to use a silane coupling agent as the coupling agent. Examples of the silane coupling agent include functional groups such as an epoxy group, an amino group, a mercapto group, an imidazole group, a vinyl group, and a methacryl group. More preferably, it is in the molecule. Further, in order to promote hydrolysis of the coupling agent, a small amount of acid such as acetic acid or hydrochloric acid may be added to the coupling treatment liquid.

  Further, the content of the coupling agent is preferably 0.01% by mass to 5% by mass, and more preferably 0.1% by mass to 1.0% by mass with respect to the coupling agent treatment liquid. preferable.

  Moreover, it is preferable to perform the process by a coupling process liquid by methods, such as immersing the copper used as a process target in the said coupling process liquid, or spray-spraying or apply | coating a coupling process liquid with respect to copper. Moreover, when copper treated with the coupling treatment liquid is dried by natural drying, heat drying, or vacuum drying, it is preferable to perform water washing or ultrasonic washing before drying depending on the type of coupling agent used. Moreover, it is preferable to determine suitably processing conditions, such as liquid temperature and processing time, according to the kind and density | concentration of a coupling agent, and it is not specifically limited.

(Corrosion inhibiting treatment liquid and treatment using it)
After the oxidation treatment, a corrosion inhibition treatment is preferably performed to suppress copper corrosion, and the corrosion inhibition treatment is preferably performed after the reduction treatment or the coupling treatment. Although it does not specifically limit as a corrosion suppression processing liquid used for a corrosion suppression process, For example, at least 1 or more types of sulfur containing organic compounds or nitrogen containing organic compounds were mix | blended as a corrosion inhibitor with solvents, such as water and an organic solvent. Preferably, it is a sulfur atom-containing organic compound such as a mercapto group, sulfide group, or disulfide group, or at least one nitrogen-containing organic compound containing —N═ or N═N or —NH ₂ in the molecule. What was mix | blended above is more preferable. Moreover, you may use what added the said corrosion inhibitor to the said oxidation treatment liquid or a coupling treatment liquid.

More specifically, the sulfur-containing organic compound is, for example, a general formula HS— (CH ₂ ) _n —R (wherein, n is an integer from 1 to 23, R is a monovalent organic group, hydrogen Or a halogen atom, preferably R is a substituted or unsubstituted amino group, an amide group, a carboxyl group, a carbonyl group, a hydroxyl group, an alkyl group having 1 to 18 carbon atoms, an alkoxy group having 1 to 8 carbon atoms, An acyloxy group, a haloalkyl group, a halogen atom, a hydrogen group, a thioalkyl group, a thiol group, an optionally substituted phenyl group, a biphenyl group, a naphthyl group, a heterocyclic ring, etc., and n is an integer from 4 to 15 More preferably, R is an amino group, an amide group, a carboxyl group, a carbonyl group, or a hydroxyl group, and n is an integer of 6 to 12. Aliphatic thiols, thiazoles or derivatives thereof (2-aminothiazole, 2-aminothiazole-4-carboxylic acid, aminothiophene, benzothiazole, 2-mercaptobenzothiazole, 2-aminobenzothiazole, 2-amino-4-methyl Benzothiazole, 2-benzothiazolol, 2,3-dihydroimidazo [2,1-b] benzothiazol-6-amine, ethyl 2- (2-aminothiazol-4-yl) -2-hydroxyiminoacetate, 2-methylbenzothiazole, 2-phenylbenzothiazole, 2-amino-4-methylthiazole, etc.), thiadiazole derivatives (1,2,3-thiadiazole, 1,2,4-thiadiazole, 1,2,5-thiadiazole, 1,3,4-thiadiazole, 2-amino-5-ethyl-1 , 3,4-thiadiazole, 5-amino-1,3,4-thiadiazole-2-thiol, 2,5-mercapto-1,3,4-thiadiazole, 3-methylmercapto-5-mercapto-1,2, 4-thiadiazole, 2-amino-1,3,4-thiadiazole, 2- (ethylamino) -1,3,4-thiadiazole, 2-amino-5-ethylthio-1,3,4-thiadiazole, etc.), mercapto Benzoic acid, mercaptonaphthol, mercaptophenol, 4-mercaptobiphenyl, mercaptoacetic acid, mercaptosuccinic acid, 3-mercaptopropionic acid, thiouracil, 3-thiourazole, 2-thiouramil, 4-thiouramil, 2-mercaptoquinoline, thioformic acid, 1 -Thiocoumarin, Thiocumothiazone, Thiocresol, Thiosarici Acid, thiothianuric acid, thionaphthol, thiotolene, thionaphthene, thionaphthene carboxylic acid, thionaphthenequinone, thiobarbituric acid, thiohydroquinone, thiophenol, thiophene, thiophthalide, thiobutene, thiolthione carbonate, thiolutidone, thiol histidine, 3-carboxypropyl disulfide 2-hydroxyethyl disulfide, 2-aminopropionic acid, dithiodiglycolic acid, D-cysteine, di-t-butyl disulfide, thiocyan, thiocyanic acid and the like are preferable.

  More specifically, examples of the nitrogen-containing organic compound include triazole derivatives (1H-1,2,3-triazole, 2H-1,2,3-triazole, 1H-1,2,4-triazole, 4H-1,2,4-triazole, benzotriazole, 1-aminobenzotriazole, 3-amino-5-mercapto-1,2,4-triazole, 3-amino-1H-1,2,4-triazole, 3 , 5-diamino-1,2,4-triazole, 3-oxy-1,2,4-triazole, aminourazole, etc.), tetrazole derivatives (tetrazolyl, tetrazolylhydrazine, 1H-1,2,3,4) -Tetrazole, 2H-1,2,3,4-tetrazole, 5-amino-1H-tetrazole, 1-ethyl-1,4-dihydroxy-5H-tetra -5-one, 5-mercapto-1-methyltetrazole, tetrazole mercaptan, etc.), oxazole derivatives (oxazole, oxazolyl, oxazoline, benzoxazole, 3-amino-5-methylisoxazole, 2-mercaptobenzoxazole, 2 -Aminooxazoline, 2-aminobenzoxazole, etc.), oxadiazole derivatives (1,2,3-oxadiazole, 1,2,4-oxadiazole, 1,2,5-oxadiazole, 1,3 , 4-oxadiazole, 1,2,4-oxadiazolone-5, 1,3,4-oxadiazolone-5, etc.), oxatriazole derivatives (1,2,3,4-oxatriazole, 1, 2,3,5-oxatriazole, etc.), purine derivatives (purine, 2-amino-6-hydroxy) -8-mercaptopurine, 2-amino-6-methylmercaptopurine, 2-mercaptoadenine, mercaptopoxanthine, mercaptopurine, uric acid, guanine, adenine, xanthine, theophylline, theobromine, caffeine, etc.), imidazole derivatives (imidazole, Benzimidazole, 2-mercaptobenzimidazole, 4-amino-5-imidazolecarboxylic acid amide, histidine, etc.), indazole derivatives (indazole, 3-indazolone, indazolol, etc.), pyridine derivatives (2-mercaptopyridine, aminopyridine, etc.), Pyrimidine derivatives (2-mercaptopyrimidine, 2-aminopyrimidine, 4-aminopyrimidine, 2-amino-4,6-dihydroxypyrimidine, 4-amino-6-hydroxy-2-merca Putopyrimidine, 2-amino-4-hydroxy-6-methylpyrimidine, 4-amino-6-hydroxy-2-methylpyrimidine, 4-amino-6-hydroxypyrazolo [3,4-d] pyrimidine, 4-amino- 6-mercaptopyrazolo [3,4-d] pyrimidine, 2-hydroxypyrimidine, 4-mercapto-1H-pyrazolo [3,4-d] pyrimidine, 4-amino-2,6-dihydroxypyrimidine, 2,4- Diamino-6-hydroxypyrimidine, 2,4,6-triaminopyrimidine, etc.), thiourea derivatives (thiourea, ethylenethiourea, 2-thiobarbituric acid, etc.), amino acids (glycine, alanine, tryptophan, proline, oxyproline) Etc.), 1,3,4-thiooxadiazolone-5, thiocoumazone, 2-thiocoumarin, thio Caffeine, thiohydantoin, thiopyrine, γ-thiopyrine, guanazine, guanazole, guanamine, oxazine, oxadiazine, melamine, 2,4,6-triaminophenol, triaminobenzene, aminoindole, aminoquinoline, aminothiophenol, aminopyrazole, etc. Is preferred.

  The type of the organic solvent is not particularly limited, but alcohols such as methanol, ethanol, n-propyl alcohol, and n-butyl alcohol, di-n-propyl ether, di-n-butyl ether, diallyl ether, and the like. Ethers, aliphatic hydrocarbons such as hexane, heptane, octane, and nonane, and aromatic hydrocarbons such as benzene, toluene, and phenol are preferably used, and one or more of these solvents may be used in combination. preferable.

  Moreover, it is preferable that the corrosion inhibitor density | concentration of the said corrosion inhibition process liquid is 0.1-5000 ppm, It is more preferable that it is 0.5-3000 ppm, It is especially preferable that it is 1-1000 ppm. When the concentration of the corrosion inhibitor is less than 0.1 ppm, the ion migration suppressing effect and the adhesive strength between the copper surface and the insulating layer tend to decrease. On the other hand, when the concentration of the corrosion inhibitor exceeds 5000 ppm, an ion migration suppressing effect can be obtained, but the adhesive strength between the copper surface and the insulating layer tends to decrease.

  Further, the treatment with the corrosion inhibiting treatment liquid is preferably performed by a method such as immersing the copper to be treated in the corrosion inhibiting treatment liquid, spraying or applying the corrosion inhibiting treatment liquid to the copper, and the like. The treatment time and the liquid temperature with the inhibition treatment liquid are not particularly limited, but it is preferable to appropriately determine according to the type and concentration of the corrosion inhibitor. Moreover, it is preferable to perform ultrasonic cleaning after the treatment.

(Wiring board and semiconductor package)
The wiring board of this invention has the wiring roughened by applying the copper surface treatment method using the copper surface treatment liquid set of this invention. Hereinafter, as an embodiment of the wiring substrate of the present invention, a semiconductor chip mounting substrate is taken as an example, and its general structure, a method of manufacturing a semiconductor chip mounting substrate by applying the copper surface treatment method of the present invention The semiconductor package of the present invention using the substrate will be described with reference to the drawings, but the present invention is not limited to these descriptions.

(Semiconductor chip mounting board)
FIG. 1 is a schematic cross-sectional view of an embodiment of a semiconductor chip mounting substrate of the present invention. Here, an embodiment in which two build-up layers (interlayer insulating layers) are formed on one side will be described, but the build-up layer may be formed on both sides as required (see FIG. 8).

  In the semiconductor chip mounting substrate shown in FIG. 1, the first wiring 106a including the semiconductor chip connection terminal and the first interlayer connection terminal 101 is formed on the side on which the semiconductor chip is mounted on the core substrate 100 which is an insulating layer. The second wiring 106 b including the second interlayer connection terminal 103 is formed on the other side of the core substrate 100, and the second interlayer connection terminal 103 is formed on the core substrate 100. It is electrically connected to the first interlayer connection terminal 101 via an interlayer connection IVH (interstitial via hole) 102. Also, a buildup layer 104 is formed on the second wiring 106b, and a third wiring 106c including a third interlayer connection terminal is formed on the buildup layer 104, and the third interlayer The connection terminal is electrically connected to the second interlayer connection terminal 103 via the second interlayer connection IVH 108. Further, an external connection terminal 107 connected to the motherboard is formed on the outermost buildup layer, and the external connection terminal 107 and the third interlayer connection terminal are electrically connected via the third interlayer connection IVH 105. It is connected. Note that the shape of the wiring and the arrangement of the connection terminals are not particularly limited, and can be appropriately designed in order to manufacture a semiconductor chip to be mounted and a target semiconductor package. Further, the semiconductor chip connection terminal and the first interlayer connection terminal can be shared. Furthermore, an insulating coating 109 such as a solder resist can be provided on the outermost buildup layer as necessary.

(Core substrate)
The material of the core substrate is not particularly limited as long as it has a certain level of strength and insulation, but an organic substrate, a ceramic substrate, a silicon substrate, a glass substrate, or the like is preferably used. In consideration of the thermal expansion coefficient and insulation, it is preferable to use a ceramic substrate or a glass substrate. As the glass substrate, a non-photosensitive glass substrate or a photosensitive glass substrate can be used. As the non-photosensitive glass substrate, for example, soda lime glass (component example: SiO ₂ 65 to 75 wt%, Al ₂ O ₃ 0.5-4 wt%, CaO 5-15 wt%, MgO 0.5-4 wt%, Na ₂ O 10-20 wt%), borosilicate glass (component example: SiO ₂ 65-80 wt%, B ₂ O _{3 5~25wt%, Al 2 O 3} 1~5wt%, CaO 5~8wt%, MgO 0.5~2wt%, Na 2 O 6~14wt%, K 2 O 1~6wt%) and the like are preferable. As the photosensitive glass, for example, those containing gold ions and silver ions as a photosensitive agent into Li _{2 O-SiO} 2 based crystallized glass is preferable.

  As the organic substrate, it is preferable to use a substrate or a resin film obtained by laminating a material (prepreg) obtained by impregnating a glass cloth with a resin. As the resin to be used, a thermosetting resin, a thermoplastic resin, or a mixed resin thereof is preferable, and a thermosetting organic insulating material is more preferable. Thermosetting resins include phenolic resin, urea resin, melamine resin, alkyd resin, acrylic resin, unsaturated polyester resin, diallyl phthalate resin, epoxy resin, polybenzimidazole resin, polyamide resin, polyamideimide resin, silicon resin, cyclohexane Resin synthesized from pentadiene, resin containing tris (2-hydroxyethyl) isocyanurate, resin synthesized from aromatic nitrile, trimerized aromatic dicyanamide resin, resin containing triallyl trimetallate, furan resin, ketone resin, Xylene resins, thermosetting resins containing condensed polycyclic aromatics, benzocyclobutene resins, and the like are preferable. As the thermoplastic resin, polyimide resin, polyphenylene oxide resin, polyphenylene sulfide resin, aramid resin, liquid crystal polymer, and the like are preferable. Moreover, it is more preferable to add a filler to these resins. Examples of the filler include silica, talc, aluminum hydroxide, aluminum borate, aluminum nitride, and alumina.

  Further, the thickness of the core substrate is not particularly limited, but is preferably 100 to 800 μm from the viewpoint of IVH formation, and more preferably 150 to 500 μm. If the thickness is less than 100 μm, it is difficult to obtain the rigidity of the substrate, and warping and twisting tend to occur. If the thickness exceeds 800 μm, the entire substrate tends to be thick and hole processing tends to be difficult.

(Build-up layer)
The interlayer insulating layer (build-up layer) 104 may be a layer made of an insulating material, and the material is not particularly limited. As the insulating material, a thermosetting resin, a thermoplastic resin, or a mixed resin thereof is preferable, and a material mainly composed of a thermosetting organic insulating material is more preferable. Thermosetting resins include phenolic resin, urea resin, melamine resin, alkyd resin, acrylic resin, unsaturated polyester resin, diallyl phthalate resin, epoxy resin, polybenzimidazole resin, polyamide resin, polyamideimide resin, silicon resin, cyclohexane Resin synthesized from pentadiene, resin containing tris (2-hydroxyethyl) isocyanurate, resin synthesized from aromatic nitrile, trimerized aromatic dicyanamide resin, resin containing triallyl trimetallate, furan resin, ketone resin, It is preferable to use a xylene resin, a thermosetting resin containing a condensed polycyclic aromatic, a benzocyclobutene resin, or the like. As the thermoplastic resin, polyimide resin, polyphenylene oxide resin, polyphenylene sulfide resin, aramid resin, liquid crystal polymer, and the like are preferable. In addition, it is preferable to add a filler to the insulating material. Examples of the filler include silica, talc, aluminum hydroxide, aluminum borate, aluminum nitride, and alumina.

(Coefficient of thermal expansion)
The thermal expansion coefficient of the core substrate 100 is not particularly limited, but is preferably approximated to the thermal expansion coefficient of the semiconductor chip and approximate to the thermal expansion coefficient of the buildup layer. The semiconductor chip, the core substrate, It is more preferable that α1 ≦ α2 ≦ α3, where α1, α2, and α3 (ppm / ° C.) are the thermal expansion coefficients of the buildup layers.

  Specifically, the thermal expansion coefficient α2 of the core substrate is preferably 7 to 13 ppm / ° C, and more preferably 9 to 11 ppm / ° C. Further, the thermal expansion coefficient α3 of the buildup layer is preferably 10 to 40 ppm / ° C, more preferably 10 to 20 ppm / ° C, and particularly preferably 11 to 17 ppm / ° C.

(Young's modulus)
The Young's modulus of the buildup layer is preferably 1 to 5 GPa in terms of stress relaxation against thermal stress. The Young's modulus and thermal expansion coefficient of the buildup layer can be controlled by the amount of filler added, and preferably the thermal expansion coefficient of the buildup layer is 10 to 40 ppm / ° C. and the Young's modulus is 1 to 5 GPa. Adjust to.

(Wiring layout and terminal shape)
The arrangement of the wiring is not particularly limited, but as shown in FIG. 5 and FIG. 6 (inner layer wiring, interlayer connection terminals, etc. are omitted), at least on the side where the semiconductor chip is mounted, the semiconductor chip connection terminal 16 (wire Bond terminals, etc.) are arranged, and on the opposite side, external connection terminals (locations where solder balls or the like are mounted) electrically connected to the mother board, developed wirings connecting them, interlayer connection terminals, etc. are arranged. 5 shows a fan-in type semiconductor chip mounting board in which the external connection terminals 19 are formed inside the semiconductor chip connection terminals 16. FIG. 6 shows the external connection terminals 19 outside the semiconductor chip connection terminals 16. Although a fan-out type semiconductor chip mounting board formed with the above, a type in which these are combined may be used. 5 and 6, reference numeral 13 denotes a semiconductor package area, 14 denotes a die bond film adhesion area (flip chip type), 15 denotes a semiconductor chip mounting area (flip chip type), and 17 denotes a die bond film adhesion area (wire bond type). , 18 is a semiconductor chip mounting area (wire bond type), and 20 is a developed wiring.

  The shape of the semiconductor chip connection terminal 16 is not particularly limited as long as wire bond connection or flip chip connection is possible. In addition, wire-bond connection or flip-chip connection is possible for both fan-out and fan-in types. Further, if necessary, a dummy pattern 21 (see FIG. 6) that is not electrically connected to the semiconductor chip may be formed. The shape and arrangement of the dummy pattern are not particularly limited, but it is preferable to arrange the dummy pattern uniformly in the semiconductor chip mounting region. As a result, voids are less likely to occur when a semiconductor chip is mounted with a die bond adhesive, and reliability can be improved.

(Shape of semiconductor chip mounting substrate)
The shape of the semiconductor chip mounting substrate is not particularly limited, but is preferably a frame shape as shown in FIG. By making the shape of the semiconductor chip mounting substrate into a frame shape, the semiconductor package can be assembled efficiently. Hereinafter, a preferred embodiment of the frame-shaped semiconductor chip mounting substrate will be described in detail with reference to FIG.

  The frame-shaped semiconductor chip mounting substrate shown in FIG. 7 has a plurality of semiconductor package regions 13 (parts to be a single semiconductor package) arranged in rows and columns in a grid at equal intervals. In addition, a plurality of such blocks are arranged in rows and columns at regular intervals in a grid pattern. In FIG. 7, the minimum two blocks necessary for explanation are shown, and the other blocks are omitted. Here, the width of the space between the semiconductor package regions is preferably 50 to 500 μm, and more preferably 100 to 300 μm. Furthermore, it is most preferable that the blade width of the dicer used when the semiconductor package is cut later is made the same.

  By disposing the semiconductor package region as described above, the semiconductor chip mounting substrate can be effectively used. Further, a positioning mark 11 or the like is preferably formed on the end portion of the semiconductor chip mounting substrate, and more preferably a pin hole by a through hole. The shape and arrangement of the pin holes may be selected so as to match the forming method and the semiconductor package assembly apparatus.

  Furthermore, it is preferable that a reinforcing pattern 24 is formed outside the space between the semiconductor package regions and the block. The reinforcing pattern may be prepared separately and bonded to the semiconductor chip mounting substrate, but is preferably a metal pattern formed at the same time as the wiring formed in the semiconductor package region. It is more preferable that the same plating such as nickel or gold is applied or an insulating coating is applied. When the reinforcing pattern is such a metal, it can also be used as a plating lead for electrolytic plating. Further, it is preferable that a cutting position alignment mark 25 for cutting with a dicer is formed outside the block.

(Manufacturing method of semiconductor chip mounting substrate)
Hereinafter, an embodiment of a method for manufacturing a semiconductor chip mounting substrate that is preferable for obtaining a highly reliable semiconductor package will be described step by step with reference to schematic cross-sectional views of FIGS. However, the order of the manufacturing process is not particularly limited as long as it does not depart from the object of the present invention.

(Process a)
(Step a) is a step of forming the first wiring 106a on the core substrate 100 as shown in FIG. Examples of the wiring formation method include a subtractive method, an additive method, a semi-additive method, and the like, and it is preferable to select according to the purpose. Note that since the first wiring 106a includes the first interlayer connection terminal 101 and the semiconductor chip connection terminal (portion electrically connected to the semiconductor chip), a semi-additive method advantageous for forming fine wiring is used. It is preferable to use it.

(Subtractive method)
In the subtractive method, a copper layer is formed on the core substrate surface or the build-up layer, an etching resist is formed in a portion to be a wiring on the copper layer, and the copper foil exposed from the etching resist is removed by etching, and wiring is performed. It is a method of forming. This copper layer can be formed, for example, by forming a thin film copper by sputtering, vapor deposition, plating or the like and then performing a method of performing electrolytic copper plating or a method of attaching a copper foil until a desired thickness is obtained. The etching resist pattern is, for example, a photomask that screen-prints resist ink, or laminates a negative photosensitive dry film for etching resist on copper foil, and transmits light in the shape of wiring on it. Can be formed by removing the portions that have not been exposed with a developing solution. Also, as an etchant used for etching, a chemical etchant used for a normal wiring board such as a solution of cupric chloride and hydrochloric acid, a ferric chloride solution, a solution of sulfuric acid and hydrogen peroxide, an ammonium persulfate solution, or the like should be used. Can do. Moreover, it is preferable to use the etching resist material which can be used for a normal wiring board as an etching resist.

(Additive method)
The additive method is a method of forming a wiring by plating only a necessary portion on a core substrate or a buildup layer. More specifically, for example, after depositing an electroless plating catalyst on the core substrate, a plating resist is formed on a surface portion where plating is not performed, and immersed in an electroless copper plating solution. Electroless plating is performed only on uncovered portions to form wiring.

(Semi-additive method)
In the semi-additive method, a thin copper layer (seed layer) is formed on the core substrate surface or build-up layer, then the necessary wiring is formed by electrolytic copper plating, and then the unnecessary thin copper layer is removed by etching. This method is optimal as a process for forming fine wiring with L / S = 35 μm / 35 μm or less. More specifically, for example, after forming a seed layer (thin film copper) on the core substrate surface by a method such as vapor deposition, plating, sputtering or bonding a copper foil, a plating resist is formed on the seed layer, After forming necessary wiring by electrolytic copper plating and removing the plating resist, an unnecessary thin copper layer is removed by an etching method to form wiring.

  When the core layer or build-up layer has an adhesive function, it is desirable to form the seed layer by bonding copper foil by pressing or laminating, but it is very difficult to directly bond thin copper foil. Therefore, the seed layer is usually formed by laminating a thick metal foil and then thinning it by etching or the like, or peeling the carrier layer after laminating the copper foil with carrier. Specifically, for example, a method of using a three-layer copper foil of carrier copper / nickel / thin film copper, removing carrier copper with an alkaline etching solution, removing nickel with a nickel etching solution, and using thin film copper as a seed layer and a thickness of 9 to 9 An example is a method in which an 18 μm copper foil is pasted and uniformly thinned to a thickness of 5 μm or less by etching to form a seed layer. Moreover, as a copper foil with a carrier used for the latter formation method, for example, a peelable copper foil using aluminum, copper, an insulating material or the like as a carrier can be exemplified, which is preferable when a seed layer having a thickness of 5 μm or less is formed. .

  In addition, the seed layer is preferably formed by sputtering, for example, by forming a base metal and a copper layer having a thickness of 200 to 500 nm by sputtering on the surface of the core substrate or the buildup layer. As a sputtering apparatus used for forming the copper layer, two-pole sputtering, three-pole sputtering, four-pole sputtering, magnetron sputtering, mirrortron sputtering, or the like can be used. In order to ensure adhesion, the base metal is formed by sputtering a metal such as Cr, Ni, Co, Pd, Zr, an alloy of Ni and Cr, or an alloy of Ni and Cu so as to have a thickness of 5 to 50 nm. It is preferable to form it.

  Moreover, the formation of the seed layer by the above plating includes, for example, a method of forming plated copper having a thickness of 0.5 to 3 μm by electroless copper plating on the surface of the core substrate or the buildup layer.

(Process b)
In step (b), as shown in FIG. 2B, a first interlayer connection IVH 102 (via hole) for connecting the first interlayer connection terminal 101 and a second wiring to be described later. Is a step of forming.

Via holes are provided with holes for connection in the core substrate or build-up layer, and then subjected to desmear treatment as necessary to electrically connect the layers, and then the holes are formed with conductive paste, plating, etc. And can be formed by filling and conducting. As the hole processing method, mechanical processing such as punching and drilling, laser processing such as CO ₂ laser, YAG laser, and excimer laser, chemical etching processing using a chemical solution, dry etching method using plasma, and the like can be applied. In the case where the core substrate 100 is a non-photosensitive base material, it is preferably formed by irradiating a laser beam such as a CO ₂ laser, a YAG laser, or an excimer laser to a portion that becomes a via hole. From the viewpoint of productivity and hole quality, it is preferable to use a CO ₂ laser. When the IVH diameter is less than 30 μm, a YAG laser capable of focusing the laser beam is suitable.

  When the core substrate 100 is a photosensitive base material, a region other than a portion that becomes a via hole is masked, irradiated with ultraviolet light, and then a hole that becomes a via hole is formed by heat treatment and etching. In addition, when the core substrate 100 is a base material that can be chemically etched with a chemical solution such as an organic solvent, it is preferable to form a hole to be a via hole by chemical etching. As described above, a hole to be a via hole is formed, and the hole is made conductive by a conductive paste or plating to form a via hole.

  Further, as a method for forming a via hole in the buildup layer, a method in which a conductive layer is previously formed on the buildup layer with a conductive paste or plating, and this is laminated on the core substrate by pressing or the like is also preferable.

(Process c)
(Step c) is a step of forming the second wiring 106b on the surface of the core substrate 100 opposite to the surface on which the first wiring 106a is formed, as shown in FIG. 2 (c). The second wiring 106b can be formed in the same manner as the first wiring in the above (step a). Note that the second wiring 106b includes the second interlayer connection terminal 103, and a semi-additive method is preferably used as a method for forming the fine wiring.

(Process d)
(Step d) is a step of forming a buildup layer (interlayer insulating layer) 104 on the surface on which the second wiring 106b is formed, as shown in FIG. 2 (d).

  Here, first, pretreatment such as degreasing and acid cleaning is preferably performed on the surface of the second wiring 106b. Next, the surface of the second wiring is roughened by the copper surface treatment method of the present invention. That is, after the noble metal treatment liquid is used to discretely form a noble metal on the copper wiring surface (on the second wiring 106b), the copper wiring surface is oxidized using the oxidation treatment liquid. To process. Thereafter, reduction treatment is preferably performed as necessary. Further, it is more preferable to perform at least one of coupling treatment and corrosion inhibition treatment. In addition, it is efficient and preferable that the processing here is performed by a horizontal transport method in which the substrate is transported and processed while being held horizontally.

  Next, the buildup layer 104 is laminated on the surface of the core substrate 100 and the surface of the second wiring 106b. The build-up layer 104 can be laminated by printing or spin coating when the insulating material is varnished, or by lamination or pressing when the insulating material is film-like. When the insulating material includes a thermosetting material, it is preferable that the insulating material is further heat-cured.

(Process e)
(Step e) is a step of forming a second interlayer connection IVH (via hole) 108 in the build-up layer 104 as shown in FIG. 2 (e). This is preferably performed in the same manner as the first interlayer connection IVH 102 in (Step b).

(Process f)
(Step f) is a step of forming the third wiring 106c on the buildup layer on which the second IVH 108 is formed, as shown in FIG. 2 (f). The third wiring 106c can be formed in the same manner as the first wiring 106a in the above (step a).

  Further, by repeating steps (d) to (f), two or more buildup layers 104 may be formed as shown in FIG. In this case, the wiring including the third interlayer connection IVH 105 formed in the outermost buildup layer becomes the external connection terminal 107 for electrical connection with the mother board or another semiconductor package. The external connection terminals can be sequentially subjected to nickel and gold plating, and may be nickel, palladium and gold plating as necessary. For the plating, either electroless plating or electrolytic plating may be used, but electroless plating is preferable particularly for a substrate having fine wiring or high-density wiring.

(Process g)
(Step g) is a step of forming an insulating coating 109 for protecting wirings other than the external connection terminals as shown in FIG. 2 (g). As the insulating coating material, a thermosetting or ultraviolet curable solder resist can be used, but an ultraviolet curable material capable of finishing the resist shape with high accuracy is preferable. The insulating coating pattern can be formed by printing as long as it is a varnish-like material, but it is preferable to use a photosensitive solder resist, a coverlay film, or a film-like resist in order to ensure more accuracy. . As a material, an epoxy-based material, a polyimide-based material, an epoxy acrylate-based material, or a fluorene-based material can be used. In addition, since such insulation coating has shrinkage | contraction at the time of hardening, if it forms only on one side, it will produce a big curvature in a board | substrate. Therefore, an insulating coating can be formed on both surfaces of the semiconductor chip mounting substrate as necessary. Furthermore, since the warpage varies depending on the thickness of the insulating coating, it is more preferable to adjust the thicknesses so that no warpage occurs when the insulating coating is formed on both surfaces. In this case, it is preferable to conduct preliminary examination and determine the thickness of the insulating coating on both sides. In order to obtain a thin semiconductor package, the thickness of the insulating coating is preferably 50 μm or less, and more preferably 30 μm or less.

(Semiconductor package)
The semiconductor package of the present invention is obtained by mounting a semiconductor chip on the wiring substrate (substrate for mounting a semiconductor chip) of the present invention. FIG. 3 shows a schematic cross-sectional view of one embodiment (flip chip type semiconductor package) of the semiconductor package of the present invention. In this semiconductor package, the semiconductor chip 111 is mounted at a predetermined position of the semiconductor chip mounting substrate of FIG. 2G, and solder balls 114 for electrical connection with the mother board are formed on the external connection terminals 107. The semiconductor chip and the semiconductor chip connection terminal are flip-chip connected by connection bumps 112. The space between the semiconductor chip and the semiconductor chip mounting substrate is sealed with an underfill material 113. The thermal expansion coefficient of the underfill material is preferably close to the thermal expansion coefficient of the semiconductor chip and the core substrate 100, but is not limited thereto. More preferably, (thermal expansion coefficient of the semiconductor chip) ≦ (thermal expansion coefficient of the underfill material) ≦ (thermal expansion coefficient of the core substrate). In addition, the mounting of the semiconductor chip can be performed using an anisotropic conductive film (ACF) or an adhesive film (NCF) that does not contain conductive particles. In this case, there is no need to seal with an underfill material. ,preferable. Furthermore, if ultrasonic waves are used together when mounting a semiconductor chip, electrical connection can be made at a low temperature and in a short time. The solder balls may be eutectic solder or Pb free solder. As a method for fixing the solder ball to the external connection terminal 107, for example, an N ₂ reflow apparatus or the like can be used. However, the method is not limited to this.

  FIG. 4 shows a cross-sectional view of an embodiment of a wire bond type semiconductor package. Although a general die bond paste can be used for mounting the semiconductor chip, it is more preferable to use a die bond film 117. Electrical connection between the semiconductor chip and the semiconductor chip connection terminal is performed by wire bonding using a gold wire 115. Further, the semiconductor chip can be sealed by transfer molding using a semiconductor sealing resin 116. In this case, the sealing region may seal only a necessary portion, for example, only the face surface of the semiconductor chip, but it is desirable to seal the entire semiconductor package region as shown in FIG. This is a particularly effective method for obtaining individual semiconductor packages in a semiconductor chip mounting substrate in which a plurality of semiconductor package regions are arranged in rows and columns by simultaneously cutting the substrate and the sealing resin with a dicer or the like.

  Hereinafter, the present invention will be described in detail based on examples, but the present invention is not limited thereto.

<Reliability of semiconductor packages>
In order to evaluate the reliability of the semiconductor package produced by applying the copper surface treatment of the present invention, a semiconductor package sample was produced as follows (see FIG. 2).

(Production of semiconductor package)
Example 1
(Process a)
A soda glass substrate (thermal expansion coefficient 11 ppm / ° C.) having a thickness of 0.4 mm is prepared as the core substrate 100 shown in FIG. 2, and a thin film copper having a thickness of 200 nm is formed on one surface by sputtering. Plating was performed to form a 10 μm thick copper layer. In addition, sputtering was performed on condition 1 shown below using the apparatus model number MLH-6315 by Nippon Vacuum Technology Co., Ltd. Thereafter, an etching resist is formed in a portion to be the first wiring 106a, and etching is performed using an etching solution containing cupric chloride 130 g / L and hydrochloric acid 100 g / L, and the etching resist is removed. A wiring 106a (including the first interlayer connection terminal 101 and the semiconductor chip connection terminal) was formed.

Condition 1
Current: 3.5A
Voltage: 500V
Argon flow rate: 35 SCCM
Pressure: 5 × 10 ⁻³ Torr (4.9 × 10 ⁻² Pa)
Deposition rate: 5 nm / second

(Process b)
A hole having a hole diameter of 50 μm was formed with a laser until reaching the first interlayer connection terminal 101 from the surface opposite to the first wiring 106a of the glass substrate on which the first wiring 106a was formed. A YAG laser LAVIA-UV2000 (manufactured by Sumitomo Heavy Industries, Ltd., trade name) was used as the laser, and a hole having IVH was formed under the conditions of a frequency of 4 kHz, a shot number of 50, and a mask diameter of 0.4 mm. Then, desmear treatment in the hole was performed.

  Thereafter, the hole is filled with conductive paste MP-200V (trade name, manufactured by Hitachi Chemical Co., Ltd.), cured at 160 ° C. for 30 minutes, and electrically connected to the first interlayer connection terminal 101 on the glass substrate. The connected first interlayer connection IVH102 (via hole) was formed.

(Process c)
A copper layer having a thickness of 10 μm is formed on the surface of the glass substrate opposite to the surface on which the first wiring 106a is formed in the same manner as in the above (step a), and this is then etched (step b). The second wiring 106b (including the second interlayer connection terminal 103) electrically connected to the first interlayer connection IVH102 (first via hole) formed in (1) was formed.

(Process d)
The surface of the second wiring 106b formed in (step c) is pretreated according to the following (step d-1), and is treated (roughened) according to (step d-2) and (step d-3). In accordance with the following (step d-4), a buildup layer was formed on the surface on the second wiring side.

(Step d-1)
The surface of the second wiring 106b was degreased 118 using an acidic degreasing solution Z-200 (trade name, manufactured by World Metal Co., Ltd.) adjusted to 200 ml / L and a liquid temperature of 50 ° C., and then the liquid temperature of 50 ° C. It was washed with hot water by immersing in water for 2 minutes, and further washed with water for 1 minute. Subsequently, it was immersed in a 3.6 N sulfuric acid aqueous solution for 1 minute and washed with water for 1 minute.

(Step d-2)
The second wiring 106b having undergone the above pretreatment step is immersed at 50 ° C. for 1 minute in a precious metal treatment solution (pH 2.5) containing 0.2 g / L of palladium chloride, 15 ml / L of hydrochloric acid, and 20 g / L of ammonium chloride. Then, 1.0 μmol / dm ^{2 of} palladium, which is a metal nobler than copper, was formed on the surface of the second wiring 106b and washed with water for 1 minute. In addition, sodium hydroxide was used for pH adjustment of the noble metal treatment solution.

(Step d-3)
After the noble metal treatment step, the surface of the second wiring 106b is placed at 50 ° C. in an alkaline oxidation treatment solution containing trisodium phosphate 10 g / L, potassium hydroxide 25 g / L, and sodium chlorite 15 g / L. By dipping for 3 minutes, a 0.07 mg / cm ² copper oxide crystal was formed on the surface of the second wiring 106b. Thereafter, it was washed with water for 5 minutes, immersed in the reduction treatment solution HIST-100D (trade name, manufactured by Hitachi Chemical Co., Ltd.) for 3 minutes at 40 ° C., further washed with water for 10 minutes, and dried at 85 ° C. for 30 minutes.

(Step d-4)
Next, an interlayer insulating layer (build-up layer) 104 was formed on the surface on the second wiring 106b side as follows. That is, an insulating varnish of a cyanate ester-based resin composition is applied to the surface on the second wiring 106b side by a spin coating method at a condition of 1500 rpm to form a resin layer having a thickness of 20 μm, and then from room temperature (25 ° C.). It heated to 230 degreeC with the temperature increase rate of 6 degreeC / min, and was thermoset by hold | maintaining at 230 degreeC for 80 minutes, and formed the 15 micrometer buildup layer.

(Process e)
A hole to be an IVH having a hole diameter of 50 μm was formed by a laser until reaching the second interlayer connection terminal 103 from the surface of the buildup layer 104 formed in the above (Step d-4). A YAG laser LAVIA-UV2000 (manufactured by Sumitomo Heavy Industries, Ltd., trade name) was used as the laser, and a hole to be IVH was formed under the conditions of a frequency of 4 kHz, a shot number of 20 and a mask diameter of 0.4 mm. Thereafter, desmear treatment was performed. The desmear treatment method was carried out by immersing in a swelling liquid circular deposit 4125 (Rohm and Haas Electronic Materials Co., Ltd., product name) at 80 ° C. for 3 minutes, washing with water for 3 minutes, and then desmearing liquid deposit MLB promoter 213 (ROHM).・ Soaked in And Haas Electronic Materials Co., Ltd., product name) at 80 ° C. for 5 minutes, washed with water for 3 minutes, and further reduced liquid circulation deposit MLB216-4 (Roam And Haas Electronic Materials Co., Ltd., product name) It was immersed for 3 minutes at 40 ° C, washed with water for 3 minutes, and then dried at 85 ° C for 30 minutes.

(Process f)
In order to form the third wiring 106c and the second IVH 108 on the buildup layer 104 formed in the above (step d-4), a Ni layer (underlying metal) having a thickness of 20 nm is formed on the buildup layer 104 by sputtering. ) And a thin film copper layer having a thickness of 200 nm is formed on the Ni layer to form a seed layer. Sputtering was performed under the condition 2 shown below using MLH-6315 manufactured by Nippon Vacuum Technology Co., Ltd.

Condition 2
(nickel)
Current: 5.0A
Voltage: 350V
Argon flow rate: 35 SCCM
Pressure: 5 × 10 ⁻³ Torr (4.9 × 10 ⁻² Pa)
Deposition rate: 0.3 nm / sec (thin film copper)
Current: 3.5A
Voltage: 500V
Argon flow rate: 35 SCCM
Pressure: 5 × 10 ⁻³ Torr (4.9 × 10 ⁻² Pa)
Deposition rate: 5 nm / second

Next, a plating resist PMER P-LA900PM (manufactured by Tokyo Ohka Kogyo Co., Ltd., trade name) was applied onto the seed layer (on the thin film copper layer) by a spin coating method to form a plating resist layer having a thickness of 10 μm. Next, the plating resist layer was exposed under the condition of 1000 mJ / cm ² and then immersed in PMER developer P-7G at 23 ° C. for 6 minutes to form a resist pattern of L / S = 10 μm / 10 μm. Thereafter, a copper sulfate plating solution (copper sulfate concentration 70 g / L, sulfuric acid concentration 170 g / L, sodium chloride 0.1 g / L, additive Kaparaside G40 (manufactured by Adtech Japan Co., Ltd.) 20 ml / L, correction agent Kaparaside GS (Adtech Japan) Electrolytic copper plating was performed using 0.3 ml / L) (conditions: current density 2 A / dm ² ) to form a third wiring 106 c having a thickness of about 5 μm. The plating resist was peeled off by immersion for 1 minute at room temperature (25 ° C.) using methyl ethyl ketone. In addition, for quick etching of the seed layer, a 5-fold diluted solution of CPE-700 (manufactured by Mitsubishi Gas Chemical Co., Ltd., trade name) is used for etching removal by immersing and shaking at 30 ° C. for 30 seconds. A wiring pattern was formed.

(Process g)
Thereafter, the steps (d) to (step f) were repeated again to form a further outermost layer wiring including the buildup layer and the external connection terminal 107. Finally, a solder resist 109 is formed, and gold plating is applied to the external connection terminals 107 and the semiconductor chip connection terminals. FIG. 1 (sectional view of one package), FIG. 5 (plan view of one package), and FIG. A semiconductor chip mounting substrate for a fan-in type BGA as shown in (Overall view of semiconductor chip mounting substrate) was produced.

(Process h)
Next, the necessary number of semiconductor chips 111 on which the connection bumps 112 were formed were mounted on the semiconductor chip mounting region of the semiconductor chip mounting substrate obtained above while applying ultrasonic waves using a flip chip bonder. Furthermore, an underfill material 113 is injected from the end of the semiconductor chip into the gap between the semiconductor chip mounting substrate and the semiconductor chip, and primary curing is performed at 80 ° C. for 1 hour and secondary curing at 150 ° C. for 4 hours using an oven. Went. Next, a lead / tin eutectic solder ball 114 having a diameter of 0.45 mm was fused to the external connection terminal 107 using an N ₂ reflow apparatus. Finally, the semiconductor chip mounting substrate was cut with a dicer equipped with a blade having a width of 200 μm to produce 22 semiconductor package samples as shown in FIG.

Example 2
In Example 1 (step d-2), Example 1 and Example 1 were used except that a precious metal treatment solution (pH 2.5) containing 0.2 g / L of palladium chloride, 15 ml / L of hydrochloric acid, and 20 g / L of glycine was used. Similarly, a fan-in type BGA semiconductor chip mounting substrate and a semiconductor package were manufactured.

Example 3
In Example 1 (step d-2), except that a noble metal treatment solution (pH 2.5) containing 0.2 g / L of palladium chloride, 15 ml / L of hydrochloric acid, and 20 g / L of citric acid monohydrate was used. In the same manner as in Example 1, a fan-in type BGA semiconductor chip mounting substrate and a semiconductor package were produced.

Example 4
In Example 1 (step d-2), except that a precious metal treatment solution (pH 2.5) containing palladium chloride 0.2 g / L, hydrochloric acid 15 ml / L, ammonium chloride 20 g / L, and glycine 20 g / L was used. Produced a semiconductor chip mounting substrate and a semiconductor package for a fan-in type BGA in the same manner as in Example 1.

Example 5
A precious metal treatment solution (pH 2.5) containing 0.2 g / L of palladium chloride, 15 ml / L of hydrochloric acid, 20 g / L of glycine, and 20 g / L of citric acid monohydrate in (Step d-2) of Example 1 A fan-in type BGA semiconductor chip mounting substrate and a semiconductor package were produced in the same manner as in Example 1 except that was used.

Example 6
Noble metal treatment including 0.2 g / L of palladium chloride, 15 ml / L of hydrochloric acid, 20 g / L of ammonium chloride, 20 g / L of glycine, and 20 g / L of citric acid monohydrate in (Step d-2) of Example 1 A fan-in type BGA semiconductor chip mounting substrate and a semiconductor package were produced in the same manner as in Example 1 except that the liquid (pH 2.5) was used.

Example 7
Example 1 (Step d-3) in Example 1 except that an alkaline oxidation treatment solution containing trisodium phosphate 10 g / L, potassium hydroxide 25 g / L, and sodium chlorate 15 g / L was used. In the same manner, a fan-in type BGA semiconductor chip mounting substrate and a semiconductor package were produced.

Example 8
Example 1 except that an alkaline oxidation treatment solution containing trisodium phosphate 10 g / L, potassium hydroxide 25 g / L, and ammonium peroxodisulfate 15 g / L was used in (Step d-3) of Example 1. In the same manner, a fan-in type BGA semiconductor chip mounting substrate and a semiconductor package were produced.

Comparative Example 1
The precious metal treatment in (Step d-2) of Example 1 is not performed, and in (Step d-3), the surface of the second wiring 106b is immersed in an oxidation treatment solution at 85 ° C. for 3 minutes, and the surface of the wiring is set to 0. A fan-in type BGA semiconductor chip mounting substrate and a semiconductor package were prepared in the same manner as in Example 1 except that a 50 mg / cm ² copper oxide crystal was formed and no reduction treatment was performed.

Comparative Example 2
The precious metal treatment in (Step d-2) of Example 1 is not performed, and in (Step d-3), the surface of the second wiring 106b is immersed in an oxidation treatment solution at 85 ° C. for 3 minutes, and the surface of the wiring is set to 0. A fan-in type BGA semiconductor chip mounting substrate and a semiconductor package were prepared in the same manner as in Example 1 except that 50 mg / cm ² of copper oxide crystals were formed.

Comparative Example 3
Example 1 except that the precious metal treatment in (Step d-2) of Example 1 and the oxidation-reduction treatment in (Step d-3) were not performed, and the surface of the second wiring 106b was roughened with a microetching agent. In the same manner as in Example 1, a fan-in type BGA semiconductor chip mounting substrate and a semiconductor package were produced. The roughening treatment with the micro-etching agent was performed by immersing the surface of the second wiring 106b in MEC-Hetch Bond CZ8100 (Micro-etching agent manufactured by MEC Co., Ltd., trade name) at 40 ° C. for 1 minute and 30 seconds, washing with water, It was immersed in a 3.6N sulfuric acid aqueous solution at room temperature for 60 seconds, further washed with water for 1 minute, and dried at 85 ° C. for 30 minutes.

Comparative Example 4
The noble metal treatment in (Step d-2) of Example 1 was not performed, and further, the oxidation-reduction treatment in the subsequent (Step d-3) was not performed. That is, a fan-in type BGA semiconductor chip mounting substrate and a semiconductor package were manufactured in the same manner as in Example 1 except that the surface of the second wiring 106b was not roughened.

Comparative Example 5
Instead of the (step d-2) in the first embodiment, the second wiring 106b is added to a treatment liquid containing 4.0 g / L of stannous chloride, 20 g / L of sulfuric acid, and 50 g / L of thiourea at 30 ° C. A semiconductor chip for a fan-in type BGA as in Example 1 except that it is immersed for 1 ^{second to} form 1.0 μmol / dm ^{2 of} tin, which is a base metal rather than copper, on the wiring surface and washed with water for 1 minute. A mounting substrate and a semiconductor package were produced.

Comparative Example 6
In (Step d-3) of Example 1, an alkaline oxidation treatment solution containing 25 g / L of potassium hydroxide and 15 g / L of sodium chlorite was used, and the surface of the second wiring 106b was applied to the treatment solution at 50 ° C. A fan-in type BGA semiconductor chip mounting substrate and a semiconductor package were prepared in the same manner as in Example 1 except that a 0.1 mg / cm ² copper oxide crystal was formed on the wiring surface by dipping for 3 minutes. Produced.

(Semiconductor package reliability test)
After performing a moisture absorption process on each of the 22 semiconductor package samples produced in Examples 1-8 and Comparative Examples 1-6, 0.5 m / min was applied to a reflow furnace having an ultimate temperature of 240 ° C. and a length of 2 m. Reflow was performed by flowing each sample under conditions. Then, the presence or absence of crack generation was examined for each sample, and the case where it occurred was determined as NG. The results are shown in Table 1.

In addition, for each of 22 semiconductor package samples mounted on a 0.8 mm thick mother board, a temperature cycle test was performed with -55 ° C, 30 minutes to 125 ° C, 30 minutes as one cycle, and the 500th cycle. At 1000th cycle and 1500th cycle, the wiring resistance resistance value was measured using a multimeter 3457A manufactured by Hewlett-Packard Company. NG was determined when the measured resistance value changed by 10% or more from the initial resistance value. The results are shown in Table 1. However, in Comparative Example 3, the wiring accuracy could not be maintained and a test substrate could not be manufactured.

<Surface treatment copper surface adhesion and smoothness>
In order to evaluate the adhesion and smoothness of the copper surface after the copper surface treatment of the present invention, an electrolytic copper foil for evaluation was prepared as follows.

(Preparation of electrolytic copper foil for evaluation)
Example 9
An electrolytic copper foil GTS-18 (trade name, manufactured by Furukawa Circuit Foil Co., Ltd.) having a thickness of 18 μm was cut into 5 cm × 8 cm × 3 sheets (for adhesion test, copper surface smoothness evaluation, copper surface appearance evaluation), and each electrolysis One surface of the copper foil was subjected to each surface treatment on the wiring surface described in (Step d-1), (Step d-2), and (Step d-3) of (Step d) of Example 1, and electrolytic copper A foil specimen was prepared. During the treatment, a test piece was attached to a rigid plate with a tape so that the electrolytic copper foil was not bent.

Example 10
As a surface treatment for the electrolytic copper foil, a test piece of an electrolytic copper foil was produced in the same manner as in Example 9, except that the same surface treatment as that in Example 2 (step d) was performed.

Example 11
As a surface treatment for the electrolytic copper foil, a test piece of an electrolytic copper foil was produced in the same manner as in Example 9 except that the same surface treatment as that in Example 3 (step d) was performed.

Example 12
As a surface treatment for the electrolytic copper foil, a test piece of an electrolytic copper foil was prepared in the same manner as in Example 9, except that the same surface treatment as that in Example 4 (step d) was performed.

Example 13
As a surface treatment for the electrolytic copper foil, a test piece of an electrolytic copper foil was prepared in the same manner as in Example 9, except that the same surface treatment as that in Example 5 (step d) was performed.

Example 14
As a surface treatment for the electrolytic copper foil, a test piece of an electrolytic copper foil was produced in the same manner as in Example 9, except that the same surface treatment as that in Example 6 (step d) was performed.

Example 15
As a surface treatment for the electrolytic copper foil, a test piece of an electrolytic copper foil was produced in the same manner as in Example 9, except that the same surface treatment as that in Example 7 (step d) was performed.

Example 16
As a surface treatment for the electrolytic copper foil, a test piece of an electrolytic copper foil was prepared in the same manner as in Example 9, except that the same surface treatment as that in Example 8 (step d) was performed.

Comparative Example 7
As a surface treatment for the electrolytic copper foil, a test piece of electrolytic copper foil was obtained in the same manner as in Example 9, except that the same surface treatment as the wiring surface treatment (pretreatment and oxidation treatment) in (Step d) of Comparative Example 1 was performed. Was made.

Comparative Example 8
As a surface treatment for the electrolytic copper foil, an electrolytic copper foil was obtained in the same manner as in Example 9 except that the same surface treatment as the wiring surface treatment (pretreatment, oxidation treatment and reduction treatment) in (Step d) of Comparative Example 2 was performed. A test piece was prepared.

Comparative Example 9
As a surface treatment for the electrolytic copper foil, a test piece of electrolytic copper foil was obtained in the same manner as in Example 9, except that the same surface treatment as the wiring surface treatment (pretreatment and etching treatment) in (Step d) of Comparative Example 3 was performed. Was made.

Comparative Example 10
As in Comparative Example 4, the electrolytic copper foil was the same as in Example 9, except that the noble metal treatment in (Step d-2) and the oxidation-reduction treatment in (Step d-3) were not performed. A test piece was prepared.

Comparative Example 11
As the surface treatment for the electrolytic copper foil, the same surface treatment as that of the wiring surface treatment (pretreatment, base metal treatment, oxidation treatment and reduction treatment) in (Step d) of Comparative Example 5 was performed, as in Example 9. A test piece of electrolytic copper foil was prepared.

Comparative Example 12
As the surface treatment for the electrolytic copper foil, the same surface treatment as the wiring surface treatment (pretreatment, precious metal treatment, oxidation treatment and reduction treatment with a treatment solution not containing phosphate) in (Step d) of Comparative Example 6 was performed. Except that, a test piece of electrolytic copper foil was prepared in the same manner as Example 9.

(Adhesion test)
MCL-LX-67 (manufactured by Hitachi Chemical Co., Ltd.) which is a double-sided copper-clad laminate impregnated with a glass cloth-cyanate ester-based resin composition having a thickness of 0.8 mm that can be used as a low dielectric loss tangent high heat resistant multilayer material , Product name) was roughened using a chemical etching roughening solution HIST-7300 (manufactured by Hitachi Chemical Co., Ltd.), and the copper surface roughness Rz was 3.5 μm. Thereafter, GXA-67N (trade name, manufactured by Hitachi Chemical Co., Ltd.), which is a prepreg obtained by impregnating a glass cloth with a cyanate ester resin composition, is laminated on the copper surface of Rz = 3.5 μm, and further on the outermost layer. One sheet of electrolytic copper foil prepared in Examples 9 to 16 and Comparative Examples 7 to 12 was laminated, and heated at a pressure of 3.0 MPa from room temperature (25 ° C.) to 230 ° C. at a rate of temperature increase of 6 ° C./min. By holding at 230 ° C. for 1 hour, lamination adhesion was performed to prepare an adhesion test substrate. In addition, the said electrolytic copper foil is adhere | attached with the insulating layer (prepreg) in the surface side which gave various surface treatments.

  Next, the initial (0 hour) adhesion and the adhesion after leaving at 150 ° C. for 120 hours and 240 hours were measured for each of the adhesion test substrates obtained above. In addition, the measurement of the peel strength (N / m) used as the said parameter | index of adhesiveness uses rheometer NRM-3002D-H (Fudo Kogyo Co., Ltd. make, brand name), and makes an electrolytic copper foil perpendicular | vertical with respect to a board | substrate. The peeling was performed at a speed of 50 mm / min. The case where the peel strength value was 300 N / m or more was indicated as ◯, and the case where the peel strength value was less than 300 N / m was indicated as ×. The results are shown in Table 2.

(Smoothness evaluation)
The surface roughness (Rz) on the surface side subjected to the surface treatment of the electrolytic copper foils produced in Examples 9 to 16 and Comparative Examples 7 to 12 is shown below using a simple atomic force microscope (AFM) Nanopics 2100. The measurement was performed under the condition 3. When Rz is 1 nm or more and 100 nm or less, ◎, when Rz exceeds 100 nm and 1000 nm or less, ◯, and when Rz is less than 1 nm or more than 1000 nm, Δ. The results are shown in Table 2.

Condition 3
Measurement length: 1μm
SCAN SPEED: 1.35 μm / sec
FORCE REFERENCE: 160

<Insulation reliability between wires>
In order to evaluate the insulation reliability between copper wires surface-treated by the copper surface treatment method of the present invention, the following evaluation substrates were produced.

(Production of evaluation substrate)
Example 17
(Process a ')
As a core substrate 100 shown in FIG. 9, a 0.4 mm thick soda glass substrate (thermal expansion coefficient 11 ppm / ° C.) was prepared, and an interlayer insulating layer 104 was formed on one side as follows. That is, an insulating varnish of a cyanate ester resin composition was applied onto a glass substrate by spin coating at 1500 rpm to form a resin layer having a thickness of 20 μm, and then increased from room temperature (25 ° C.) to 6 ° C./min. Heating to 230 ° C. at a temperature rate and thermosetting by maintaining at 230 ° C. for 80 minutes, an interlayer insulating layer 104 was formed. Thereafter, a seed layer 150 made of a Ni layer having a thickness of 20 nm and a thin film copper having a thickness of 200 nm was formed in the same manner as in Step 1 of Example 1.

Next, a plating resist PMER P-LA900PM (trade name, manufactured by Tokyo Ohka Kogyo Co., Ltd.) was applied on the seed layer 150 by a spin coating method to form a plating resist layer having a thickness of 10 μm. Next, the plating resist layer was exposed under the condition of 1000 mJ / cm ² , and then immersed in PMER developer P-7G at 23 ° C. for 6 minutes to form a resist pattern 151. Thereafter, electrolytic copper plating was performed using a copper sulfate plating solution to form a wiring 106 having a thickness of about 5 μm. The plating resist was peeled off by immersion for 1 minute at room temperature (25 ° C.) using methyl ethyl ketone. In addition, for quick etching of the seed layer, a 5-fold diluted solution of CPE-700 (manufactured by Mitsubishi Gas Chemical Co., Ltd., trade name) is used for etching removal by immersing and shaking at 30 ° C. for 30 seconds. The wiring 106 was formed.

(Process d ')
For each of the wirings 106 formed in the above (step a ′), each surface is formed in the same manner as (step d-1), (step d-2), and (step d-3) in (step d) of Example 1. After the treatment, the interlayer insulating layer (build-up layer) 104 shown in FIG. 9 (d ′) is formed in the same manner as in (Step d-4) of Example 1, and the L / S shown in FIG. = 5 μm / 5 μm, and 32 evaluation substrates each having L / S = 10 μm / 10 μm shown in FIG. 11 were prepared.

Example 18
A substrate for evaluation was produced in the same manner as in Example 17 except that the same surface treatment as that in (Step d) of Example 2 was performed as each surface treatment in (Step d ′) above.

Example 19
An evaluation substrate was produced in the same manner as in Example 17 except that the same surface treatment as that in (Step d) of Example 3 was performed as each surface treatment in (Step d ′) above.

Example 20
An evaluation substrate was prepared in the same manner as in Example 17 except that the same surface treatment as that in (Step d) of Example 4 was performed as each surface treatment in (Step d ′) above.

Example 21
An evaluation substrate was produced in the same manner as in Example 17 except that the same surface treatment as that in (Step d) of Example 5 was performed as each surface treatment in (Step d ′) above.

Example 22
An evaluation substrate was produced in the same manner as in Example 17 except that the same surface treatment as that in Example 6 (Step d) was performed as each surface treatment in (Step d ′) above.

Example 23
An evaluation substrate was produced in the same manner as in Example 17 except that the same surface treatment as that in Example 7 (Step d) was performed as each surface treatment in (Step d ′) above.

Example 24
An evaluation substrate was produced in the same manner as in Example 17 except that the same surface treatment as that in (Step d) of Example 8 was performed as each surface treatment in (Step d ′) above.

Comparative Example 13
For each evaluation in the same manner as in Example 17 except that the same surface treatment as the wiring surface treatment (pretreatment and oxidation treatment) in (Step d) of Comparative Example 1 was performed as each surface treatment in (Step d ′) above. A substrate was produced.

Comparative Example 14
As each surface treatment in the above (Step d ′), the same surface treatment as that in Example 17 was performed except that the same surface treatment as the wiring surface treatment (pretreatment, oxidation treatment and reduction treatment) in (Step d) of Comparative Example 2 was performed. An evaluation substrate was prepared.

Comparative Example 15
For each evaluation in the same manner as in Example 17 except that the same surface treatment as the wiring surface treatment (pretreatment and etching treatment) in (Step d) of Comparative Example 3 was performed as each surface treatment in (Step d ′) above. A substrate was produced.

Comparative Example 16
In the above (Step d ′), as in Comparative Example 4, the evaluation was performed in the same manner as in Example 17 except that the precious metal treatment in (Step d-2) and the oxidation-reduction treatment in (Step d-3) were not performed. A substrate was produced.

Comparative Example 17
Examples except that the same surface treatment as the wiring surface treatment (pretreatment, base metal treatment, oxidation treatment, and reduction treatment) in (Step d) of Comparative Example 5 was performed as each surface treatment in (Step d ′) above. An evaluation substrate was produced in the same manner as in FIG.

Comparative Example 18
As each surface treatment in the above (step d ′), the same surface as the wiring surface treatment (pretreatment, noble metal treatment, oxidation treatment and reduction treatment with a treatment solution not containing phosphate) in (step d) of Comparative Example 6 An evaluation substrate was produced in the same manner as in Example 17 except that the treatment was performed.

(Insulation reliability test between wires)
For each of the evaluation substrates prepared in Examples 17 to 24 and Comparative Examples 13 to 18, the insulation resistance value between the wirings of L / S = 5/5 μm and L / S = 10/10 μm was measured as follows. did. However, the evaluation board of Comparative Example 15 was not measured because the wiring accuracy could not be maintained.

  First, using an R-8340A type digital ultra-high resistance microammeter manufactured by Advantest Corporation, a voltage of DC 5 V was applied between the wires at room temperature for 30 seconds, and the insulation resistance value between the wires was measured. A digital multimeter 3457A manufactured by Hewlett-Packard (HP) Co., Ltd. was used for measuring the insulation resistance of 1 GΩ or less.

  Next, a voltage of DC 5 V is continuously applied between the wirings in a constant humidity and constant temperature layer maintained at 85 ° C. and relative humidity 85%, and the same as above after 24 h, 48 h, 96 h, 200 h, 500 h, and 1,000 h. The insulation resistance value between the wires was measured. In addition, the constant-humidity thermostat used Hitachi, Ltd. EC-10HHPS type | mold constant temperature and constant temperature, and it measured until 1000 hours after input.

The evaluation board measured as described above is rejected when the minimum value of the insulation resistance value is less than 1.0 × 10 ⁹ Ω (1 GΩ), and when it is 1.0 × 10 ⁹ Ω or more. The number of evaluation boards that passed the test was examined. The results are shown in Tables 3 and 4.

<Discussion>
As shown in Table 1, the semiconductor packages produced in Examples 1 to 8 showed extremely good reliability. Moreover, as shown in Table 2, the electrolytic copper foils produced in Examples 9 to 16 have dense and uniform fine unevenness of several tens of nanometer level on the surface, and the surface and the insulating layer are 150 ° C. The adhesive strength (peel strength) after leaving for 240 hours was 300 N / m or more, which was good. Further, as shown in Table 3 and Table 4, the inter-wiring insulation reliability in the evaluation boards fabricated in Examples 17 to 24 is extremely high at both L / S = 5/5 μm and L / S = 10/10 μm. It was good.

  On the other hand, when the precious metal treatment and the oxidation treatment according to the present invention were not performed, as shown in Comparative Examples 1 to 18, the reliability of the semiconductor package, the smoothness of the copper surface, the adhesion between the copper surface and the insulating layer, and the insulation between wirings I couldn't satisfy all of the reliability. When the oxidation treatment was performed without the precious metal treatment, as shown in Comparative Examples 7, 8, 13, and 14, the smoothness and the inter-wiring insulation reliability were inferior as compared with the Examples. In addition, when the microetching treatment was performed, as shown in Comparative Examples 3, 9, and 15, the amount of copper dissolved was large, so that it could not be applied to fine wiring. Further, when the surface roughening treatment was not performed, as shown in Comparative Examples 4, 10, and 16, the adhesiveness, the reliability of the semiconductor package, and the inter-wiring insulation reliability were inferior. Further, when the base metal treatment and the oxidation treatment are performed, as shown in Comparative Examples 5, 11, and 17, the reliability, smoothness, and adhesion of the semiconductor package are compared with those when the noble metal treatment and the oxidation treatment are performed. All of the reliability and the insulation reliability between wirings were inferior. Furthermore, even when noble metal treatment and oxidation treatment are performed, if no phosphate is included in the oxidation treatment solution, as shown in Comparative Examples 6, 12, and 18, the effect of performing the noble metal treatment Could not be obtained sufficiently.

  Therefore, according to the present invention, uniform fine unevenness of several tens of nanometers with good adhesion strength between the copper surface and the insulating layer can be formed on the copper surface with high productivity, and the inter-wiring insulation reliability can be improved. An excellent wiring board and a highly reliable semiconductor package can be manufactured with high productivity.

It is sectional drawing which shows one Embodiment of the wiring board (substrate for semiconductor chip mounting) of this invention. It is process drawing which shows one Embodiment of the manufacturing method of the wiring board (substrate for semiconductor chip mounting) of this invention. It is sectional drawing which shows one Embodiment of the semiconductor package (flip chip type) of this invention. It is sectional drawing which shows one Embodiment of the semiconductor package (wire bond type) of this invention. It is a top view which shows one Embodiment of the wiring board (board | substrate for fan-in type semiconductor chips) of this invention. It is a top view which shows one Embodiment of the wiring board (board | substrate for fan-out type semiconductor chips mounting) of this invention. It is a top view showing a part of frame shape of the wiring board (semiconductor chip mounting board | substrate) of this invention. It is sectional drawing which shows one Embodiment of the wiring board (substrate for semiconductor chip mounting) of this invention. It is process drawing which shows one Embodiment of the manufacturing method of the board | substrate for wiring insulation reliability evaluation produced in the Example. It is a top view of the board | substrate for insulation reliability evaluation between wiring produced in the Example (L / S = 5micrometer / 5micrometer). It is a top view of the board | substrate for insulation reliability evaluation between wiring produced in the Example (L / S = 10micrometer / 10micrometer).

Explanation of symbols

11. Positioning mark (guide hole for alignment)
13. Semiconductor package region 14. Die bond film bonding area (flip chip type)
15. Semiconductor chip mounting area (flip chip type)
16. Semiconductor chip connection terminal 17. Die bond film bonding area (wire bond type)
18. Semiconductor chip mounting area (wire bond type)
19. External connection terminal 20. Expanded wiring 21. Dummy pattern 22. Semiconductor chip mounting substrate 23. Block 24. Reinforcing pattern 25. Cutting alignment mark 100. Core substrate 101. First interlayer connection terminal 102. IVH (via hole) for first interlayer connection
103. Second interlayer connection terminal 104. Interlayer insulation layer (build-up layer)
105. Third interlayer connection IVH (via hole)
106. Wiring 106a. First wiring 106b. Second wiring 106c. Third wiring 107. External connection terminal 108. Second layer connection IVH (via hole)
109. Insulation coating (solder resist)
111. Semiconductor chip 112. Connection bump 113. Underfill material 114. Solder balls 115. Gold wire 116. Sealing resin for semiconductor 117. Die bond film 118. Seed layer 119. Resist pattern

Claims (15)

A copper surface treatment liquid set for roughening the copper surface,
An acidic noble metal treatment solution for discretely forming a metal nobler than copper on the copper surface, including a salt of a metal nobler than copper;
An alkaline oxidation treatment solution containing a phosphate and an oxidizing agent, and oxidizing the copper surface treated with the noble metal treatment solution;
A copper surface treatment liquid set.   2. The salt of a metal nobler than copper is a salt containing at least one metal selected from the group consisting of gold, silver, platinum, palladium, rhodium, rhenium, ruthenium, osmium and iridium. Copper surface treatment solution set.   The copper surface treatment liquid set according to claim 1 or 2, wherein the noble metal treatment liquid further contains one or more compounds selected from the group consisting of ammonium salts, amino acids, hydroxycarboxylic acids, and hydroxycarboxylates.   The oxidant is one or more selected from the group consisting of chlorate, chlorite, hypochlorite, perchlorate, and peroxodisulfate. The copper surface treatment liquid set described in 1.   The copper surface treatment liquid set according to any one of claims 1 to 4, wherein the phosphate is one or more selected from the group consisting of trisodium phosphate, tripotassium phosphate, and trilithium phosphate.   The copper surface treatment liquid set according to any one of claims 1 to 5, wherein the noble metal treatment liquid contains 0.1 to 10 mmol / L of a salt of a metal nobler than the copper.   The copper surface treatment liquid set according to any one of claims 1 to 6, wherein the oxidation treatment liquid contains 1 to 40 g / L of the phosphate and 1 to 100 g / L of the oxidizing agent.   The copper surface treatment liquid used after the treatment with the oxidation treatment liquid further includes one or more treatment liquids selected from the group consisting of a reduction treatment liquid, a coupling treatment liquid, and a corrosion inhibition treatment liquid. The copper surface treatment liquid set according to any one of the above.   The copper surface treatment liquid set in any one of Claims 1-8 for roughening a copper surface so that it may become 1 nm or more and 1000 nm or less by Rz.   A copper surface treatment method in which at least a noble metal treatment liquid and an oxidation treatment liquid of the copper surface treatment liquid set according to claim 1 are sequentially used to roughen the copper surface. The copper surface treatment method according to claim 10, wherein a formation amount of the noble metal than the copper formed on the copper surface by the noble metal treatment liquid is 0.001 μmol / dm ² or more and 40 μmol / dm ² or less. .   The copper surface treatment method according to claim 10 or 11, wherein the roughness of the copper surface after the treatment is 1 nm or more and 1000 nm or less in terms of Rz.   Copper surface-treated by the copper surface treatment method according to claim 10.   The wiring board which has the copper wiring surface-treated by the surface treatment method of the copper in any one of Claims 10-12.   The semiconductor package which mounts a semiconductor chip in the predetermined position of the wiring board of Claim 14.

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