JP2009155668A - Pretreatment liquid for promoting starting of electroless palladium plating reaction, electroless plating method using the pretreatment liquid, connection terminal formed by the electroless plating method, and semiconductor package using the connection terminal and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a pretreatment liquid for promoting starting of electroless palladium plating reaction for forming a film of uniform thickness by suppressing non-formation of electroless palladium plating film formed on a plated body functioned as a protective layer for an electroless nickel plating alloy film or reduction in thickness, an electroless plating method using the same, a connection terminal, a semiconductor package using the connection terminal, and its manufacturing method. <P>SOLUTION: Disclosed are the pretreatment liquid for promoting starting of electroless palladium plating reaction for immersing the electroless palladium plating film before forming to promote starting of the electroless palladium plating reaction when performing depositing the electroless nickel plating alloy film, the electroless palladium plating film, and a substitution gold plating film on the plated body, or further performing electroless plating for depositing the electroless plating film, the electroless plating method using the pretreatment liquid, the connection terminal formed by the electroless plating method, the semiconductor package using the connection terminal, and its manufacturing method. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to an electroless palladium plating reaction start acceleration pretreatment liquid, an electroless plating method using the pretreatment liquid, a connection terminal formed by the electroless plating method, a semiconductor package using the connection terminal, and a manufacturing method thereof About.

  The development of the information society in recent years has been remarkable, and consumer devices have been reduced in size, weight, performance, and functionality, such as personal computers and mobile phones. Industrial equipment includes wireless base stations, optical communication devices, and servers. In addition, there is a demand for improvement in function in the same way, regardless of whether it is large or small, such as routers and other network related devices.

  In addition, with the increase in the amount of information transmitted, the frequency of signals handled tends to increase year by year, and high-speed processing and high-speed transmission technology are being developed. With regard to mounting relations, the development of system-on-chip (SoC), system-in-package (SiP), etc., as new high-density mounting technologies, as well as higher-speed and higher-performance LSIs such as CPUs, DSPs, and various types of memory are actively developed. Has been done.

  For this reason, build-up type multilayer wiring boards have come to be used for semiconductor chip mounting boards and motherboards in order to cope with high frequency, high density wiring, and high functionality. Electronic device manufacturers have been competing in high-density packaging to achieve smaller, thinner, and lighter products, and rapid technological progress has been made in narrowing the multi-pin pitch of packages. From QFP (Quad Flat Package) to BGA (Ball Grid Array) / CSP (Chip Size Package) mounting on the surface.

  The semiconductor chip is connected to the semiconductor chip mounting substrate by, for example, gold wire bonding, and the semiconductor package is connected to the wiring board (mother board) by solder balls. In many cases, the semiconductor chip connection terminal and the connection terminal of the solder ball are plated with gold in order to ensure a good metal bond.

  Semiconductor packages are rapidly becoming smaller and higher in wiring density, and in the electrolytic gold plating process, special wiring is required for gold plating on the pad surface, and its application is becoming difficult. As a method for solving this problem, an electroless gold plating process requiring no gold plating wiring has begun to attract attention.

  When electroless plating technology is used, an electroless nickel plating film, a displacement gold plating film, or even an electroless gold plating is formed on the copper surface of a semiconductor chip connection terminal or a solder ball connection terminal (electroless nickel / gold Is a general method (see, for example, Patent Document 1).

  However, if the displacement gold plating film is formed after the electroless nickel plating film is formed, the electroless nickel plating film is corroded by the displacement gold plating solution and the connection strength is reduced. There is a method of improving the connection strength by suppressing the corrosion of the electroless nickel plating film by forming an electroless palladium plating film between the film and the film.

  In recent years, an electroless palladium-phosphorus alloy film containing hypophosphorous acid or phosphorous acid as a reducing agent has been used as an electroless palladium plating film to form an electroless palladium-phosphorus alloy film containing phosphorus. A technique for forming an electrolytic palladium-phosphorus / gold plating film has been reported. (For example, refer nonpatent literature 1).

  After forming an electroless nickel plating alloy film, when using an electroless palladium plating solution containing hypophosphorous acid or phosphorous acid as a reducing agent to form an electroless palladium-phosphorous plating alloy film containing phosphorus, In electroless palladium plating solution using phosphorous acid or phosphorous acid as a reducing agent, the activity is low and precipitation is difficult to occur, so there are conductor terminals that delay the start of electroless palladium plating reaction. There is a case where a terminal of a conductor in which no electroless palladium-phosphorus plating alloy film is formed or a conductor of a thin electroless palladium-phosphorous plating alloy film is formed. In some cases, the electrolytic palladium-phosphorus plating alloy film does not function as a protective layer for the electroless nickel plating alloy film, and a connection terminal with low connection strength may be formed. .

  Even when electroless palladium plating solution using formic acid or the like as a reducing agent, which is highly active and easily deposits on the electroless nickel plating film, is used, as the plating area is reduced, hypophosphorous acid and phosphorous acid are used. As with the electroless palladium plating solution using acid as the reducing agent, the start of the electroless palladium plating reaction is delayed, and terminals with no electroless palladium plating film formed or terminals with thin conductors are formed. May not function as a protective layer for the electroless nickel plating alloy film, and a connection terminal having low connection strength may be formed.

Japanese Patent Application No. 2006-334384 Journal of Surface Technology Association (Vol, 58, No35 (2007))

  The present invention has been made to improve the above-described problems of the prior art, and to form an electroless palladium plating film having a uniform thickness on the electroless nickel plating alloy film formed on the object to be plated. An electroless palladium plating reaction initiation promoting pretreatment liquid, an electroless plating method using the pretreatment liquid, a connection terminal formed by the electroless plating method, a semiconductor package using the connection terminal, and a method for manufacturing the same It is for the purpose.

  After an electroless nickel plating alloy film is formed on the object to be plated, it is immersed in an electroless palladium plating reaction start acceleration pretreatment liquid that accelerates the start of the electroless palladium plating reaction of the present invention. Electrolytic palladium plating reaction start time can be shortened as much as possible, and the thickness of the electroless palladium plating film at all locations of the object to be plated is made uniform, and further, replacement gold plating is formed or further electroless gold plating film is formed. By forming in order, a to-be-plated body with high connection reliability can be produced.

That is, the present invention relates to the following matters.
(1) When an electroless nickel plating alloy film, an electroless palladium plating film, and a displacement gold plating film are formed on the object to be plated, or further electroless plating is performed to form an electroless gold plating film, electroless palladium An electroless palladium plating reaction start acceleration pretreatment liquid that is immersed before forming a plating film to promote the start of the electroless palladium plating reaction.

(2) The electroless palladium according to the above (1), wherein the electroless palladium plating reaction initiation promoting pretreatment liquid for promoting the initiation of the electroless palladium plating reaction is mainly composed of a complexing agent, a reducing agent and a pH adjuster. Pretreatment solution for accelerating plating reaction start.
(3) The electroless palladium plating reaction start acceleration pretreatment liquid according to (2) above, wherein the complexing agent is ammonia or amines.

(4) The reducing agent is hypophosphorous acid and salts thereof, phosphorous acid and salts thereof, formic acid and salts thereof, borohydride compounds and amine boranes, aliphatic carboxylic acids and ammonium salts thereof, potassium salts, sodium The electroless palladium plating reaction initiation promoting pretreatment liquid according to (2) above, which is at least one compound selected from salts.

(5) The electroless palladium plating reaction start pretreatment liquid according to any one of (1) to (4), wherein the object to be plated is an electrical insulator or a conductor.
(6) The electroless palladium plating reaction start acceleration pretreatment liquid according to (5), wherein the electrical insulator is an organic material, ceramic, silicone, or glass.

(7) The electroless palladium plating reaction start acceleration pretreatment liquid according to (5), wherein the conductor is copper, tungsten, molybdenum, or aluminum.
(8) The electroless palladium plating reaction start pretreatment liquid according to any one of (1) to (7), wherein the surface area of the object to be plated is 1 mm ² or less.

(9) In an electroless plating method of forming an electroless nickel plating alloy film, an electroless palladium plating film, and a displacement gold plating film on a body to be plated, or further forming an electroless gold plating film, electroless palladium plating An electroless plating method characterized by immersing in an electroless palladium plating reaction initiation promoting pretreatment solution for promoting the initiation of an electroless palladium plating reaction before forming a film.

(10) An electroless nickel plating alloy film is formed on a conductor terminal that is an object to be plated and immersed in an electroless palladium plating reaction start pretreatment solution that promotes the start of the electroless palladium plating reaction; A connection terminal formed by an electroless plating method of forming a palladium plating film and further forming a displacement gold plating or further forming an electroless gold plating film.

(11) The electroless palladium plating film has a purity of 90% by weight to 99% by weight on top of one layer of electroless palladium plating film having a purity of 90% by weight or more, or an electroless palladium plating film having a purity of 99% by weight or more. The connection terminal according to the above (10), wherein less than electroless palladium plating film is formed in two layers.

(12) An electroless nickel plating alloy film is formed on a conductor terminal which is an object to be plated and immersed in an electroless palladium plating reaction start acceleration pretreatment solution for promoting the start of the electroless palladium plating reaction; Connection terminal formed by an electroless plating method for forming a palladium plating film and a displacement gold plating film or further forming an electroless gold plating film, a substrate for supporting the conductor, a semiconductor chip, and the semiconductor chip and the conductor A semiconductor package comprising a connecting conductor for connecting the two.

(13) A step of forming a conductor on the surface of the substrate, a step of forming an electroless nickel plating alloy film on the surface of the conductor, and an electroless palladium plating reaction start acceleration pretreatment liquid that accelerates the start of the electroless palladium plating reaction After dipping, a single layer of electroless palladium plating film having a purity of 90% by weight or more, or an electroless palladium plating film having a purity of 90% by weight to less than 99% by weight on top of an electroless palladium plating film having a purity of 99% by weight or more A plating film is formed on a conductor and a connection terminal is formed by welding a solder on the conductive film by a process of forming two layers, a step of forming a displacement gold plating film, or a process of forming an electroless gold plating film. A step of mounting a semiconductor chip on the solder of the connection terminal and a step of forming a connection conductor for connecting the semiconductor chip and the conductor. A method of manufacturing a semiconductor package to be butterflies.

  According to the present invention, an electroless palladium plating reaction start acceleration pretreatment liquid for forming an electroless palladium plating film having a uniform thickness on the electroless nickel plating alloy film formed on the object to be plated, this pretreatment It is possible to provide an electroless plating method using a liquid, a connection terminal formed by the electroless plating method, a semiconductor package using the connection terminal, and a manufacturing method thereof.

  In the present invention, an electroless nickel plating alloy film is formed on an object to be plated and immersed in an electroless palladium plating reaction start acceleration pretreatment solution that accelerates the start of electroless palladium plating reaction. Forming, further forming a displacement gold plating or forming an electroless gold plating film, an electroless plating method, an electroless palladium plating reaction start promoting pretreatment liquid for promoting the start of the electroless palladium plating reaction, and It features a method of electroless plating and an object to be plated plated with a pretreatment liquid.

The electric insulator as the object to be plated used in the present invention may be any organic material, ceramic, silicone, glass or the like as long as it has electric insulation, and is not particularly limited.
As the organic material, a thermosetting resin, a thermoplastic resin, or a mixed resin thereof can be used, but a thermosetting organic insulating material is preferable.

  Thermosetting resins include phenolic resin, urea resin, melamine resin, alkyd resin, acrylic resin, unsaturated polyester resin, diallyl phthalate resin, epoxy resin, polybenzimidazole resin, polyamide resin, polyamideimide resin, silicone resin, cyclohexane Resin synthesized from pentadiene, resin containing tris (2-hydroxyethyl) isocyanurate, resin synthesized from aromatic nitrile, trimerized aromatic dicyanamide resin, resin containing triallyl trimethacrylate, furan resin, ketone resin, xylene Resins, thermosetting resins containing condensed polycyclic aromatics, benzocyclobutene resins, and the like can be used.

  Examples of the thermoplastic resin include polyimide resin, polyphenylene oxide resin, polyphenylene sulfide resin, aramid resin, and liquid crystal polymer.

Further, as the non-photosensitive glass out of a glass, soda lime glass (component _{example: SiO 2 65~75wt%, Al 2} O 3 0.5~4wt%, CaO 5~15wt%, MgO 0.5~4wt% , Na ₂ O 10-20 wt%), borosilicate glass (component example: SiO ₂ 65-80 wt%, B ₂ O ₃ 5-25 wt%, Al ₂ O ₃ 1-5 wt%, CaO 5-8 wt%, MgO 0 0.5 to ₂ wt%, Na ₂ O 6 to 14 wt%, K ₂ O 1 to 6 wt%) and the like.

Also, it includes those containing gold ions and silver ions as a photosensitive agent into Li _{2 O-SiO} 2 based crystallized glass as photosensitive glass.

The conductor as the object to be plated used in the present invention may be made of a metal such as copper, tungsten, molybdenum, or aluminum, or an alloy thereof, as long as it can form an electroless nickel plating alloy film.
The shape of the object to be plated used in the present invention may be spherical, flat, fibrous, or flat, and the shape is not particularly limited.

The surface area of the object to be plated is not particularly limited, but is 1 mm ² or less. As the surface area becomes smaller, 1 mm ² or less, the deposition of the electroless palladium plating film on the electroless nickel plating is less likely to occur. Therefore, the smaller the area, the more the electroless palladium that promotes the start of the electroless palladium plating reaction. The effect of the pretreatment solution for promoting the start of the plating reaction appears remarkably.

  In the present invention, electroless nickel plating is a method in which nickel ions in a plating solution are deposited on the surface where conductor terminals such as copper, tungsten, molybdenum, and aluminum are activated by movement of a reducing agent of nickel ions. The composition of the electroless nickel plating film is usually an alloy with nickel containing an element (phosphorus, boron, nitrogen, etc.) caused by a reducing agent, and the electroless nickel / phosphorous alloy plating film, Electroless nickel / boron alloy plating film.

The electroless nickel plating film is preferably nickel having a purity of 80% by weight or more. If the electroless nickel plating film is less than 80% by weight, connection reliability may be lowered.
A purity of 90% by weight or more is more preferable. The film thickness of the electroless nickel plating film is preferably 0.1 to 20 μm. If the thickness is less than 0.1 μm, the plating effect is not improved and the connection reliability is not improved. It is not preferable because it is not economical and is not economical. Furthermore, the thickness of the electroless nickel is more preferably in the range of 0.5 to 10 μm.

  As the complexing agent used in the present invention, ammonia or amines can be used. As amines, a saturated alkylamine compound or an unsaturated alkylamine compound can be used.

  Saturated alkylamine compounds include monoamines such as methylamine, ethylamine, propylamine, dimethylamine, trimethylamine, methylethylamine, isopropylamine, diamines such as methylenediamine, ethylenediamine, propylenediamine, butylenediamine, dimethylenetriamine, and diethylenetriamine. And polyamines such as triethylenetetramine, tetraethylenepentamine, pentaethylenehexamine, and ethylenediaminetetraacetic acid, diethylenetriaminepentaacetic acid, N-hydroxyethylethylenediaminetriacetic acid, nitrilotriacetic acid, and their alkali metal salts, glycine Various amine acids such as N-methylglycine are also included.

  Examples of unsaturated alkylamine compounds include monoethynylamine, diethynylamine, monovinylamine, divinylamine, monoallylamine, diallylamine, propenylamine, isopropenylamine, monolines such as aniline, N-monoethynylethylenediamine, N-monovinylethylenediamine N-monoallylethylenediamine, N, N′-diallylethylenediamine, N-isopropenylethylenediamine, diamines such as N-phenylethylenediamine, N-allyldiethylenetriamine, N, N′-diallyldiethylenetriamine, N-vinyltriethylenetetramine, etc. And various unsaturated alkylamines of the polyamines. These ammonia or amines can be used alone or in admixture of two or more.

  The concentration is preferably 0.01 to 5 mol / L, more preferably 0.03 to 3 mol / L, and still more preferably 0.1 to 1 mol / L. If it is less than 0.01 mol / L, the effect of promoting the start of the electroless palladium plating reaction cannot be obtained. If it exceeds 5 mol / L, the effect is not improved further and it is not economical, which is not preferable.

  As the reducing agent used in the present invention, hypophosphorous acid, hypophosphite such as sodium hypophosphite, phosphorous acid, phosphite such as sodium phosphite, hydrogenation such as sodium borohydride Boron compounds, amine boranes such as dimethylamine borane, diethylamine borane, propionic acid, butyric acid, isobutyric acid, acetic acid, oxalic acid, malonic acid, succinic acid, malic acid, tartaric acid, citric acid, adipic acid, fumaric acid, maleic acid and These aliphatic carboxylic acids such as ammonium salt, potassium salt and sodium salt can be used alone or in admixture of two or more.

  The concentration is preferably 0.001 to 5 mol / L, more preferably 0.01 to 3 mol / L, and still more preferably 0.05 to 1 mol / L. If it is less than 0.001 mol / L, the effect of promoting the start of the electroless palladium plating reaction cannot be obtained. If it exceeds 5 mol / L, the effect is not improved further and it is not economical, which is not preferable.

  The pH adjuster used in the present invention is not particularly limited as long as it is an acid or an alkali. As the acid, hydrochloric acid, sulfuric acid, nitric acid and the like can be used, and as the alkali, alkali metal and alkaline earth metal hydroxide solutions such as sodium hydroxide, potassium hydroxide and sodium carbonate can be used, and there is no particular limitation. .

The electroless palladium plating reaction start acceleration pretreatment liquid used in the present invention for promoting the start of electroless palladium plating reaction includes boric acid such as boric acid and potassium borate in addition to a complexing agent, a reducing agent and a pH adjuster. It is also possible to add buffering agents such as salt.
It is also possible to add one or more monovalent, divalent, trivalent alcohol and polyhydric alcohol.

  The electroless palladium plating film formed after the electroless nickel plating alloy film is formed on the object to be plated and immersed in the pretreatment liquid for promoting the start of electroless palladium plating reaction that promotes the start of electroless palladium plating reaction. One layer of electroless palladium plating film of 90% by weight or more, or two layers of electroless palladium plating film having a purity of 90% by weight to less than 99% by weight are formed on top of an electroless palladium plating film of 99% by weight or more It only has to be done.

  The film thickness of one layer of electroless palladium plating film having a purity of 90% by weight or more is preferably in the range of 0.001 to 0.4 μm, more preferably in the range of 0.01 to 0.2 μm, and 0.03 to 0.4 mm. More preferably, it is in the range of 15 μm. If it exceeds 0.4 μm, it is not preferable because it is not economical. If the thickness is less than 0.001 μm, there may be a terminal on which the palladium plating film is not deposited, and it may not be uniformly deposited on all the objects to be plated, which may reduce the connection reliability. Further, if the purity of palladium is less than 90% by weight, the connection reliability may be lowered, which is not preferable.

  In an electroless palladium plating film in which an electroless palladium plating film having a purity of 90% by weight to less than 99% by weight is formed in two layers on top of an electroless palladium plating film having a purity of 99% by weight or more, the purity is 99% by weight or more. The electroless palladium plating film is preferably in the range of 0.001 to 0.4 μm, more preferably in the range of 0.01 to 0.2 μm, and still more preferably in the range of 0.03 to 0.1 μm. If the thickness is less than 0.001 μm, there may be a terminal on which the palladium plating film is not deposited, and it may not be uniformly deposited on all the objects to be plated, which may reduce the connection reliability.

  The electroless palladium plating film having a purity of 90% by weight to less than 99% by weight is preferably in the range of 0.03 to 0.3 μm, more preferably in the range of 0.04 to 0.2 μm, and 0.06 to 0.15 μm. More preferably, it is the range. If it exceeds 0.3 μm, it is not preferable because it is not economical.

  The sum of the film thicknesses of the electroless palladium plating film having a palladium purity of 99% by weight or more and the electroless palladium plating film having a palladium purity of 90% by weight to less than 99% by weight is in the range of 0.031 to 0.5 μm. Is preferable, the range of 0.04 to 0.3 μm is more preferable, and the range of 0.06 to 0.2 μm is more preferable.

  In the displacement gold plating, the purity of palladium is 90% by weight to 99% by weight by a substitution reaction between an electroless palladium plating film having a palladium purity of 90% by weight to less than 99% by weight and gold ions in the solution. A gold film is formed on the surface of less than electroless palladium plating film, and some plating solutions contain a cyanide compound and others do not contain a cyanide compound, but any plating solution can be used.

The electroless gold plating film is a reduction-type electroless gold plating film, preferably gold having a purity of 99% by weight or more, and if it is less than 99% by weight, connection reliability may be lowered. . Furthermore, the purity of the electroless gold plating film is more preferably 99.5% by weight or more.
For the gold plating, a substitution reduction type gold plating solution can also be used.

  The sum of the thickness of the displacement gold plating film and the electroless gold plating film in consideration of wire bonding properties is preferably 0.04 to 3 μm, more preferably in the range of 0.06 to 1 μm. More preferably, it is in the range of 0.1 to 0.5 μm. If it is less than 0.04 μm, the success rate of wire bonding decreases. If it exceeds 3 μm, the effect is not improved further and it is not economical, which is not preferable.

  In consideration of solder connection reliability, only replacement gold plating may be used, but electroless gold plating may be further performed. The sum of the thicknesses of the displacement gold plating film and the electroless gold plating film is preferably in the range of 0.005 to 3 μm, more preferably in the range of 0.01 to 0.5 μm, and 0.04 to More preferably, it is in the range of 0.2 μm. If it is less than 0.005 μm, the solder connection reliability is lowered. If it exceeds 3 μm, the effect is not improved further and it is not economical, which is not preferable.

  Any solder can be used as long as it is solder for solder balls, solder for surface mounting electronic components and wiring boards, solder on semiconductor chips, solder for solder bumps, etc. There is no limitation, and for example, spherical, hemispherical, cubic, rectangular parallelepiped, or protruding solders can be used.

  Furthermore, eutectic solder of 60% tin and 40% lead, tin containing no lead, and tin alloy containing one or more elements such as silver, copper, zinc, bismuth, germanium, palladium, nickel, and indium can also be used. . As a specific example, Sn-3.0Ag-0.5Cu can be used.

  Hereinafter, an electroless palladium plating reaction start acceleration pretreatment liquid and a pretreatment method according to the present invention, and a pretreated substrate to be plated will be described with reference to the drawings. In particular, the case where the object to be plated is a semiconductor chip mounting substrate will be described in detail.

(Metal coat)
A metal selected from copper, tin, chromium, nickel, zinc, aluminum, cobalt, gold, platinum, silver, palladium, and the metal having a film thickness of 5 nm to 0.4 μm on the wiring surface after the copper wiring is formed By wiring the surface of the wiring continuously or discretely with a metal made of an alloy containing, a wiring having a surface roughness Ra of 0.01 to 0.4 μm was formed.

  The most preferred state is that copper, tin, chromium, nickel, zinc, aluminum, cobalt and alloys of the above metals are converted into oxides, hydroxides, or combinations thereof, either during or after application, either spontaneously or deliberately. In other words, a layer of the above polyvalent metal oxide, hydroxide, or a combination thereof is formed on the circuit.

In addition to the metal, metals such as molybdenum, titanium, tungsten, lead, iron, indium, thallium, bismuth, ruthenium, rhodium, gallium, germanium can be used, and an alloy containing at least one of these metals is used. You can also.
Examples of methods for attaching the metals to the wiring surface include electroless plating, electroplating, substitution reaction, spray spraying, coating, sputtering, and vapor deposition.

(Method of forming irregularities on the wiring surface)
As a method for forming irregularities on the wiring surface, there are a method using an acidic solution, a method using an alkaline solution, and a method using a treatment liquid having an oxidizing agent or a reducing agent.

(Acid solution)
As the acidic solution, a compound selected from hydrochloric acid, sulfuric acid, nitric acid, phosphoric acid, acetic acid, formic acid, cupric chloride, ferric sulfate and other iron compounds, alkali metal chlorides, ammonium persulfate and the like, or a combination thereof Or an aqueous solution containing acidic hexavalent chromium such as chromic acid, chromic acid-sulfuric acid, chromic acid-hydrofluoric acid, dichromic acid, dichromic acid-borofluoric acid, or the like. Regarding the concentration and treatment time of these treatment liquids, it is preferable to select and use conditions appropriately so that the surface roughness Ra is 0.01 to 0.4 μm.

(Alkaline solution)
As the above alkaline solution, alkali metal or alkaline earth metal hydroxide solutions such as sodium hydroxide, potassium hydroxide and sodium carbonate can be used, and these solutions are added with an organic acid, a chelating agent or the like. It is also possible to use it. Regarding the concentration and treatment time of these treatment liquids, it is preferable to select and use conditions appropriately so that the surface roughness Ra is 0.01 to 0.4 μm.

(Treatment liquid having oxidizing agent or reducing agent)
The copper wiring may be immersed in an aqueous solution containing an oxidizing agent to form a copper oxide film on the copper surface, and then the copper oxide film may be reduced by a reduction treatment to form a fine uneven shape on the copper wiring surface. In that case, after processing using the said acidic or alkaline solution, it is possible to process in combination, What is necessary is just to process so that surface roughness may be 0.01-0.4 micrometer in Ra. .

As the aqueous solution containing the oxidizing agent, an oxidizing agent such as sodium chlorite can be used, and an aqueous solution containing an OH anion source and a buffering agent such as trisodium phosphate is preferable.
Moreover, as aqueous solution which performs a reduction process, the aqueous solution which added formaldehyde, paraformaldehyde, the aromatic aldehyde compound in the alkaline solution adjusted to pH 9.0-13.5, hypophosphorous acid, hypophosphite, etc. An aqueous solution containing it can be used.

  Moreover, it is preferable to perform the degreasing process which cleans the wiring surface using a solvent, acidic aqueous solution, or alkaline aqueous solution as pre-processing of these processes. The degreasing treatment is not particularly limited as long as alkaline and acidic aqueous solutions are used, but the above-described acidic aqueous solution or alkaline aqueous solution is preferable. Furthermore, it is preferable to clean the wiring surface with a 1-5 N sulfuric acid aqueous solution. The degreasing treatment and the sulfuric acid cleaning may be appropriately combined.

(Formation of Si-O-Si)
As the compound having a Si—O—Si bond, silica glass, a compound containing a ladder structure, and the like are preferable.

(Silica glass)
The silica glass (SiO ₂ ) preferably has a thickness of 0.002 to 5 μm, more preferably 0.005 to 1 μm, and still more preferably 0.01 to 0.2 μm. If the thickness of the silica glass exceeds 5 μm, via processing using a laser or the like in the via hole forming process tends to be difficult, and if it is less than 0.002 μm, formation of the silica glass layer tends to be difficult.

(Compound containing ladder structure)
The compound including the ladder structure is a compound including a ladder structure represented by the general formula (1), wherein each R is independently a hydrogen atom, a reactive group, a hydrophilic group, or a hydrophobic group. It may be selected from a group. As reactive groups, amino groups, hydroxyl groups, carboxyl groups, epoxy groups, mercapto groups, thiol groups, oxazoline groups, cyclic ester groups, cyclic ether groups, isocyanate groups, acid anhydride groups, ester groups, amino groups , Formyl group, carbonyl group, vinyl group, hydroxy-substituted silyl group, alkoxy-substituted silyl group, halogen-substituted silyl group and the like.

  Examples of hydrophilic groups include polysaccharide groups, polyether groups, hydroxyl groups, carboxyl groups, sulfuric acid groups, sulfonic acid groups, phosphoric acid groups, phosphonium bases, heterocyclic groups, amino groups, salts and esters thereof.

  Examples of the hydrophobic group include a compound selected from an aliphatic hydrocarbon group having 1 to 60 carbon atoms, an aromatic hydrocarbon group having 6 to 60 carbon atoms, a heterocyclic group, and a polysiloxane residue. Of these, a reactive group is most preferred.

(Coupling agent)
Furthermore, after the compound having the Si—O—Si bond is formed on the wiring surface, the treatment can be performed using a solution containing a coupling agent. The content of the coupling agent is preferably 0.01 to 5% by weight, more preferably 0.1 to 1.0% by weight, based on the entire solution. By using the coupling agent, the adhesion strength between the wiring and the interlayer insulating layer (build-up layer) can be improved.

Examples of the coupling agent to be used include a silane coupling agent, an aluminum coupling agent, a titanium coupling agent, and a zirconium coupling agent, and among them, a Si-O-Si silane coupling agent is preferable. The silane coupling agent has a functional group such as an epoxy group, amino group, mercapto group, imidazole group, vinyl group or methacryl group in the molecule, and at least one or more of these silane coupling agents. A solution containing a mixture of
As the solvent used for preparing the silane coupling agent solution, water, alcohol, ketones or the like can be used.

  A small amount of acid such as acetic acid or hydrochloric acid can also be added to promote hydrolysis of the coupling agent. The content of the coupling agent is preferably 0.01 to 5% by weight, more preferably 0.1 to 1.0% by weight, based on the entire solution.

  The treatment with the coupling agent can be carried out by a method such as immersion, spray spraying, coating, etc. in the coupling agent solution prepared as described above. The substrate treated with the silane coupling agent is dried by natural drying, heat drying, or vacuum drying. Depending on the type of coupling agent used, it may be washed with water or ultrasonically before drying. It is.

(Photocatalyst particles)
After the compound having the Si—O—Si bond described above is formed, TiO ₂ , ZnO, SrTiO ₃ , CdS, GaP, InP, GaAs, BaTiO ₃ , BaTi ₄ O ₉ , K ₂ NbO ₃ , Nb ₂ O ₅ , Fe ₂ O ₃ , Ta ₂ O ₅ , K ₃ Ta ₃ Si ₂ O ₃ , WO ₃ , SnO ₂ , Bi ₂ O ₃ , BiVO ₄ , NiO, Cu ₂ O, SiC, MoS _2, InPb, RuO ₂ , CeO ₂ or the like, and further it is also possible to apply Ti, Nb, Ta, photocatalyst particles are layered oxide containing at least one element selected from V.

Of these catalysts, TiO ₂ which is harmless and excellent in chemical stability is most preferable. As TiO ₂ , any of anatase, rutile and brookite can be used. In the compound containing the ladder structure represented by the general formula (1), the photocatalyst particles can be mixed and applied.

  In addition, the photocatalyst particles can be used before, after or before and after the treatment with the silane coupling agent, or further mixed in the silane coupling agent. After the photocatalyst particles are applied and dried, heat treatment and light irradiation can be performed as necessary. As the type of light irradiation, ultraviolet light, visible light, and infrared light can be used, but it is most preferable to use ultraviolet light.

(Adhesion improver)
As the adhesion improver, a thermosetting resin, a thermoplastic resin, or a mixed resin thereof can be used, but a thermosetting organic insulating material is preferably a main component.
Adhesion improvers include phenol resin, urea resin, melamine resin, alkyd resin, acrylic resin, unsaturated polyester resin, diallyl phthalate resin, epoxy resin, polybenzimidazole resin, polyamide resin, polyamideimide resin, silicone resin, cyclohexane Resin synthesized from pentadiene, resin containing tris (2-hydroxyethyl) isocyanurate, resin synthesized from aromatic nitrile, trimerized aromatic dicyanamide resin, resin containing triallyl trimethacrylate, furan resin, ketone resin, xylene Resins, thermosetting resins containing condensed polycyclic aromatics, benzocyclobutene resins, fluororesins, polyimide resins, polyphenylene oxide resins, polyphenylene sulfide resins, aramid resins, liquid crystal polymers, and the like can be used.

(Corrosion inhibitor)
A corrosion inhibitor can be applied to at least a part of the wiring surface, and the corrosion inhibitor only needs to contain at least one S-containing organic compound or N-containing organic compound.

Specific examples of the corrosion inhibitor include a compound containing a sulfur atom such as a mercapto group, sulfide group or disulfide group, or an N-containing organic compound containing —N═, N═N or NH ₂ in the molecule. Can be used in addition to the acidic solution, the alkaline solution or the coupling agent solution described above, and the corrosion inhibitor before or after the treatment with the solution containing the coupling agent. It is possible to perform the treatment using a solution containing.

(Compounds containing sulfur atoms such as mercapto groups, sulfide groups or disulfide groups)
As a compound containing a sulfur atom such as a mercapto group, a sulfide group or a disulfide group, an aliphatic thiol (HS— (CH ₂ ) _n —R (where n is an integer from 1 to 23, R is R represents preferably an amino group, an amide group, a carboxyl group, a carbonyl group, or a hydroxyl group, which is a monovalent organic group, a hydrogen group or a halogen atom. The alkyl group having 1 to 18 carbon atoms, the alkoxy group having 1 to 8 carbon atoms, the acyloxy group, the haloalkyl group, the halogen atom, the hydrogen group, the thioalkyl group, the thiol group, and optionally substituted phenyl Group, biphenyl group, naphthyl group, heterocyclic ring, etc. Further, there may be only one amino group, amide group, carboxyl group, hydroxyl group in R, Preferably, it may have one or more substituents such as the above-described alkyl group, etc. In the formula, it is preferable to use a compound in which n is an integer from 1 to 23, and n is 4 Compounds represented by integers up to 15 are more preferred, and compounds represented by integers up to 6-12 are more preferred, and thiazole derivatives (thiazole, 2-aminothiazole, 2-aminothiazole-4- Carboxylic acid, aminothiophene, benzothiazole, 2-mercaptobenzothiazole, 2-aminobenzothiazole, 2-amino-4-methylbenzothiazole, 2-benzothiazolol, 2,3-dihydroimidazo [2,1-b Benzothiazol-6-amine, 2- (2-aminothiazol-4-yl) -2-hydroxyiminoacetic acid ethyl, 2- Tilbenzothiazole, 2-phenylbenzothiazole, 2-amino-4-methylthiazole, etc.), thiadiazole derivatives (1,2,3-thiadiazole, 1,2,4-thiadiazole, 1,2,5-thiadiazole, 1, 3,4-thiadiazole, 2-amino-5-ethyl-1,3,4-thiadiazole, 5-amino-1,3,4-thiadiazole-2-thiol, 2,5-mercapto-1,3,4 Thiadiazole, 3-methylmercapto-5-mercapto-1,2,4-thiadiazole, 2-amino-1,3,4-thiadiazole, 2- (ethylamino) -1,3,4-thiadiazole, 2-amino- 5-ethylthio-1,3,4-thiadiazole, etc.), mercaptobenzoic acid, mercaptonaphthol, mercaptophenol, 4-methyl Captobiphenyl, mercaptoacetic acid, mercaptosuccinic acid, 3-mercaptopropionic acid, thiouracil, 3-thiourazole, 2-thiouramil, 4-thiouramil, 2-mercaptoquinoline, thioformic acid, 1-thiocoumarin, thiocomotiazone, thiocresol, thiosalicylic acid, Thiothianuric acid, thionaphthol, thiotolene, thionaphthene, thionaphthenecarboxylic acid, thionaphthenequinone, thiobarbituric acid, thiohydroquinone, thiophenol, thiophene, thiophthalide, thiophene, thiolthione carbonate, thiolutidone, thiolhistidine, 3-carboxypropyl disulfide, 2 -Hydroxyethyl disulfide, 2-aminopropionic acid, dithiodiglycolic acid, D-cysteine, di-t-butyl disulfide, thiosi Anne, thiocyanic acid and the like.

(Compound containing at least one N-containing organic compound containing —N═ or N═N or NH ₂ in the molecule)
Preferred compounds as the compound containing at least one N-containing organic compound containing —N═ or N═N or NH ₂ in the molecule are triazole derivatives (1H-1,2,3-triazole, 2H-1,2, 3-triazole, 1H-1,2,4-triazole, 4H-1,2,4-triazole, benzotriazole, 1-aminobenzotriazole, 3-amino-5-mercapto-1,2,4-triazole, 3 -Amino-1H-1,2,4-triazole, 3,5-diamino-1,2,4-triazole, 3-oxy-1,2,4-triazole, aminourazole, etc.), tetrazole derivatives (tetrazolyl, Tetrazolylhydrazine, 1H-1,2,3,4-tetrazole, 2H-1,2,3,4-tetrazole, 5-amino-1H-teto Razole, 1-ethyl-1,4-dihydroxy-5H-tetrazol-5-one, 5-mercapto-1-methyltetrazole, tetrazole mercaptan, etc.), oxazole derivatives (oxazole, oxazolyl, oxazoline, benzoxazole, 3-amino-5 -Methylisoxazole, 2-mercaptobenzoxazole, 2-aminooxazoline, 2-aminobenzoxazole, etc.), oxadiazole derivatives (1,2,3-oxadiazole, 1,2,4-oxadiazole, 1 , 2,5-oxadiazole, 1,3,4-oxadiazole, 1,2,4-oxadiazolone-5, 1,3,4-oxadiazolone-5, etc.), oxatriazole derivatives (1 , 2,3,4-oxatriazole, 1,2,3,5-oxatriazol Etc.), purine derivatives (purine, 2-amino-6-hydroxy-8-mercaptopurine, 2-amino-6-methylmercaptopurine, 2-mercaptoadenine, mercaptohypoxanthine, mercaptopurine, uric acid, guanine, adenine, xanthine , Theophylline, theobromine, caffeine, etc.), imidazole derivatives (imidazole, benzimidazole, 2-mercaptobenzimidazole, 4-amino-5-imidazolecarboxylic acid amide, histidine, etc.), indazole derivatives (indazole, 3-indazolone, indazolol, etc.) ), Pyridine derivatives (2-mercaptopyridine, aminopyridine, etc.), pyrimidine derivatives (2-mercaptopyrimidine, 2-aminopyrimidine, 4-aminopyrimidine, 2-amino-4,6-dihydride) Xypyrimidine, 4-amino-6-hydroxy-2-mercaptopyrimidine, 2-amino-4-hydroxy-6-methylpyrimidine, 4-amino-6-hydroxy-2-methylpyrimidine, 4-amino-6-hydroxypyrazolo [3,4-d] pyrimidine, 4-amino-6-mercaptopyrazolo [3,4-d] pyrimidine, 2-hydroxypyrimidine, 4-mercapto-1H-pyrazolo [3,4-d] pyrimidine, 4- Amino-2,6-dihydroxypyrimidine, 2,4-diamino-6-hydroxypyrimidine, 2,4,6-triaminopyrimidine, etc.), thiourea derivatives (thiourea, ethylenethiourea, 2-thiobarbituric acid, etc.) , Amino acids (glycine, alanine, tryptophan, proline, oxyproline, etc.), 1.3,4-thiooxy Sadiazolone-5, thiocoumazone, 2-thiocoumarin, thiosaccharin, thiohydantoin, thiopyrine, γ-thiopyrine, guanazine, guanazole, guanamine, oxazine, oxadiazine, melamine, 2,4,6-triaminophenol, triaminobenzene, aminoindole Aminoquinoline, aminothiophenol, aminopyrazole and the like.

(Corrosion inhibitor solution)
Water and an organic solvent can be used for the preparation of the solution containing the corrosion inhibitor. The type of the organic solvent is not particularly limited, but alcohols such as methanol, ethanol, n-propyl alcohol and n-butyl alcohol, ethers such as di-n-propyl ether, di-n-butyl ether and diallyl ether, Aliphatic hydrocarbons such as hexane, heptane, octane, and nonane, and aromatic hydrocarbons such as benzene, toluene, and phenol can be used, and these solvents can be used alone or in combination of two or more.

(Corrosion inhibitor concentration and treatment time)
The concentration of the corrosion inhibitor solution is preferably from 0.1 to 5000 ppm, more preferably from 0.5 to 3000 ppm, and even more preferably from 1 to 1000 ppm. When the concentration of the corrosion inhibitor is less than 0.1 ppm, the migration suppressing effect is not sufficient, and sufficient adhesion strength between the wiring and the insulating resin cannot be obtained. When the concentration of the corrosion inhibitor exceeds 5000 ppm, a migration suppressing effect can be obtained, but sufficient adhesion strength between the wiring and the insulating resin cannot be obtained. There is no restriction | limiting in particular about the time which processes a wiring surface with the solution containing a corrosion inhibitor, It is preferable to change suitably according to the kind and density | concentration of a corrosion inhibitor.

(L / S)
When wiring is formed by the semi-additive method, a plating resist is formed in a required pattern on a thin metal layer (seed layer), wiring is formed by electrolytic copper plating through the seed layer, and then the plating resist is peeled off. The cross-sectional area (S) of the wiring portion including the electrolytic copper plating layer and the seed layer under the electrolytic copper plating layer in the finished state, and the seed layer is removed by etching or the like, or the surface roughness Ra is 0 on the wiring surface. Including an electrolytic copper plating layer and a seed layer under the electrolytic copper plating layer after forming an insulating film containing at least one coupling agent or corrosion inhibitor by performing a treatment of 0.001 to 0.4 μm The area ratio (= S ′ / S) with respect to the cross-sectional area (S ′) of the wiring portion is preferably 0.5 to 1.0, more preferably 0.7 to 1.0.

(Electroless palladium plating reaction start acceleration pretreatment liquid, pretreatment method and substrate to which pretreatment is applied)
FIG. 1 and FIG. 8 show an embodiment (single-sided build-up layer) of a semiconductor chip mounting substrate which is an object to be plated to which the electroless palladium plating reaction initiation promoting pretreatment liquid and pretreatment method and pretreatment according to the present invention are applied. A cross-sectional schematic diagram of (two layers) is shown. Here, an embodiment in which the build-up layer is formed only on one side will be described, but the build-up layer may be formed on both sides as shown in FIG. 8 if necessary.

  The electroless palladium plating reaction start pretreatment liquid and pretreatment method according to the present invention, and the substrate to be plated to which the pretreatment is applied, the semiconductor chip mounting substrate, as shown in FIG. A first wiring 106 a including a semiconductor chip connection terminal and a first interlayer connection terminal 101 is formed on the core substrate 100 which is an insulating layer.

  A second wiring 106b including the second interlayer connection terminal 103 is formed on the other side of the core substrate, and the first interlayer connection terminal and the second interlayer connection terminal are connected to the first interlayer connection of the core substrate. It is electrically connected via an IVH (interstitial via hole) 102. A buildup layer 104 is formed on the second wiring side of the core substrate, and a third wiring 106c including a third interlayer connection terminal is formed on the buildup layer. The three interlayer connection terminals are electrically connected via the second interlayer connection IVH 108.

When a plurality of buildup layers are formed, the same structure is stacked, and external connection terminals 107 connected to the motherboard are formed on the outermost buildup layer. The shape of the wiring, the arrangement of each connection terminal, and the like are not particularly limited, and can be appropriately designed for manufacturing a semiconductor chip to be mounted and a target semiconductor package.
Further, the semiconductor chip connection terminal and the first interlayer connection terminal can be shared.
Furthermore, an insulating coating 109 such as a solder resist can be provided on the outermost buildup layer as necessary.

(Core substrate)
The material of the core substrate is not particularly limited, but an organic substrate, a ceramic substrate, a silicone substrate, a glass substrate, or the like can be used. In consideration of the thermal expansion coefficient and insulation, it is preferable to use ceramic or glass.

Among the non-photosensitive glasses, soda lime glass (component example: SiO ₂ 65 to 75 wt%, Al ₂ O ₃ 0.5 to ₄ wt%, CaO 5 to 15 wt%, MgO 0.5 to 4 wt%, Na ₂ O 10-20 wt%), borosilicate glass (component example: SiO ₂ 65-80 wt%, B ₂ O ₃ 5-25 wt%, Al ₂ O ₃ 1-5 wt%, CaO 5-8 wt%, MgO 0.5 ˜2 wt%, Na ₂ O 6-14 wt%, K ₂ O 1-6 wt%) and the like.
Also, it includes those containing gold ions and silver ions as a photosensitive agent into Li _{2 O-SiO} 2 based crystallized glass as photosensitive glass.

  As the organic substrate, a substrate or a resin film obtained by laminating a material in which a glass cloth is impregnated with a resin can be used. As the resin to be used, a thermosetting resin, a thermoplastic resin, or a mixed resin thereof can be used, but a thermosetting organic insulating material is preferable.

  Thermosetting resins include phenolic resin, urea resin, melamine resin, alkyd resin, acrylic resin, unsaturated polyester resin, diallyl phthalate resin, epoxy resin, polybenzimidazole resin, polyamide resin, polyamideimide resin, silicone resin, cyclohexane Resin synthesized from pentadiene, resin containing tris (2-hydroxyethyl) isocyanurate, resin synthesized from aromatic nitrile, trimerized aromatic dicyanamide resin, resin containing triallyl trimethacrylate, furan resin, ketone resin, xylene Resins, thermosetting resins containing condensed polycyclic aromatics, benzocyclobutene resins, and the like can be used.

Examples of the thermoplastic resin include polyimide resin, polyphenylene oxide resin, polyphenylene sulfide resin, aramid resin, and liquid crystal polymer.
A filler may be added to these resins. Examples of the filler include silica, talc, aluminum hydroxide, aluminum borate, aluminum nitride, and alumina.

  The thickness of the core substrate is preferably 100 to 800 μm from the viewpoint of IVH formation, and more preferably 150 to 500 μm.

(Build-up layer)
The interlayer insulating layer (build-up layer) 104 is made of an insulating material, and a thermosetting resin, a thermoplastic resin, or a mixed resin thereof can be used as the insulating material.
The build-up layer preferably contains a thermosetting organic insulating material as a main component.

  Thermosetting resins include phenolic resin, urea resin, melamine resin, alkyd resin, acrylic resin, unsaturated polyester resin, diallyl phthalate resin, epoxy resin, polybenzimidazole resin, polyamide resin, polyamideimide resin, silicone resin, cyclohexane Resin synthesized from pentadiene, resin containing tris (2-hydroxyethyl) isocyanurate, resin synthesized from aromatic nitrile, trimerized aromatic dicyanamide resin, resin containing triallyl trimethacrylate, furan resin, ketone resin, xylene Resins, thermosetting resins containing condensed polycyclic aromatics, benzocyclobutene resins, and the like can be used.

  Examples of the thermoplastic resin include polyimide resin, polyphenylene oxide resin, polyphenylene sulfide resin, aramid resin, and liquid crystal polymer.

  A filler may be added to the insulating material. Examples of the filler include silica, talc, aluminum hydroxide, aluminum borate, aluminum nitride, and alumina.

(Coefficient of thermal expansion)
It is preferable that the thermal expansion coefficient of the semiconductor chip and the thermal expansion coefficient of the core substrate are approximated, and that the thermal expansion coefficient of the core substrate and the thermal expansion coefficient of the buildup layer are approximated. It is not a thing. Further, when the thermal expansion coefficients of the semiconductor chip, the core substrate, and the buildup layer are α1, α2, and α3 (ppm / ° C.), it is more preferable that α1 ≦ α2 ≦ α3.

  Specifically, the thermal expansion coefficient α2 of the core substrate is preferably 7 to 13 ppm / ° C, and more preferably 9 to 11 ppm / ° C. The thermal expansion coefficient α3 of the buildup layer is preferably 10 to 40 ppm / ° C, more preferably 10 to 20 ppm / ° C, and further preferably 11 to 17 ppm / ° C.

(Young's modulus)
The Young's modulus of the buildup layer is preferably 1 to 5 GPa in terms of stress relaxation against thermal stress. It is preferable to add the filler in the buildup layer by appropriately adjusting the addition amount so that the thermal expansion coefficient of the buildup layer is 10 to 40 ppm / ° C. and the Young's modulus is 1 to 5 GPa.

(Manufacturing method of a semiconductor chip mounting substrate, which is an object to be plated to which the pretreatment liquid and the electroless palladium plating reaction start acceleration pretreatment solution according to the present invention are applied)
A semiconductor chip mounting substrate, which is an object to be plated, to which the pretreatment solution and the pretreatment solution for promoting electroless palladium plating reaction according to the present invention are applied, can be produced by a combination of the following production methods. The order of the manufacturing process is not particularly limited as long as it does not depart from the object of the present invention.

(Wiring formation method)
As a method of forming wiring, a metal foil is formed on the core substrate surface or build-up layer, and unnecessary portions of the metal foil are removed by etching (subtract method). A method of forming wiring only by plating (additive method), forming a thin metal layer (seed layer) on the core substrate surface or build-up layer, and then forming the necessary wiring by electrolytic plating, then thin metal There is a method of removing the layer by etching (semi-additive method).

(Wiring formation by etching)
An etching resist is formed in a portion that becomes a wiring of the metal foil, and a chemical etching solution is sprayed and sprayed on a portion exposed from the etching resist, and unnecessary metal foil is removed by etching to form a wiring. For example, when a copper foil is used as the metal foil, an etching resist material that can be used for an ordinary wiring board can be used as the etching resist.

  For example, a resist ink is silkscreen printed to form an etching resist, or a negative photosensitive dry film for etching resist is laminated on a copper foil, and a photomask that transmits light on the wiring shape is formed thereon. Overlap, exposure with ultraviolet rays is performed, and portions not exposed are removed with a developer to form an etching resist.

  As the chemical etching solution, a chemical etching solution used for a normal wiring board, such as a solution of cupric chloride and hydrochloric acid, a ferric chloride solution, a solution of sulfuric acid and hydrogen peroxide, and an ammonium persulfate solution can be used.

(Wiring formation by plating)
Also, the wiring can be formed only by performing plating only on necessary portions on the core substrate or the build-up layer, and a wiring forming technique by normal plating can be used. For example, after depositing the electroless plating catalyst on the core substrate, forming a plating resist on the surface portion where plating is not performed, immersing in an electroless plating solution, and only in locations not covered by the plating resist, Electroless plating is performed to form wiring.

(Wiring formation by semi-additive method)
As a method of forming a seed layer of the semi-additive method on the surface of the core substrate or the build-up layer, there are a method by vapor deposition or plating and a method of bonding a metal foil. Also, a subtractive metal foil can be formed by the same method.

(Formation of seed layer by vapor deposition or plating)
A seed layer can be formed on the core substrate surface or the build-up layer by vapor deposition or plating. For example, when a base metal and a thin film copper layer are formed by sputtering as a seed layer, the sputtering apparatus used to form the thin film copper layer is a bipolar sputtering, a three-pole sputtering, a four-pole sputtering, a magnetron sputtering, a mirror. Tron sputtering or the like can be used.

The target used for sputtering is sputtered 5 to 50 nm using, for example, a metal such as Cr, Ni, Co, Pd, Zr, Ni / Cr, or Ni / Cu as a base metal in order to ensure adhesion. Thereafter, a seed layer can be formed by sputtering 200 to 500 nm using copper as a target.
Moreover, it can also form by plating 0.5-3 micrometers electroless copper plating on the core substrate surface or a buildup layer.

(Method of bonding metal foil)
When the core substrate or the build-up layer has an adhesive function, the seed layer can be formed by bonding metal foils by pressing or laminating. However, since it is very difficult to directly bond a thin metal layer, there are a method of thinning a metal foil with a carrier after laminating a thick metal foil, a method of peeling a carrier layer after laminating a metal foil with a carrier, etc. is there.

For example, the former has a three-layer copper foil of carrier copper / nickel / thin film copper, the carrier copper is removed with an alkaline etching solution, nickel is removed with a nickel etching solution, and the latter is made of aluminum, copper, insulating resin, etc. The peelable copper foil can be used, and a seed layer of 5 μm or less can be formed.
Alternatively, a 9 to 18 μm thick copper foil may be attached, and the seed layer may be formed by etching so that the thickness is 5 μm or less.

(Semi-additive wiring formation)
A plating resist is formed in a necessary pattern on the seed layer formed by the above-described method, and wiring is formed by electrolytic copper plating through the seed layer. Thereafter, the plating resist is peeled off, and finally the seed layer is removed by etching or the like to form a wiring.

(Wiring shape)
The shape of the wiring is not particularly limited, but at least a semiconductor chip connection terminal 16 (wire bond terminal or the like) is provided on the side on which the semiconductor chip is mounted, and an external connection connection terminal (solder) electrically connected to the motherboard on the opposite side. A place where a ball or the like is mounted), a developed wiring that connects them, an interlayer connection terminal, and the like.

  The wiring arrangement is not particularly limited, but as shown in FIG. 3 (inner layer wiring, interlayer connection terminals, etc. are omitted), a fan-in type in which external connection terminals are formed inside the semiconductor chip connection terminals, or FIG. The fan-out type in which external connection terminals are formed outside the semiconductor chip connection terminals as shown in FIG.

  FIG. 5 is a plan view of the fan-in type semiconductor chip mounting substrate, and FIG. 6 is a plan view of the fan-out type semiconductor chip mounting substrate. The shape of the semiconductor chip connection terminal 16 is not particularly limited as long as wire bond connection or flip chip connection is possible. Moreover, wire-bond connection or flip-chip connection is possible for both fan-out and fan-in types.

  Furthermore, if necessary, a dummy pattern 21 (see FIG. 6) that is not electrically connected to the semiconductor chip may be formed. The shape and arrangement of the dummy pattern are not particularly limited, but it is preferable to arrange the dummy pattern uniformly in the semiconductor mounting region. As a result, voids are less likely to occur when a semiconductor chip is mounted with a die bond adhesive, and reliability can be improved.

(Bahia Hall)
Since the semiconductor chip mounting substrate has a plurality of wiring layers, via holes for electrically connecting the wirings of the respective layers can be provided. The via hole can be formed by providing a connection hole in the core substrate or the build-up layer and filling the hole with a conductive paste or plating. Examples of the hole processing method include mechanical processing such as punching and drilling, laser processing, chemical etching processing using a chemical solution, and dry etching using plasma.

  In addition, as a method for forming a via hole in the buildup layer, there is a method in which a conductive layer is formed in advance on the buildup layer with a conductive paste or plating, and this is laminated on a core substrate by pressing or the like.

(Formation of insulation coating)
An insulating coating can be formed on the external connection terminal side of the semiconductor chip mounting substrate. The pattern can be formed by printing if it is a varnish-like material, but it is preferable to use a photosensitive solder resist, a coverlay film, or a film-like resist in order to ensure higher accuracy. As a material, an epoxy-based material, a polyimide-based material, an epoxy acrylate-based material, or a fluorene-based material can be used.

  Since such an insulating coating has shrinkage at the time of curing, if it is formed only on one side, a large warp tends to occur on the substrate. Therefore, an insulating coating can be formed on both surfaces of the semiconductor chip mounting substrate as necessary. Furthermore, since the warpage varies depending on the thickness of the insulating coating, it is more preferable to adjust the thickness of the insulating coating on both sides so that no warpage occurs.

In that case, it is preferable to conduct preliminary examination and determine the thicknesses of the insulating coatings on both sides.
In order to obtain a thin semiconductor package, the thickness of the insulating coating is preferably 50 μm or less, and more preferably 30 μm or less.

(Terminal plating)
Electroless nickel plating film having a lead concentration of 0.01 wt% or less on the surface of copper formed as semiconductor chip connection terminals 16 (wire bond terminals, etc.) and external connection terminals (locations where solder balls are mounted) The replacement palladium plating film or the electroless palladium plating film, the replacement gold plating film, and the electroless gold plating film are formed in this order.

(Electroless palladium plating reaction start acceleration pretreatment liquid, pretreatment method, and method for producing a plated object to which pretreatment is applied)
A semiconductor chip mounting substrate, which is an object to be plated, to which the treatment and pretreatment method using the electroless palladium plating reaction start acceleration pretreatment liquid is applied can be manufactured by the following steps.

  2A to 2G are schematic cross-sectional views showing an example of an embodiment of a method for manufacturing a semiconductor chip mounting substrate to which the treatment and pretreatment method using the electroless palladium plating reaction initiation promoting pretreatment liquid according to the present invention are applied. Shown in the figure. However, the order of the manufacturing process is not particularly limited as long as it does not depart from the object of the present invention.

(Process a)
(Step a) is a step of forming the first wiring 106a on the core substrate 100 as shown in FIG.

  For example, an etching resist can be formed in a first wiring shape on a core substrate having a copper layer formed on one side, and wiring can be produced using an etching solution such as copper chloride or iron chloride. In order to produce a copper layer on a substrate, a copper layer can be obtained by forming a thin film by sputtering, vapor deposition, plating or the like and then plating the film to a desired thickness by electrolytic copper plating.

  Note that the first wiring 106a includes the first interlayer connection terminal 101 and the semiconductor chip connection terminal (portion electrically connected to the semiconductor chip), and a semi-additive method is used as a method for forming the fine wiring. May be.

(Process b)
In step (b), as shown in FIG. 2B, a first interlayer connection IVH 102 (via hole) for connecting the first interlayer connection terminal 101 and a second wiring to be described later is formed. It is a process of forming.

The via hole can be formed by using laser light when the core substrate is a non-photosensitive substrate. Examples of the non-photosensitive substrate include, but are not limited to, the non-photosensitive glass described above. In this case, the laser beam to be used is not limited, and a CO ₂ laser, a YAG laser, an excimer laser, or the like can be used.

  When the core substrate is a photosensitive base material, a region other than the via hole is masked, and the via hole portion is irradiated with ultraviolet light. Examples of the photosensitive base material include the above-described photosensitive glass, but are not limited thereto.

In this case, via holes are formed by heat treatment and etching after irradiation with ultraviolet light.
Further, when the core substrate is a base material that can be chemically etched by a chemical solution such as an organic solvent, a via hole can be formed by chemical etching. The formed via hole can be filled with a conductive paste or plating to form an electrically conductive layer for interlayer connection in order to electrically connect the interlayer.

(Process c)
Step (c) is a step of forming the second wiring 106b on the surface of the core substrate opposite to the first wiring 106a, as shown in FIG. 2 (c). A copper layer is formed on the surface opposite to the first wiring of the core substrate in the same manner as in the step (a), an etching resist is formed on the copper layer in a necessary wiring shape, and an etching solution such as copper chloride or iron chloride is added The second wiring is formed by using this.

  As a method for forming a copper layer, a copper layer is obtained by forming a copper thin film by sputtering, vapor deposition, electroless plating, etc. in the same manner as in (Step a), and then copper plating to a desired thickness using electrolytic copper plating. It is done.

  Note that the second wiring includes the second interlayer connection terminal 103, and a semi-additive method may be used as a method for forming the fine wiring.

(Process d)
(Step d) is a step of forming a buildup layer (interlayer insulating layer) 104 on the surface on which the second wiring is formed as shown in FIG. First, the degreasing treatment or sulfuric acid cleaning is performed on the second wiring surface. It is immersed in an aqueous solution containing an acid, an alkali or an oxidizing agent, and the treatment is carried out so that the Ra (average roughness) of the copper wiring surface becomes 0.01 to 0.4 μm.

  When immersed in an aqueous solution containing an oxidizing agent, the surface of the copper wiring surface is set to 0.01 to 0.4 μm by further immersion in an aqueous solution containing a reducing agent and reducing the copper oxide film. Process.

  Next, a metal selected from copper, tin, chromium, nickel, zinc, aluminum, cobalt, gold, platinum, silver, palladium or an alloy containing the metal is electrolessly plated, electroplated, displacement reaction, spray sprayed, and applied. By such a method, the processing is performed so that the Ra of the wiring surface becomes 0.01 to 0.4 μm.

  A compound having a Si—O—Si bond is formed on the surface, followed by treatment with a solution containing at least one coupling agent or adhesion improver to form a very thin insulating film on the second wiring surface. Form.

  Next, the buildup layer 104 is formed on the surface of the core substrate 100 and the surface of the second wiring 106b. As the insulating material of the buildup layer 104, a thermosetting resin, a thermoplastic resin, or a mixed resin thereof can be used as described above, but it is preferable that the thermosetting material is a main component.

  In the case of a varnish-like material, the build-up layer can be obtained by printing or spin coating or in the case of a film-like insulating material by using a technique such as laminating or pressing. When the insulating material includes a thermosetting material, it is desirable to further heat and cure.

(Process e)
(Step e) is a step of forming a second interlayer connection IVH (via hole) 108 in the build-up layer, as shown in FIG. 2 (e). A typical laser drilling device can be used. A CO ₂ laser, a YAG laser, an excimer laser, or the like can be used as the type of laser used in the laser drilling machine, but a CO ₂ laser is preferable in terms of productivity and hole quality.

Further, when the IVH diameter is less than 30 μm, a YAG laser capable of focusing the laser beam is suitable.
Further, when the build-up layer is a material that can be chemically etched by a chemical solution such as an organic solvent, a via hole can be formed by chemical etching.

(Process f)
(Step f) is a step of forming a third wiring 106c on the build-up layer in which the second via hole is formed, as shown in FIG. 2 (f).
Moreover, as a process for forming fine wiring with L / S = 35 μm / 35 μm or less, the above-described semi-additive method is preferable.

  A seed layer is formed on the buildup layer by a method such as vapor deposition or plating or a method of bonding a metal foil. A plating resist is formed in a necessary pattern on the seed layer formed by the above-described method, and wiring is formed by electrolytic copper plating through the seed layer. Thereafter, the plating resist is peeled off, and finally the seed layer is removed by etching or the like to form fine wiring.

  (Steps d) to (step f) may be repeated to produce two or more buildup layers 104 as shown in FIG. In this case, the interlayer connection terminal formed in the outermost buildup layer becomes the external connection terminal 107.

(Process g)
In step (g), as shown in FIG. 2 (g), a step of forming an insulating coating 109 for protecting wirings other than external connection terminals, semiconductor chip connection terminals 16 (wire bond terminals, etc.), and external connection Electroless nickel plating film, substituted palladium plating film or electroless palladium plating film with a lead concentration of 0.01 wt% or less on the surface of copper formed as a connection terminal (where solder balls are mounted), replacement gold In this process, the plating film and the electroless gold plating film are formed in this order.

  As the insulating coating material, a solder resist is generally used, and a thermosetting type or an ultraviolet curing type can be used, but an ultraviolet curing type capable of finishing the resist shape with high accuracy is preferable.

(Shape of semiconductor chip mounting substrate)
The shape of the semiconductor chip mounting substrate 22 is not particularly limited, but is preferably a frame shape as shown in FIG. By making the shape of the semiconductor chip mounting substrate in this way, it is possible to efficiently assemble the semiconductor package. Hereinafter, a preferable frame shape will be described in detail.

As shown in FIG. 7, a block 23 is formed in which a plurality of semiconductor package regions 13 (parts to be a single semiconductor package) are arranged in rows and columns at regular intervals.
Further, such a block is formed in a plurality of rows and columns. Although only two blocks are shown in FIG. 7, the blocks may be arranged in a lattice shape as necessary.

Here, the width of the space between the semiconductor package regions is preferably 50 to 500 μm, and more preferably 100 to 300 μm.
Furthermore, it is most preferable that the blade width of the dicer used when the semiconductor package is cut later is made the same.

By arranging the semiconductor package region in this way, the semiconductor chip mounting substrate can be effectively used.
Further, it is preferable to form a positioning mark 11 or the like at the end of the semiconductor chip mounting substrate, and it is more preferable that the pin hole is a through hole. The shape and arrangement of the pin holes may be selected so as to match the forming method and the semiconductor package assembly apparatus.

  Furthermore, it is preferable to form a reinforcing pattern 24 in the space between the semiconductor package regions or outside the block. The reinforcing pattern may be separately manufactured and bonded to the semiconductor chip mounting substrate, but is preferably a metal pattern formed at the same time as the wiring formed in the semiconductor package region, and the surface thereof is similar to the wiring. More preferably, nickel, gold, or the like is plated or an insulating coating is applied.

When the reinforcing pattern is such a metal, it can also be used as a plating lead for electrolytic plating.
Moreover, it is preferable to form the cutting position alignment mark 25 at the time of cutting with a dicer outside the block. In this way, a frame-shaped semiconductor chip mounting substrate can be manufactured.

(Semiconductor package)
FIG. 3 is a schematic cross-sectional view showing an example of an embodiment of the flip chip type semiconductor package of the present invention. As shown in FIG. 3, the semiconductor package according to the present invention has a semiconductor chip 111 mounted on the semiconductor chip mounting substrate, and flips the semiconductor chip and the semiconductor chip connection terminals using connection bumps 112. It can be obtained by electrical connection by chip connection.

  Further, in these semiconductor packages, it is preferable to seal between the semiconductor chip and the semiconductor chip mounting substrate with an underfill material 113 as shown in the figure. The thermal expansion coefficient of the underfill material is preferably close to the thermal expansion coefficient of the semiconductor chip and the core substrate 100, but is not limited thereto. Preferably, (thermal expansion coefficient of the semiconductor chip) ≦ (thermal expansion coefficient of the underfill material) ≦ (thermal expansion coefficient of the core substrate).

The semiconductor chip can be mounted using an anisotropic conductive film (ACF) or an adhesive film (NCF) that does not contain conductive particles. In this case, since it is not necessary to seal with an underfill material, it is more preferable.
Furthermore, it is particularly preferable to use ultrasonic waves together with the semiconductor chip because electrical connection can be made at a low temperature and in a short time.

  FIG. 4 shows a cross-sectional view of an embodiment of a wire bond type semiconductor package. Although a general die bond paste can be used for mounting the semiconductor chip, it is more preferable to use a die bond film 117. The electrical connection between the semiconductor chip and the semiconductor chip connection terminal is generally performed by wire bonding using a gold wire 115. The semiconductor chip can be sealed by transfer molding using a semiconductor sealing resin 116.

  In that case, at least the face surface of the semiconductor chip is sealed with a semiconductor sealing resin, but only a necessary portion of the sealing region may be sealed, but the entire semiconductor package region is sealed as shown in FIG. It is more preferable to stop. This is a particularly effective method in the case where a plurality of semiconductor package regions are arranged in rows and columns and the substrate and the sealing resin are cut simultaneously with a dicer or the like.

For example, solder balls 114 can be mounted on the external connection terminals for electrical connection with the motherboard. For the solder balls, eutectic solder or Pb-free solder is used. As a method for fixing the solder balls to the external connection terminals, an N ₂ reflow device is generally used, but the method is not limited thereto.

  In the case of a semiconductor chip mounting substrate in which a plurality of semiconductor package regions are arranged in rows and columns, finally, each semiconductor package is cut using a dicer or the like.

EXAMPLES Hereinafter, although this invention is demonstrated in detail based on an Example, this invention is not restrict | limited to this.
Example 1
(Process a)
A 0.4 mm thick soda glass substrate (thermal expansion coefficient: 11 ppm / ° C.) was prepared as the core substrate 100, a 200 nm copper thin film was formed on one side by sputtering, and then plated to a thickness of 10 μm by electrolytic copper plating. Sputtering was performed under the condition 1 shown below using a device model number MLH-6315 manufactured by Nippon Vacuum Technology Co., Ltd.

  Thereafter, an etching resist is formed in a portion to be the first wiring 106a, and etching is performed using a ferric chloride etchant, thereby the first wiring 106a (including the first interlayer connection terminal 101 and the semiconductor chip connection terminal). Formed.

<Condition 1>
Current: 3.5A
Voltage: 500V
Argon flow rate: 35 SCCM
Pressure: 5 × 10 ⁻³ Torr (4.9 × 10 ⁻² Pa)
Deposition rate: 5 nm / second

(Process b)
An IVH hole having a hole diameter of 50 μm was formed with a laser until it reached the first interlayer connection terminal from the surface opposite to the first wiring of the glass substrate on which the first wiring was formed. YAG laser LAVIA-UV2000 (manufactured by Sumitomo Heavy Industries, Ltd., trade name) was used as the laser, and IVH holes were formed under the conditions of a frequency of 4 kHz, a shot number of 50, and a mask diameter of 0.4 mm.

  The obtained IVH hole was filled with conductive paste MP-200V (trade name, manufactured by Hitachi Chemical Co., Ltd.), cured at 160 ° C. for 30 minutes, and electrically connected to the first interlayer connection terminal of the glass substrate. The first interlayer connection IVH (via hole) was formed.

(Process c)
In order to electrically connect with the first interlayer connection IVH (first via hole) formed in (Step b), 200 nm copper is sputtered on the surface of the glass substrate opposite to the first wiring. After forming the thin film, plating was performed to a thickness of 10 μm by electrolytic copper plating. Sputtering was performed in the same manner as in (Step a).

  Further, as in (Step a), an etching resist is formed in the shape of the second wiring, and etching is performed using a ferric chloride etchant to perform the second wiring 106b (including the second interlayer connection terminal 103). Formed.

(Process d)
After immersing in the acid degreasing solution Z-2000 (trade name, manufactured by World Metal Co., Ltd.) adjusted to 200 ml / l on the second wiring side surface formed in (Step c) at a liquid temperature of 50 ° C. for 2 minutes, It was washed with hot water by immersing it in water at a liquid temperature of 50 ° C. for 2 minutes, and further washed with water for 1 minute.

  Subsequently, it was immersed in a 100 ml / l sulfuric acid aqueous solution for 1 minute and washed with water for 1 minute. After performing the pretreatment shown above, the concentration of the imidazole silane coupling agent IS-1000 (trade name, manufactured by Japan Energy Co., Ltd.) is 0.55 wt% in the aqueous solution adjusted to pH 5 with acetic acid. It was immersed for 10 minutes in the adjusted aqueous solution. After further washing with water for 1 minute, drying was performed at room temperature.

Next, the buildup layer 104 was formed as follows. That is, cyanate - After 10μm formed at 1500min ^-1 by Toesuteru system spin coating an insulating varnish of the resin composition was heated from room temperature to 230 ° C. at a heating rate of 6 ℃ · ^{min -1,} 1 hour at 230 ° C. By holding, it was thermoset to form a build-up layer.

(Process e)
An IVH hole having a hole diameter of 50 μm was formed with a laser until reaching the second interlayer connection terminal 103 from the surface of the buildup layer 104. YAG laser LAVIA-UV2000 (manufactured by Sumitomo Heavy Industries, Ltd., trade name) was used as the laser, and IVH holes were formed under the conditions of a frequency of 4 kHz, a shot number of 20 and a mask diameter of 0.4 mm.

(Process f)
In order to form the third wiring and the second via hole, a base metal Ni layer 20 nm serving as a seed layer was formed by sputtering, and a thin film copper layer 200 nm was further formed. Sputtering was performed under the condition 2 shown below using a product name MLH-6315 manufactured by Nippon Vacuum Technology Co., Ltd.

<Condition 2>
(nickel)
Current: 5.0A
Voltage: 500V
Voltage argon flow rate: 35 SCCM
Pressure: 5 × 10 −3 Torr (4.9 × 10 −2 Pa)
Deposition rate: 0.3 nm / second

(copper)
Current: 5.0A
Voltage: 500V
Argon flow rate: 35 SCCM
Pressure: 5 × 10 −3 Torr (4.9 × 10 −2 Pa)
Deposition rate: 5 nm / second

Next, a plating resist layer having a thickness of 20 μm was formed on the seed layer by spin coating using a plating resist PMER P-LA900PM (trade name, manufactured by Tokyo Ohka Kogyo Co., Ltd.). Exposure was performed at 1000 mJ / cm ² , and immersion rocking was performed at 23 ° C. for 6 minutes using PMER developer P-7G to form a resist pattern of L / S = 10 μm / 10 μm. Then, pattern copper plating was performed 5 micrometers using the copper sulfate plating solution.

The plating resist was removed by dipping for 1 minute at room temperature (25 ° C.) using methyl ethyl ketone.
For quick etching of the seed layer, a 5-fold diluted solution of CPE-700 (manufactured by Mitsubishi Gas Chemical Co., Ltd., trade name) is used for etching removal by immersing and shaking at 30 ° C. for 30 seconds, and wiring. Formed.

(Process g)
Thereafter, the steps (d) to (step f) are repeated again to form one more layer of the outermost layer wiring including the buildup layer and the external connection terminal 107, and finally the solder resist 109 is formed. A fan-in type BGA semiconductor chip mounting substrate as shown in FIG. 5 (sectional view of one package), FIG. 5 (plan view of one package) and FIG. 7 (overall view of the semiconductor chip mounting substrate) was produced.

  At this time, the first BGA semiconductor chip mounting substrate having an opening diameter of 600 μm above the external connection terminal 107 opened by exposure, development, and removal after being coated with the solder resist 109, has a diameter of 300 μm. The second BGA semiconductor chip mounting substrate, the third BGA semiconductor chip mounting substrate having a diameter of 200 μm, the fourth BGA semiconductor chip mounting substrate having a diameter of 100 μm, and the fifth BGA semiconductor chip having a diameter of 75 μm A mounting substrate was produced.

(Process h)
The first to fifth BGA semiconductor chip mounting substrates are immersed in a degreasing solution Z-200 (trade name, manufactured by World Metal Co., Ltd.) at 50 ° C. for 3 minutes, washed with water for 2 minutes, and then 100 g / l. It was immersed in an ammonium persulfate solution for 1 minute, washed with water for 2 minutes, immersed in 10% sulfuric acid for 1 minute, and washed with water for 2 minutes. Subsequently, immersion treatment was performed at 25 ° C. for 5 minutes in SA-100 (trade name, manufactured by Hitachi Chemical Co., Ltd.), which is a plating activation treatment solution, and washed with water for 2 minutes.

(Process i)
Subsequently, it was immersed in NIPS-100 (trade name, manufactured by Hitachi Chemical Co., Ltd.), which is an electroless nickel plating solution, for 25 minutes at 85 ° C. and washed with water for 1 minute.

(Process j)
Subsequently, an immersion treatment was performed at 50 ° C. for 1 minute in an electroless palladium plating reaction start acceleration pretreatment liquid that promotes the start of the electroless palladium plating reaction having the following composition.
Ethylenediamine: 0.1 mol / l
Sodium hypophosphite: 0.1 mol / l
pH: 8
(PH is adjusted with NaOH or HCl)

(Process k)
Subsequently, TPD-30 (Uemura Kogyo Co., Ltd., trade name), which is an electroless palladium plating solution capable of forming an electroless palladium plating film having a purity of palladium of 90% by weight or more, is applied at 50 ° C. for 8 minutes 20 Second, it was dipped and washed with water for 1 minute. The purity of palladium at this time was approximately 95.5% by weight (palladium: 95.5% by weight, phosphorus: 4.5% by weight), and the film thickness was 0.1 μm.

(Process l)
Then, it immersed in HGS-100 (Hitachi Chemical Co., Ltd., brand name) which is a substitution gold plating solution for 10 minutes at 85 degreeC, and washed with water for 1 minute.

(Process m)
Subsequently, it was immersed in HGS-2000 (trade name, manufactured by Hitachi Chemical Co., Ltd.), which is an electroless gold plating solution, at 70 ° C. for 30 minutes and washed with water for 5 minutes. The total thickness of the displacement gold plating and electroless gold plating film at this time was 0.3 μm.

<Solder connection reliability>
About the semiconductor chip mounting substrate obtained above, the connection reliability of the connection terminals was evaluated according to the following criteria.

  For the first semiconductor chip mounting substrate with an opening diameter of 600 μm, 0.76 mm (φ) Sn-3.0Ag-0.5Cu solder ball is mounted on the second semiconductor chip mounting with an opening diameter of 300 μm. For the substrate, 0.45 mm (φ) Sn-3.0Ag-0.5Cu solder ball, and for the first semiconductor chip mounting substrate having an opening diameter of 200 μm, 0.30 mm (φ) Sn— For a second semiconductor chip mounting substrate having a 3.0Ag-0.5Cu solder ball and an opening diameter of 100 μm, an Sn-3.0Ag-0.5Cu solder ball having an opening diameter of 0.15 mm (φ) For the first semiconductor chip mounting substrate having a diameter of 75 μm, 0.12 mm (φ) Sn-3.0Ag-0.5Cu solder balls are used, and 10 of each of the first to fifth substrates. Connected to 0 solder connection terminals in a refree oven (peak temperature 252 ° C) and using an impact-resistant high-speed bond tester 4000HS (trade name, manufactured by Daisy), share of solder balls under the condition of 200 mm / sec. A (shear) test was performed, and the solder connection strength was evaluated according to the following criteria. The results are shown in Table 1. In addition, A, B, C, and D shown in Table 1 indicate the following states.

A: Breakage due to shearing in the solder balls at all 1000 connection terminals.
B: There are 1 or more and 10 or less breaks in a mode other than shear breakage in a solder ball.
C: There are 11 or more and 50 or less breaks in modes other than shear breakage in the solder balls.
D: There are 51 or more breaks due to modes other than shear breakage in the solder balls.

<Electroless palladium plating film thickness>
The thickness of the electroless palladium plating film at the external connection terminal 107 of each of the produced semiconductor chip mounting substrates 1 to 5 was measured with a fluorescent X-ray film thickness measuring device. In addition, the number of measurement locations is 1000 locations. When a 1 cm x 1 cm hull cell test copper plate (manufactured by Yamamoto Metal Tester Co., Ltd., trade name) is used, the same steps as steps hm are performed, and the film thickness of the electroless palladium plating on this copper plate is 100%. The film thickness at the external connection terminal was evaluated according to the following evaluation criteria, and the precipitation at the external connection terminal was examined. The results are shown in Table 1. In addition, A, B, C, and D shown in Table 1 indicate the following states.

A: The film thickness is 90% or more in all 1000 connection terminals.
B: There are 1 to 10 terminals lower than 90%.
C: There are 11 or more and 50 or less terminals that are lower than 90%.
D: There are 51 or more terminals lower than 90%.

Example 2
Instead of the electroless palladium plating reaction start acceleration pretreatment liquid for promoting the start of the electroless palladium plating reaction shown in step j of Example 1, the electroless palladium plating reaction start acceleration pretreatment liquid having the following composition was used. Except for the change, the procedure was the same as in Example 1. The results are shown in Table 1.
Ethylenediamine: 0.1 mol / l
Citric acid: 0.2 mol / l
Sodium hypophosphite: 0.1 mol / l
pH: 8
(PH is adjusted with NaOH or HCl)

Example 3
Instead of the electroless palladium plating reaction start acceleration pretreatment liquid for promoting the start of the electroless palladium plating reaction shown in step j of Example 1, the electroless palladium plating reaction start acceleration pretreatment liquid having the following composition was used. Except for the change, the procedure was the same as in Example 1. The results are shown in Table 1.
Ethylenediamine: 0.1 mol / l
Glycine: 0.3 mol / l
Sodium hypophosphite: 0.1 mol / l
pH: 8
(PH is adjusted with NaOH or HCl)

Example 4
Instead of the electroless palladium plating reaction start acceleration pretreatment liquid for promoting the start of the electroless palladium plating reaction shown in step j of Example 1, the electroless palladium plating reaction start acceleration pretreatment liquid having the following composition was used. Except for the change, the procedure was the same as in Example 1. The results are shown in Table 1.
Ethylenediamine: 0.1 mol / l
Glycine: 0.3 mol / l
Sodium hypophosphite: 0.1 mol / l
Ethanol: 0.4 ml / l
pH: 8
(PH is adjusted with NaOH or HCl)

Example 5
Instead of the electroless palladium plating reaction start acceleration pretreatment liquid for promoting the start of the electroless palladium plating reaction shown in step j of Example 1, the electroless palladium plating reaction start acceleration pretreatment liquid having the following composition was used. Except for the change, the procedure was the same as in Example 1. The results are shown in Table 1.
28% NH ₄ OH: 160 ml / l
NH ₄ Cl: 0.15 mol / l
Sodium hypophosphite: 0.1 mol / l
pH: 8
(PH is adjusted with NaOH or HCl)

Example 6
Instead of the electroless palladium plating reaction start acceleration pretreatment liquid for promoting the start of the electroless palladium plating reaction shown in step j of Example 1, the electroless palladium plating reaction start acceleration pretreatment liquid having the following composition was used. Except for the change, the procedure was the same as in Example 1. The results are shown in Table 1.
28% NH ₄ OH: 160 ml / l
EDTA ₄ Na: 0.1 mol / l
Sodium hypophosphite: 0.1 mol / l
pH: 8
(PH is adjusted with NaOH or HCl)

Example 7
In step k shown in Example 1, an electroless palladium plating solution having the following composition was used in place of TPD-30 (Uemura Kogyo Co., Ltd., trade name), and immersion treatment was performed at 50 ° C. for 6 minutes, followed by washing with water for 1 minute. Otherwise, the same process as in Example 1 was performed. The purity of palladium at this time was approximately 97% by weight (palladium: 97% by weight, phosphorus: 3% by weight), and the film thickness was 0.1 μm. The results are shown in Table 1.
Palladium chloride: 0.01 mol / l
Ethylenediamine: 0.08 mol / l
Sodium hypophosphite: 0.03 mol / l
Thiodiglycolic acid: 10ppm
pH: 8

Example 8
In step k shown in Example 1, an electroless palladium plating solution having the following composition was used in place of TPD-30 (Uemura Kogyo Co., Ltd., trade name), and immersion treatment was performed at 50 ° C. for 6 minutes, followed by washing with water for 1 minute. Otherwise, the same process as in Example 1 was performed. At this time, the purity of palladium was approximately 94% by weight (palladium: 94% by weight, phosphorus: 6% by weight), and the film thickness was 0.1 μm. The results are shown in Table 1.
Palladium chloride: 0.01 mol / l
Ethylenediamine: 0.08 mol / l
Sodium hypophosphite: 0.12 mol / l
Thiodiglycolic acid: 10ppm
pH: 8

Comparative Example 1
The same processes as in Example 1 were performed except that the process j shown in Example 1 was not performed. The results are shown in Table 1.

Comparative Example 2
After performing the same steps as steps a to i shown in Example 1, in the step k shown in Example 1, electroless palladium plating having the following composition instead of TPD-30 (Uemura Kogyo Co., Ltd., trade name) The liquid was used for immersion treatment at 50 ° C. for 6 minutes and washed with water for 1 minute. Thereafter, steps 1 to m of Example 1 were performed. The purity of palladium at this time was approximately 97% by weight (palladium: 97% by weight, phosphorus: 3% by weight), and the film thickness was 0.1 μm. The results are shown in Table 1.
Palladium chloride: 0.01 mol / l
Ethylenediamine: 0.08 mol / l
Sodium hypophosphite: 0.03 mol / l
Thiodiglycolic acid: 10ppm
pH: 8

(Comparative Example 3)
After performing the same steps as steps a to i shown in Example 1, in the step k shown in Example 1, electroless palladium plating having the following composition instead of TPD-30 (Uemura Kogyo Co., Ltd., trade name) The liquid was used for immersion treatment at 50 ° C. for 6 minutes and washed with water for 1 minute. Thereafter, steps 1 to m of Example 1 were performed. At this time, the purity of palladium was approximately 94% by weight (palladium: 94% by weight, phosphorus: 6% by weight), and the film thickness was 0.1 μm. The results are shown in Table 1.
Palladium chloride: 0.01 mol / l
Ethylenediamine: 0.08 mol / l
Sodium hypophosphite: 0.12 mol / l
Thiodiglycolic acid: 10ppm
pH: 8

  The film thickness of the electroless palladium plating film was measured using a fluorescent X-ray film thickness measuring apparatus SFT9500 (trade name, manufactured by SII Nano Technology Co., Ltd.).

  As shown in Table 1, Examples 1 to 8 of the present invention are electroless which promotes the start of the electroless palladium plating reaction according to the present invention after an electroless nickel plating alloy film is formed on the object to be plated. By immersing in the pretreatment solution that promotes the start of the palladium plating reaction, the electroless palladium plating reaction start time in the object to be plated can be shortened as much as possible, and the thickness of the electroless palladium plating film at all locations of the object to be plated is uniform. In addition, by forming a displacement gold plating or further forming an electroless gold plating film in this order, it is possible to provide an object to be plated with high connection reliability.

It is sectional drawing of the semiconductor chip mounting substrate to which one Embodiment of this invention is applied. (A)-(g) is process drawing which shows one Embodiment of the manufacturing method of the semiconductor chip mounting substrate of this invention. 1 is a cross-sectional view of a flip chip type semiconductor package to which an embodiment of the present invention is applied. 1 is a cross-sectional view of a wire bond type semiconductor package to which an embodiment of the present invention is applied. It is a top view of the fan-in type semiconductor chip mounting board | substrate of this invention. It is a top view of the fan-out type semiconductor chip mounting substrate of the present invention. It is a top view showing the frame shape of the semiconductor chip mounting substrate of this invention. It is sectional drawing of the semiconductor chip mounting substrate to which one Embodiment of this invention is applied.

Explanation of symbols

11 Positioning mark (guide hole for alignment)
13 Semiconductor package area 14 Die bond film adhesion area (flip chip type)
15 Semiconductor chip mounting area (flip chip type)
16 Semiconductor chip connection terminal 17 Die bond film adhesion area (wire bond type)
18 Semiconductor chip mounting area (wire bond type)
19 External connection terminal 20 Expanded wiring 21 Dummy pattern 22 Semiconductor chip mounting board 23 Block 24 Reinforcement pattern 25 Cutting alignment mark

100 Core substrate 101 First interlayer connection terminal 102 First interlayer connection IVH (via hole)
103 Second interlayer connection terminal 104 Interlayer insulating layer (build-up layer)
105 Third layer connection IVH (via hole)
106a First wiring 106b Second wiring 106c Third wiring 107 External connection terminal 108 Second interlayer connection IVH (via hole)
109 Insulation coating (solder resist)
111 Semiconductor chip 112 Connection bump 113 Underfill material 114 Solder ball 115 Gold wire 116 Semiconductor sealing resin 117 Die bond film

Claims (13)

  When an electroless nickel plating alloy film, an electroless palladium plating film, and a displacement gold plating film are formed on the object to be plated, or when an electroless plating is further performed, an electroless palladium plating film is applied. An electroless palladium plating reaction start pretreatment liquid that is immersed before formation to promote the start of the electroless palladium plating reaction.   The electroless palladium plating reaction initiation promotion according to claim 1, wherein the electroless palladium plating reaction initiation acceleration pretreatment liquid for promoting the initiation of the electroless palladium plating reaction is mainly composed of a complexing agent, a reducing agent and a pH adjuster. Pretreatment liquid.   The electroless palladium plating reaction start acceleration pretreatment liquid according to claim 2, wherein the complexing agent is ammonia or amines.   The reducing agent is selected from hypophosphorous acid and salts thereof, phosphorous acid and salts thereof, formic acid and salts thereof, borohydride compounds and amine boranes, aliphatic carboxylic acids and ammonium salts thereof, potassium salts, and sodium salts. The electroless palladium plating reaction initiation promoting pretreatment solution according to claim 2, which is at least one kind of compound.   The electroless palladium plating reaction start pretreatment liquid according to any one of claims 1 to 4, wherein the object to be plated is an electrical insulator or a conductor.   The electroless palladium plating reaction initiation promoting pretreatment liquid according to claim 5, wherein the electrical insulator is an organic material, ceramic, silicone, or glass.   The electroless palladium plating reaction start acceleration pretreatment liquid according to claim 5, wherein the conductor is copper, tungsten, molybdenum, or aluminum. The surface area of the object to be plated is 1 mm ² or less. The electroless palladium plating reaction start pretreatment liquid according to any one of claims 1 to 7.   Forming an electroless palladium plating film in an electroless plating method for forming an electroless nickel plating alloy film, an electroless palladium plating film, and a displacement gold plating film on a body to be plated, or further forming an electroless gold plating film Before performing, the electroless-plating method characterized by immersing in the electroless palladium-plating reaction start acceleration | stimulation pretreatment liquid which accelerates | stimulates the start of electroless palladium-plating reaction.   An electroless nickel plating alloy film is formed on the terminal of the conductor, which is the object to be plated, and immersed in an electroless palladium plating reaction start pretreatment solution that promotes the start of the electroless palladium plating reaction, and then the electroless palladium plating film And a connection terminal formed by an electroless plating method of forming a displacement gold plating or further forming an electroless gold plating film.   The electroless palladium plating film is a single layer of electroless palladium plating film having a purity of 90% by weight or more, or a non-electrolytic palladium plating film having a purity of 90% by weight to less than 99% by weight on the electroless palladium plating film having a purity of 99% by weight or more. The connection terminal according to claim 10, wherein the electrolytic palladium plating film is formed of two layers.   An electroless nickel plating alloy film is formed on the terminal of the conductor, which is the object to be plated, and immersed in an electroless palladium plating reaction start pretreatment solution that promotes the start of the electroless palladium plating reaction, and then the electroless palladium plating film And a connection terminal formed by an electroless plating method for forming a displacement gold plating film or further forming an electroless gold plating film, a substrate supporting the conductor, a semiconductor chip, and connecting the semiconductor chip and the conductor A semiconductor package comprising a connecting conductor.   After the step of forming a conductor on the surface of the substrate, the step of forming an electroless nickel plating alloy film on the surface of the conductor, the electroless palladium plating reaction start acceleration pretreatment solution for promoting the start of the electroless palladium plating reaction Two layers of electroless palladium plating film having a purity of 90% by weight or more and less than 99% by weight on top of one layer of electroless palladium plating film having a purity of 90% by weight or more, or electroless palladium plating film having a purity of 99% by weight or more A step of forming a plating film on a conductor, a step of forming a connection terminal by forming a plating film on the conductor by a step of forming a displacement gold plating film or a step of forming an electroless gold plating film, A step of mounting a semiconductor chip on the solder of the connection terminal; and a step of forming a connection conductor for connecting the semiconductor chip and the conductor. The method of manufacturing a semiconductor package.

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