JP2007262579A - Copper surface treatment method and copper - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a copper surface treatment method by which ruggedness exceeding 1 μm is not formed by the copper surface treatment and the adhesive strength between a copper surface and an insulating layer can be therefore ensured, and insulation reliability between wires can be enhanced, and to provide copper. <P>SOLUTION: The copper surface treatment method is provided which comprises the steps of: discretely depositing a metal more noble than copper on the copper surface; and oxidizing the copper surface with an alkaline solution containing an oxidizing agent. The surface-treated copper by the method is also provided. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a copper surface treatment method and copper subjected to surface treatment by the surface treatment method.

  The development of the information society in recent years has been remarkable, and consumer devices have been reduced in size, weight, performance, and functionality, such as personal computers and mobile phones. Industrial equipment includes wireless base stations, optical communication devices, and servers. In addition, there is a demand for improvement in functions in the same way regardless of whether it is large or small, such as routers and other network-related devices. In addition, with the increase in the amount of information transmitted, the frequency of signals handled tends to increase year by year, and high-speed processing and high-speed transmission technology are being developed. With regard to mounting relations, the development of system-on-chip (SoC), system-in-package (SiP), etc., as new high-density mounting technologies, as well as higher-speed and higher-performance LSIs such as CPUs, DSPs, and various types of memory are actively developed Has been done. For this reason, the semiconductor chip mounting board and the mother board are also built-up type multilayer wiring boards in which fine wiring of L / S = 30 μm / 30 μm or less is formed in order to cope with high frequency, high density wiring, and high functionality. Has come to be used.

  A substrate on which fine wiring is formed is performed by a subtractive method or a semi-additive method.

  In a general wiring formation process by the subtractive method, an etching resist is formed on the copper surface, and then exposure and development are performed to form a resist pattern. Next, unnecessary copper is etched and a resist is removed to form wiring.

  In a general wiring forming process by a semi-additive method, a plating resist is formed on the copper (seed layer) surface, and then exposure and development are performed to form a resist pattern. Next, wiring is formed by performing electroplating, resist stripping, and etching.

  In addition, after these wirings are formed, a solder resist or a coverlay can be formed on the wirings in order to protect the wirings other than the external connection terminals and the semiconductor chip connection terminals.

  In order to increase the formation rate of fine wiring with respect to the design value of L / S width by these methods, it is necessary to form a resist pattern as designed. However, in the formation of fine wiring with L / S = 30 μm / 30 μm or less, there is a problem that it is difficult to obtain the accuracy of the resist pattern on the glossy copper surface due to the influence of halation caused by light reflection.

  In addition, there is a problem that the adhesion between the copper surface and the resist pattern is reduced, and the resist pattern is peeled off. On the other hand, there is a problem that sufficient adhesion cannot be obtained between the wiring (copper) and the solder resist or between the wiring and the coverlay as the wiring becomes finer. Therefore, in order to solve these problems, it is important to make the copper surface non-gloss and strengthen the adhesion between the copper surface and the resist.

  On the other hand, a build-up type multilayer wiring board is manufactured by repeating an interlayer insulating layer forming step and a wiring forming step. In this manufacturing method, it is important to ensure the adhesive strength between the wiring and the insulating resin and the insulation reliability between the wirings.

  In order to satisfy the characteristics shown above, conventionally, the following copper surface treatment method has been performed.

  That is, this is a method in which a roughened shape on the order of microns is imparted to the copper surface to make the copper surface non-glossy, and further, an adhesion effect between the copper surface and the resist or the copper surface and the insulating resin is obtained by the anchor effect. For example, a method of imparting a micron-order roughened shape to a copper surface using an aqueous solution containing a main agent composed of an inorganic acid and a copper oxidizing agent and an auxiliary composed of at least one azole and at least one etching inhibitor. (Japanese Laid-Open Patent Publication No. 2000-282265), a method for forming chromate treatment and coupling agent treatment after forming continuous irregularities having a height of 1.5 to 5.0 μm by microetching (Japanese Laid-Open Patent Publication No. 2000-282265). 9-246720).

  In addition, by providing fine copper oxide needle-like crystals on the copper surface to form irregularities, the copper surface is made dull, and by the anchor effect, the adhesion between the copper surface and the resist or the copper surface and the insulating resin Is the way to get. For example, there is a method of imparting fine copper oxide needle crystals by immersing at about 80 ° C. using an alkaline aqueous solution containing an oxidizing agent such as sodium chlorite (Japanese Patent Publication No. 7-13304). Issue gazette).

  In addition, after forming irregularities with fine copper oxide needle crystals on the copper surface, by performing a reduction treatment, to give fine metal copper needle crystals, matte the copper surface, and further by the anchor effect, This is a method for obtaining an adhesive force between a copper surface and a resist or between a copper surface and an insulating resin. For example, by using an alkaline aqueous solution containing an oxidizing agent such as sodium chlorite, soaking at about 80 ° C., fine needle-like crystals of copper oxide are imparted, and then at least one kind of amine boranes and boron-based There is a method (Japanese Patent No. 2656622) for imparting fine metallic copper needle-like crystals by performing a reduction treatment with an acidic solution mixed with a chemical.

  A first conventional technique for imparting a micron-order roughened shape to the copper surface and improving the adhesive strength between the copper surface and the resist or between the copper surface and the insulating resin has a Rz of 1.5 to 5 μm on the copper surface. Unevenness was formed, and the adhesive strength was secured by the anchor effect. However, in the formation of fine wiring, if the roughness of the copper interface with a narrow L / S and close contact with the resist becomes rougher than 1 μm, it is difficult to completely remove the resist from the copper surface during development. Therefore, there is a problem that a short circuit occurs between the copper wirings during the subsequent etching process. Similarly, when removing the resist, it is difficult to completely remove the resist from the copper surface, so that there is a problem that the adhesion between the subsequent copper surface and the insulating resin or between the copper surface and the solder resist cannot be obtained. In addition, there is a problem that non-precipitation of plating or uneven plating occurs during gold plating processing of external connection terminals and the like.

  In addition, in the fine wiring formation by the semi-additive method, the copper seed layer is thin, and particularly the thickness of the copper seed layer formed by sputtering is 0.1 μm to 1.0 μm. There is a problem that unevenness cannot be formed on the copper surface.

  Furthermore, since the unevenness of the wiring surface is a rough shape exceeding 1 μm, when a high-speed electrical signal is applied to such a wiring, the electrical signal is concentrated and flows near the surface of the wiring due to the skin effect. There is a problem of increased loss. In addition, when the wiring is smaller than L / S = 25 μm / 25 μm, there is a problem that the wiring becomes thin or the variation in the wiring width increases.

  A second conventional technique for improving the adhesive strength between a copper surface and a resist or a copper surface and an insulating resin by imparting fine copper oxide needle-like crystals to the copper surface is a surface roughness Rz (ten points) of the wiring surface. By forming irregularities with an average roughness of 0.1 to 1.5 μm, the adhesive strength was secured by the anchor effect as in the first prior art. However, in the formation of fine wiring, if the unevenness on the copper surface that is in close contact with the resist becomes needle-like, the problem is that a short circuit occurs between the wiring due to the remaining resist as described above, the copper surface and the insulating resin or copper surface There is a problem that adhesion between the solder resist and the solder resist cannot be obtained, gold plating non-precipitation or gold plating unevenness occurs.

  Further, in the formation of fine wiring by the semi-additive method, it is possible to form irregularities on the copper seed layer formed by sputtering or the like. However, since the resist cannot be completely removed from the copper surface as described above, it is difficult to form a wiring on the seed layer, a short circuit occurs between the wiring, the copper surface and the insulating resin or the copper surface. There is a problem that adhesion between the solder resist and the solder resist cannot be obtained, gold plating non-precipitation or gold plating unevenness occurs.

  Furthermore, there is a problem that the unevenness of the unevenness is large, and when Rz <0.5 μm, there is a problem that the adhesion reliability at high temperature and high humidity is lowered. There is a problem of becoming. Further, since the needle-like crystal of copper oxide is fragile, it cannot be processed by a horizontal line, and there is a problem that workability is poor when processing a thin plate. In addition, the copper oxide needle-like crystals dissolve in the through-hole connection plating process, resulting in a pink ring (pink ring) around the through-hole. And the separation between the copper surface and the insulating resin is likely to occur. In addition, since a high-temperature alkaline solution is used, the surface of the insulating resin is easily eroded, and the insulation reliability is likely to decrease due to ion contamination or insulation deterioration. In addition, when washing with water after the oxidation treatment, there is a problem in that the complicated acicular crystal irregularities of copper oxide cannot sufficiently wash the water between the acicular crystals, and the insulation reliability tends to be lowered due to residual ions between the crystals. .

  A third conventional technique for improving the adhesive strength between a copper surface and a resist or a copper surface and an insulating resin by imparting fine metallic copper needle-like crystals to the copper surface is as follows. Since the needle-like crystal never dissolves, no pink ring is generated. However, as in the case of the second prior art, in the fine wiring formation, there is a problem that a short circuit occurs between the wirings due to the resist remaining, and a problem that the adhesion between the copper surface and the insulating resin or the copper surface and the solder resist cannot be obtained , Gold plating undeposited or gold plating unevenness problem, reliability deterioration at high temperature and high humidity, transmission loss problem, workability problem during thin plate processing, ion contamination or insulation deterioration of insulating material There is a problem of deterioration in insulation reliability due to oxidization, and a problem of deterioration in insulation reliability due to water washability after oxidation-reduction treatment.

  The object of the present invention is to improve the above-mentioned problems of the prior art, and without forming irregularities exceeding 1000 nm on the copper surface, the adhesive strength between the copper surface and the resist or the copper surface and the insulating resin. It is to provide a copper surface treatment method that can secure various properties and improve various reliability, and copper whose surface is treated by the surface treatment method.

  That is, the present invention is characterized by the following items (1) to (12).

  (1) A copper surface treatment method comprising a step of discretely forming a metal nobler than copper on a copper surface, and then a step of oxidizing the copper surface with an alkaline solution containing an oxidizing agent.

  (2) The copper according to (1), further including a step of performing one or more treatments selected from the group consisting of a reduction treatment, a coupling treatment, and a corrosion inhibition treatment after the step of oxidizing the copper surface. Surface treatment method.

  (3) The above (1) or wherein the oxidizing agent is one or more selected from the group consisting of chlorate, chlorite, hypochlorite, perchlorate, and peroxodisulfate The copper surface treatment method according to (2).

  (4) The above-mentioned (1), wherein the metal nobler than copper is a metal selected from the group consisting of gold, silver, platinum, palladium, rhodium, rhenium, ruthenium, osmium, iridium, or an alloy containing the metal. )-(3) The surface treatment method of copper in any one.

(5) The copper surface treatment method according to any one of the above (1) to (4), wherein a formation amount of a noble metal than the copper is 0.001 μmol / dm ² or more and 40 μmol / dm ² or less. .

  (6) The copper surface treatment method according to the above (1) to (5), wherein the roughness of the copper surface after treatment is 1 nm to 1000 nm in terms of Rz.

  (7) Copper obtained by discretely forming a noble metal on the copper surface and then oxidizing the copper surface with an alkaline solution containing an oxidizing agent.

  (8) The copper according to (7) above, which is further subjected to one or more treatments selected from the group consisting of reduction treatment, coupling treatment, and corrosion inhibition treatment after the oxidation treatment.

  (9) The above (7) or wherein the oxidizing agent is one or more selected from the group consisting of chlorates, chlorites, hypochlorites, perchlorates, and peroxodisulfates. Copper as described in (8).

  (10) The metal nobler than copper is a metal selected from the group consisting of gold, silver, platinum, palladium, rhodium, rhenium, ruthenium, osmium, iridium, or an alloy containing the metal. The copper according to any one of (7) to (9) above.

(11) The copper according to any one of the above (7) to (10), wherein the amount of the metal more precious than the copper formed on the surface is 0.001 μmol / dm ² or more and 40 μmol / dm ² or less. .

  (12) The copper according to (7) to (11) above, wherein the roughness of the copper surface after the treatment is 1 nm or more and 1000 nm or less in Rz.

  According to the present invention as described above, the adhesive strength between the copper surface and the resist or the copper surface and the insulating resin can be secured and various reliability can be improved without forming irregularities exceeding 1000 nm on the copper surface. It is possible to provide a copper surface treatment method and copper whose surface is treated by the surface treatment method.

  In addition, this application is a Japanese patent application previously filed by the same applicant, that is, 2005-069058 (application date March 11, 2005), 2005-277732 (application date September 26, 2005). And 2005-287038 (filing date: September 30, 2005), the contents of which are incorporated herein by reference.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. Here, as an application example of the copper surface treatment method of the present invention, the surface treatment of the copper wiring of the semiconductor chip mounting substrate will be described as an example, but the same can be applied as other copper surface treatment methods.

(Copper surface unevenness forming method)
By forming a noble metal on the copper surface discretely, and then oxidizing the copper surface with an alkaline solution containing an oxidant, fine and uneven copper oxide crystals are formed on the copper surface. Can be formed. Further, by performing a reduction treatment after the oxidation treatment, fine irregularities due to dense and uniform metal copper crystals can be formed. Furthermore, after the oxidation treatment, it is preferable to perform at least one of coupling treatment and corrosion inhibition treatment. After the oxidation treatment, the reduction treatment, the coupling treatment or the corrosion inhibition treatment, the copper surface roughness generated by the surface treatment of these copper is 1 nm or more and 1,000 nm in terms of Rz (10-point average roughness). The following is preferable. Further, Rz is more preferably 1 nm or more and 100 nm or less, and further preferably 1 nm or more and 50 nm or less. If Rz is less than 1 nm, the adhesive strength with a resist or an insulating resin tends to be reduced, and if Rz exceeds 1,000 nm, problems of the prior art tend to occur. “Dense and uniform” means that the shape of the copper surface is processed with a scanning electron microscope (SEM) or with a focused ion beam processing observation device (FIB) and observed with a scanning ion microscope (SIM) image. In this case, the size and height of the copper oxide or metal copper crystals are 1 nm or more and 1,000 nm or less, and the formed crystals are dense.

  Below, each process mentioned above is demonstrated in detail. In the present invention, as a pretreatment for each treatment, it is desirable to perform a degreasing treatment for cleaning the copper surface, a pickling treatment, or a combination thereof as appropriate.

(Metal forming method nobler than copper)
The method of discretely forming a metal noble from copper on the copper surface is not particularly limited, but a metal noble than copper is electroless plating, electroplating, displacement plating, spray spraying, coating, sputtering, vapor deposition, etc. Thus, it is preferable to form the base so as to be uniformly dispersed on the copper surface without completely covering the copper surface. More preferably, it is a method of discretely forming a metal nobler than copper on the copper surface by displacement plating. Displacement plating utilizes the difference in ionization tendency between copper and a metal nobler than copper, and according to this, a metal nobler than copper can be easily and inexpensively formed on the copper surface. .

  The metal nobler than copper is not particularly limited, and a metal selected from gold, silver, platinum, palladium, rhodium, rhenium, ruthenium, osmium, iridium or an alloy containing these metals can be used.

In addition, the amount of the metal nobler than the copper formed discretely on the copper surface is not particularly limited, but is preferably 0.001 μmol / dm ² or more and 40 μmol / dm ² or less. The formation amount is more preferably at 0.01μmol / dm ² or more and 10 .mu.mol / dm ² or less, more preferably 0.1 [mu] mol / dm ² or more and is 4μmol / dm ² or less. If the formation amount is less than 0.001 μmol / dm ² , it tends to be difficult to form dense and uniform fine irregularities, and if it exceeds 40 μmol / dm ² , the adhesive strength tends to decrease. In addition, the amount of discretely formed noble metal on the copper surface is determined by dissolving the noble metal on the copper surface with aqua regia and then quantitatively analyzing the solution with an atomic absorption photometer. Can be sought. The term “discrete” means that the noble metal formed in an amount of 0.001 μmol / dm ² or more and 40 μmol / dm ² or less is dispersed on the copper surface without completely covering the copper surface with the noble metal. Meaning.

(Copper surface oxidation method)
In the present invention, after a metal noble than copper is discretely formed on the copper surface as described above, the copper surface is oxidized with an alkaline solution containing an oxidizing agent.

  The alkaline solution containing the oxidizing agent is not particularly limited. For example, an alkaline solution containing an alkali metal or an alkaline earth metal may be added to chlorate, chlorite, hypochlorite, perchlorate. The alkaline solution further contains an oxidizing agent such as peroxodisulfate. The alkaline solution containing the alkali metal or alkaline earth metal is, for example, an alkali metal compound such as sodium hydroxide, potassium hydroxide, or sodium carbonate or water obtained by treating an alkaline earth metal compound with water or an ion exchange resin. It can be obtained by adding to a solvent. More specifically, the oxidizing agent is, for example, sodium hypochlorite, sodium chlorite, sodium chlorate, sodium perchlorate, potassium hypochlorite, potassium chlorite, potassium chlorate, Examples include potassium perchlorate, ammonium peroxodisulfate, potassium peroxodisulfate, and sodium peroxodisulfate. Moreover, you may add a phosphate to the said alkaline solution. Although it does not specifically limit as a phosphate which can be used, For example, a trisodium phosphate, a tripotassium phosphate, a trilithium phosphate etc. are mentioned. Furthermore, you may add a well-known organic acid and a chelating agent to the said alkaline solution.

By the oxidation treatment with the alkaline solution containing the oxidizing agent as described above, irregularities due to copper oxide crystals can be formed on the copper surface. The crystal amount of copper oxide is preferably 0.001 mg / cm ² or more and 0.3 mg / cm ² or less, more preferably 0.01 mg / cm ² or more and 0.2 mg / cm ² or less, It is particularly preferably 0.03 mg / cm ² or more and 0.1 mg / cm ² or less. If the copper oxide crystal amount is less than 0.001 mg / cm ² , the resist peels off or the adhesive strength with the insulating resin or the like tends to decrease, and if it exceeds 0.3 mg / cm ² , problems of the prior art occur. It tends to be easier. The amount of copper oxide crystals formed on the copper surface can be examined by measuring the amount of electrolytic reduction. For example, using oxidized copper as a working electrode (cathode), a constant amount of electricity of 0.5 mA / cm ² is applied, and the surface potential of copper completely changes from the potential of copper oxide to the potential of metallic copper. The amount of copper oxide crystals can be determined from the amount of electrolytic reduction by measuring the time until a stable potential of −1.0 V or less is obtained.

Moreover, the temperature of the alkaline solution in performing the oxidation treatment with the alkaline solution containing the oxidizing agent is not particularly limited, but it is preferably 20 to 95 ° C, more preferably 30 to 80 ° C, 40 It is particularly preferable to carry out at ~ 60 ° C. The concentration of the alkaline solution containing the oxidizing agent and the oxidation treatment time with the solution are appropriately set so that the amount of crystal of the copper oxide is 0.001 mg / cm ² or more and 0.3 mg / cm ² or less. It is preferable to select.

(Reduction treatment method)
The unevenness due to the copper oxide crystal formed on the copper surface by the oxidation treatment can be made uneven by the reduction treatment. In this reduction treatment, an aqueous solution in which formaldehyde, paraformaldehyde, paraformaldehyde, an aromatic aldehyde compound, etc. are added to an alkaline solution adjusted to pH 9.0 to 13.5, hypophosphorous acid, hypophosphite, etc. An aqueous solution added, an aqueous solution added with dimethylamine borane or a compound containing the same, an aqueous solution added with a boron hydride salt or a compound containing the same can be used. More specifically, for example, HIST-100 (manufactured by Hitachi Chemical Co., Ltd., trade names, including HIST-100B and HIST-100D) can be used as the solution for the reduction treatment. Moreover, it is although it does not specifically limit as an alkaline solution shown here, For example, it is an alkaline solution containing an alkali metal or an alkaline-earth metal. More specifically, for example, it can be obtained by adding an alkali metal compound or alkaline earth metal compound such as sodium hydroxide, potassium hydroxide or sodium carbonate to a solvent such as water or water treated with an ion exchange resin. it can.

  Moreover, although the said method is a method of reduce | restoring a copper oxide chemically, it can also reduce | restore a copper oxide electrically electrically.

(Coupling process)
After the oxidation treatment, a coupling treatment may be performed to improve the adhesive strength between the copper surface and the insulating layer (build-up layer, etc.). The coupling treatment is performed after the reduction treatment or the corrosion inhibition treatment. It may be done later. Thereby, adhesiveness can be improved. Examples of the coupling agent used in the coupling treatment include silane coupling agents, aluminum coupling agents, titanium coupling agents, and zirconium coupling agents, and these include one or more types. You may use together. Of these, silane coupling agents are preferable, and the silane coupling agent has a functional group such as an epoxy group, amino group, mercapto group, imidazole group, vinyl group, or methacryl group in the molecule. Is preferred. The coupling agent can be used as a solution containing the same, and the solvent used for the preparation of the coupling agent solution is not particularly limited, but water, alcohol, ketones, and the like can be used. It is. A small amount of acid such as acetic acid or hydrochloric acid can be added to promote hydrolysis of the coupling agent. In addition, the content of the coupling agent is preferably 0.01% by mass to 5% by mass and more preferably 0.1% by mass to 1.0% by mass with respect to the entire coupling agent solution. preferable. The treatment with the coupling agent can be performed by a method of immersing copper to be treated in the coupling agent solution adjusted as described above, or spraying or applying the coupling agent solution to copper. The copper treated with the silane coupling agent is dried by natural drying, heat drying, or vacuum drying. Depending on the type of coupling agent used, it may be washed with water or ultrasonically before drying. Is possible.

(Corrosion suppression treatment)
After the oxidation treatment, a corrosion inhibition treatment may be performed to suppress copper corrosion, and the corrosion inhibition treatment may be performed after the reduction treatment or after the coupling treatment. Although it does not specifically limit as a corrosion inhibitor used for a corrosion inhibition process, For example, what is necessary is just to contain at least 1 sort (s) or more of a sulfur containing organic compound or a nitrogen containing organic compound. The corrosion inhibitor is not particularly limited, but is a compound containing a sulfur atom such as a mercapto group, a sulfide group, or a disulfide group, or a nitrogen-containing organic containing —N═ or N═N or —NH ₂ in the molecule. A compound containing at least one compound is preferable.

Examples of the compound containing a sulfur atom such as a mercapto group, a sulfide group, or a disulfide group include aliphatic thiol (HS— (CH ₂ ) nR (where n is 1 to 23). An integer, R represents a monovalent organic group, a hydrogen group or a halogen atom), and R may be an amino group, an amide group, a carboxyl group, a carbonyl group, or a hydroxyl group Although not limited to this, it is not limited to this, but is an alkyl group having 1 to 18 carbon atoms, an alkoxy group having 1 to 8 carbon atoms, an acyloxy group, a haloalkyl group, a halogen atom, a hydrogen group, a thioalkyl group, a thiol group, or a substituted group. May be a phenyl group, a biphenyl group, a naphthyl group, a heterocyclic ring, etc. The amino group, amide group, carboxyl group, and hydroxyl group in R are It may be sufficient, preferably 1 or more, and may further have a substituent such as the above alkyl group, etc. In addition, it is preferable to use a compound in which n is an integer from 1 to 23. More preferably, a compound in which n is an integer from 4 to 15 is more preferable, and a compound from an integer from 6 to 12 is particularly preferable.), A thiazole derivative (for example, thiazole, 2- Aminothiazole, 2-aminothiazole-4-carboxylic acid, aminothiophene, benzothiazole, 2-mercaptobenzothiazole, 2-aminobenzothiazole, 2-amino-4-methylbenzothiazole, 2-benzothiazolol, 2, 3-dihydroimidazo [2,1-b] benzothiazol-6-amine, 2- (2-aminothiazol-4-yl) Ethyl 2-hydroxyiminoacetate, 2-methylbenzothiazole, 2-phenylbenzothiazole, 2-amino-4-methylthiazole, etc.), thiadiazole derivatives (1,2,3-thiadiazole), 1,2,4-thiadiazole, 1,2,5-thiadiazole, 1,3,4-thiadiazole, 2-amino-5-ethyl-1,3,4-thiadiazole, 5-amino-1,3,4-thiadiazole-2-thiol, 2, 5-mercapto-1,3,4-thiadiazole, 3-methylmercapto-5-mercapto-1,2,4-thiadiazole, 2-amino-1,3,4-thiadiazole, 2- (ethylamino) -1, 3,4-thiadiazole, 2-amino-5-ethylthio-1,3,4-thiadiazole, etc.), mercaptobenzoic acid, mercaptona Phthol, mercaptophenol, 4-mercaptobiphenyl, mercaptoacetic acid, mercaptosuccinic acid, 3-mercaptopropionic acid, thiouracil, 3-thiourazol, 2-thiouramil, 4-thiouramil, 2-mercaptoquinoline, thioformic acid, 1-thiocoumarin, thiocoumotiazone Thiocresol, thiosalicylic acid, thiothianuric acid, thionaphthol, thiotolene, thionaphthene, thionaphthenecarboxylic acid, thionaphthenequinone, thiobarbituric acid, thiohydroquinone, thiophenol, thiophene, thiophthalide, thiobutene, thiothione carbonate, thiolutidone, thiol histidine, 3-carboxypropyl disulfide, 2-hydroxyethyl disulfide, 2-aminopropionic acid, dithiodiglycolic acid, D-system Emissions, di -t- butyl disulfide, thiocyanate, etc. thiocyanate acid.

Preferred compounds as the compound containing at least one N-containing organic compound containing —N═, N═N, or —NH ₂ in the molecule are triazole derivatives (1H-1,2,3-triazole, 2H-1, 2,3-triazole, 1H-1,2,4-triazole, 4H-1,2,4-triazole, benzotriazole, 1-aminobenzotriazole, 3-amino-5-mercapto-1,2,4-triazole 3-amino-1H-1,2,4-triazole, 3,5-diamino-1,2,4-triazole, 3-oxy-1,2,4-triazole, aminourazole, etc.), tetrazole derivatives ( Tetrazolyl, tetrazolylhydrazine, 1H-1,2,3,4-tetrazole, 2H-1,2,3,4-tetrazole, 5-amino-1H -Tetrazole, 1-ethyl-1,4-dihydroxy-5H-tetrazol-5-one, 5-mercapto-1-methyltetrazole, tetrazole mercaptan, etc.), oxazole derivatives (oxazole, oxazolyl, oxazoline, benzoxazole, 3-amino- 5-methylisoxazole, 2-mercaptobenzoxazole, 2-aminooxazoline, 2-aminobenzoxazole, etc.), oxadiazole derivatives (1,2,3-oxadiazole, 1,2,4-oxadiazole, 1,2,5-oxadiazole, 1,3,4-oxadiazole, 1,2,4-oxadiazolone-5, 1,3,4-oxadiazolone-5, etc.), oxatriazole derivatives ( 1,2,3,4-oxatriazole, 1,2,3,5-oxatriazole Sol), purine derivatives (purine, 2-amino-6-hydroxy-8-mercaptopurine, 2-amino-6-methylmercaptopurine, 2-mercaptoadenine, mercaptohypoxanthine, mercaptopurine, uric acid, guanine, adenine, Xanthine, theophylline, theobromine, caffeine, etc.), imidazole derivatives (imidazole, benzimidazole, 2-mercaptobenzimidazole, 4-amino-5-imidazolecarboxylic acid amide, histidine, etc.), indazole derivatives (indazole, 3-indazolone, indazolol) ), Pyridine derivatives (2-mercaptopyridine, aminopyridine, etc.), pyrimidine derivatives (2-mercaptopyrimidine, 2-aminopyrimidine, 4-aminopyrimidine, 2-amino-4,6-di) Droxypyrimidine, 4-amino-6-hydroxy-2-mercaptopyrimidine, 2-amino-4-hydroxy-6-methylpyrimidine, 4-amino-6-hydroxy-2-methylpyrimidine, 4-amino-6-hydroxypyramid Zolo [3,4-d] pyrimidine, 4-amino-6-mercaptopyrazolo [3,4-d] pyrimidine, 2-hydroxypyrimidine, 4-mercapto-1H-pyrazolo [3,4-d] pyrimidine, 4 -Amino-2,6-dihydroxypyrimidine, 2,4-diamino-6-hydroxypyrimidine, 2,4,6-triaminopyrimidine, etc.), thiourea derivatives (thiourea, ethylenethiourea, 2-thiobarbituric acid, etc.) ), Amino acids (glycine, alanine, tryptophan, proline, oxyproline, etc.), 1,3,4-thio Oxadiazolone-5, thiocoumazone, 2-thiocoumarin, thiosaccharin, thiohydantoin, thiopyrine, γ-thiopyringanazine, guanazole, guanamine, oxazine, oxadiazine, melamine, 2,4,6-triaminophenol, triaminobenzene Aminoindole, aminoquinoline, aminothiophenol, aminopyrazole and the like.

  Moreover, water and an organic solvent can be used for adjustment of the solution containing the said corrosion inhibitor. The type of the organic solvent is not particularly limited, but alcohols such as methanol, ethanol, n-propyl alcohol and n-butyl alcohol, ethers such as di-n-propyl ether, di-n-butyl ether and diallyl ether. Aliphatic hydrocarbons such as hexane, heptane, octane and nonane, and aromatic hydrocarbons such as benzene, toluene and phenol can be used, and these solvents can be used alone or in combination of two or more. It is also possible to add the corrosion inhibitor to an alkaline solution or a coupling agent solution containing the oxidizing agent.

  The concentration of the solution containing the corrosion inhibitor is preferably 0.1 to 5000 ppm, more preferably 0.5 to 3000 ppm, and particularly preferably 1 to 1000 ppm. When the concentration of the corrosion inhibitor is less than 0.1 ppm, the ion migration suppressing effect and the adhesive strength between the copper surface and the insulating layer tend to decrease. On the other hand, when the concentration of the corrosion inhibitor exceeds 5000 ppm, an ion migration suppressing effect can be obtained, but the adhesive strength between the copper surface and the insulating layer tends to decrease. The treatment time with the solution containing the corrosion inhibitor is not particularly limited, but it is preferable to appropriately change the treatment time according to the type and concentration of the corrosion inhibitor. It is also possible to perform ultrasonic cleaning after the treatment.

(Resist)
Examples of the resist used in the present invention include an etching resist, a plating resist, a solder resist, and a coverlay. The etching resist and the plating resist are peeled off after forming the wiring and are not left on the substrate or the like in order to use for the purpose of wiring formation. The solder resist or coverlay is formed on the substrate surface for the purpose of wiring protection other than external connection terminals and semiconductor chip connection terminals. These resists can be used in liquid or film form, and preferably have photosensitivity.

(Semiconductor chip mounting substrate)
FIG. 1 shows a schematic cross-sectional view of an embodiment (two-sided build-up layer 2 layers) of a semiconductor chip mounting substrate of the present invention. Here, the embodiment in which the buildup layer (interlayer insulating layer) is formed only on one side will be described. However, the buildup layer may be formed on both sides as shown in FIG.

  As shown in FIG. 1, the semiconductor chip mounting substrate of the present invention includes a semiconductor chip connection terminal and a first interlayer connection terminal 101 on a core substrate 100 which is an insulating layer on the side where the semiconductor chip is mounted. Wiring 106a is formed. A second wiring 106b including the second interlayer connection terminal 103 is formed on the other side of the core substrate, and the first interlayer connection terminal and the second interlayer connection terminal are connected to the first interlayer connection of the core substrate. It is electrically connected via an IVH (interstitial via hole) 102. A buildup layer 104 is formed on the second wiring side of the core substrate, and a third wiring 106c including a third interlayer connection terminal is formed on the buildup layer. The three interlayer connection terminals are electrically connected via the second interlayer connection IVH 108.

  When a plurality of buildup layers are formed, the same structure is stacked, and an external connection terminal 107 connected to the motherboard is formed on the outermost buildup layer, and the external connection terminal and the third layer are further formed. The connection terminal is electrically connected through the third interlayer connection IVH 105. The shape of the wiring, the arrangement of each connection terminal, and the like are not particularly limited, and can be appropriately designed for manufacturing a semiconductor chip to be mounted and a target semiconductor package. Further, the semiconductor chip connection terminal and the first interlayer connection terminal can be shared. Furthermore, an insulating coating 109 such as a solder resist can be provided on the outermost buildup layer as necessary.

(Core substrate)
The material of the core substrate is not particularly limited, but an organic substrate, a ceramic substrate, a silicon substrate, a glass substrate, or the like can be used. In consideration of the thermal expansion coefficient and insulation, it is preferable to use ceramic or glass. Among the non-photosensitive glasses, soda lime glass (component example: SiO ₂ 65 to 75 wt%, Al ₂ O ₃ 0.5 to ₄ wt%, CaO 5 to 15 wt%, MgO 0.5 to 4 wt%, Na ₂ O _10~20wt%), borosilicate glass (component _{example: SiO 2 65~80wt%, B 2} O 3 5~25wt%, Al 2 O 3 1~5wt%, CaO 5~8wt%, MgO 0.5 ˜2 wt%, Na ₂ O 6-14 wt%, K ₂ O 1-6 wt%) and the like. Also, it includes those containing gold ions and silver ions as a photosensitive agent into Li _{2 O-SiO} 2 based crystallized glass as photosensitive glass.

  As the organic substrate, a substrate or a resin film obtained by laminating a material obtained by impregnating a glass cloth with a resin can be used. As the resin to be used, a thermosetting resin, a thermoplastic resin, or a mixed resin thereof can be used, but a thermosetting organic insulating material is preferable. Thermosetting resins include phenolic resin, urea resin, melamine resin, alkyd resin, acrylic resin, unsaturated polyester resin, diallyl phthalate resin, epoxy resin, polybenzimidazole resin, polyamide resin, polyamideimide resin, silicon resin, cyclohexane Resin synthesized from pentadiene, resin containing tris (2-hydroxyethyl) isocyanurate, resin synthesized from aromatic nitrile, trimerized aromatic dicyanamide resin, resin containing triallyl trimetallate, furan resin, ketone resin, A xylene resin, a thermosetting resin containing a condensed polycyclic aromatic, a benzocyclobutene resin, or the like can be used. Examples of the thermoplastic resin include polyimide resin, polyphenylene oxide resin, polyphenylene sulfide resin, aramid resin, and liquid crystal polymer.

  A filler may be added to these resins. Examples of the filler include silica, talc, aluminum hydroxide, aluminum borate, aluminum nitride, and alumina.

  The thickness of the core substrate is preferably 100 to 800 μm from the viewpoint of IVH formation, and more preferably 150 to 500 μm.

(Build-up layer)
The interlayer insulating layer (build-up layer) 104 is made of an insulating material, and a thermosetting resin, a thermoplastic resin, or a mixed resin thereof can be used as the insulating material. The build-up layer preferably contains a thermosetting organic insulating material as a main component. Thermosetting resins include phenolic resin, urea resin, melamine resin, alkyd resin, acrylic resin, unsaturated polyester resin, diallyl phthalate resin, epoxy resin, polybenzimidazole resin, polyamide resin, polyamideimide resin, silicon resin, cyclohexane Resin synthesized from pentadiene, resin containing tris (2-hydroxyethyl) isocyanurate, resin synthesized from aromatic nitrile, trimerized aromatic dicyanamide resin, resin containing triallyl trimetallate, furan resin, ketone resin, A xylene resin, a thermosetting resin containing a condensed polycyclic aromatic, a benzocyclobutene resin, or the like can be used. Examples of the thermoplastic resin include polyimide resin, polyphenylene oxide resin, polyphenylene sulfide resin, aramid resin, and liquid crystal polymer.

  A filler may be added to the insulating material. Examples of the filler include silica, talc, aluminum hydroxide, aluminum borate, aluminum nitride, and alumina.

(Coefficient of thermal expansion)
It is preferable that the thermal expansion coefficient of the semiconductor chip and the thermal expansion coefficient of the core substrate are approximated, and that the thermal expansion coefficient of the core substrate and the thermal expansion coefficient of the buildup layer are approximated. It is not a thing. Further, when the thermal expansion coefficients of the semiconductor chip, the core substrate, and the buildup layer are α1, α2, and α3 (ppm / ° C.), it is more preferable that α1 ≦ α2 ≦ α3.

  Specifically, the thermal expansion coefficient α2 of the core substrate is preferably 7 to 13 ppm / ° C., more preferably 9 to 11 ppm / ° C. The thermal expansion coefficient α3 of the buildup layer is preferably 10 to 40 ppm / ° C, more preferably 10 to 20 ppm / ° C, and particularly preferably 11 to 17 ppm / ° C.

(Young's modulus)
The Young's modulus of the buildup layer is preferably 1 to 5 GPa in terms of stress relaxation against thermal stress. It is preferable to add the filler in the buildup layer by appropriately adjusting the addition amount so that the thermal expansion coefficient of the buildup layer is 10 to 40 ppm / ° C. and the Young's modulus is 1 to 5 GPa.

(Manufacturing method of semiconductor chip mounting substrate)
The semiconductor chip mounting substrate can be manufactured by a combination of the following manufacturing methods. The order of the manufacturing process is not particularly limited as long as it does not depart from the object of the present invention.

(Wiring formation method)
Wiring is formed by forming a metal foil on the core substrate surface or build-up layer and removing unnecessary portions of the metal foil by etching (subtractive method). Necessary on the core substrate surface or build-up layer A method of forming a wiring by plating only at an appropriate location (additive method), forming a thin metal layer (seed layer) on the core substrate surface or build-up layer, and then forming the necessary wiring by electrolytic plating, and then thin There is a method of removing the metal layer by etching (semi-additive method).

(Wiring formation by subtractive method)
An etching resist can be formed at a location to be a wiring on the metal foil, and a chemical etching solution can be sprayed and sprayed onto a portion exposed from the etching resist to remove an unnecessary metal foil to form a wiring. For example, when a copper foil is used as the metal foil, an etching resist material that can be used for an ordinary wiring board can be used as the etching resist. For example, a resist mask is silk-screen printed to form an etching resist, or a negative photosensitive dry film for etching resist is laminated on a copper foil, and a photomask that transmits light in the shape of a wiring on it. Are exposed to ultraviolet rays, and the portions not exposed are removed with a developer to form an etching resist. As the chemical etching solution, a chemical etching solution used for a normal wiring board, such as a solution of cupric chloride and hydrochloric acid, a ferric chloride solution, a solution of sulfuric acid and hydrogen peroxide, and an ammonium persulfate solution can be used.

(Wiring formation by additive method)
Further, the wiring can be formed by plating only at a necessary portion on the core substrate or the build-up layer, and a wiring forming technique by normal plating can be used. For example, after depositing the electroless plating catalyst on the core substrate, forming a plating resist on the surface portion where plating is not performed, immersing in an electroless plating solution, and only in locations not covered by the plating resist, Electroless plating is performed to form wiring.

(Wiring formation by semi-additive method)
As a method for forming a seed layer used for the semi-additive method on the core substrate surface or the build-up layer, there are a method by vapor deposition or plating, and a method of bonding a metal foil. Further, a subtractive metal foil can be formed by the same method.

(Formation of seed layer by vapor deposition or plating)
The seed layer can be formed on the core substrate surface or the build-up layer by vapor deposition or plating. For example, when a base metal and a thin film copper layer are formed by sputtering as a seed layer, the sputtering apparatus used to form the thin film copper layer is a bipolar sputtering, a three-pole sputtering, a four-pole sputtering, a magnetron sputtering, a mirror. Tron sputtering or the like can be used. The target used for sputtering is, for example, Cr, Ni, Co, Pd, Zr, Ni / Cr, Ni / Cu, or the like as a base metal and sputtering with a thickness of 5 to 50 nm in order to ensure adhesion. Thereafter, a seed layer can be formed by performing sputtering with a thickness of 200 to 500 nm using copper as a target. Alternatively, plated copper having a thickness of 0.5 to 3 μm may be formed on the surface of the core substrate or the buildup layer by electroless copper plating.

(Method of bonding metal foil)
When the core substrate or the buildup layer has an adhesive function, the seed layer can also be formed by bonding metal foils together by pressing or laminating. However, since it is very difficult to directly bond a thin metal layer, there are a method of thinning a metal foil with a carrier after laminating a thick metal foil, a method of peeling a carrier layer after laminating a metal foil with a carrier, etc. is there. For example, as the former, there is a three-layer copper foil of carrier copper / nickel / thin film copper, and carrier copper can be removed with an alkali etching solution and nickel can be removed with a nickel etching solution. As the latter, a peelable copper foil using aluminum, copper, an insulating material or the like as a carrier can be used, and a seed layer having a thickness of 5 μm or less can be formed. Alternatively, a seed layer may be formed by attaching a copper foil having a thickness of 9 to 18 μm, uniformly thinning it so as to have a thickness of 5 μm or less by etching.

  A plating resist is formed in a necessary pattern on the seed layer formed by the above-described method, and wiring is formed by electrolytic copper plating through the seed layer. Thereafter, the plating resist is peeled off, and finally the seed layer is removed by etching or the like, whereby the wiring can be formed.

(Wiring shape)
The shape of the wiring is not particularly limited, but at least a semiconductor chip connection terminal 16 (wire bond terminal or the like) is provided on the side where the semiconductor chip is mounted, and an external connection terminal (solder ball) electrically connected to the motherboard on the opposite side. Etc.) and development wirings connecting them, interlayer connection terminals, and the like. The wiring arrangement is not particularly limited, but a fan-in type semiconductor in which an external connection terminal 19 is formed inside the semiconductor chip connection terminal 16 as shown in FIG. A chip mounting board, a fan-out type semiconductor chip mounting board in which the external connection terminals 19 are formed outside the semiconductor chip connection terminals 16 as shown in FIG. 6, or a combination of these may be used. In FIGS. 5 and 6, 13 is a semiconductor package region, 14 is a die bond film adhesion region (flip chip type), 15 is a semiconductor chip mounting region (flip chip type), and 17 is a die bond film adhesion region (wire bond type). , 18 is a semiconductor chip mounting area (wire bond type), and 20 is a developed wiring. The shape of the semiconductor chip connection terminal 16 is not particularly limited as long as wire bond connection or flip chip connection is possible. In addition, wire-bond connection or flip-chip connection is possible for both fan-out and fan-in types. Further, if necessary, a dummy pattern 21 (see FIG. 6) that is not electrically connected to the semiconductor chip may be formed. The shape and arrangement of the dummy pattern are not particularly limited, but it is preferable to arrange the dummy pattern uniformly in the semiconductor chip mounting region. As a result, voids are less likely to occur when a semiconductor chip is mounted with a die bond adhesive, and reliability can be improved.

(Bahia Hall)
Since the multilayer semiconductor chip mounting substrate has a plurality of wiring layers, via holes for electrically connecting the wirings of the respective layers can be provided. The via hole can be formed by providing a hole for connection in the core substrate or the build-up layer and filling the hole with a conductive paste or plating. Examples of the hole processing method include mechanical processing such as punching and drilling, laser processing, chemical etching processing using a chemical solution, and dry etching using plasma.

  In addition, as a method for forming a via hole in the buildup layer, there is a method in which a conductive layer is formed in advance on the buildup layer with a conductive paste or plating, and this is laminated on a core substrate by pressing or the like.

(Formation of insulation coating)
An insulating coating can be formed on the external connection terminal side of the semiconductor chip mounting substrate. The pattern can be formed by printing if it is a varnish-like material, but it is preferable to use a photosensitive solder resist, a coverlay film, or a film-like resist in order to ensure higher accuracy. As a material, an epoxy-based material, a polyimide-based material, an epoxy acrylate-based material, or a fluorene-based material can be used.

  Since such an insulating coating has shrinkage at the time of curing, if it is formed only on one side, a large warp tends to occur on the substrate. Therefore, an insulating coating can be formed on both surfaces of the semiconductor chip mounting substrate as necessary. Furthermore, since the warpage varies depending on the thickness of the insulating coating, it is more preferable to adjust the thickness of the insulating coating on both sides so that no warpage occurs. In that case, it is preferable to conduct preliminary examination and determine the thicknesses of the insulating coatings on both sides. In order to obtain a thin semiconductor package, the thickness of the insulating coating is preferably 50 μm or less, and more preferably 30 μm or less.

(Plating of wiring)
Nickel and gold plating can be sequentially applied to necessary portions of the wiring. Furthermore, nickel, palladium, or gold plating may be used as necessary. These platings are applied to the semiconductor chip connection terminals of the wiring and the external connection terminals for electrical connection with the mother board or other semiconductor package. For this plating, either electroless plating or electrolytic plating may be used.

(Manufacturing method of semiconductor chip mounting substrate)
Such a semiconductor chip mounting substrate can be manufactured by the following processes. 2A to 2G are schematic cross-sectional views showing an embodiment of a method for manufacturing a semiconductor chip mounting substrate according to the present invention. However, the order of the manufacturing process is not particularly limited as long as it does not depart from the object of the present invention.

(Process a)
(Step a) is a step of forming the first wiring 106a on the core substrate 100 as shown in FIG. For example, the first wiring 106a is made by degreasing a copper layer of a core substrate having a copper layer formed on one side, washing with hydrochloric acid or sulfuric acid, and then, on the copper layer, gold or silver which is a noble metal than copper In addition, a metal selected from platinum, palladium, rhodium, rhenium, ruthenium, osmium, and iridium, or an alloy containing these metals is discretely formed, and an oxidation treatment is performed by immersing in an alkaline aqueous solution containing an oxidizing agent. Thereafter, an etching resist was formed in a first wiring shape on the oxidized copper layer, and the copper layer was etched with an etching solution such as copper chloride, iron chloride, sulfuric acid-hydrogen peroxide, and nitric acid-hydrogen peroxide. Thereafter, it can be produced by removing the etching resist. Moreover, it is preferable to perform one or more processes of a reduction process, a coupling process, and a corrosion suppression process after the said oxidation process. In any case, the processing is performed so that the Rz on the wiring surface is 1 nm or more and 1,000 nm or less. The copper layer can be formed on the core substrate 100 by forming a copper thin film by sputtering, vapor deposition, plating, or the like and then performing electrolytic copper plating until a desired thickness is achieved. Note that the first wiring 106a includes the first interlayer connection terminal 101 and the semiconductor chip connection terminal (portion electrically connected to the semiconductor chip), and a semi-additive method is used as a method for forming the fine wiring. May be.

(Process b)
In step (b), as shown in FIG. 2B, a first interlayer connection IVH 102 (via hole) for connecting the first interlayer connection terminal 101 and a second wiring to be described later is used. Is a step of forming.

When the core substrate 100 is a non-photosensitive base material, a hole to be a via hole can be formed by irradiating a laser beam such as a CO ₂ laser, a YAG laser, or an excimer laser to a portion to be a via hole. From the viewpoint of productivity and hole quality, it is preferable to use a CO ₂ laser. When the IVH diameter is less than 30 μm, a YAG laser capable of focusing the laser beam is suitable. In addition, examples of the non-photosensitive substrate include the non-photosensitive glass described above, but are not limited thereto. When the core substrate 100 is a photosensitive base material, a region other than a portion that becomes a via hole is masked, irradiated with ultraviolet light, and then a hole that becomes a via hole is formed by heat treatment and etching. Examples of the photosensitive substrate include, but are not limited to, the photosensitive glass described above. Further, when the core substrate 100 is a base material that can be chemically etched with a chemical solution such as an organic solvent, a hole that becomes a via hole can be formed by chemical etching. After forming the via hole as described above, in order to electrically connect the layers, after performing desmear treatment as necessary, the hole is made conductive by a conductive paste or plating, This is a via hole.

(Process c)
(Step c) is a step of forming the second wiring 106b on the surface of the core substrate 100 opposite to the first wiring 106a, as shown in FIG. The second wiring 106b can be formed on the surface opposite to the first wiring of the core substrate 100 in the same manner as the first wiring in the above (step a). As a method for forming a copper layer, as in (Step a), after forming a copper thin film by sputtering, vapor deposition, plating, or the like, electrolytic copper plating is performed until a desired thickness is obtained. Note that the second wiring 106b includes the second interlayer connection terminal 103, and a semi-additive method may be used as a method for forming the fine wiring.

(Process d)
(Step d) is a step of forming a buildup layer (interlayer insulating layer) 104 on the surface on which the second wiring 106b is formed as shown in FIG. 2 (d). Here, first, the surface of the second wiring 106b is desirably degreased and washed with hydrochloric acid or sulfuric acid. Next, a metal more precious than copper, for example, a metal selected from gold, silver, platinum, palladium, rhodium, rhenium, ruthenium, osmium, iridium or an alloy containing these metals is discretely applied to the copper wiring surface ( Formed on the second wiring 106b) and immersed in an alkaline solution containing an oxidizing agent to perform an oxidation treatment, and then a reduction treatment is performed as necessary. Thereafter, at least one of coupling treatment and corrosion inhibition treatment is further performed so that the roughness Rz of the copper wiring surface is 1 nm or more and 1,000 nm or less.

  Next, the buildup layer 104 is formed on the surface of the core substrate 100 and the surface of the second wiring 106b. As the insulating material for the build-up layer 104, a thermosetting resin, a thermoplastic resin, or a mixed resin thereof can be used as described above, but it is preferable to use a thermosetting material as a main component. The build-up layer 104 can be formed by printing or spin coating when the insulating material is varnished, or by lamination or pressing when the insulating material is film-like. When the insulating material includes a thermosetting material, it is desirable to further heat and cure.

(Process e)
(Step e) is a step of forming a second interlayer connection IVH (via hole) 108 in the build-up layer 104 as shown in FIG. 2 (e). It can be performed in the same manner as the first interlayer connection IVH 102 in the step (b).

(Process f)
(Step f) is a step of forming the third wiring 106c on the buildup layer on which the second IVH 108 is formed, as shown in FIG. 2 (f). The third wiring 106c can be formed in the same manner as the first wiring 106a in the above (step a). As a process for forming a fine wiring of L / S = 35 μm / 35 μm or less, the above-described semi-additive method is preferable. Further, it is preferable to form the seed layer described above on the buildup layer 104 by a method such as vapor deposition or plating or a method of bonding a metal foil. In this case, a plating resist is formed on the seed layer in a necessary pattern, wiring is formed by electrolytic copper plating through the seed layer, the plating resist is peeled off, and finally the seed layer is removed by etching or the like. Thus, a fine wiring can be formed.

  (Step d) to (Step f) may be repeated to produce two or more buildup layers 104 as shown in FIG. 2 (g). In this case, the interlayer connection terminal formed in the outermost buildup layer becomes the external connection terminal 107.

(Process g)
(Step g) is a step of forming an insulating coating 109 for protecting the wiring and the like other than the external connection terminals 107 as shown in FIG. As the insulating coating material, a solder resist is used, and a thermosetting type or an ultraviolet curing type can be used, but an ultraviolet curing type capable of finishing the resist shape with high accuracy is preferable. First, the external connection terminal 107 and other wirings are degreased, and then washed with hydrochloric acid or sulfuric acid. Next, a metal selected from gold, silver, platinum, palladium, rhodium, rhenium, ruthenium, osmium and iridium, which are noble metals than copper, or an alloy containing these metals is discretely formed, and an oxidizing agent Oxidation treatment is performed by immersing in an alkaline aqueous solution containing. Thereafter, it is preferable to further perform a reduction treatment. Thereafter, at least one of coupling treatment and corrosion inhibition treatment may be performed. In any case, the treatment is performed so that the Rz on the wiring surface is 1 nm or more and 1,000 nm or less. Thereafter, a solder resist is formed on portions other than the external connection terminals 107, and the external connection terminals 107 are exposed. It is electrically connected to the third wiring via the third interlayer connection IVH 105.

(Shape of semiconductor chip mounting substrate)
The shape of the semiconductor chip mounting substrate is not particularly limited, but is preferably a frame shape as shown in FIG. By making the shape of the semiconductor chip mounting substrate 22 into a frame shape, the semiconductor package can be assembled efficiently. Hereinafter, a preferable frame shape will be described in detail.

  As shown in FIG. 7, a block 23 is formed in which a plurality of semiconductor package regions 13 (parts to be a single semiconductor package) are arranged in rows and columns at regular intervals. Further, such a block is formed in a plurality of rows and columns. Although only two blocks are illustrated in FIG. 7, the blocks may be arranged in a lattice shape as necessary. Here, the width of the space between the semiconductor package regions is preferably 50 to 500 μm, and more preferably 100 to 300 μm. Furthermore, it is most preferable that the blade width of the dicer used when the semiconductor package is cut later is made the same.

  By arranging the semiconductor package region in this way, the semiconductor chip mounting substrate can be effectively used. Further, it is preferable to form a positioning mark 11 or the like at the end of the semiconductor chip mounting substrate, and it is more preferable that the pin hole is a through hole. The shape and arrangement of the pin holes may be selected so as to match the forming method and the semiconductor package assembly apparatus.

  Furthermore, it is preferable to form a reinforcing pattern 24 in the space between the semiconductor package regions or outside the block. The reinforcing pattern may be separately manufactured and bonded to the semiconductor chip mounting substrate, but is preferably a metal pattern formed at the same time as the wiring formed in the semiconductor package region, and the surface thereof is similar to the wiring. More preferably, nickel, gold, or the like is plated or an insulating coating is applied. When the reinforcing pattern is such a metal, it can also be used as a plating lead for electrolytic plating. Moreover, it is preferable to form the cutting position alignment mark 25 at the time of cutting with a dicer outside the block. In this way, a frame-shaped semiconductor chip mounting substrate can be manufactured.

(Semiconductor package)
FIG. 3 is a schematic cross-sectional view showing an embodiment of the flip chip type semiconductor package of the present invention. As shown in FIG. 3, the semiconductor package of the present invention is such that the semiconductor chip 111 is further mounted on the semiconductor chip mounting substrate of the present invention, and the connection bumps 112 are used to connect the semiconductor chip and the semiconductor chip connection terminals. Are electrically connected by flip-chip connection.

  Further, in these semiconductor packages, it is preferable to seal between the semiconductor chip and the semiconductor chip mounting substrate with an underfill material 113 as shown in the figure. The thermal expansion coefficient of the underfill material is preferably approximate to the thermal expansion coefficient of the semiconductor chip 111 and the core substrate 100, but is not limited thereto. More preferably, (thermal expansion coefficient of the semiconductor chip) ≦ (thermal expansion coefficient of the underfill material) ≦ (thermal expansion coefficient of the core substrate). Furthermore, the semiconductor chip can be mounted using an anisotropic conductive film (ACF) or an adhesive film (NCF) that does not contain conductive particles. In this case, since it is not necessary to seal with an underfill material, it is more preferable. Furthermore, it is particularly preferable to use ultrasonic waves together with the semiconductor chip because electrical connection can be made at a low temperature and in a short time.

  FIG. 4 shows a cross-sectional view of an embodiment of the wire bond type semiconductor package of the present invention. Although a general die bond paste can be used for mounting the semiconductor chip, it is more preferable to use a die bond film 117. Electrical connection between the semiconductor chip and the semiconductor chip connection terminal is performed by wire bonding using a gold wire 115. The semiconductor chip can be sealed by transfer molding using a semiconductor sealing resin 116. In this case, the sealing region may seal only a necessary portion, for example, only the face surface of the semiconductor chip, but it is more preferable to seal the entire semiconductor package region as shown in FIG. This is a particularly effective method in the case where a plurality of semiconductor package regions are arranged in rows and columns and the substrate and the sealing resin 116 are cut simultaneously with a dicer or the like.

In addition, for example, a solder ball 114 can be mounted on the external connection terminal 107 for electrical connection with the motherboard. For the solder balls, eutectic solder or Pb-free solder is used. As a method for fixing the solder ball to the external connection terminal 107, for example, an N ₂ reflow apparatus or the like can be used. However, the method is not limited to this.

  A plurality of semiconductor packages formed by mounting a plurality of semiconductor chips on the semiconductor chip mounting substrate are finally cut into individual semiconductor packages using a dicer or the like.

  Hereinafter, the present invention will be described in detail based on examples, but the present invention is not limited thereto.

Example 1
In order to evaluate the reliability of the semiconductor package produced by applying the copper surface treatment of the present invention, a semiconductor package sample was produced as follows.

(Process a)
A 0.4 mm thick soda glass substrate (thermal expansion coefficient: 11 ppm / ° C.) was prepared as the core substrate 100, a 200 nm copper thin film was formed on one side by sputtering, and then plated to a thickness of 10 μm by electrolytic copper plating. In addition, sputtering was performed on condition 1 shown below using the apparatus model number MLH-6315 by Nippon Vacuum Technology Co., Ltd.

Condition 1
Current: 3.5A
Voltage: 500V
Argon flow rate: 35 SCCM (0.059 Pa · m ³ / s)
Pressure: 5 × 10 ⁻³ Torr (6.6 × 10 ⁻¹ Pa)
Deposition rate: 5 nm / second

  After that, an etching resist is formed in a portion to be the first wiring 106a, etched using a ferric chloride etchant, and the etching resist is removed, whereby the first wiring 106a (first interlayer connection terminal 101 is formed). And a semiconductor chip connection terminal).

(Process b)
A hole having a hole diameter of 50 μm was formed with a laser until reaching the first interlayer connection terminal 101 from the surface opposite to the first wiring 106a of the glass substrate on which the first wiring 106a was formed. A YAG laser LAVIA-UV2000 (manufactured by Sumitomo Heavy Industries, Ltd., trade name) was used as the laser, and a hole having IVH was formed under the conditions of a frequency of 4 kHz, a shot number of 50, and a mask diameter of 0.4 mm. Then, desmear treatment in the hole was performed. Thereafter, the hole is filled with conductive paste MP-200V (trade name, manufactured by Hitachi Chemical Co., Ltd.), cured at 160 ° C. for 30 minutes, and electrically connected to the first interlayer connection terminal 101 on the glass substrate. The first interlayer connection IVH102 (via hole) was formed.

(Process c)
In order to electrically connect to the first interlayer connection IVH 102 (first via hole) formed in (Step b), a surface of the glass substrate opposite to the first wiring 106a is sputtered to 200 nm. After forming the copper thin film, plating was performed to a thickness of 10 μm by electrolytic copper plating. Sputtering was performed in the same manner as in (Step a).

  Thereafter, as in (Step a), an etching resist is formed in the shape of the second wiring 106b, etched using a ferric chloride etchant, and the etching resist is removed, whereby the second wiring 106b ( A second interlayer connection terminal 103 is formed.

(Process d)
(Step d-1)
The wiring surface on the second wiring 106b side formed in (Step c) was immersed in an acidic degreasing solution Z-200 (trade name, manufactured by World Metal Co., Ltd.) adjusted to 200 ml / L for 2 minutes at a liquid temperature of 50 ° C. Then, it was washed with hot water by immersing in water at a liquid temperature of 50 ° C. for 2 minutes, and further washed with water for 1 minute. Subsequently, it was immersed in a 3.6 N sulfuric acid aqueous solution for 1 minute and washed with water for 1 minute.

(Process d-2)
The second wiring 106b having undergone the pretreatment step is immersed in a substituted palladium plating solution SA-100 (Hitachi Chemical Industry Co., Ltd., product name) at 30 ° C. for 3 minutes, and palladium plating, which is a noble metal than copper, is performed. the 1.0 [mu] mol / dm ² applied, washed with water for 1 minute, further, 50 to the oxidation treatment solution was added sodium chlorite 15 g / L alkaline solution containing sodium triphosphate 10 g / L and potassium hydroxide 25 g / L By immersing at 3 ° C. for 3 minutes, a 0.07 mg / cm ² copper oxide crystal was formed on the surface of the second wiring 16b. Thereafter, it was washed with water for 5 minutes and dried at 85 ° C. for 30 minutes.

(Process d-3)
Next, an interlayer insulating layer (build-up layer) 104 was formed on the surface on the second wiring 106b side as follows. That is, an insulating varnish of a cyanate ester-based resin composition is applied to the surface on the second wiring 106b side by a spin coating method at a condition of 1500 rpm to form a resin layer having a thickness of 20 μm, and then from room temperature (25 ° C.). Heating to 230 ° C. at a temperature rising rate of 6 ° C./min and thermosetting by holding at 230 ° C. for 80 minutes, a 15 μm buildup layer 104 was formed.

(Process e)
A hole to be an IVH with a hole diameter of 50 μm was formed with a laser until reaching the second interlayer connection terminal 103 from the surface of the buildup layer 104 formed in the above (step d-3). A YAG laser LAVIA-UV2000 (manufactured by Sumitomo Heavy Industries, Ltd., trade name) was used as the laser, and a hole to be IVH was formed under the conditions of a frequency of 4 kHz, a shot number of 20 and a mask diameter of 0.4 mm. Thereafter, desmear treatment was performed. As a desmear treatment method, it was immersed in a swelling liquid circular positive hole 4125 (Rohm and Haas Electronic Materials Co., Ltd., product name) at 80 ° C. for 3 minutes and then washed with water for 3 minutes. Then, it was immersed in desmear liquid circulation MLB promoter 213 (Rohm and Haas Electronic Materials Co., Ltd., product name) at 80 ° C. for 5 minutes and then washed with water for 3 minutes. Subsequently, it was immersed in a reducing liquid circuposit MLB216-4 (Rohm and Haas Electronic Materials Co., Ltd., product name) at 40 ° C. for 3 minutes, washed with water for 3 minutes, and dried at 85 ° C. for 30 minutes.

(Process f)
In order to form the third wiring 106c and the second IVH 108 on the buildup layer 104 formed in the above (step d-3), a Ni layer (underlying metal) having a thickness of 20 nm is formed on the buildup layer 104 by sputtering. ) And a thin film copper layer having a thickness of 200 nm is formed on the Ni layer to form a seed layer. Sputtering was performed under the condition 2 shown below using MLH-6315 manufactured by Nippon Vacuum Technology Co., Ltd.

Condition 2
(Ni layer)
Current: 5.0A
Current: 350V
Voltage argon flow rate: 35 SCCM (0.059 Pa · m ³ / s)
Pressure: 5 × 10 ⁻³ Torr (6.6 × 10 ⁻¹ Pa)
Deposition rate: 0.3 nm / second (thin copper layer)
Current: 3.5A
Voltage: 500V
Argon flow rate: 35 SCCM (0.059 Pa · m ³ / s)
Pressure: 5 × 10 ⁻³ Torr (6.6 × 10 ⁻¹ Pa)
Deposition rate: 5 nm / second

Next, a plating resist PMER P-LA900PM (manufactured by Tokyo Ohka Kogyo Co., Ltd., trade name) was applied onto the seed layer (on the thin film copper layer) by a spin coating method to form a plating resist layer having a thickness of 10 μm. Next, the plating resist layer was exposed under the condition of 1000 mJ / cm ² and then immersed in PMER developer P-7G at 23 ° C. for 6 minutes to form a resist pattern of L / S = 10 μm / 10 μm. Thereafter, electrolytic copper plating was performed using a copper sulfate plating solution to form a third wiring 106c having a thickness of about 5 μm. The plating resist was peeled off by immersion for 1 minute at room temperature (25 ° C.) using methyl ethyl ketone. In addition, for quick etching of the seed layer, a 5-fold diluted solution of CPE-700 (manufactured by Mitsubishi Gas Chemical Co., Ltd., trade name) is used for etching removal by immersing and shaking at 30 ° C. for 30 seconds. A wiring pattern was formed.

(Process g)
Thereafter, the steps (d) to (step f) were repeated again to form a further outermost layer wiring including the buildup layer and the external connection terminal 107.

  Finally, a solder resist 109 is formed, and then the external connection terminal 107 and the semiconductor chip connection terminal are subjected to gold plating, and FIG. 1 (sectional view for one package), FIG. 5 (plan view for one package), And the semiconductor chip mounting substrate for fan-in type BGA as shown in FIG. 7 (semiconductor chip mounting substrate whole figure) was produced.

(Process h)
The semiconductor chip 111 in which the connection bumps 112 are formed in the semiconductor chip mounting region of the semiconductor chip mounting substrate manufactured by the above (steps a) to (g) is necessary while applying ultrasonic waves using a flip chip bonder. A large number were installed. Furthermore, an underfill material 113 is injected from the end of the semiconductor chip into the gap between the semiconductor chip mounting substrate and the semiconductor chip, and primary curing is performed at 80 ° C. for 1 hour and secondary curing at 150 ° C. for 4 hours using an oven. went. Next, a lead / tin eutectic solder ball 114 having a diameter of 0.45 mm was fused to the external connection terminal 107 using an N ₂ reflow apparatus. Finally, the semiconductor chip mounting substrate was cut with a dicer equipped with a blade having a width of 200 μm to produce the semiconductor package shown in FIG.

(Example 2)
After forming a copper oxide crystal on the surface of the second wiring 106b in (Step d-2), before forming the buildup layer 104 in (Step d-3), the surface of the second wiring 106b is left for 5 minutes. Washing with water, immersion in reduction treatment solution HIST-100D (trade name, manufactured by Hitachi Chemical Co., Ltd.) for 3 minutes at 40 ° C., washing with water for 10 minutes, and drying at 85 ° C. for 30 minutes. Produced the semiconductor chip mounting substrate and semiconductor package for fan-in type BGA in the same manner as in Example 1.

(Example 3)
After forming a copper oxide crystal on the surface of the second wiring 106b in (Step d-2), before forming the buildup layer 104 in (Step d-3), the surface of the second wiring 106b is left for 5 minutes. Example except that it was washed with water, dipped in 0.5% by weight aqueous solution of γ-aminopropyltriethoxysilane at 30 ° C. for 3 minutes, further washed with water for 1 minute, and dried at 85 ° C. for 30 minutes. In the same manner as in Example 1, a fan-in type BGA semiconductor chip mounting substrate and a semiconductor package were produced.

Example 4
After forming a copper oxide crystal on the surface of the second wiring 106b in (Step d-2), before forming the buildup layer 104 in (Step d-3), the surface of the second wiring 106b is left for 5 minutes. Washed with water, immersed in an ethanol solution having a concentration of 2-amino-6-hydroxy-8-mercaptopurine (trade name, manufactured by Wako Pure Chemical Industries, Ltd.) of 10 ppm at 25 ° C. for 10 minutes, further washed with water for 1 minute, A fan-in type BGA semiconductor chip mounting substrate and a semiconductor package were produced in the same manner as in Example 1 except that the corrosion inhibition treatment step of drying at 85 ° C. for 30 minutes was performed.

(Example 5)
After forming a copper oxide crystal on the surface of the second wiring 106b in (Step d-2), before forming the buildup layer 104 in (Step d-3), the surface of the second wiring 106b is left for 5 minutes. Washed with water, immersed in an ethanol solution having a concentration of 10 ppm of 3-amino-5-mercapto-1,2,4-triazole (manufactured by Wako Pure Chemical Industries, Ltd.) at 25 ° C. for 10 minutes, and further for 1 minute A fan-in type BGA semiconductor chip mounting substrate and a semiconductor package were produced in the same manner as in Example 1 except that the corrosion inhibition treatment step was performed by washing with water and drying at 85 ° C. for 30 minutes.

(Example 6)
After forming a copper oxide crystal on the surface of the second wiring 106b in (Step d-2), before forming the buildup layer 104 in (Step d-3), the surface of the second wiring 106b is left for 5 minutes. Washed with water, immersed in an ethanol solution having a concentration of 2-amino-6-hydroxy-8-mercaptopurine (trade name, manufactured by Wako Pure Chemical Industries, Ltd.) of 10 ppm at 25 ° C. for 10 minutes, further washed with water for 1 minute, A corrosion inhibition treatment process is performed by drying at 85 ° C. for 30 minutes, and then further immersed in a 0.5% by weight aqueous solution of γ-aminopropyltriethoxysilane at 30 ° C. for 3 minutes, further washed with water for 1 minute, and then at 85 ° C. for 30 minutes. A fan-in type BGA semiconductor chip mounting substrate and a semiconductor package were produced in the same manner as in Example 1 except that the coupling process step for drying was performed.

(Example 7)
After forming a copper oxide crystal on the surface of the second wiring 106b in (Step d-2), before forming the buildup layer 104 in (Step d-3), the surface of the second wiring 106b is left for 5 minutes. Washed with water, immersed in a 0.5% by weight aqueous solution of γ-aminopropyltriethoxysilane at 30 ° C. for 3 minutes, further washed with water for 1 minute, and dried at 85 ° C. for 30 minutes. It is immersed in an ethanol solution having a concentration of amino-5-mercapto-1,2,4-triazole (manufactured by Wako Pure Chemical Industries, Ltd., trade name) of 10 ppm at 25 ° C. for 10 minutes, further washed with water for 1 minute, and 85 ° C. A semiconductor chip mounting substrate for a fan-in type BGA and a semiconductor package were produced in the same manner as in Example 1 except that the corrosion inhibition treatment process for drying for 30 minutes was performed.

(Example 8)
After forming a copper oxide crystal on the surface of the second wiring 106b in (Step d-2), before forming the buildup layer 104 in (Step d-3), the surface of the second wiring 106b is left for 5 minutes. It is washed with water, immersed in a reducing solution HIST-100D (trade name, manufactured by Hitachi Chemical Co., Ltd.) for 3 minutes at 40 ° C., and further washed with water for 10 minutes. Thereafter, γ-aminopropyltriethoxysilane 0 For fan-in type BGA as in Example 1, except that a coupling treatment step of immersing in a 5% by weight aqueous solution at 30 ° C. for 3 minutes, further washing with water for 1 minute, and drying at 85 ° C. for 30 minutes was performed. A semiconductor chip mounting substrate and a semiconductor package were produced.

Example 9
After forming a copper oxide crystal on the surface of the second wiring 106b in (Step d-2), before forming the buildup layer 104 in (Step d-3), the surface of the second wiring 106b is left for 5 minutes. It is washed with water, immersed in a reduction treatment solution HIST-100D (manufactured by Hitachi Chemical Co., Ltd., trade name) for 3 minutes at 40 ° C., and further washed with water for 10 minutes. -8-Mercaptopurine (made by Wako Pure Chemical Industries, Ltd., trade name) is immersed in an ethanol solution having a concentration of 10 ppm at 25 ° C. for 10 minutes, further washed with water for 1 minute, and dried at 85 ° C. for 30 minutes. A fan-in type BGA semiconductor chip mounting substrate and a semiconductor package were produced in the same manner as in Example 1 except that the steps were performed.

(Example 10)
After forming a copper oxide crystal on the surface of the second wiring 106b in (Step d-2), before forming the buildup layer 104 in (Step d-3), the surface of the second wiring 106b is left for 5 minutes. It is washed with water, immersed in a reduction treatment solution HIST-100D (trade name, manufactured by Hitachi Chemical Co., Ltd.) for 3 minutes at 40 ° C., and further washed with water for 10 minutes. Thereafter, 3-amino-5-mercapto is further added. -1,2,4-triazole (made by Wako Pure Chemical Industries, Ltd., trade name) is immersed in an ethanol solution having a concentration of 10 ppm at 25 ° C. for 10 minutes, further washed with water for 1 minute, and dried at 85 ° C. for 30 minutes. A fan-in type BGA semiconductor chip mounting substrate and a semiconductor package were produced in the same manner as in Example 1 except that the corrosion inhibition treatment step was performed.

(Example 11)
After forming a copper oxide crystal on the surface of the second wiring 106b in (Step d-2), before forming the buildup layer 104 in (Step d-3), the surface of the second wiring 106b is left for 5 minutes. It is washed with water, immersed in a reduction treatment solution HIST-100D (manufactured by Hitachi Chemical Co., Ltd., trade name) for 3 minutes at 40 ° C., and further washed with water for 10 minutes. Thereafter, 2-amino-6-hydroxy is further added. -8-Mercaptopurine (made by Wako Pure Chemical Industries, Ltd., trade name) is immersed in an ethanol solution having a concentration of 10 ppm at 25 ° C. for 10 minutes, further washed with water for 1 minute, and dried at 85 ° C. for 30 minutes. Then, the substrate is further immersed in a 0.5% by weight aqueous solution of γ-aminopropyltriethoxysilane at 30 ° C. for 3 minutes, washed with water for 1 minute, and dried at 85 ° C. for 30 minutes. Except performing the pulling process, the fan in the same manner as in Example 1 - was produced semiconductor chip mounting substrate and a semiconductor package in type BGA.

(Example 12)
After forming a copper oxide crystal on the surface of the second wiring 106b in (Step d-2), before forming the buildup layer 104 in (Step d-3), the surface of the second wiring 106b is left for 5 minutes. Washing with water, reducing treatment HIST-100D (manufactured by Hitachi Chemical Co., Ltd., trade name) for 3 minutes at 40 ° C. and further washing with water for 10 minutes, followed by further γ-aminopropyltriethoxysilane A coupling treatment step of immersing in a 0.5% by weight aqueous solution at 30 ° C. for 3 minutes, further washing with water for 1 minute, and drying at 85 ° C. for 30 minutes is performed, and then 3-amino-5-mercapto-1,2, Immerse it in an ethanol solution having a concentration of 4-triazole (trade name, manufactured by Wako Pure Chemical Industries, Ltd.) of 10 ppm at 25 ° C. for 10 minutes, wash with water for 1 minute, and dry at 85 ° C. for 30 minutes. Except performing the corrosion inhibiting treatment step of the fan in the same manner as in Example 1 - was produced semiconductor chip mounting substrate and a semiconductor package in type BGA.

(Example 13)
Instead of the substituted palladium plating solution SA-100 (Hitachi Chemical Industry Co., Ltd., product name) used in (Step d-2), a substituted gold plating solution HGS-500 (Hitachi Chemical Industry Co., Ltd., product name) was used. After immersing the surface of the second wiring 106b in the replacement gold plating solution at 30 ° C. for 1 minute, applying 1.0 μmol / dm ^{2 of} gold plating, which is a noble metal than copper, to the wiring surface, and washing with water for 1 minute. Further, the surface of the second wiring 106b is immersed in an oxidizing solution containing 15 g / L of sodium chlorite in an alkaline solution containing 10 g / L of trisodium phosphate and 25 g / L of potassium hydroxide at 50 ° C. for 3 minutes. Then, 0.03 mg / cm ² of copper oxide crystals are formed, further washed with water for 5 minutes, and reduced to a treatment liquid HIST-100D (trade name, manufactured by Hitachi Chemical Co., Ltd.) at 40 ° C. for 3 minutes. A fan-in type BGA semiconductor chip mounting substrate and a semiconductor package were produced in the same manner as in Example 1 except that the reduction treatment step was performed in which the substrate was soaked, washed with water for 10 minutes, and dried at 85 ° C. for 30 minutes. .

(Example 14)
In place of the substituted palladium plating solution SA-100 (Hitachi Chemical Industry Co., Ltd., product name) used in (Step d-2), silver nitrate 7.5 g / L, ammonia hydroxide 75 g / L, sodium thiosulfate pentahydrate The surface of the second wiring 106b is immersed in the replacement silver plating solution for 20 seconds at 30 ° C. using a replacement silver plating solution containing 30 g / L of the product, and the surface of the wiring is silver nobler than copper. After applying 1.0 μmol / dm ² and washing with water for 1 minute, it was further added to an oxidation treatment solution obtained by adding 15 g / L of sodium chlorite to an alkaline solution containing 10 g / L of trisodium phosphate and 25 g / L of potassium hydroxide. For 3 minutes to form 0.05 mg / cm ² of copper oxide crystals on the surface of the second wiring 106b, and then washed with water for 5 minutes to reduce the reduction treatment solution HIST-1. Example 1 except that a reduction treatment step was performed in 00D (manufactured by Hitachi Chemical Co., Ltd., trade name) at 40 ° C. for 3 minutes, followed by washing with water for 10 minutes and drying at 85 ° C. for 30 minutes. Thus, a semiconductor chip mounting substrate for a fan-in type BGA and a semiconductor package were produced.

(Comparative Example 1)
After performing the pretreatment in (Step d-1) in (Step d), the surface of the second wiring 106b is subjected to an oxidation treatment solution at 85 ° C. for 3 minutes without performing substitution palladium plating in (Step d-2). A fan-in type BGA semiconductor chip mounting substrate and a semiconductor package were produced in the same manner as in Example 1 except that immersion was performed to form a 0.50 mg / cm ² copper oxide crystal on the wiring surface.

(Comparative Example 2)
After performing the pretreatment in (Step d-1) in (Step d), the surface of the second wiring 106b is subjected to an oxidation treatment solution at 85 ° C. for 3 minutes without performing substitution palladium plating in (Step d-2). Immersion is performed to form a 0.50 mg / cm ² copper oxide crystal on the surface of the wiring 106b, and then the substrate is washed with water for 5 minutes, and the reduction treatment liquid HIST-100D (trade name, manufactured by Hitachi Chemical Co., Ltd.) A fan-in type BGA semiconductor chip mounting substrate and a semiconductor as in Example 1 except that the reduction treatment step was carried out for 3 minutes at 40 ° C, followed by washing with water for 10 minutes and drying at 85 ° C for 30 minutes. A package was produced.

(Comparative Example 3)
After performing the pretreatment in (Step d-1) in (Step d), the surface of the second wiring 106b is made of a microetching agent without performing substitution palladium plating and oxidation treatment in (Step d-2). After immersing in etch bond CZ8100 (trade name, manufactured by MEC Co., Ltd.) at 40 ° C. for 1 minute and 30 seconds, washing with water, then immersing in a 3.6N sulfuric acid aqueous solution at room temperature for 60 seconds, and further washing with water for 1 minute, 85 A fan-in type BGA semiconductor chip mounting substrate and a semiconductor package were produced in the same manner as in Example 1 except that the substrate was dried at 30 ° C. for 30 minutes.

(Comparative Example 4)
After the pretreatment in (Step d-1) in (Step d), the step (Step d-2) was not performed. That is, the unevenness forming process was not performed. Other than that was carried out similarly to Example 1, and produced the semiconductor chip mounting substrate and semiconductor package for fan-in type BGA.

(Example 15)
In order to evaluate the adhesion, cleanliness, smoothness, glossiness, and surface shape of the copper surface after the copper surface treatment of the present invention, an 18 μm electrolytic copper foil GTS-18 (trade name, manufactured by Furukawa Circuit Foil Co., Ltd.) Cut into 5 cm x 8 cm x 5 sheets (for adhesion test, copper surface cleanliness evaluation, copper surface smoothness evaluation, copper surface shape evaluation, copper surface gloss evaluation), and implemented on one side of each electrolytic copper foil Each surface treatment (pretreatment, noble metal formation and oxidation treatment) for the wiring surface described in (Step d-1) and (Step d-2) of Example 1 was performed to prepare a test piece of electrolytic copper foil.

(Example 16)
As the surface treatment for the electrolytic copper foil, the same treatment as in Example 15 was performed, except that the same surface treatment as the surface treatment (pretreatment, noble metal formation, oxidation treatment and reduction treatment) on the wiring surface described in Example 2 was performed. A test piece of electrolytic copper foil was prepared.

(Example 17)
As the surface treatment for the electrolytic copper foil, Example 15 and Example 15 were performed except that the same surface treatment as each surface treatment (pretreatment, noble metal formation, oxidation treatment and coupling treatment) for the wiring surface described in Example 3 was performed. Similarly, a test piece of electrolytic copper foil was produced.

(Example 18)
As the surface treatment for the electrolytic copper foil, Example 15 and Example 15 were performed except that the same surface treatment as each surface treatment (pretreatment, noble metal formation, oxidation treatment and corrosion inhibition treatment) for the wiring surface described in Example 4 was performed. Similarly, a test piece of electrolytic copper foil was produced.

Example 19
As the surface treatment for the electrolytic copper foil, Example 15 and Example 15 were performed except that the same surface treatment as each surface treatment (pretreatment, noble metal formation, oxidation treatment and corrosion inhibition treatment) for the wiring surface described in Example 5 was performed. Similarly, a test piece of electrolytic copper foil was produced.

(Example 20)
As the surface treatment for the electrolytic copper foil, except that the same surface treatment as each surface treatment (pretreatment, noble metal formation, oxidation treatment, corrosion inhibition treatment and coupling treatment) described in Example 6 was performed, A test piece of electrolytic copper foil was prepared in the same manner as in Example 15.

(Example 21)
As the surface treatment for the electrolytic copper foil, except that the surface treatment similar to each surface treatment (pretreatment, noble metal formation, oxidation treatment, coupling treatment and corrosion inhibition treatment) for the wiring surface described in Example 7 was performed, A test piece of electrolytic copper foil was prepared in the same manner as in Example 15.

(Example 22)
As the surface treatment for the electrolytic copper foil, except that the same surface treatment as each surface treatment (pretreatment, noble metal formation, oxidation treatment, reduction treatment and coupling treatment) for the wiring surface described in Example 8 was performed. A test piece of electrolytic copper foil was prepared in the same manner as in Example 15.

(Example 23)
As the surface treatment for the electrolytic copper foil, except that the same surface treatment as each surface treatment (pretreatment, noble metal formation, oxidation treatment, reduction treatment and corrosion inhibition treatment) for the wiring surface described in Example 9 was performed. A test piece of electrolytic copper foil was prepared in the same manner as in Example 15.

(Example 24)
As the surface treatment for the electrolytic copper foil, except that the same surface treatment as each surface treatment (pretreatment, noble metal formation, oxidation treatment, reduction treatment and corrosion inhibition treatment) for the wiring surface described in Example 10 was performed. A test piece of electrolytic copper foil was prepared in the same manner as in Example 15.

(Example 25)
As the surface treatment for the electrolytic copper foil, the same surface treatment as the surface treatment (pretreatment, noble metal formation, oxidation treatment, reduction treatment, corrosion inhibition treatment and coupling treatment) described in Example 11 was performed. Except that, an electrolytic copper foil test piece was prepared in the same manner as in Example 15.

(Example 26)
As the surface treatment for the electrolytic copper foil, the same surface treatment as the surface treatment (pretreatment, noble metal formation, oxidation treatment, reduction treatment, coupling treatment, and corrosion inhibition treatment) for the wiring surface described in Example 12 was performed. Except that, an electrolytic copper foil test piece was prepared in the same manner as in Example 15.

(Example 27)
As the surface treatment for the electrolytic copper foil, except that the same surface treatment as each surface treatment (pretreatment, noble metal (gold) formation and oxidation treatment, reduction treatment) for the wiring surface described in Example 13 was performed. In the same manner as in Example 15, a test piece of electrolytic copper foil was prepared.

(Example 28)
The surface treatment for the electrolytic copper foil was carried out in the same way as the surface treatment (pretreatment, noble metal (silver) formation and oxidation treatment, reduction treatment) described in Example 14 except that the same surface treatment was applied. In the same manner as in Example 15, a test piece of electrolytic copper foil was prepared.

(Comparative Example 5)
As a surface treatment for the electrolytic copper foil, a test of the electrolytic copper foil was performed in the same manner as in Example 15 except that the surface treatment similar to each surface treatment (pretreatment and oxidation treatment) for the wiring surface described in Comparative Example 1 was performed. A piece was made.

(Comparative Example 6)
As the surface treatment for the electrolytic copper foil, electrolytic copper was obtained in the same manner as in Example 15 except that the same surface treatment as the surface treatment (pretreatment, oxidation treatment and reduction treatment) for the wiring surface described in Comparative Example 2 was performed. A foil specimen was prepared.

(Comparative Example 7)
As a surface treatment for the electrolytic copper foil, a test of the electrolytic copper foil was performed in the same manner as in Example 15 except that the surface treatment similar to each surface treatment (pretreatment and etching treatment) for the wiring surface described in Comparative Example 3 was performed. A piece was made.

(Comparative Example 8)
As a surface treatment for the electrolytic copper foil, an electrolytic copper foil was obtained in the same manner as in Example 15 except that the surface treatment similar to each surface treatment (no pretreatment and unevenness formation treatment) for the wiring surface described in Comparative Example 4 was performed. A test piece was prepared.

(Example 29)
In order to evaluate the insulation resistance value between the wires and the PCT resistance by the copper surface treatment of the present invention in (Step d), the following evaluation substrate was prepared.

(Process a ′)
A 0.4 mm thick soda glass substrate (thermal expansion coefficient 11 ppm / ° C.) was prepared as the core substrate 100 shown in FIGS. 9 and 10, and the interlayer insulating layer 104 was formed on one side as follows. That is, an insulating varnish of a cyanate ester resin composition was applied onto a glass substrate by spin coating at 1500 rpm to form a resin layer having a thickness of 20 μm, and then increased from room temperature (25 ° C.) to 6 ° C./min. Heating to 230 ° C. at a temperature rate and thermosetting by maintaining at 230 ° C. for 80 minutes, an interlayer insulating layer 104 was formed. Thereafter, only the copper thin film 118 having a thickness of 200 nm was formed by (Step a) of Example 1.

Next, a plating resist PMER P-LA900PM (manufactured by Tokyo Ohka Kogyo Co., Ltd., trade name) was applied on the copper foil film by a spin coating method to form a plating resist layer having a thickness of 10 μm. Next, the plating resist layer was exposed under the condition of 1000 mJ / cm ² and then immersed in PMER developer P-7G for 6 minutes at 23 ° C. to form a resist pattern 119. Thereafter, electrolytic copper plating was performed using a copper sulfate plating solution to form a wiring 106 having a thickness of about 5 μm. The plating resist was peeled off by immersion for 1 minute at room temperature (25 ° C.) using methyl ethyl ketone. In addition, for quick etching of the seed layer, a 5-fold diluted solution of CPE-700 (manufactured by Mitsubishi Gas Chemical Co., Ltd., trade name) is used for etching removal by immersing and shaking at 30 ° C. for 30 seconds. The wiring 106 was formed.

(Process d ')
The surface treatment (pretreatment, noble metal formation, oxidation treatment) described in (Step d-1) and (Step d-2) of Example 1 is performed on the wiring 106 formed in the above (Step a ′). Then, an interlayer insulating layer (build-up layer) 104 shown in FIG. 9 and a solder resist 109 shown in FIG. 10 are formed, respectively, and L / S = 5 μm / 5 μm shown in FIG. 11 and L / S = 10 μm shown in FIG. Thirty-two evaluation substrates each having a size of / 10 μm were prepared.

(Example 30)
As each surface treatment in the above (Step d ′), except that the same surface treatment as each surface treatment (pretreatment, noble metal formation, oxidation treatment and reduction treatment) for the wiring surface described in Example 2 was performed. An evaluation substrate was prepared in the same manner as in Example 29.

(Example 31)
As each surface treatment in the above (Step d ′), except that the same surface treatment as each surface treatment (pretreatment, noble metal formation, oxidation treatment and coupling treatment) for the wiring surface described in Example 3 was performed, An evaluation substrate was produced in the same manner as in Example 29.

(Example 32)
As each surface treatment in the above (Step d ′), except that the same surface treatment as each surface treatment (pretreatment, noble metal formation, oxidation treatment and corrosion inhibition treatment) for the wiring surface described in Example 4 was performed, An evaluation substrate was produced in the same manner as in Example 29.

(Example 33)
As each surface treatment in the above (step d ′), except that a surface treatment similar to each surface treatment (pretreatment, noble metal formation, oxidation treatment and corrosion inhibition treatment) for the wiring surface described in Example 5 was performed, An evaluation substrate was produced in the same manner as in Example 29.

(Example 34)
As each surface treatment in the above (step d ′), the same surface treatment as that for each surface treatment (pretreatment, precious metal formation, oxidation treatment, corrosion inhibition treatment and coupling treatment) described in Example 6 is performed. A substrate for evaluation was produced in the same manner as in Example 29 except that.

(Example 35)
As each surface treatment in the above (step d ′), the same surface treatment as the surface treatment (pretreatment, noble metal formation, oxidation treatment, coupling treatment, and corrosion inhibition treatment) for the wiring surface described in Example 7 is performed. A substrate for evaluation was produced in the same manner as in Example 29 except that.

(Example 36)
As each surface treatment in the above (step d ′), the same surface treatment as each surface treatment (pretreatment, noble metal formation, oxidation treatment, reduction treatment and coupling treatment) for the wiring surface described in Example 8 was performed. Except for the above, an evaluation substrate was produced in the same manner as in Example 29.

(Example 37)
As each surface treatment in the above (step d ′), the same surface treatment as each surface treatment (pretreatment, noble metal formation, oxidation treatment, reduction treatment and corrosion inhibition treatment) for the wiring surface described in Example 9 was performed. Except for the above, an evaluation substrate was produced in the same manner as in Example 29.

(Example 38)
As each surface treatment in the above (step d ′), the same surface treatment as each surface treatment (pretreatment, noble metal formation, oxidation treatment, reduction treatment and corrosion inhibition treatment) for the wiring surface described in Example 10 was performed. Except for the above, an evaluation substrate was produced in the same manner as in Example 29.

(Example 39)
Surfaces similar to the respective surface treatments (pretreatment, noble metal formation, oxidation treatment, reduction treatment, corrosion inhibition treatment and coupling treatment) for the wiring surface described in Example 11 as the respective surface treatments in (Step d ′) above. A substrate for evaluation was produced in the same manner as in Example 29 except that the treatment was performed.

(Example 40)
Surfaces similar to the respective surface treatments (pretreatment, noble metal formation, oxidation treatment, reduction treatment, coupling treatment and corrosion inhibition treatment) for the wiring surface described in Example 12 as the respective surface treatments in (Step d ′) above. A substrate for evaluation was produced in the same manner as in Example 29 except that the treatment was performed.

(Example 41)
As each surface treatment in the above (step d ′), the same surface treatment as the surface treatment (pretreatment, noble metal (gold) formation, oxidation treatment, reduction treatment) for the wiring surface described in Example 13 was performed. Produced a substrate for evaluation in the same manner as in Example 29.

(Example 42)
As each surface treatment in the above (step d ′), the same surface treatment as the surface treatment (pretreatment, noble metal (silver) formation, oxidation treatment, reduction treatment) for the wiring surface described in Example 14 was performed. Produced a substrate for evaluation in the same manner as in Example 29.

(Comparative Example 9)
Evaluation was performed in the same manner as in Example 29, except that each surface treatment in the above (Step d ′) was subjected to the same surface treatment as the surface treatment (pretreatment and oxidation treatment) for the wiring surface described in Comparative Example 1. A substrate was prepared.

(Comparative Example 10)
As Example 29, except that each surface treatment in the above (Step d ′) was subjected to the same surface treatment as each surface treatment (pretreatment, oxidation treatment and reduction treatment) for the wiring surface described in Comparative Example 2. Similarly, an evaluation substrate was produced.

(Comparative Example 11)
Evaluation was performed in the same manner as in Example 29, except that each surface treatment in the above (Step d ′) was subjected to the same surface treatment as the surface treatment (pretreatment and etching treatment) on the wiring surface described in Comparative Example 3. A substrate was prepared.

(Comparative Example 12)
Same as Example 29, except that each surface treatment in the above (step d ′) was subjected to the same surface treatment as the surface treatment (no pretreatment and unevenness formation treatment) for the wiring surface described in Comparative Example 4. An evaluation substrate was prepared.

(Example 43)
In order to evaluate the resist pattern formability and the wiring formability when the copper surface treatment of the present invention was used as a pretreatment for resist pattern formation, the following evaluation substrates were prepared.

(Process a ′)
A 0.4 mm thick soda glass substrate (thermal expansion coefficient 11 ppm / ° C.) was prepared as the core substrate 100 shown in FIGS. 9 and 10, and the interlayer insulating layer 104 was formed on one side as follows. That is, an insulating varnish of a cyanate ester resin composition was applied onto a glass substrate by spin coating at 1500 rpm to form a resin layer having a thickness of 20 μm, and then increased from room temperature (25 ° C.) to 6 ° C./min. Heating to 230 ° C. at a temperature rate and thermosetting by maintaining at 230 ° C. for 80 minutes, an interlayer insulating layer 104 was formed. Thereafter, only the copper thin film 118 was formed by (Step a) of Example 1.

  Furthermore, each surface treatment (pretreatment, noble metal formation, oxidation treatment) described in Example 1 (Step d-1) and (Step d-2) was performed on the copper thin film 118 formed above.

Next, a plating resist PMER P-LA900PM (manufactured by Tokyo Ohka Kogyo Co., Ltd., trade name) was applied onto the copper foil film subjected to the copper surface treatment by a spin coating method to form a plating resist layer having a thickness of 10 μm. Next, the plating resist layer was exposed under the condition of 1000 mJ / cm ² and then immersed in PMER developer P-7G for 6 minutes at 23 ° C. to form a resist pattern 119. Thereafter, electrolytic copper plating was performed using a copper sulfate plating solution to form a wiring 106 having a thickness of about 5 μm. The plating resist was peeled off by immersion for 1 minute at room temperature (25 ° C.) using methyl ethyl ketone. In addition, for quick etching of the seed layer, a 5-fold diluted solution of CPE-700 (manufactured by Mitsubishi Gas Chemical Co., Ltd., trade name) is used for etching removal by immersing and shaking at 30 ° C. for 30 seconds. Wiring 106 was formed, and 32 evaluation substrates with L / S = 5 μm / 5 μm shown in FIG. 11 and L / S = 10 μm / 10 μm shown in FIG.

(Example 44)
As each surface treatment in the above (step a ′), except that the surface treatment similar to each surface treatment (pretreatment, noble metal formation, oxidation treatment and reduction treatment) for the wiring surface described in Example 2 was performed. An evaluation substrate was prepared in the same manner as in Example 43.

(Example 45)
As each surface treatment in the above (step a ′), except for performing the same surface treatment as each surface treatment (pretreatment, noble metal formation, oxidation treatment and coupling treatment) on the wiring surface described in Example 3, An evaluation substrate was produced in the same manner as in Example 43.

(Example 46)
As each surface treatment in the above (step a ′), except for performing the same surface treatment as each surface treatment (pretreatment, noble metal formation, oxidation treatment and corrosion inhibition treatment) for the wiring surface described in Example 4, An evaluation substrate was produced in the same manner as in Example 43.

(Example 47)
As each surface treatment in the above (Step a ′), except that the same surface treatment as each surface treatment (pretreatment, noble metal formation, oxidation treatment and corrosion inhibition treatment) for the wiring surface described in Example 5 was performed, An evaluation substrate was produced in the same manner as in Example 43.

(Example 48)
As each surface treatment in the above (step a ′), the same surface treatment as the surface treatment (pretreatment, noble metal formation, oxidation treatment, corrosion inhibition treatment and coupling treatment) for the wiring surface described in Example 6 is performed. A substrate for evaluation was produced in the same manner as in Example 43 except that.

(Example 49)
As each surface treatment in the above (step a ′), the same surface treatment as that for each surface treatment (pretreatment, noble metal formation, oxidation treatment, coupling treatment and corrosion inhibition treatment) described in Example 7 is performed. A substrate for evaluation was produced in the same manner as in Example 43 except that.

(Example 50)
As each surface treatment in the above (step a ′), the same surface treatment as the surface treatment (pretreatment, noble metal formation, oxidation treatment, reduction treatment and coupling treatment) for the wiring surface described in Example 8 was performed. A substrate for evaluation was produced in the same manner as in Example 43 except for the above.

(Example 51)
As each surface treatment in the above (step a ′), the same surface treatment as each surface treatment (pretreatment, noble metal formation, oxidation treatment, reduction treatment and corrosion inhibition treatment) for the wiring surface described in Example 9 was performed. A substrate for evaluation was produced in the same manner as in Example 43 except for the above.

(Example 52)
As each surface treatment in the above (step a ′), the same surface treatment as each surface treatment (pretreatment, noble metal formation, oxidation treatment, reduction treatment and corrosion inhibition treatment) for the wiring surface described in Example 10 was performed. A substrate for evaluation was produced in the same manner as in Example 43 except for the above.

(Example 53)
Surfaces similar to the respective surface treatments (pretreatment, noble metal formation, oxidation treatment, reduction treatment, corrosion inhibition treatment and coupling treatment) for the wiring surface described in Example 11 as the respective surface treatments in (Step a ′) above An evaluation substrate was produced in the same manner as in Example 43 except that the treatment was performed.

(Example 54)
Surfaces similar to the respective surface treatments (pretreatment, noble metal formation, oxidation treatment, reduction treatment, coupling treatment and corrosion inhibition treatment) for the wiring surface described in Example 12 as the respective surface treatments in (Step a ′) above An evaluation substrate was produced in the same manner as in Example 43 except that the treatment was performed.

(Example 55)
As each surface treatment in the above (step a ′), except that the same surface treatment as each surface treatment (pretreatment, noble metal (gold) formation, oxidation treatment, reduction treatment) for the wiring surface described in Example 13 was performed. Produced an evaluation substrate in the same manner as in Example 43.

(Example 56)
As each surface treatment in the above (step a ′), the same surface treatment as the surface treatment (pretreatment, noble metal (silver) formation, oxidation treatment, reduction treatment) for the wiring surface described in Example 14 was performed. Produced an evaluation substrate in the same manner as in Example 43.

(Comparative Example 13)
Evaluation was performed in the same manner as in Example 43, except that each surface treatment (pretreatment and oxidation treatment) on the wiring surface described in Comparative Example 1 was performed as each surface treatment in (Step a ′). A substrate was prepared.

(Comparative Example 14)
As Example 43, each surface treatment in the above (Step a ′) was performed except that the same surface treatment as the surface treatment (pretreatment, oxidation treatment and reduction treatment) for the wiring surface described in Comparative Example 2 was performed. Similarly, an evaluation substrate was produced.

(Comparative Example 15)
Evaluation was performed in the same manner as in Example 43, except that each surface treatment in the above (step a ′) was subjected to the same surface treatment as the surface treatment (pretreatment and etching treatment) on the wiring surface described in Comparative Example 3. A substrate was prepared.

(Comparative Example 16)
Same as Example 43, except that each surface treatment in the above (Step a ′) was subjected to the same surface treatment as the surface treatment (no pretreatment and concavo-convex formation treatment) for the wiring surface described in Comparative Example 4. An evaluation substrate was prepared.

(Example 57)
In order to evaluate the presence or absence of pink ring generation by the copper surface treatment of the present invention, the following evaluation substrate was prepared.

  After performing electroplating on the copper thin film 118 formed in the same manner as (Step a ′) of Example 43, and after performing each surface treatment (pretreatment and precious metal formation, oxidation treatment) of (Step a ′) GXA of a prepreg in which a glass cloth is impregnated with a cyanate ester resin composition on the copper surface after the surface treatment without performing a wiring formation process (resist application, exposure, development, electroplating, resist peeling, etching) -67N (trade name, manufactured by Hitachi Chemical Co., Ltd.) is stacked, heated at a pressure of 3.0 MPa from room temperature (25 ° C.) to 230 ° C. at a temperature increase rate of 6 ° C./min, and held at 230 ° C. for 1 hour. And laminated.

  Thereafter, 20 holes each having a hole diameter of 0.1 mm, 0.2 mm, and 0.3 mm were formed in the laminate obtained above by laser, and a pink ring occurrence evaluation substrate was prepared.

(Example 58)
As each surface treatment in the above (step a ′), except that the surface treatment similar to each surface treatment (pretreatment, noble metal formation, oxidation treatment, reduction treatment) for the wiring surface described in Example 2 was performed. An evaluation substrate was prepared in the same manner as in Example 57.

(Example 59)
As each surface treatment in the above (step a ′), except for performing the same surface treatment as each surface treatment (pretreatment, noble metal formation, oxidation treatment, coupling treatment) for the wiring surface described in Example 3, An evaluation substrate was produced in the same manner as in Example 57.

(Example 60)
As each surface treatment in the above (step a ′), except for performing the same surface treatment as each surface treatment (pretreatment, noble metal formation, oxidation treatment, corrosion inhibition treatment) for the wiring surface described in Example 4, An evaluation substrate was produced in the same manner as in Example 57.

(Example 61)
As each surface treatment in the above (step a ′), except for performing the same surface treatment as each surface treatment (pretreatment, noble metal formation, oxidation treatment, corrosion inhibition treatment) for the wiring surface described in Example 5, An evaluation substrate was produced in the same manner as in Example 57.

(Example 62)
As each surface treatment in the above (Step a ′), the same surface treatment as the surface treatment (pretreatment, noble metal formation, oxidation treatment, corrosion inhibition treatment, coupling treatment) for the wiring surface described in Example 6 is performed. A substrate for evaluation was produced in the same manner as in Example 57 except that.

(Example 63)
Surfaces similar to the respective surface treatments (pretreatment, noble metal formation, oxidation treatment, reduction treatment, coupling treatment, corrosion inhibition treatment) for the wiring surface described in Example 7 as the respective surface treatments in (Step a ′) above A substrate for evaluation was produced in the same manner as in Example 57 except that the treatment was performed.

(Example 64)
As each surface treatment in the above (step a ′), the same surface treatment as the surface treatment (pretreatment, noble metal formation, oxidation treatment, reduction treatment and coupling treatment) for the wiring surface described in Example 8 was performed. A substrate for evaluation was produced in the same manner as in Example 57 except for the above.

(Example 65)
As each surface treatment in the above (step a ′), the same surface treatment as each surface treatment (pretreatment, noble metal formation, oxidation treatment, reduction treatment and corrosion inhibition treatment) for the wiring surface described in Example 9 was performed. A substrate for evaluation was produced in the same manner as in Example 57 except for the above.

Example 66
As each surface treatment in the above (step a ′), the same surface treatment as each surface treatment (pretreatment, noble metal formation, oxidation treatment, reduction treatment and corrosion inhibition treatment) for the wiring surface described in Example 10 was performed. A substrate for evaluation was produced in the same manner as in Example 57 except for the above.

(Example 67)
Surfaces similar to the respective surface treatments (pretreatment, noble metal formation, oxidation treatment, reduction treatment, corrosion inhibition treatment, coupling treatment) for the wiring surface described in Example 11 as the respective surface treatments in (Step a ′) above. A substrate for evaluation was produced in the same manner as in Example 57 except that the treatment was performed.

(Example 68)
As each surface treatment in the above (step a ′), the same surface treatment as the surface treatment (pretreatment, noble metal formation, oxidation treatment, reduction treatment, coupling treatment, corrosion inhibition treatment) for the wiring surface described in Example 12 A substrate for evaluation was produced in the same manner as in Example 57 except that the treatment was performed.

(Example 69)
As each surface treatment in the above (step a ′), except that the same surface treatment as each surface treatment (pretreatment, noble metal (gold) formation, oxidation treatment, reduction treatment) for the wiring surface described in Example 13 was performed. Produced an evaluation substrate in the same manner as in Example 57.

(Example 70)
As each surface treatment in the above (step a ′), the same surface treatment as the surface treatment (pretreatment, noble metal (silver) formation, oxidation treatment, reduction treatment) for the wiring surface described in Example 14 was performed. Produced an evaluation substrate in the same manner as in Example 57.

(Comparative Example 17)
Evaluation was conducted in the same manner as in Example 57, except that each surface treatment (pretreatment and oxidation treatment) for the wiring surface described in Comparative Example 1 was performed as each surface treatment in (Step a ′) above. A substrate was prepared.

(Comparative Example 18)
Example 57 and Example 57 except that each surface treatment in the above (Step a ′) was subjected to the same surface treatment as the surface treatment (pretreatment, oxidation treatment and reduction treatment) for the wiring surface described in Comparative Example 2. Similarly, an evaluation substrate was produced.

(Comparative Example 19)
Evaluation was performed in the same manner as in Example 57, except that each surface treatment in the above (Step a ′) was subjected to the same surface treatment as the surface treatment (pretreatment and etching treatment) on the wiring surface described in Comparative Example 3. A substrate was prepared.

(Comparative Example 20)
As each surface treatment in the above (Step a ′), the same surface treatment as that in Example 57 was performed except that the surface treatment similar to each surface treatment (without pretreatment and unevenness formation treatment) described in Comparative Example 4 was performed. An evaluation substrate was prepared.

(Example 71)
In order to evaluate the appearance when the gold plating treatment was performed by the copper surface treatment of the present invention, the following evaluation substrate was prepared.

  (Step a) to (Step f) shown in Example 2 are performed, and then (Step g) is repeated again from (Step d) to (Step f) to include the buildup layer 104 and the external connection terminal 107. A further outer layer wiring was formed.

  Next, each surface treatment (pretreatment, noble metal formation, oxidation treatment) described in (Step d-1) and (Step d-2) of Example 1 was performed on the wiring formed as described above. Thereafter, a solder resist 109 is formed, and further, a gold plating process is performed on the external connection terminal 107 portion, and FIG. 1 (sectional view for one package), FIG. A semiconductor chip mounting substrate (evaluation substrate) for a fan-in type BGA as shown in FIG.

  In addition, the said gold plating process was performed according to the procedure of following (1)-(4).

(1) The substrate for evaluation after formation of the solder resist 109 was immersed in an acidic degreasing solution Z-200 (trade name, manufactured by World Metal Co., Ltd.) adjusted to 200 ml / L with water for 2 minutes at a liquid temperature of 50 ° C. It was washed with hot water by immersing it in water at a temperature of 50 ° C. for 2 minutes, and further washed with water for 1 minute.

(2) Next, after being immersed in a 3.6N sulfuric acid aqueous solution for 1 minute, washed with water for 1 minute, then immersed in substituted palladium plating solution SA-100 (Hitachi Chemical Co., Ltd., product name) at 30 ° C. for 3 minutes, Palladium was selectively applied to the external connection terminal 107 and washed with water for 1 minute.

(3) Next, it is immersed in electroless nickel plating solution NIPS-100 (Hitachi Chemical Industry Co., Ltd., product name) at 85 ° C. for 15 minutes, and 5 μm of nickel is selectively applied to the external connection terminal 107 portion for 1 minute. Washed with water.

(4) Next, it was immersed in a displacement gold plating solution HGS-500 (Hitachi Chemical Industry Co., Ltd., product name) at 85 ° C. for 10 minutes, and gold was selectively applied to the external connection terminal 107 part by 0.05 μm. After rinsing with water for 5 minutes, it is immersed in electroless gold plating solution HGS-2000 (Hitachi Chemical Industry Co., Ltd., product name) at 60 ° C. for 40 minutes, and 0.5 μm of gold is selectively applied to the external connection terminal portion for 5 minutes. It was washed with water and dried at 85 ° C. for 30 minutes.

(Example 72)
Example except that each surface treatment in the above (Step g) was subjected to the same surface treatment as each surface treatment (pretreatment, noble metal formation, oxidation treatment, reduction treatment) for the wiring surface described in Example 2. An evaluation substrate was produced in the same manner as in 71.

(Example 73)
As each surface treatment in the above (Step g), except that the surface treatment similar to each surface treatment (pretreatment, noble metal formation, oxidation treatment, coupling treatment) for the wiring surface described in Example 3 was performed. An evaluation substrate was prepared in the same manner as in Example 71.

(Example 74)
As each surface treatment in the above (Step g), except that the same surface treatment as each surface treatment (pretreatment, noble metal formation, oxidation treatment, corrosion inhibition treatment) for the wiring surface described in Example 4 was performed. An evaluation substrate was prepared in the same manner as in Example 71.

(Example 75)
As each surface treatment in the above (Step g), except that the same surface treatment as each surface treatment (pretreatment, noble metal formation, oxidation treatment, corrosion inhibition treatment) for the wiring surface described in Example 5 was performed. An evaluation substrate was prepared in the same manner as in Example 71.

(Example 76)
As each surface treatment in the above (step g), the same surface treatment as each surface treatment (pretreatment, precious metal formation, oxidation treatment, corrosion inhibition treatment, coupling treatment) for the wiring surface described in Example 6 was performed. A substrate for evaluation was produced in the same manner as in Example 71 except for the above.

(Example 77)
As each surface treatment in the above (Step g), the same surface treatment as each surface treatment (pretreatment, precious metal formation, oxidation treatment, coupling treatment, corrosion inhibition treatment) for the wiring surface described in Example 7 was performed. A substrate for evaluation was produced in the same manner as in Example 71 except for the above.

(Example 78)
As each surface treatment in the above (step g), except that the same surface treatment as each surface treatment (pretreatment, noble metal formation, oxidation treatment, reduction treatment, coupling treatment) for the wiring surface described in Example 8 was performed. Produced an evaluation substrate in the same manner as in Example 71.

(Example 79)
As each surface treatment in the above (step g), the same surface treatment as the surface treatment (pretreatment, noble metal formation, oxidation treatment, reduction treatment, corrosion inhibition treatment) for the wiring surface described in Example 9 was performed. Produced an evaluation substrate in the same manner as in Example 71.

(Example 80)
As each surface treatment in the above (step g), except that the same surface treatment as each surface treatment (pretreatment, noble metal formation, oxidation treatment, reduction treatment, corrosion inhibition treatment) for the wiring surface described in Example 10 was performed. Produced an evaluation substrate in the same manner as in Example 71.

(Example 81)
Surface treatment similar to each surface treatment (pretreatment, noble metal formation, oxidation treatment, reduction treatment, corrosion inhibition treatment, coupling treatment) for the wiring surface described in Example 11 as each surface treatment in (Step g) above A substrate for evaluation was produced in the same manner as in Example 71 except that.

(Example 82)
Surface treatment similar to each surface treatment (pretreatment, noble metal formation, oxidation treatment, reduction treatment, coupling treatment, corrosion inhibition treatment) for the wiring surface described in Example 12 as each surface treatment in (Step g) above A substrate for evaluation was produced in the same manner as in Example 71 except that.

(Example 83)
As each surface treatment in the above (Step g), except that the same surface treatment as each surface treatment (pretreatment, noble metal (gold) formation, oxidation treatment, reduction treatment) for the wiring surface described in Example 13 was performed. An evaluation substrate was prepared in the same manner as in Example 71.

(Example 84)
As each surface treatment in the above (step g), except that the same surface treatment as each surface treatment (pretreatment, noble metal (silver) formation, oxidation treatment, reduction treatment) for the wiring surface described in Example 14 was performed. An evaluation substrate was prepared in the same manner as in Example 71.

(Comparative Example 21)
For each evaluation in the same manner as in Example 71, except that each surface treatment in the above (Step g) was subjected to the same surface treatment as the surface treatment (pretreatment, oxidation treatment) for the wiring surface described in Comparative Example 1. A substrate was produced.

(Comparative Example 22)
Same as Example 71, except that each surface treatment in the above (Step g) was subjected to the same surface treatment as the surface treatment (pretreatment, oxidation treatment, reduction treatment) for the wiring surface described in Comparative Example 2. An evaluation substrate was prepared.

(Comparative Example 23)
For each evaluation in the same manner as in Example 71, except that each surface treatment in the above (Step g) was subjected to the same surface treatment as the surface treatment (pretreatment, etching treatment) for the wiring surface described in Comparative Example 3. A substrate was produced.

(Comparative Example 24)
As each surface treatment in the above (Step g), the same surface treatment as that of each surface treatment (pretreatment and no concavo-convex formation treatment) described in Comparative Example 4 was performed, as in Example 71. An evaluation substrate was prepared.

  The various test samples prepared as described above were subjected to each evaluation test as follows.

(Semiconductor package reliability test)
After performing moisture absorption treatment on each of the 22 semiconductor package samples described in Examples 1-14 and Comparative Examples 1-4, 0.5 m / min was applied to a reflow furnace having an ultimate temperature of 240 ° C. and a length of 2 m. Reflow was performed by flowing each sample under conditions. Then, the presence or absence of crack generation was examined for each sample, and the case where it occurred was determined as NG. The results are shown in Table 1.

  Each of the 22 semiconductor package samples was mounted on a 0.8 mm thick mother board and subjected to a temperature cycle test under the conditions of -55 ° C, 30 minutes to 125 ° C, 30 minutes. The 500th cycle, the 1000th cycle, In the 1500th cycle, the conduction resistance value of the wiring was measured using a multimeter 3457A manufactured by Hewlett-Packard Company. NG was determined when the measured resistance value changed by 10% or more from the initial resistance value. The results are shown in Table 1. However, in Comparative Example 3, the wiring accuracy could not be maintained and a test substrate could not be manufactured.

(Adhesion test)
MCL-LX-67 (manufactured by Hitachi Chemical Co., Ltd.) which is a double-sided copper-clad laminate impregnated with a glass cloth-cyanate ester resin composition having a thickness of 0.8 mm that can be used as a low dielectric loss tangent high heat resistant multilayer material , Product name) was roughened using a chemical etching roughening solution HIST-7300 (manufactured by Hitachi Chemical Co., Ltd.), and the copper surface roughness Rz was 3.5 μm. Thereafter, GXA-67N (trade name, manufactured by Hitachi Chemical Co., Ltd.), which is a prepreg in which a glass cloth is impregnated with a cyanate ester resin composition, is laminated on a copper surface of Rz = 3.5 μm, and further on the outermost layer. One sheet of the electrolytic copper foil prepared in Examples 15 to 28 and Comparative Examples 5 to 8 was laminated, and heated at a pressure of 3.0 MPa from room temperature (25 ° C.) to 230 ° C. at a temperature rising rate of 6 ° C./min. By holding at 230 ° C. for 1 hour, lamination adhesion was performed to prepare an adhesion test substrate. In addition, the said electrolytic copper foil is adhere | attached with the insulating layer (prepreg) in the surface side which gave various surface treatments.

  Next, the initial (0 hour) adhesion and the adhesion after leaving at 150 ° C. for 120 hours and 240 hours were measured for each of the adhesion test substrates obtained above. In addition, the measurement of the peel strength (N / m) used as the said parameter | index of adhesiveness uses rheometer NRM-3002D-H (Fudo Kogyo Co., Ltd. make, brand name), and makes an electrolytic copper foil perpendicular | vertical with respect to a board | substrate. The peeling was performed at a speed of 50 mm / min. The case where the peel strength value was 300 N / m or more was indicated as ◯, and the case where the peel strength value was less than 300 N / m was indicated as ×. The results are shown in Table 2.

(Copper surface cleanliness evaluation test)
About the surface side which gave surface treatment of each electrolytic copper foil produced in Examples 15-28 and Comparative Examples 5-8, it extracted at 85 degreeC for 1 hour with 20 ml of pure waters, and the cation and anion of an extract liquid The qualitative analysis of was performed by ion chromatography. The ion chromatograph was performed on condition 2 shown below using DX-500 by Dionex.

Condition 2
Cation measurement conditions Eluent: 8 mmol / L-Methanesulfonic acid Injection amount: 100 μL
Separation column: 2 mmφ × 250 mm longPac CS14
Detector: Conductivity meter Anion measurement conditions Eluent: Mixture of 2.7 mmol / L-sodium carbonate and 0.3 mmol / L-sodium bicarbonate Injection amount: 500 μL
Separation column: 4 mmφ × 200 mm longPac AS12A
Detector: Electric conductivity meter

  Furthermore, nitric acid was added to the extract, and the quantitative analysis of metal ions was performed by the ICP issuance analysis method. The ICP issuance analysis method was performed using SPS3000 manufactured by SII Nanotechnology. When the detected amount of each cation / anion and each metal ion indicating the degree of detergency shows a value of 1 μg / sheet or more, +++, when the detected amount is 0.1 μg / sheet or more and less than 1 μg / sheet ++, 0.04 μg / sheet or more and less than 0.1 μg / sheet showing a value of +, and less than 0.04 μg / sheet showing a value of −. The results are shown in Table 3.

(Copper surface smoothness evaluation test)
The surface roughness (Rz) of the surface side subjected to the surface treatment of the electrolytic copper foils prepared in Examples 15 to 28 and Comparative Examples 5 to 8 is shown below using a simple atomic force microscope (AFM) Nanopics 2100. The measurement was performed under the condition 3.

Condition 3
Measurement length: 1 μm
SCAN SPEED: 1.35 μm / sec
FORCE REFERENCE: 160

  When Rz is 1 nm or more and 100 nm or less, ◎, when Rz exceeds 100 nm and 1000 nm or less, ◯, and when Rz is less than 1 nm or more than 1000 nm, Δ. The results are shown in Table 2.

(Copper surface shape evaluation test)
The surface shape of the surface side subjected to the surface treatment of the electrolytic copper foils produced in Examples 15 to 28 and Comparative Examples 5 to 8 was examined. In the observation with a scanning electron microscope (S-4700: manufactured by Hitachi, Ltd.) at a magnification of 100,000 times, a copper surface shape having a fine and uniform unevenness was evaluated as ◯, and a case where the copper surface shape was not as X. The results are shown in Table 2. However, in Comparative Example 4, since (Step d-2) was not performed, the unevenness on the copper surface could not be observed.

(Copper surface gloss evaluation test)
The surface side which gave the surface treatment of the electrolytic copper foil produced in Examples 15-28 and Comparative Examples 5-8 was observed visually, and the presence or absence of surface glossiness was investigated. A matte one was marked with ◯, and a glossy one with x. The results are shown in Table 2.

(Insulation between wiring by copper surface treatment to wiring)
About each evaluation board | substrate described in Examples 29-42 and Comparative Examples 9-12, the short circuit between wiring of L / S = 5 / 5micrometer and L / S = 10 / 10micrometer, and wiring are performed as follows. Four evaluation boards without disconnection were selected, and the insulation resistance value between the wirings was measured. However, the evaluation board of Comparative Example 11 was not measured because the wiring accuracy could not be maintained.

  First, using an R-8340A digital ultra-high resistance microammeter manufactured by Advantest Corporation, a voltage of DC 5 V was applied between the L / S wires at room temperature for 30 seconds, and the insulation resistance value between the L / S wires was measured. did. A digital multimeter 3457A manufactured by Hewlett-Packard (HP) Co., Ltd. was used for measuring the insulation resistance of 1 GΩ or less.

  Next, in a constant humidity and constant temperature layer maintained at 85 ° C. and a relative humidity of 85%, a DC5V voltage was continuously applied between the L / S wirings, and after 24 h, 48 h, 96 h, 200 h, 500 h, and 1,000 h. In the same manner as described above, the insulation resistance value between the L / S wirings was measured. In addition, the constant-humidity thermostat used Hitachi, Ltd. EC-10HHPS type | mold constant temperature and constant temperature, and it measured until 1000 hours after input.

For the four evaluation substrates measured as described above, the minimum value of the insulation resistance value was x when it was less than 1 GΩ, and it was marked when it was 1.0 × 10 ⁹ Ω or more. The results are shown in Tables 4 and 5.

(Resist pattern formation evaluation test)
In (step a ′) described in Examples 43 to 56 and Comparative Examples 13 to 16, the formation success rate of the resist pattern 119 was evaluated. The evaluation method is to measure the width of the resist where the resist remains at the place where the wiring is formed, or the formed resist does not peel off, and the resist of each L / S is formed. A product having an error with respect to the design value within ± 10% was regarded as a non-defective product, and the ratio was examined. The results are shown in Table 6. However, about the evaluation board | substrate of the comparative example 15, since the copper thin film 118 lose | disappears by performing copper surface treatment, it did not measure.

(Wiring formation evaluation test)
In (Step a ′) described in Examples 43 to 56 and Comparative Examples 13 to 16, the success rate of forming the wiring 106 was evaluated. As an evaluation method, a product having no short circuit between wires or disconnection of wires and having an error within ± 10% of the design value of copper plating thickness within ± 10% was regarded as a non-defective product, and the ratio was examined. The results are shown in Table 6. However, about the evaluation board | substrate of the comparative example 15, since the copper thin film 118 lose | disappears by performing copper surface treatment, it did not measure.

(PCT resistance evaluation test)
The evaluation substrates described in Examples 29 to 42 and Comparative Examples 9 to 12 were subjected to a PCT resistance test (121 ° C., 200 h, 0.2 MPa). The evaluation method is that between the wiring 106 and the insulating layer (build-up layer) 104 after the PCT resistance test, between the insulating layer 104 and the insulating layer (build-up layer) 104, between the wiring 106 and the solder resist 109, and between the insulating layer 104 and the solder resist. Those having no swelling and peeling between 109 were regarded as non-defective products, and the ratios were examined. The results are shown in Table 7. However, in Comparative Example 11, a test substrate could not be created because the formed wiring disappeared.

(Pink ring occurrence evaluation test)
About each board | substrate for evaluation described in Examples 57-70 and Comparative Examples 17-20, it immersed in 18% hydrochloric acid for 3 hours, and investigated the ratio which a pink ring (pink ring) generate | occur | produces around a hole. The results are shown in Table 8.

(Evaluation of gold plating appearance and solder resist state)
About the board | substrate for evaluation described in Examples 71-84 and Comparative Examples 21-24, the gold plating external appearance is observed visually or with a microscope, when there is no unevenness of gold plating, when there is unevenness of gold plating △, and the case where gold plating has not yet been deposited, was marked with ×. In addition, as the state of the solder resist, “O” indicates that there is no peeling and no gold plating deposits under the solder resist, and “X” indicates that the solder resist is not. The results are shown in Table 9.

  As shown in Table 1, among the semiconductor packages produced in Examples 1 to 14, Examples 2 and 8 to 14 in which the reduction treatment was performed after the oxidation treatment with the alkaline solution showed extremely good reliability.

  In addition, as shown in Table 2, the electrolytic copper foils produced in Examples 15 to 28 have dense and uniform tens of nano level unevenness on the surface, thereby suppressing the gloss of the copper surface, The adhesion strength (peel strength) between the surface and the insulating layer after standing at 150 ° C. for 240 hours was 300 N / m or more, which was good. In addition, as shown in Table 3, since various ions were not detected from the surface of the electrolytic copper foil produced in Examples 15 to 28, it can be said that the surface has good cleaning properties.

  Further, as shown in Tables 4 and 5, the inter-wiring insulation reliability in the evaluation boards produced in Examples 29 to 42 is extremely high at both L / S = 5/5 μm and L / S = 10/10 μm. It was good. Further, as shown in Table 6, the resist pattern formation success rate in the evaluation substrates produced in Examples 43 to 56 was very good even at L / S = 5/5 μm and L / S = 10/10 μm. Further, as shown in Table 6, the success rate of wiring formation in the evaluation substrates produced in Examples 43 to 56 was very good even at L / S = 5/5 μm and L / S = 10/10 μm. Further, as shown in Table 7, the PCT resistance in the evaluation substrates produced in Examples 29 to 42 is between the buildup layer and the wiring, between the buildup layer and the insulating layer, between the solder resist and the wiring, and between the solder resist and the insulating layer. In any case, it was extremely good.

  Also, as shown in Table 8, among the evaluation substrates produced in Examples 57 to 70, Examples 58 and 64-70 subjected to the reduction treatment were very good with no pink ring.

  Moreover, as shown in Table 9, the appearance of the gold plating in the evaluation substrates produced in Examples 71 to 84 is very good, and Examples 72 and 78 to 84 subjected to the reduction treatment were subjected to the gold plating treatment. There was no peeling of the solder resist and no gold plating deposition under the solder resist, which was very good.

  On the other hand, in the prior art, as shown in Comparative Examples 1 to 24, smoothness, adhesion, copper surface shape, copper surface gloss, copper surface cleanability, inter-wiring insulation reliability, resist pattern formation, wiring formation In addition, all of the properties due to PCT resistance and gold plating treatment could not be satisfied.

  Therefore, according to the copper surface treatment method of the present invention, fine and uniform fine irregularities of several tens of nanometers can be formed on the copper surface, so that the adhesive strength between the copper surface and the insulating layer is improved. Is possible. As a result, without the occurrence of pink ring, wiring board and semiconductor chip mounting substrate with excellent insulation reliability between wires, fine wiring formation, reflow resistance, temperature cycle property, gold plating treatment to external connection terminals This makes it possible to manufacture a semiconductor package that is superior to the above.

  It will be appreciated by those skilled in the art that the foregoing is a preferred embodiment of the invention and that many changes and modifications can be made without departing from the spirit and scope of the invention.

1 is a cross-sectional view of a semiconductor chip mounting substrate to which an embodiment of the present invention is applied. (A)-(g) is process drawing which shows one Embodiment of the manufacturing method of the semiconductor chip mounting substrate of this invention. 1 is a cross-sectional view of a flip chip type semiconductor package to which an embodiment of the present invention is applied. 1 is a cross-sectional view of a wire bond type semiconductor package to which an embodiment of the present invention is applied. The top view of the fan-in type semiconductor chip mounting board | substrate of this invention. The top view of the fan-out type semiconductor chip mounting substrate of this invention. The top view showing the frame shape of the semiconductor chip mounting substrate of this invention. 1 is a cross-sectional view of a semiconductor chip mounting substrate to which an embodiment of the present invention is applied. (A '), (d') is process drawing which shows one Embodiment of the evaluation board | substrate manufacturing method for a test of this invention. (A '), (d') is process drawing which shows one Embodiment of the evaluation board | substrate manufacturing method for a test of this invention. The top view of the evaluation board for electric corrosion tests to which one embodiment of the present invention is applied. The top view of the evaluation board for electric corrosion tests to which one embodiment of the present invention is applied.

Explanation of symbols

11. Positioning mark (guide hole for alignment)
13. Semiconductor package region 14. Die bond film bonding area (flip chip type)
15. Semiconductor chip mounting area (flip chip type)
16. Semiconductor chip connection terminal 17. Die bond film bonding area (wire bond type)
18. Semiconductor chip mounting area (wire bond type)
19. External connection terminal 20. Expanded wiring 21. Dummy pattern 22. Semiconductor chip mounting substrate 23. Block 24. Reinforcing pattern 25. Cutting alignment mark 100 Core substrate 101 First interlayer connection terminal 102 IVH (via hole) for first interlayer connection
103 Second interlayer connection terminal 104 Interlayer insulating layer (build-up layer)
105 Third layer connection IVH (via hole)
106 wiring 106a first wiring 106b second wiring 106c third wiring 107 external connection terminal 108 second interlayer connection IVH (via hole)
109 Insulation coating (solder resist)
111 Semiconductor chip 112 Connection bump 113 Underfill material 114 Solder ball 115 Gold wire 116 Sealing resin for semiconductor 117 Die bond film

Claims (12)

  A copper surface treatment method comprising: a step of discretely forming a metal nobler than copper on a copper surface; and a step of oxidizing the copper surface with an alkaline solution containing an oxidizing agent.   The copper surface treatment method according to claim 1, further comprising a step of performing one or more treatments selected from the group consisting of a reduction treatment, a coupling treatment, and a corrosion inhibition treatment after the step of oxidizing the copper surface. .   The said oxidizing agent is 1 or more types selected from the group which consists of a chlorate, a chlorite, a hypochlorite, a perchlorate, and peroxodisulfate, The claim 1 or 2 Copper surface treatment method.   The metal nobler than copper is a metal selected from the group consisting of gold, silver, platinum, palladium, rhodium, rhenium, ruthenium, osmium, iridium, or an alloy containing the metal. The surface treatment method of copper in any one. The copper surface treatment method according to any one of claims 1 to 4, wherein an amount of a metal nobler than copper is 0.001 µmol / dm ² or more and 40 µmol / dm ² or less.   The copper surface treatment method according to claim 1, wherein the roughness of the copper surface after the treatment is 1 nm or more and 1000 nm or less in terms of Rz.   Copper obtained by discretely forming a metal nobler than copper on the copper surface, and then oxidizing the copper surface with an alkaline solution containing an oxidizing agent.   The copper according to claim 7, further comprising one or more treatments selected from the group consisting of a reduction treatment, a coupling treatment, and a corrosion inhibition treatment after the oxidation treatment.   The said oxidizing agent is 1 or more types selected from the group which consists of a chlorate, a chlorite, a hypochlorite, a perchlorate, a peroxodisulfate, The Claim 7 or 8 copper.   The metal nobler than copper is a metal selected from the group consisting of gold, silver, platinum, palladium, rhodium, rhenium, ruthenium, osmium, iridium, or an alloy containing the metal. Copper in any one of 7-9. 11. The copper according to claim 7, wherein the amount of metal nobler than copper formed on the surface is 0.001 μmol / dm ² or more and 40 μmol / dm ² or less.   Copper of Claims 7-11 whose roughness of the said copper surface after a process is 1 nm or more and 1000 nm or less by Rz.

Images