JP2000286557A - Multilayer printed wiring board and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a multilayer printed wiring board whose connection reliability of a via hole can be improved and to provide a manufacturing method of the multilayer printed wiring board. SOLUTION: Voids 35a are installed on the roughened face 35 of a conductor circuit 29. In the voids 35a, affinity with plating liquid is superior and plating infiltrates into the voids 35a and is beset in an anchor part in a plating process. Thus, the roughened face 35 of the conductor circuit 29 is adhered still more closely with the via holes 130. Namely, plating is inserted into the conductor of the via holes 130 in the voids 35a of the conductor circuit 29 at forming of the via hole 130 on the lower conductor circuit 29, so that adhesion can be enhanced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multilayer printed wiring board in which interlayer resin insulating layers and conductive circuits are alternately laminated, and a method of manufacturing the multilayer printed wiring board.

[0002]

2. Description of the Related Art In recent years, so-called build-up multilayer wiring boards have been receiving attention due to a demand for higher density of the multilayer wiring boards. This build-up multilayer wiring board is manufactured, for example, by a method disclosed in Japanese Patent Publication No. 4-55555. That is, an insulating material made of a photosensitive adhesive for electroless plating is applied on a core substrate having a conductor circuit, dried, and exposed and developed to form an interlayer insulating material layer having a via hole opening. I do. Next, after roughening the surface of the interlayer insulating material layer by treatment with an oxidizing agent or the like, a plating resist is provided on the roughened surface, and electroless plating is performed on a portion where no resist is formed, thereby forming two layers including via holes. Is formed. By repeating such a process a plurality of times, a multilayered build-up wiring board can be obtained.

[0003]

In a multilayer printed wiring board, since the adhesion between a conductor circuit made of a metal such as copper and an interlayer resin insulation layer made of a resin is low, the conductor circuit is roughened or By providing the roughened layer, the adhesion between the interlayer resin insulating layer and the conductor circuit is improved. However, in a heat cycle that repeats high and low temperatures,
Peeling of the via holes occurred.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to propose a multilayer printed wiring board capable of improving connection reliability of a via hole and a method of manufacturing the multilayer printed wiring board. It is in.

[0005]

According to the present invention, there is provided a multilayer printed wiring board in which interlayer resin insulating layers and conductive circuits are alternately laminated, wherein voids are formed on the surface of the conductive circuits. Is a technical feature.

Further, the present invention provides a method for manufacturing a multilayer printed wiring board comprising alternately laminating interlayer resin insulating layers and conductive circuits, wherein a conductive circuit is formed, and then an interlayer resin insulating layer is formed. After forming an opening for forming a via hole in the resin insulating layer, the surface of the interlayer resin insulating layer is roughened, and a void is formed on the surface of the conductive circuit.

In the multilayer printed wiring board of the present invention,
Since the void is formed on the surface of the conductor circuit, the connection reliability of the via hole is improved by connecting the via hole to the void.

According to a second aspect of the present invention, the void has an average diameter of 1 μm or less.
About 20 μm is desirable. If it is too large, the connection will be broken, and if it is too small, the connection reliability cannot be sufficiently ensured.

According to the method for manufacturing a multilayer printed wiring board of the second aspect, when the interlayer resin insulating layer is roughened, voids can be formed on the surface of the conductor circuit by the roughening solution, so that the process can be simplified. . It is desirable to provide a dissimilar metal layer made of a metal different from the metal constituting the conductor circuit on the surface of the conductor circuit. This is because a battery reaction occurs between the conductor circuit and the dissimilar metal layer, and the conductor circuit dissolves to easily form a void. If the conductor circuit is copper,
Such a dissimilar metal layer includes Cu-Ni-P, Cu
A roughened plating layer made of -Co-P, Ti, Al, Fe,
Zn, Cr, Ni, Co, Sn, precious metals (Ag, Au,
Pt, Pd) are preferable.

The thickness of such a dissimilar metal layer is 0.01
Adjusted at 20 μm. As the roughening solution used,
Acids, oxidants and alkalis. Organic acids such as formic acid and acetic acid, and inorganic acids such as hydrochloric acid, sulfuric acid, hydrofluoric acid and phosphoric acid can be used as the acid. The oxidizing agent is an aqueous solution of chromic acid, alkaline permanganate, or the like. As the alkali, an aqueous solution of sodium hydroxide, potassium hydroxide or the like is suitable.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS In an embodiment of the present invention, voids are formed by a local battery reaction. A dissimilar metal layer is provided on the surface of the conductor circuit. Specifically, Pd is optimal. P
As a method for forming d, in addition to sputtering, Pd-S
A method in which a catalyst composed of n colloid is provided, and Pd ions are reduced with an activator such as an acid to obtain metal palladium is optimal from the viewpoint of cost.

When Pd and Cu form a battery, an aqueous solution of chromic acid becomes an electrolytic solution when the interlayer resin insulating layer is roughened with chromic acid or the like, and the Cu portion is dissolved to form voids. It is desirable that the surface of the conductor circuit be roughened in advance.

More specifically, an etching solution containing a cupric complex and an organic acid is allowed to act as follows under conditions of coexistence of oxygen, such as spraying and bubbling, to dissolve the copper conductor of the conductor circuit and form a void. To form

[0014]

Embedded image Cu + Cu (II) A _n → 2Cu (I) A _{n / 2} ↓ Aeration 2Cu (I) A _{n / 2} + N / 4O ₂ + NAH → 2Cu (II) A _n + N / 2H ₂ O [In the formula, A represents a complexing agent (acting as a chelating agent), and n represents a coordination number. ]

The cupric complex used in the present invention is preferably an azole cupric complex. This cupric complex of azoles acts as an oxidizing agent for oxidizing metallic copper and the like. As the azoles, diazole, triazole and tetrazole are preferable. Among them, imidazole, 2-methylimidazole, 2-ethylimidazole, 2-ethyl-4-methylimidazole, 2-phenylimidazole, 2-undecylimidazole and the like are preferable. The addition amount of the cupric complex of azoles is preferably 1 to 15% by weight. This is because it is excellent in solubility and stability, and can also dissolve noble metals such as Pd constituting the catalyst core.

In order to dissolve copper oxide, an organic acid is added to a cupric complex of an azole. Specific examples include formic acid, acetic acid, propionic acid, butyric acid, valeric acid, caproic acid, acrylic acid, crotonic acid, oxalic acid, malonic acid,
At least one selected from the group consisting of succinic acid, glutaric acid, maleic acid, benzoic acid, glycolic acid, lactic acid, malic acid, and sulfamic acid is preferred. The content of organic acids is
0.1 to 30% by weight is preferred. This is for maintaining the solubility of the oxidized copper and ensuring the solubility stability.

The generated cuprous complex dissolves under the action of an acid and combines with oxygen to form a cupric complex, which again contributes to the oxidation of copper.

Further, in order to assist the dissolution of copper and the oxidizing action of azoles, halogen ions, for example, fluorine ions, chlorine ions, bromine ions and the like may be added to the etching solution. In the present invention, halogen ions can be supplied by adding hydrochloric acid, sodium chloride, or the like. The amount of halogen ions is preferably 0.01 to 20% by weight. This is because adhesion between the formed roughened surface and the interlayer resin insulating layer is excellent.

An etching solution is prepared by dissolving a cuprous complex of an azole and an organic acid (halogen ion if necessary) in water. The roughened surface according to the present invention can be formed by using a commercially available etching solution, for example, “Mech Etch Bond” manufactured by Mec Corporation.

In the present invention, the etching amount is preferably 1 to 10 μm. This is because an etching treatment exceeding this range causes a connection failure between the formed roughened surface and the via-hole conductor.

The interlayer resin insulating layer used in the present invention can be formed using an electroless plating adhesive. Adhesive for electroless plating is based on thermosetting resin, especially heat-treated resin particles cured, heat-resistant resin particles dissolved in acid or oxidizing agent, inorganic particles or fibrous filler, etc., if necessary. Can be included.

As the thermosetting resin base, epoxy resin, phenol resin, polyimide resin and the like can be used. When a part of the thermosetting group is sensitized, a part of the thermosetting group is reacted with methacrylic acid, acrylic acid, or the like to be acrylated. Among them, acrylates of epoxy resins are most suitable. As the epoxy resin, a novolak type epoxy resin, an alicyclic epoxy resin, or the like can be used. As the thermoplastic resin to be added, polyether sulfone, polysulfone, polyphenylene sulfone, polyphenylene sulfide, polyphenyl ether, polyether imide, or the like can be used.

As the heat-resistant resin particles, (1) the average particle size is
Heat-resistant resin powder of 10 μm or less, (2) agglomerated particles obtained by aggregating heat-resistant resin powder having an average particle size of 2 μm or less, (3) heat-resistant powder resin powder having an average particle size of 2 to 10 μm and an average particle size of 2μ
m and a mixture with a heat-resistant resin powder having a mean particle size of 2 or less.
The average particle size is 2 μm on the surface of the heat-resistant resin powder of ~ 10 μm.
Pseudo particles to which one or both of the following heat-resistant resin powder and inorganic powder are adhered, (5) the average particle diameter is 0.8 to 2.
0 μm heat-resistant resin powder, average particle size 0.1-0.8 μm
It is desirable to use at least one kind of particles selected from heat-resistant resin powders and mixtures thereof. This is because these particles can form a more complex anchor. The roughened surface obtained by these particles has a maximum roughness (Rma).
x) is from 0.1 to 20 μm.

As the heat-resistant resin particles soluble in an acid or an oxidizing agent, amino resin (melamine resin, urea resin, guanamine resin, etc.) and epoxy resin (bisphenol epoxy resin cured with an amine-based curing agent) are most suitable. ), Bismaleimide-triazine resin and the like can be used.

The interlayer resin insulating layer may have a plurality of layers. For example, the lower layer is a reinforcing layer composed of inorganic particles or fibrous filler and a resin base, and the upper layer is an adhesive layer for electroless plating.

The lower layer is formed by dispersing heat-resistant resin particles having an average particle size of 0.1 to 2.0 μm soluble in an acid or an oxidizing agent in a heat-resistant resin hardly soluble in an acid or an oxidizing agent. It may be an adhesive layer for plating.

As the inorganic particles, silica, alumina, talc and the like can be used. As the fibrous filler, at least one of calcium carbonate whisker, aluminum borate whisker, aramid fiber, carbon fiber and the like can be used.

Next, one method of manufacturing the printed wiring board of the present invention will be described. The following method is based on the semi-additive method, but may use the full-additive method.

(1) First, a wiring board having a conductive circuit formed on the surface of the board is manufactured. As the substrate, a resin insulating substrate such as a glass epoxy substrate, a polyimide substrate, a bismaleimide-triazine resin substrate, a ceramic substrate, a metal substrate, or the like can be used.

The conductor circuit is formed on the substrate by a method of etching the copper-clad laminate after electroless plating or electrolytic plating, or a method of electroless plating on a substrate such as a glass epoxy substrate, a polyimide substrate, a ceramic substrate, or a metal substrate. A method of forming an adhesive layer for use, roughening the surface of the adhesive layer to a roughened surface, and electroless plating the roughened surface, or a so-called semi-additive method (electroless plating of the entire roughened surface). After plating, forming a plating resist, applying a thick electrolytic plating to a portion where no plating resist is formed, removing the plating resist, etching, and forming a conductor circuit including an electrolytic plating film and an electroless plating film. Method of forming). The conductor circuit preferably has a copper pattern.

Next, a roughened layer is formed on the conductor circuit. The roughened layer is formed by spraying or dipping the etching solution comprising the aqueous solution of the cupric complex of an azole and an organic acid as described above, and bubbling. Note that the conductor circuit is preferably an electroless plating film or an electrolytic plating film. This is because a roughened surface is not easily formed in a conductor circuit obtained by etching a rolled copper foil.

Further, the roughened layer may be covered with a layer of a metal or a noble metal having an ionization tendency larger than that of copper and equal to or less than titanium. These metal or precious metal layers
It is possible to prevent the conductor circuit from dissolving due to a local electrode reaction that occurs when the roughened layer is covered and the interlayer resin insulating layer is roughened. The thickness of the layer is preferably 0.1 to 2 μm.

As such a metal, there is at least one selected from the group consisting of titanium, aluminum, zinc, iron, indium, thallium, cobalt, nickel, tin, lead and bismuth. Noble metals include gold, silver, platinum and palladium. Of these, tin is particularly preferred. Tin is advantageous because it can form a thin layer by electroless displacement plating and can follow the roughened layer.

For coating tin, tin borofluoride-thiourea or tin chloride-thiourea liquid is used. in this case,
An Sn layer of about 0.1 to 2 μm is formed by the substitution reaction of Cu—Sn. In the case of a noble metal, a method such as sputtering or vapor deposition can be adopted.

Further, a through hole is formed in such a wiring board, and the wiring layer on the front surface and the back surface can be electrically connected through the through hole. Further, the wiring board may be filled with a low-viscosity resin such as a bisphenol F-type epoxy resin between the through-holes and the conductor circuits of the wiring board to ensure the smoothness of the wiring board.

(2) An adhesive for electroless plating is applied on the wiring board thus manufactured and dried to provide an interlayer resin insulating layer. For coating, a roll coater, a curtain coater or the like can be used.

At this point, the interlayer resin insulating layer provided on the conductor circuit of the substrate is a portion having a large area other than on the conductor circuit pattern because the thickness of the interlayer resin insulating layer on the conductor circuit pattern is small. In many cases, the interlayer resin insulating layer becomes thick and irregularities are generated. Therefore, it is desirable that the interlayer resin insulating layer in the uneven state is pressed while being heated using a metal plate or a metal roll to flatten the surface of the interlayer resin insulating layer.

(3) Next, while curing the interlayer resin insulation layer, an opening for forming a via hole is provided in the interlayer resin insulation layer.

The curing treatment of the interlayer resin insulation layer is performed by thermosetting when the resin matrix of the adhesive for electroless plating is a thermosetting resin, and is performed by exposing with a UV ray or the like when the resin matrix is a photosensitive resin. .

The opening for forming the via hole is formed using laser light or oxygen plasma when the resin matrix of the adhesive for electroless plating is a thermosetting resin, and exposed when the resin matrix is a photosensitive resin. Perforate in development processing. In the exposure and development process, a photomask (a glass substrate is preferable) on which a circular pattern for forming a via hole is drawn is placed on the photosensitive interlayer resin insulating layer with the circular pattern side in close contact. , Exposure and development processing.

(4) Next, the surface of the interlayer resin insulating layer (adhesive layer for electroless plating) provided with openings for forming via holes is roughened. In particular, in the present invention, the surface of the adhesive layer is roughened by dissolving and removing the heat-resistant resin particles present on the surface of the adhesive layer for electroless plating with an acid or an oxidizing agent. At this time, the depth of the depression formed in the roughened surface is preferably about 1 to 5 μm.

As the acid, phosphoric acid, hydrochloric acid, sulfuric acid, or an organic acid such as formic acid or acetic acid can be used. In particular, it is desirable to use an organic acid. This is because when the roughening treatment is performed, the metal conductor layer exposed from the via hole is hardly corroded.

As the oxidizing agent, it is desirable to use chromic acid or permanganate (such as potassium permanganate).

(5) Next, a catalyst nucleus is provided on the roughened surface of the interlayer resin insulating layer. It is desirable to use a noble metal ion or a noble metal colloid for providing the catalyst nucleus, and generally, palladium chloride or a palladium colloid is used. It is desirable to perform a heat treatment to fix the catalyst core.
Palladium is preferred as such a catalyst core.

(6) Next, a thin electroless plating film is formed on the entire surface of the interlayer resin insulating layer provided with the roughened catalyst nuclei. This electroless plating film is preferably an electroless copper plating film,
The thickness is set to 1 to 5 μm, and more preferably to 2 to 3 μm. In addition, as the electroless copper plating solution, those having a liquid composition that is used in a usual manner can be used. For example, copper sulfate: 29 g /
l, sodium carbonate: 25 g / l, EDTA: 140 g /
1, sodium hydroxide: 40 g / l, 37% formaldehyde: 150 ml, (pH = 11.5).

(7) Next, a photosensitive resin film (dry film) is laminated on the electroless plating film thus formed, and a photomask on which a plating resist pattern is drawn is formed on the photosensitive resin film. A non-conductive portion having a plating resist pattern is formed by placing a glass substrate (preferably a glass substrate) in close contact, exposing, and developing.

(8) Next, an electrolytic plating film is formed on portions other than the non-conductor portion on the electroless plating film, and a conductor circuit and a conductor portion serving as a via hole are provided. As the electrolytic plating, it is desirable to use electrolytic copper plating, the thickness of which is 10 to 20 μm.
Is good.

(9) Next, after removing the plating resist of the non-conductive portion, a mixed solution of sulfuric acid and hydrogen peroxide, sodium persulfate, ammonium persulfate, ferric chloride,
The electroless plating film is dissolved and removed with an etching solution such as cupric chloride to obtain an independent conductor circuit and a via hole having two layers of the electroless plating film and the electrolytic plating film. The palladium catalyst nuclei on the roughened surface exposed to the non-conductive portion can be dissolved and removed with chromic acid or the like.

(10) Next, a roughened surface having voids is formed on the surfaces of the conductor circuit and the via hole thus obtained. The roughened surface is formed by the above-described etching method. At this time, the catalyst nuclei between the conductor circuits can be removed (reduced). In this case, the above-described step of removing the catalyst nucleus becomes unnecessary. Note that the removal (reduction) of the catalyst nuclei does not only mean the case where the catalyst nuclei are completely removed, but also includes a case where the catalyst nuclei are reduced to a range sufficient to establish the insulation between the conductor circuits.

(11) Next, an interlayer resin insulating layer is formed on the substrate according to the step (2). (12) If necessary, the steps (3) to (9) are repeated to form a multilayer, thereby producing a multilayer printed wiring board.

The above processing is a semi-additive method. However, after roughening the adhesive layer for electroless plating and forming a plating resist on the surface, electroless plating is performed to form a conductor pattern. In the full additive method, the surface may be roughened so as to provide voids on the surface of the conductor circuit.

[0052]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A multilayer printed wiring board according to an embodiment of the present invention and a method for manufacturing the same will be described below with reference to the drawings. First, the configuration of the multilayer printed wiring board 10 according to the first embodiment of the present invention will be described with reference to FIG. In the multilayer printed wiring board 10, through holes 6 are formed in the core substrate 1, and conductor circuits 5 are formed on both surfaces of the core substrate 1. On the core substrate 1, a lower interlayer resin insulation layer (adhesive layer) 16 having via holes 30 and conductor circuits 29 formed thereon is disposed. On the lower interlayer resin insulation layer 16, an upper interlayer resin insulation layer (adhesive layer) 116 in which a via hole 130 and a conductor circuit 129 are formed is arranged.

On the upper surface side of the multilayer printed wiring board, a solder bump 76U for connection to a land of an IC chip (not shown) is provided in the opening 71 of the solder resist 70. Solder bumps 76 for connection to lands on a daughter board (not shown) are formed in the openings 71 on the lower surface side.
D is provided. The solder bumps (76U) are connected to the through holes (6) via via holes (130) formed in the interlayer resin insulation layer (116) and via holes (30) formed in the interlayer resin insulation layer (16). On the other hand, the solder bump 76D is connected to the through hole 6 via a via hole 130 formed in the interlayer resin insulating layer 116 and a via hole 30 formed in the interlayer resin insulating layer 16.

The roughened surface 35 of the conductor circuit 29 has voids 3
5a. The void 35a has excellent affinity with the plating solution, and in the plating step, the plating penetrates into the void 35a and follows the anchor-shaped portion, so that the roughened surface 35 of the conductor circuit 29 and the via hole 130 are further formed. In close contact.
That is, when the via hole 130 is formed on the lower conductor circuit 29 by plating, the conductor of the via hole 130 is cut into the void 35a of the conductor circuit 29, so that the adhesion can be increased. Note that a gap may be left in the void 35a as shown in FIG.

Next, a method for manufacturing the above-described printed wiring board will be described with reference to FIG. Here, first, A.I. Adhesive for electroless plating, B. The raw material composition for preparing a resin filler will be described. Preparation of Adhesive Composition A for Electroless Plating (1) 35 parts by weight of a 25% by weight acrylate of a cresol novolac type epoxy resin (manufactured by Nippon Kayaku: molecular weight 2500)
Photosensitive monomer (Toa Gosei: Aronix M31
5) 3.15 parts by weight, 0.5 parts by weight of an antifoaming agent (S-65 manufactured by San Nopco) and 3.6 parts by weight of N-methylpyrrolidone (NMP) were mixed by stirring.

(2) 12 parts by weight of polyether sulfone (PES), 7.2 parts by weight of an average particle diameter of 1.0 μm of epoxy resin particles (manufactured by Sanyo Chemical Co., trade name: polymer pole), and 0.2 parts by weight of an average particle diameter
After mixing 3.09 parts by weight of 5 μm, further add NMP 30
Parts by weight were added and mixed by stirring with a bead mill.

(3) 2 parts by weight of an imidazole curing agent (manufactured by Shikoku Kasei: 2E4MZ-CN), a photoinitiator (manufactured by Ciba-Geigy:
2 parts by weight of Irgacure I-907), 0.2 parts by weight of a photosensitizer (DETX-S, manufactured by Nippon Kayaku), and 1.5 parts by weight of NMP were stirred and mixed. (4) The mixtures (1) to (3) were mixed to obtain an adhesive composition for electroless plating.

Preparation of Resin Filler B (1) 100 parts by weight of bisphenol F type epoxy monomer (manufactured by Yuka Shell: molecular weight 310, trade name: YL983U) and an average particle diameter of 1.6 μm, and the surface was coated with a silane coupling agent. SiO ₂ spherical particles [manufactured by Admatech: CRS 11
01-CE, where the maximum particle size is equal to or less than the thickness (15 μm) of an inner copper pattern described later. ] 170 parts by weight, 1.5 leveling agent (manufactured by San Nopco: trade name Perenol S4) 1.5
Parts by weight are kneaded with three rolls, and the viscosity of the mixture is adjusted to 23.
The temperature was adjusted to 45,000 to 49,000 cps at ± 1 ° C.

(2) Imidazole curing agent (manufactured by Shikoku Chemicals, trade name: 2E4MZ-CN) 6.5 parts by weight. (3) The mixtures (1) and (2) were mixed to prepare a resin filler.

Manufacturing of Printed Wiring Board FIGS. 1A to 7S are cross-sectional views of a printed wiring board manufactured according to the process according to the first embodiment of the present invention. (1) As shown in FIG. 1A, in this embodiment, the thickness is 1 mm.
1 made of bismaleimide triazine (BT) resin
A copper-clad laminate 3 in which 18 μm copper foil 2 was laminated on both surfaces of was used as a starting material.

(2) First, drill holes 4 are formed in the copper-clad laminate 3.
, An electroless plating is performed, and an inner copper pattern (lower conductive circuit) 5 is provided on both surfaces of the substrate 1 by etching the copper foil in a pattern according to a conventional method, thereby forming a through hole 6 (FIG. 1). (B)).

Next, on the surface of the inner layer copper pattern 5, the land surface and the inner wall of the through hole 6, roughened layers 7, 8,
9 (FIG. 1C). The roughened layers 7, 8, 9 are formed by washing the above-mentioned substrate with water and drying, and then spraying an etchant on both surfaces of the substrate by spraying to spray the surface of the inner layer copper pattern 5,
The through-hole 6 was formed by etching the land surface and inner wall. The etching solution used was a mixture of 10 parts by weight of an imidazole copper (II) complex, 7 parts by weight of glycolic acid, 5 parts by weight of potassium chloride, and 78 parts by weight of ion-exchanged water.

(3) Next, the resin layers 11 and 12 are
0 between the inner copper patterns 5 and in the through holes 6. Here, first, the resin layers 11 and 12 are coated with the resin filler B prepared in advance on both surfaces of the wiring board 10 by a roll coater, and the resin layer B is formed between the inner layer copper pattern 5 and the through hole 6.
Filled in at 100 ℃ for 1 hour, 120 ℃ for 3 hours, 150 ℃
For 1 hour and by heating at 180 ° C. for 7 hours, respectively, to form a cured product (FIG. 1 (D)).

(4) One side of the substrate obtained in the process of (3) was polished with a belt sander. In this polishing, a # 600 belt polishing paper (manufactured by Sankyo Rikagaku Co., Ltd.) was used to prevent the resin filler from remaining on the roughened layer 7 of the inner copper pattern 5 and the land surface of the through hole 6. Next, buffing was performed to remove the scratches caused by the belt sander polishing. Such a series of polishing was similarly performed on the other surface of the substrate to obtain a wiring substrate 13 as shown in FIG.

In this wiring board 13, resin layer 11 is provided between inner layer copper patterns 5, and resin layer 1 is provided in through hole 6.
2 are provided. The roughened layer 7 of the inner layer copper pattern 5 and the roughened layer 8 on the land surface of the through hole 6 are removed, and both surfaces of the substrate are smoothed by a resin filler. The resin layer 11 is in close contact with the inner copper pattern 5 via the roughened layer 7a on the side surface of the inner copper pattern 5, and the resin layer 12 is in close contact with the inner wall of the through hole 6 via the roughened layer 9 on the inner wall of the through hole 6. are doing.

(5) Further, as shown in FIG. 2 (F), the exposed upper surface of the land of the inner layer copper pattern 5 and the through hole 6 is removed.
Roughening was performed by the etching process (2) to form roughened layers 14 and 15 having a thickness of 3 μm. 45 directly above and obliquely above the roughened surface
When photographed with an electron microscope from an angle of °, an average of 11 anchors were formed in an area per 5 μm square, an average of 11 depressions were formed in an area per 5 μm square, and 22 ridges were formed in an area per 5 μm square. Was observed. Furthermore, this roughened surface has a Su-Pd
A colloidal catalyst (Cataplay 44, Shipley) was applied to reduce Pd ions to Pd atoms with 1 NHu.

(6) An adhesive composition A for electroless plating prepared in advance was applied to both surfaces of the obtained wiring board using a roll coater. The composition was left standing for 20 minutes in a horizontal state, and then dried at 60 ° C. for 30 minutes to form an adhesive layer (interlayer resin insulating layer) 16 having a thickness of 35 μm (FIG. 2 (G)).

(7) As shown in FIG. 3H, a photomask film 18 on which a black circle 17 of 85 μmφ is printed is brought into close contact with both surfaces of the wiring board on which the adhesive layer 16 is formed in (6). . 500mJ / cm
Exposure at ² .

Then, the wiring board was spray-developed using a DMDG solution to form an opening 19 serving as a 85 μmφ via hole in the adhesive layer 16 (FIG. 3).
(I)). Furthermore, this wiring board is
Exposure at 100 mJ / cm ² , 1 hour at 100 ° C, then 150 ° C
By performing the heat treatment for 5 hours, an opening (opening for forming a via hole) 19 having excellent dimensional accuracy corresponding to a photomask film was formed. The adhesive layer 16 having a thickness of 35 μm functioned as an interlayer insulating material layer, and the inner layer copper pattern 5 was partially exposed in the via hole forming opening.

(8) Next, 80 g of the substrate after the treatment of (7)
/ L of chromic acid aqueous solution for 1 minute to dissolve and remove the epoxy resin particles present on the surface of the adhesive layer 16. By this processing, the roughened layers 20, 21 as shown in FIG.
Was formed on the surface of the adhesive layer 16 and the inner wall surface of the via hole opening. Thereafter, the obtained substrate 22 was immersed in a neutralizing solution (manufactured by Shipley) and then washed with water. Void (5 μm average diameter) is formed in the inner copper pattern 5 by the chromic acid treatment.
m) 14a occurred.

Further, on the surface of the roughened wiring board,
Again palladium catalyst (Cypresit 4
4), the roughened layer 20 of the adhesive layer 16
Then, a catalyst core 33 was attached to the roughened layer 21 of the via hole opening (FIG. 4K).

(9) The obtained substrate was immersed in an electroless copper plating bath under the following conditions to obtain a substrate having a thickness of 1.6 as shown in FIG.
A μm electroless copper plating film 23 was formed on the entire roughened surface. Electroless plating solution; EDTA: 150 g / l Copper sulfate: 20 g / l HCHO: 30 ml / l NaOH: 40 g / l α, α'-bipyridyl: 80 mg / l PEG: 0.1 g / l None Electroplating condition; 30 minutes at 70 ° C liquid temperature

(10) Next, a commercially available photosensitive dry film (not shown) was attached to the electroless copper plating film 23, and a mask film (not shown) on which a pattern was printed was placed. This substrate was exposed at 100 mJ / cm ² and then exposed to 0.8 mJ / cm ^2.
4M, a plating resist 27 having a thickness of 15 μm was provided as shown in FIG.

(11) Next, the obtained substrate was subjected to electrolytic copper plating under the following conditions, and a thickness of 15 μm as shown in FIG.
m of electrolytic copper plating film 28 was formed. Electrolytic plating solution; Sulfuric acid: 180 g / l Copper sulfate: 80 g / l Additive: 1 ml / l (Additives are manufactured by Atotech Japan: trade name Capalaside G
L) Electroplating conditions; Current density: 1 A / dm ² hours: 30 minutes Temperature: room temperature

(12) After the plating resist 26 is peeled off with 5% KOH, it is etched with a mixed solution of sulfuric acid and hydrogen peroxide.
Electroless plating film 2 existing under plating resist 26
3 was dissolved away. As shown in FIG. 5 (O), a thickness of 18 μm comprising the electroless copper plating film 23 and the electrolytic copper plating film 28
m conductor circuits 29 (including via holes 30) were obtained.

Further, an etching solution containing a mixture of 10 parts by weight of an imidazole copper (II) complex, 7 parts by weight of glycolic acid, 5 parts by weight of potassium chloride, and 78 parts by weight of ion-exchanged water is sprayed onto the conductor circuit 29 (via hole). 30)
A roughened surface 35 was formed on the surface, and the palladium catalyst 33 on the surface of the adhesive layer 16 was removed to produce a multilayer printed wiring board 31 as shown in FIG. 5 (P).

(14) Further, the above steps 6) to (8) are performed to form an adhesive layer 116 on the conductor circuit 29 (FIG. 6 (Q)).
Here, when the adhesive layer 116 is roughened, the conductive circuits 29
Voids 35a are formed in the roughened surface 35 of FIG.

(15) Subsequently, the above (9) to (13) are repeated to form a conductor circuit 129 and a via hole 1 on the adhesive layer 116.
30 was formed to obtain a multilayer printed wiring board shown in FIG. The roughened surface 35 of the conductor circuit 29 having the void 35a has an excellent affinity with the plating solution, and the plating penetrates into the void 35a and follows the anchor-shaped portion. The hole 130 is further in close contact. That is, when the via hole 130 is formed on the lower conductor circuit 29 by plating, the conductor of the via hole 130 is cut into the void 35a of the conductor circuit 29, so that the adhesion can be increased.

(16) Solder bumps are formed on the above-mentioned multilayer printed wiring board. First, 60 dissolved in DMDG
46.67 g of an oligomer (molecular weight: 4000) of a cresol novolak type epoxy resin (manufactured by Nippon Kayaku Co., Ltd.) in which 50% of an epoxy group of the acrylate is acrylated, and 80% by weight of a bisphenol A type epoxy dissolved in methyl ethyl ketone Resin (made of Yuka Shell, Epicoat 10
01) 15.0 g, imidazole curing agent (Shikoku Chemicals,
2E4MZ-CN) 1.6 g, polyvalent acrylic monomer (R604, manufactured by Nippon Kayaku) which is a photosensitive monomer
g, also polyvalent acrylic monomer (manufactured by Kyoeisha Chemical, DP
E6A) 1.5 g and a dispersant defoamer (manufactured by San Nopco Co., S-65) 0.71 g were mixed, and 2 g of benzophenone as a photoinitiator (manufactured by Kanto Kagaku) was added to this mixture, followed by photosensitization. 0.2g of Michler's ketone (manufactured by Kanto Chemical Co.)
A solder resist composition adjusted to a · s was obtained. The viscosity was measured using a B-type viscometer (Tokyo Keiki, DVL-B
In the case of 60 rpm, the rotor No. 4,6 rp
m, the rotor No. According to 3.

(17) The above-mentioned solder resist composition is applied to both sides of the multilayer printed wiring board obtained in the above (16) in a thickness of 20 μm.
Was applied. Then at 70 ° C for 20 minutes at 70 ° C
After performing a drying process for 30 minutes, a 5 mm-thick photomask film on which a circular pattern (mask pattern) is drawn is placed in close contact with the substrate, exposed to ultraviolet light of 1000 mJ / cm ² , and subjected to DMTG development processing. . And then 8
1 hour at 0 ° C, 1 hour at 100 ° C, 1 hour at 120 ° C,
Heat treatment was performed at 150 ° C. for 3 hours to form a solder resist layer (thickness: 20 μm) 70 having an opening (opening diameter: 200 μm) 71 of the solder pad portion (including the via hole and its land portion) (FIG. 7). (S)).

(18) Next, nickel chloride 2.31 × 10 ⁻¹ m
ol / l, sodium hypophosphite 2.8 × 10 ⁻¹ mol /
1 and 1.85 × 10 ⁻¹ mol / l of sodium citrate, and the substrate 3 was placed in an electroless nickel plating solution having a pH of 4.5.
0 was immersed for 20 minutes to form a nickel plating layer 72 having a thickness of 5 μm in the opening 71. Further, the substrate was treated with potassium cyanide 4.1 × 10 ⁻² mol / l, ammonium chloride 1.87 × 10 ⁻¹ mol / l, sodium citrate 1.
16 × 10 ⁻¹ mol / l, sodium hypophosphite 1.7 × 10
Immersion in an electroless gold plating solution of ^-1 mol / l at 80 ° C. for 7 minutes and 20 seconds to form a film having a thickness of 0.2 mm on the nickel plating layer.
By forming a gold plating layer 74 of 03 μm, a solder pad 75 is formed in the via hole 130 (see FIG. 7 (T)).

(19) Then, a solder paste is printed as a low melting point metal on the opening 71 of the solder resist layer 70.
By performing reflow at 200 ° C., solder bumps (solder bodies) 76U and 76D are formed.
Was completed (see FIG. 8).

[0083]

As described above, in the multilayer printed wiring board and the method of manufacturing the multilayer printed wiring board of the present invention, since the void is formed on the surface of the conductor circuit, the void is closely attached to the via hole. The connection reliability of the via hole can be improved.

[Brief description of the drawings]

1 (A), 1 (B), 1 (C), 1
(D) is a manufacturing process diagram of the multilayer printed wiring board according to the first example of the present invention.

FIGS. 2 (E), 2 (F), and 2 (G) are manufacturing process diagrams of the multilayer printed wiring board according to the first embodiment of the present invention.

FIGS. 3 (H), 3 (I), and 3 (J) are manufacturing process diagrams of the multilayer printed wiring board according to the first embodiment of the present invention.

FIGS. 4 (K), 4 (L), and 4 (M) are manufacturing process diagrams of the multilayer printed wiring board according to the first embodiment of the present invention.

FIGS. 5 (N), 5 (O), and 5 (P) are manufacturing process diagrams of the multilayer printed wiring board according to the first embodiment of the present invention.

FIGS. 6 (Q) and 6 (R) are manufacturing process diagrams of the multilayer printed wiring board according to the first embodiment of the present invention.

FIGS. 7 (S) and 7 (T) are manufacturing process diagrams of the multilayer printed wiring board according to the first embodiment of the present invention.

FIG. 8 is a sectional view of the multilayer printed wiring board according to the first embodiment of the present invention.

FIG. 9 is a sectional view of the multilayer printed wiring board according to the first embodiment of the present invention.

[Explanation of symbols]

 Reference Signs List 1 substrate 2 copper foil 3 copper-clad laminate 5 inner layer copper pattern 6 through hole 7, 8, 9, 14, 15, 20, 21 roughened layer 14a void 10, 13, 22 wiring board 11, 12 resin layer 16, 116 Adhesive layer (interlayer resin insulating layer) 19 Opening 23 Electroless copper plating film 27 Plating resist 28 Electrolytic copper plating film 29 Conductor circuit 30 Via hole 31 Multilayer printed wiring board 33 Catalyst core 35 Roughened surface 35a Void 45 Roughened layer 129 Conductor circuit

 ──────────────────────────────────────────────────続 き Continued on the front page F-term (reference) 5E343 AA02 AA12 BB15 BB24 BB71 CC33 CC35 CC43 EE37 EE55 GG04 5E346 AA06 AA12 AA15 AA35 AA43 BB01 CC08 CC32 CC58 DD03 DD22 DD33 DD47 EE34 EE38 FF02 FF07 GG17 GG17 GG07

Claims (2)

[Claims] 1. A multilayer printed wiring board in which interlayer resin insulating layers and conductive circuits are alternately laminated, wherein a void is formed on the surface of the conductive circuit. 2. A method for manufacturing a multilayer printed wiring board comprising alternately laminating an interlayer resin insulation layer and a conductor circuit, comprising: forming a conductor circuit; forming an interlayer resin insulation layer; A method for manufacturing a multilayer printed wiring board, comprising: providing an opening for forming a via hole; roughening the surface of the interlayer resin insulating layer; and forming a void in the surface of the conductive circuit.