JP4746252B2 - Multilayer printed circuit board - Google Patents

Description

〔式中、Ａは錯化剤（キレート剤として作用）、ｎは配位数を示す。〕
【００５３】
上記反応式に示すように、発生した第一銅錯体は、酸の作用で溶解し、酸素と結合して第二銅錯体となって、再び銅の酸化に寄与する。
【００５４】
本発明で用いる第二銅錯体は、アゾール類の第二銅錯体がよい。この種の第二銅錯体は、金属銅等を酸化する酸化剤として作用する。アゾール類としては、ジアゾール、トリアゾール、テトラゾールがよい。中でも、イミダゾール、２−メチルイミダゾール、２−エチルイミダゾール、２−エチル−４−メチルイミダゾール、２−フェニルイミダゾール、２−ウンデシルイミダゾール等がよい。アゾール類の第二銅錯体の添加量は、１〜15重量％がよい。溶解性及び安定性に優れるからである。
【００５５】
有機酸は、酸化銅を溶解させるために、第二銅錯体と配合する。アゾール類の第二銅錯体を用いる場合には、有機酸は、ギ酸、酢酸、プロピオン酸、酪酸、吉草酸、カプロン酸、アクリル酸、クロトン酸、シュウ酸、マロン酸、コハク酸、グルタル酸、マレイン酸、安息香酸、グリコール酸、乳酸、リンゴ酸、スルファミン酸からなる群より選ばれる少なくとも１種がよい。有機酸の含有量は、0.1 〜30重量％がよい。酸化された銅の溶解性を維持し、かつ溶解安定性を確保するためである。
【００５６】
本発明にかかるエッチング液には、銅の溶解やアゾール類の酸化作用を補助するために、フッ素イオン、塩素イオン、臭素イオン等のハロゲンイオンを加えてもよい。かかるハロゲンイオンは、塩酸、塩化ナトリウム等として供給することができる。ハロゲンイオンの添加量は、0.01〜20重量％がよい。形成された粗化面とソルダーレジスト層との密着性に優れるからである。
【００５７】
本発明にかかるエッチング液は、アゾール類の第二銅錯体と有機酸（必要に応じてハロゲンイオン）とを、水に溶解して調製することができる。また、市販のエッチング液、例えば、メック社製、商品名「メック エッチボンド」を用いることができる。
【００５８】
かかるエッチング液による平均エッチング量は、0.1 〜10μｍがよい。0.1 μｍ未満では、粗化面とソルダーレジスト層との密着性が低下し、10μｍを超えると、樹脂残りが発生し易く、また、５０μｍ以下の微細配線では、断線等が起こり易くなる。
【００５９】
本発明では、このようにして形成される粗化面上に、金属層を被覆することができる。かかる金属層は、チタン、亜鉛、鉄、インジウム、タリウム、コバルト、ニッケル、スズ、鉛、ビスマス及び貴金属からなる群より選ばれる少なくとも１種の金属からなる。かかる金属層の被覆は、めっき、蒸着、電着、スパッタのいずれかの方法で行うことができる。形成される膜の均一性という点では、めっきで行うのがよい。
【００６０】
また、本発明では、かかる金属層が均一に形成されるようにするために、粗化面を形成した後、その粗化面を熱処理してから、金属層を形成させることができる。熱処理により、エッチング液及びその残留成分が蒸発し、粗化面の表面状態が均一になるために、金属層が形成し易くなる。
【００６１】
熱処理の温度は、粗化面の形状や厚み、はんだパッド用導体回路の金属成分や厚み等により、種々の範囲に設定することができる。特に、５０〜２５０℃の範囲内がよい。５０℃未満の場合は、熱処理の効果が見られないし、２５０℃を超えると、粗化面が酸化され、形成された金属層が不均一になる。
【００６２】
本発明では、このようにして形成される所定形状の粗化面上に、ソルダーレジスト層を形成する。かかるソルダーレジスト層の厚さは、５〜４０μｍがよい。
薄過ぎると、ソルダーレジスト層がソルダーダムとして機能せず、また、厚過ぎると、はんだバンプ用の開口部を形成し難くなる上、はんだ体と接触して、はんだ体にクラックが生じる原因となるからである。
【００６３】
ソルダーレジスト層は、種々の樹脂から形成することができる。例えば、ビスフェノールＡ型エポキシ樹脂やそのアクリレートか、ノボラック型エポキシ樹脂やそのアクリレートを、アミン系硬化剤やイミダゾール硬化剤等で硬化させて形成することができる。
【００６４】
特に、ソルダーレジスト層に開口を設けて、はんだバンプを形成する場合、ノボラック型エポキシ樹脂かそのアクリレートを、イミダゾール硬化剤で硬化させるのが好ましい。かかる樹脂からなるソルダーレジスト層は、鉛のマイグレーション（鉛イオンがソルダーレジスト層内を拡散する現象）が少ないという利点を持つ。
【００６５】
また、ノボラック型エポキシ樹脂のアクリレートをイミダゾール硬化剤で硬化させた樹脂の場合、耐熱性、耐アルカリ性に優れ、はんだが溶融する温度（200 ℃前後）でも劣化せず、ニッケルめっきや金めっきのような強塩基性のめっき液で分解しない。ノボラック型エポキシ樹脂のアクリレートとしては、フェノールノボラックやクレゾールノボラックのグリシジルエーテルを、アクリル酸やメタクリル酸等と反応させたエポキシ樹脂等を挙げることができる。
【００６６】
しかし、ノボラック型エポキシ樹脂のアクリレートから形成されるソルダーレジスト層は、剛直骨格を持つ樹脂で構成されるので、導体回路との間で剥離が生じ易い。本発明にかかる粗化面は、かかる剥離を防止でき、有利である。
【００６７】
イミダゾール硬化剤は、25℃で液状であるのが望ましい。液状であれば、均一混合し易いからである。かかる硬化剤としては、1-ベンジル−2-メチルイミダゾール（品名：1B2MZ ）、1-シアノエチル−2-エチル−4-メチルイミダゾール（品名：2E4MZ-CN）、4-メチル−2-エチルイミダゾール（品名：2E4MZ ）を挙げることができる。
【００６８】
かかる樹脂及び硬化剤は、グリコールエーテル系の溶剤に溶解し、ソルダーレジスト用組成物とするのが望ましい。かかる組成物からソルダーレジスト層を形成すると、遊離酸素が発生せず、銅パッド表面を酸化させない。また、人体に対する有害性も少ない。
【００６９】
グリコールエーテル系の溶剤としては、次の一般式：
ＣＨ₃Ｏ−（ＣＨ₂ＣＨ₂Ｏ）_n−ＣＨ₃（ｎ＝１〜５）
で表される溶媒を用いることができる。
【００７０】
特に望ましくは、ジエチレングリコールジメチルエーテル（ＤＭＤＧ）及びトリエチレングリコールジメチルエーテル（ＤＭＴＧ）からなる群より選ばれる少なくとも１種を用いる。これらの溶剤は、30〜50℃程度の加温により、ベンゾフェノンやミヒラーケトン等の反応開始剤を完全に溶解させることができる。かかる溶剤の量は、ソルダーレジスト用組成物の10〜40重量％がよい。
【００７１】
イミダゾール硬化剤の添加量は、ソルダーレジスト用組成物の総固形分に対して、１〜10重量％とすることが望ましい。添加量がこの範囲内にあれば、均一混合し易いからである。
【００７２】
上述したようなソルダーレジスト用組成物には、この他に、各種消泡剤やレベリング剤、開始剤、光増感剤、耐熱性や耐塩基性の改善と可撓性付与のための熱硬化性樹脂、解像度改善のための感光性モノマー等を添加することができる。
【００７３】
レベリング剤としては、アクリル酸エステルの重合体からなるものがよい。また、開始剤としては、チバガイギー製のイルガキュアＩ９０７、光増感剤としては日本化薬製のＤＥＴＸ−Ｓがよい。
【００７４】
熱硬化性樹脂には、ビスフェノール型エポキシ樹脂を用いることができる。このビスフェノール型エポキシ樹脂には、ビスフェノールＡ型エポキシ樹脂とビスフェノールＦ型エポキシ樹脂があり、耐塩基性を重視する場合には前者が、低粘度化が要求される場合（塗布性を重視する場合）には後者がよい。
【００７５】
感光性モノマーには、多価アクリル系モノマーを用いることができる。多価アクリル系モノマーは、解像度を向上させることができるからである。例えば、日本化薬製のＤＰＥ−６Ａや共栄社化学製のＲ−６０４等の多価アクリル系モノマーを用いることができる。
【００７６】
かかるソルダーレジスト用組成物には、色素や顔料等を添加してもよい。配線パターンを隠蔽できるからである。かかる色素としては、フタロシアニングリーンを用いることが望ましい。
【００７７】
また、かかるソルダーレジスト用組成物は、２５℃で０．５〜１０Ｐａ・ｓ、より望ましくは、１〜１０Ｐａ・ｓの粘度を有するのがよい。ロールコータで塗布し易いからである。
【００７８】
かかる組成物よりなるソルダーレジスト層に開口部を、露光、現像処理により形成することができる。
【００７９】
次に、本発明のプリント配線板を製造する方法について説明する。以下の方法は、主として、セミアディティブ法によるものであるが、フルアディティブ法を採用してもよい。
【００８０】
本発明では、はんだパッドとなる導体回路を基板の表面に形成した配線基板を作製する。基板としては、ガラスエポキシ基板、ポリイミド基板、ビスマレイミド−トリアジン樹脂基板等の樹脂絶縁基板、セラミック基板、金属基板等を用いることができる。
【００８１】
かかる配線基板は、内部に複数層の導体回路が形成された多層プリント配線板であってもよい。かかる複数層の導体回路を形成する方法としては、例えば、基板上に設けられた下層導体回路上に、層間絶縁樹脂層として、無電解めっき用接着剤からなる接着剤層を形成し、この接着剤層表面を粗化して粗化面とし、この粗化面全体に薄付けの無電解めっきを施し、めっきレジストを形成し、めっきレジスト非形成部分に厚付けの電解めっきを施した後、めっきレジストを除去し、エッチング処理して、電解めっき膜と無電解めっき膜とからなる２層の導体回路を形成する方法がある。導体回路は、いずれも銅パターンがよい。
【００８２】
無電解めっき用接着剤は、酸や酸化剤に可溶性の硬化処理された耐熱性樹脂粒子が、酸や酸化剤に難溶性の未硬化の耐熱性樹脂中に分散されてなるものが最適である。かかる耐熱性樹脂粒子は、酸や酸化剤で処理することによって溶解除去され、表面に蛸つぼ状のアンカーからなる粗化面を形成するからである。なお、かかる無電解めっき用接着剤は、組成の異なる２層により構成してもよい。
【００８３】
酸や酸化剤に可溶性の硬化処理された耐熱性樹脂粒子としては、(1) 平均粒径が10μｍ以下の耐熱性樹脂粉末、(2) 平均粒径が２μｍ以下の耐熱性樹脂粉末を凝集させた凝集粒子、(3) 平均粒径が２〜10μｍの耐熱性樹脂粉末と平均粒径が２μｍ未満の耐熱性樹脂粉末との混合物、(4) 平均粒径が２〜10μｍの耐熱性樹脂粉末の表面に、平均粒径が２μｍ以下の耐熱性樹脂粉末及び無機粉末の少なくとも１種を付着させた疑似粒子、(5) 平均粒径が０．１〜０．８μｍの耐熱性樹脂粉末と平均粒径が０．８μｍを超え２μｍ未満の耐熱性樹脂粉末との混合物、(6) 平均粒径が０．１〜１．０μｍの耐熱性樹脂粉末からなる群より選ばれる少なくとも１種の粒子を用いることが望ましい。これらは、より複雑なアンカーを形成するからである。これらの粒子により得られる粗化面は、０．１〜２０μｍの最大粗度（Ｒｍａｘ）を有することができる。
【００８４】
かかる耐熱性樹脂粒子の混合比は、耐熱性樹脂からなるマトリックスの固形分の５〜５０重量％、望ましくは１０〜４０重量％がよい。また、かかる耐熱性樹脂粒子は、アミノ樹脂（メラミン樹脂、尿素樹脂、グアナミン樹脂等）、エポキシ樹脂等からなるのがよい。
【００８５】
酸や酸化剤に難溶性の未硬化の耐熱性樹脂としては、熱硬化性樹脂と熱可塑性樹脂との樹脂複合体、又は感光性樹脂と熱可塑性樹脂との樹脂複合体からなるのが望ましい。前者については耐熱性が高く、後者についてはバイアホール用の開口をフォトリソグラフィーにより形成できるからである。
【００８６】
かかる熱硬化性樹脂としては、エポキシ樹脂、フェノール樹脂、ポリイミド樹脂等を用いることができる。また、感光化する場合は、熱硬化基をメタクリル酸やアクリル酸等とアクリル化反応させる。特に、エポキシ樹脂のアクリレートが最適である。エポキシ樹脂としては、フェノールノボラック型、クレゾールノボラック型等のノボラック型エポキシ樹脂、ジシクロペンタジエン変性させた脂環式エポキシ樹脂等を用いることができる。
【００８７】
熱可塑性樹脂としては、ポリエーテルスルフォン（ＰＥＳ）、ポリスルフォン（ＰＳＦ）、ポリフェニレンスルフォン（ＰＰＳ）、ポリフェニレンサルファイド（ＰＰＥＳ）、ポリフェニルエーテル（ＰＰＥ）、ポリエーテルイミド（ＰＩ）等を用いることができる。
【００８８】
熱硬化性樹脂（感光性樹脂）と熱可塑性樹脂の混合割合は、熱硬化性樹脂（感光性樹脂）／熱可塑性樹脂＝９５／５〜５０／５０がよい。耐熱性を損なうことなく、高い物性値が得られるからである。
【００８９】
次に、かかる無電解めっき用接着剤を硬化させて、層間絶縁樹脂層を形成する一方、この層間樹脂樹脂層には、バイアホール形成用の開口を設けることができる。
【００９０】
バイアホール形成用の開口は、無電解めっき用接着剤の樹脂マトリックスが熱硬化樹脂である場合は、レーザー光や酸素プラズマ等を用いて穿孔し、感光性樹脂である場合は、露光現像処理にて穿孔する。なお、露光現像処理は、バイアホール形成用に円パターンが描画されたフォトマスク（ガラス基板がよい）を、円パターン側が感光性の層間樹脂絶縁層の上に密着するように載置した後、露光、現像処理する。
【００９１】
次に、バイアホール形成用開口を設けた層間樹脂絶縁層（無電解めっき用接着剤層）の表面を粗化する。特に、無電解めっき用接着剤層の表面に存在する耐熱性樹脂粒子を、酸や酸化剤で溶解除去することにより、接着剤層表面を粗化処理する。このとき、層間樹脂絶縁層に粗化面が形成される。
【００９２】
酸としては、リン酸、塩酸、硫酸等の無機酸、又は蟻酸や酢酸等の有機酸を用いることができる。特に、有機酸を用いるのが望ましい。粗化処理した場合に、バイアホールから露出する金属導体層を腐食させ難いからである。酸化剤としては、クロム酸、過マンガン酸塩（過マンガン酸カリウム等）を用いるのが望ましい。
【００９３】
かかる粗化面は、０．１〜２０μｍの最大粗度（Ｒｍａｘ）を有するのが好ましい。厚過ぎると層自体が損傷、剥離し易く、薄過ぎると密着性が低下するからである。特に、セミアディティブ法では、０．１〜５μｍがよい。密着性が確保されつつ、無電解めっき膜が除去されるからである。
【００９４】
次に、粗化した層間樹脂絶縁層上に触媒核を付与し、全面に薄付けの無電解めっき膜を形成する。この無電解めっき膜は、無電解銅めっきがよく、厚みは、１〜５μｍ、より望ましくは、２〜３μｍとする。なお、無電解銅めっき液としては、常法で採用される液組成のものを使用することができる。例えば、硫酸銅：10ｇ／Ｌ、ＥＤＴＡ：50ｇ／Ｌ、水酸化ナトリウム：８ｇ／Ｌ、37％ホルムアルデヒド：10ｍＬ、からなる液組成のものがよい。
【００９５】
次に、このように形成した無電解めっき膜上に、感光性樹脂フィルム（ドライフィルム）をラミネートし、この感光性樹脂フィルム上に、めっきレジストパターンが描画されたフォトマスク（ガラス基板がよい）を密着させて載置し、露光し、現像処理することにより、めっきレジストパターンを配設した非導体部分を形成する。
【００９６】
次に、無電解銅めっき膜上の非導体部分以外に電解めっき膜を形成し、導体回路とバイアホールとなる導体部を設ける。電解めっきとしては、電解銅めっきを用いることが望ましく、その厚みは、５〜20μｍがよい。
【００９７】
次に、非導体回路部分のめっきレジストを除去した後、更に、硫酸と過酸化水素の混合液や過硫酸ナトリウム、過硫酸アンモニウム、塩化第二鉄、塩化第二銅等のエッチング液にて無電解めっき膜を除去し、無電解めっき膜と電解めっき膜の２層からなる独立した導体回路とバイアホールを得る。なお、非導体部分に露出した粗化面上の触媒核は、クロム酸、硫酸と過酸化水素との混合液等により溶解除去する。
【００９８】
次いで、表層のはんだパッドとなる導体回路に、本発明にかかる粗化面を形成する。かかる粗化面は、前述したアゾール類の第二銅錯体と有機酸の水溶液からなるエッチング液を導体回路表面にスプレイするか、かかるエッチング液に導体回路を浸漬し、バブリングする方法により形成することができる。なお、導体回路は、無電解めっき膜又は電解めっき膜が望ましい。厚延銅箔をエッチングした導体回路では、粗化面が形成され難いからである。
【００９９】
このようにして形成された粗化面は、更に、その後、エッチング処理、研磨処理、酸化処理、酸化還元処理等によって処理することができ、めっき被膜で被覆することもできる。
【０１００】
また、かかる粗化面は、チタン、亜鉛、鉄、インジウム、タリウム、コバルト、ニッケル、スズ、鉛、ビスマス及び貴金属からなる群より選ばれる少なくとも１種の金属からなる金属層によって被覆することができる。被覆方法は、めっき（電解めっき、無電解めっき、置換めっきのいずれかの中選ばれる方法）、蒸着、電着、スパッタ等で行うことができる。
【０１０１】
かかる処理を施された粗化面を有する導体回路上には、前述したようなソルダーレジスト層を形成することができる。
【０１０２】
【実施例】
図面を参照して、本発明を実施例及び比較例に基づいて説明する。
実施例１
無電解めっき用接着剤調製用の原料組成物（上層用接着剤）
〔樹脂組成物Ａ〕
クレゾールノボラック型エポキシ樹脂（日本化薬製、分子量2500）の25％アクリル化物を80wt％の濃度でＤＭＤＧに溶解させた樹脂液を35重量部、感光性モノマー（東亜合成製、アロニックスＭ315 ）3.15重量部、消泡剤（サンノプコ製、Ｓ−65）0.5 重量部、ＮＭＰ 3.6重量部を攪拌混合して得た。
【０１０３】
〔樹脂組成物Ｂ〕
ポリエーテルスルフォン（ＰＥＳ）12重量部、エポキシ樹脂粒子（三洋化成製、ポリマーポール）の平均粒径 1.0μｍのものの 7.2重量部と、平均粒径 0.5μｍのものの3.09重量部とを混合した後、更にＮＭＰ30重量部を添加し、ビーズミルで攪拌混合して得た。
【０１０４】
〔硬化剤組成物Ｃ〕
イミダゾール硬化剤（四国化成製、2E4MZ-CN）２重量部、光開始剤（チバガイギー製、イルガキュア Ｉ−907 ）２重量部、光増感剤（日本化薬製、DETX-S）0.2 重量部、ＮＭＰ 1.5重量部を攪拌混合して得た。
【０１０５】
層間樹脂絶縁剤調製用の原料組成物（下層用接着剤）
〔樹脂組成物Ｄ〕
クレゾールノボラック型エポキシ樹脂（日本化薬製、分子量2500）の25％アクリル化物を80wt％の濃度でＤＭＤＧに溶解させた樹脂液を35重量部、感光性モノマー（東亜合成製、アロニックスＭ315 ）４重量部、消泡剤（サンノプコ製、Ｓ−65）0.5 重量部、ＮＭＰ 3.6重量部を攪拌混合して得た。
【０１０６】
〔樹脂組成物Ｅ〕
ポリエーテルスルフォン（ＰＥＳ）12重量部とエポキシ樹脂粒子（三洋化成製、ポリマーポール）の平均粒径 0.5μｍのものの14.49重量部とを混合した後、更にＮＭＰ30重量部を添加し、ビーズミルで攪拌混合して得た。
【０１０７】
〔硬化剤組成物Ｆ〕
イミダゾール硬化剤（四国化成製、2E4MZ-CN）２重量部、光開始剤（チバガイギー製、イルガキュア Ｉ−907 ）２重量部、光増感剤（日本化薬製、DETX-S）0.2 重量部、ＮＭＰ1.5 重量部を攪拌混合して得た。
【０１０８】
樹脂充填剤調製用の原料組成物
〔樹脂組成物Ｇ〕
ビスフェノールＦ型エポキシモノマー（油化シェル製、分子量310 、YL983U） 100重量部、表面にシランカップリング剤がコーティングされた平均粒径 1.6μｍのSiＯ₂球状粒子（アドマテック製、CRS 1101−CE、ここで、最大粒子の大きさは後述する内層銅パターンの厚み（15μｍ）以下とする） 170重量部、レベリング剤（サンノプコ製、ペレノールＳ４）1.5 重量部を攪拌混合することにより、その混合物の粘度を23±１℃で45,000〜49,000cps に調整して得た。
【０１０９】
〔硬化剤組成物Ｈ〕
イミダゾール硬化剤（四国化成製、2E4MZ-CN）6.5 重量部。
【０１１０】
プリント配線板の製造
図１３〜３０は、本発明にかかるプリント配線板の一例を製造する際の一連の製造工程の各工程における縦断面図をそれぞれ示す。
(1) 図１３に示すような、厚さ１mmのガラスエポキシ樹脂又はＢＴ（ビスマレイミドトリアジン）樹脂からなる基板４の両面に18μｍの銅箔５がラミネートされている銅張積層板６を出発材料とした。
【０１１１】
まず、この銅張積層板６には、図１４に示すように、ドリル孔７を削孔し、無電解めっき処理を施し、パターン状にエッチングすることにより、基板６の両面に内層銅パターン（下層導体回路）８とスルーホール９を形成した。
【０１１２】
(2) 内層銅パターン８とスルーホール９を形成した基板を水洗いし、乾燥した後、酸化浴（黒化浴）として、NaOH（10ｇ／Ｌ）、NaClＯ₂（40ｇ／Ｌ）、Na₃PO₄（６ｇ／Ｌ）、還元浴として、NaOH（10ｇ／Ｌ）、NaBH₄（６ｇ／Ｌ）を用いた酸化−還元処理により、内層銅パターン８とスルーホール９の表面に粗化面１０，１１を設け、図１４に示すような配線基板１２を製造した。
【０１１３】
(3)樹脂組成物Ｇと硬化剤組成物Ｈとを混合混練して樹脂充填剤を得、この樹脂充填剤を、調製後24時間以内に、基板１２の両面にロールコータを用いて塗布することにより、導体回路８間あるいはスルーホール９内に充填し、70℃、20分間で乾燥させて、樹脂層１３，１４を形成した。
【０１１４】
(4) 前記(3) の処理を終えた基板の片面を、＃600 のベルト研磨紙（三共理化学製）を用いたベルトサンダー研磨により、内層銅パターン８の表面やスルーホール９のランド１１の表面に樹脂充填剤が残らないように研磨し、次いで、前記ベルトサンダー研磨による傷を取り除くためのバフ研磨を行った。このような一連の研磨を基板の他方の面についても同様に行った。
【０１１５】
(5) 次いで、100 ℃で１時間、120 ℃で３時間、 150℃で１時間、 180℃で７時間の加熱処理を行って樹脂充填剤を硬化し、図１５に示すような配線基板１５を作製した。この配線基板１５では、スルーホール９等に充填された樹脂充填剤の表層部及び内層導体回路８の上面の粗化面１０，１１が除去されており、基板の両面が平滑化され、樹脂層１３と内層導体回路８の側面とスルーホール９のランド表面とが粗化面１０ａ，１１ａを介して強固に密着し、また、スルーホール９の内壁面と樹脂層１４とが粗化面１１ａを介して強固に密着している。即ち、この工程により、樹脂層１３，１４の表面と内層銅パターン８の表面が同一平面となる。
【０１１６】
(6)導体回路を形成したプリント配線板１５に、アルカリ脱脂してソフトエッチングして、次いで、塩化パラジウウムと有機酸からなる触媒溶液で処理して、Ｐｄ触媒を付与し、この触媒を活性化した後、硫酸銅３．２×１０^−２モル／Ｌ、硫酸ニッケル３．９×１０^−３モル／Ｌ、クエン酸ナトリウム５．４×１０^−２モル／Ｌ、次亜リン酸ナトリウム３．３×１０^−１モル／Ｌ、界面活性剤（日信化学工業製、サーフィール４６５）１．１×１０^−４モル／Ｌ、ｐＨ＝９からなる無電解めっき液に浸積し、浸漬１分後に、４秒当たり１回に割合で振動、揺動させて、図１６に示すように、銅導体回路８とスルーホール９のランドの表面にＣｕ−Ｎｉ−Ｐからなる針状合金の粗化層１６，１７を設けた。
【０１１７】
更に、ホウフッ化スズ０．１モル／Ｌ、チオ尿素１．０モル／Ｌ、温度３５℃、ｐＨ＝１．２の条件でＣｕ−Ｓｎ置換反応させ、粗化層１６，１７の表面に厚さ０．３μｍＳｎ層を設けた。Ｓｎ層は特に図示していない。
【０１１８】
(7)樹脂組成物Ｄ及びＥと硬化剤組成物Ｆとを攪拌混合し、粘度1.5 Pa・ｓに調整して層間樹脂絶縁剤（下層用）を得た。次いで、樹脂組成物Ａ及びＢと硬化剤組成物Ｃとを攪拌混合し、粘度７Pa・ｓに調整して無電解めっき用接着剤溶液（上層用）を得た。
【０１１９】
(8) 前記(6) の基板１８の両面に、前記(7) で得られた粘度 1.5Pa・ｓの層間樹脂絶縁剤（下層用）を、調製後24時間以内にロールコータで塗布し、水平状態で20分間放置してから、60℃で30分の乾燥（プリベーク）を行い、次に、前記(7) で得られた粘度７Pa・ｓの感光性の接着剤溶液（上層用）を、調製後24時間以内に塗布し、水平状態で20分間放置してから、60℃で30分の乾燥（プリベーク）を行い、図１７に示すような厚さ35μｍの接着剤層１９を形成した。
【０１２０】
(9) 前記(8) で接着剤層１９を形成した基板の両面に、図１８に示すように、85μｍφの黒円２０が印刷されたフォトマスクフィルム２１を密着させ、超高圧水銀灯により 500mJ／cm²で露光した。この基板をＤＭＴＧ溶液でスプレー現像し、更に、超高圧水銀灯により3000mJ／cm²で露光し、100 ℃で１時間、120 ℃で１時間、その後 150℃で３時間の加熱処理（ポストベーク）することにより、図１９に示すような、フォトマスクフィルム２１に相当する寸法精度に優れた85μｍφの開口（バイアホール形成用開口）２２を有する厚さ35μｍの層間樹脂絶縁層（２層構造）１９とした。なお、バイアホールとなる開口２２には、スズめっき層を部分的に露出させた。
【０１２１】
(10)開口２２が形成された基板を、クロム酸に19分間浸漬し、層間樹脂絶縁層１９の表面に存在するエポキシ樹脂粒子を溶解除去することにより、この層間樹脂絶縁層１９の表面を粗化し、図２０に示すような粗化面２３，２４を形成し、その後、中和溶液（シプレイ社製）に浸漬してから水洗いした。
【０１２２】
更に、粗面化処理（粗化深さ６μｍ）した基板の表面に、パラジウム触媒（アトテック製）を付与することにより、層間樹脂絶縁層１９の表面２３とバイアホール用開口の内壁面２４とに触媒核を付けた。
【０１２３】
(11)このようにして形成した配線基板を、以下に示す組成の無電解銅めっき水溶液中に浸漬して、図２１に示すように、粗面全体に厚さ0.6μｍの無電解銅めっき膜２５を形成した。

【０１２４】
(12)前記(11)で形成した無電解銅めっき膜２５上に、図２２に示すように、黒円２６が印刷された市販の感光性ドライフィルム２７を張り付け、マスクを載置して、100 mJ／cm²で露光、0.8 ％炭酸ナトリウムで現像処理し、図２３に示すような、厚さ15μｍのめっきレジスト２８を設けた。
【０１２５】
(13)次いで、レジスト非形成部分に以下の条件で電解銅めっきを施し、図２４に示すような厚さ15μｍの電解銅めっき膜２９を形成した。

【０１２６】
(14)めっきレジスト２８を５％ＫＯＨで剥離除去した後、そのめっきレジスト２８の下の無電解めっき膜２５を、硫酸と過酸化水素の混合液でエッチング処理して溶解除去し、図２５に示すような、無電解銅めっき膜２５と電解銅めっき膜２９とからなる厚さ18μｍの導体回路３０（バイアホール３１を含む）を形成した。
【０１２７】
(15)(6)と同様の処理を行い、Cu-Ni-Ｐ針状合金からなる粗化面を形成し、更に、その表面にSn置換を行った。
【０１２８】
(16)前記(7)〜(15)の工程を繰り返すことにより、更に上層の導体回路を形成し、多層配線基板を得た。
【０１２９】
(17)表層の導体回路を、イミダゾール銅（II）錯体１０重量部、グリコール酸７重量部、塩化カリウム５重量部からなるエッチング液、メック社商品名「メックエッチボンド」にて、スプレイを施して、搬送ロールにて送ることでエッチング処理して、図２６に示すような厚さ３μｍの粗化面３２を形成した。この粗化面には、スズ置換は行わなかった。
【０１３０】
この粗化面を電子走査顕微鏡（×５０００）にて真上から測定すると、２５μｍ²の範囲に、図４〜８に示すような錨状部１が平均１１個、窪み部が平均１１個、稜線が平均２２本確認された。
【０１３１】
(18)一方、ＤＭＤＧに溶解させた60重量％のクレゾールノボラック型エポキシ樹脂（日本化薬製）のエポキシ基50％をアクリル化した感光性付与のオリゴマー（分子量4000）を 46.67ｇ、メチルエチルケトンに溶解させた80重量％のビスフェノールＡ型エポキシ樹脂（油化シェル製、エピコート1001）15.0ｇ、イミダゾール硬化剤（四国化成製、2E4MZ-CN）1.6 ｇ、感光性モノマーである多価アクリルモノマー（日本化薬製、Ｒ604 ）３ｇ、同じく多価アクリルモノマー（共栄社化学製、DPE6A ） 1.5ｇ、分散系消泡剤（サンノプコ社製、Ｓ−65）0.71ｇを混合し、更に、この混合物に対して光開始剤としてのベンゾフェノン（関東化学製）を２ｇ、光増感剤としてのミヒラーケトン（関東化学製）を 0.2ｇ加えて、粘度を25℃で 2.0Pa・ｓに調整したソルダーレジスト用組成物を得た。なお、粘度測定は、Ｂ型粘度計（東京計器、 DVL-B型）で 60rpmの場合はローターNo.4、６rpm の場合はローターNo.3によった。
【０１３２】
(19)前記(16)で得られた多層配線基板の両面に、図２７に示すようにして、このソルダーレジスト用組成物３３を20μｍの厚さで塗布した。次いで、70℃で20分間、70℃で30分間の乾燥処理を行った後、図２８に示すように、円パターン（マスクパターン）３４が描画された厚さ５mmのフォトマスクフィルム３５を密着させて載置し、1000mJ／cm²の紫外線で露光し、DMTG現像処理した。そして、更に、80℃で１時間、 100℃で１時間、 120℃で１時間、 150℃で３時間の条件で加熱処理し、図２９に示すように、はんだパッド部分３６（バイアホールとそのランド部分３７を含む）を開口した（開口径 200μｍ）ソルダーレジスト層（厚み20μｍ）３８を形成し、プリント配線板３９を製造した。
【０１３３】
(20)次に、ソルダーレジスト層３８を形成した基板３９を、塩化ニッケル30ｇ／Ｌ、次亜リン酸ナトリウム10ｇ／Ｌ、クエン酸ナトリウム10ｇ／ＬからなるｐＨ＝５の無電解ニッケルめっき液に20分間浸漬して、図３０に示すように、開口部３６，３７に厚さ５μｍのニッケルめっき層４０を形成した。更に、その基板を、シアン化金カリウム２ｇ／Ｌ、塩化アンモニウム75ｇ／Ｌ、クエン酸ナトリウム50ｇ／Ｌ、次亜リン酸ナトリウム10ｇ／Ｌからなる無電解金めっき液に93℃の条件で23秒間浸漬して、ニッケルめっき層４０上に厚さ0.03μｍの金めっき層４１を形成した。
【０１３４】
(21)そして、ソルダーレジスト層３８の開口部に、はんだペーストを印刷して 200℃でリフローすることによりはんだバンプ（はんだ体）４２を形成し、はんだバンプ４２を有するプリント配線板４３を製造した。なお、このプリント配線板では、通常配線（７５μｍ線幅）と微細配線（５０μｍ線幅）の部分を設け、微細配線の部分では、更に、配線密度が疎（４００μｍ間隔）の部分と配線密度が密（５０μｍ間隔）の部分を設けた。
【０１３５】
実施例２
図３１は、この例のプリント配線板の断面図である。この例では、基本的には実施例１と同様であるが、工程(17)において、表層の導体回路（はんだパッド用導体回路）の粗化面を、図９〜図１２に示すような金属層５１で被覆した。金属としてはニッケルを用い、被覆には、無電解めっきを用いた。得られたニッケル層の厚さは、０．０４μｍであった。
【０１３６】
また、この例では、工程(18)〜(21)によって、ソルダーレジスト層３８の開口部に、図３１に示すような、ニッケル層５１上のニッケルめっき層５２と、その上の金めっき層５３とを介して、はんだバンプ（はんだ体）５４を形成した。
【０１３７】
実施例３
基本的に実施例２と同様であるが、はんだパッド用導体回路の粗化面を被覆する金属層として、無電解めっきによるニッケル層の代わりに、置換めっきによるスズ層を用いた。このスズ層の厚さは、０．０３μｍであった。
【０１３８】
実施例４
基本的に実施例２と同様であるが、はんだパッド用導体回路の粗化面を被覆する金属層として、無電解めっきによるニッケル層の代わりに、無電解めっきによる亜鉛層を用いた。この亜鉛層の厚さは、０．０５μｍであった。
【０１３９】
実施例５
基本的に実施例２と同様であるが、はんだパッド用導体回路の粗化面を被覆する金属層として、無電解めっきによるニッケル層の代わりに、蒸着による金属層を用いた。この金属層は、鉄及びコバルトからなり、０．０５μｍの厚さを有していた。
【０１４０】
比較例１及び２
基本的に実施例１と同様であるが、比較例１では、表層の導体回路に、酸化浴（黒化浴）として、NaOH（10ｇ／Ｌ）、NaClＯ₂（40ｇ／Ｌ）、Na₃PO₄（６ｇ／Ｌ）を用い、還元浴として、NaOH（10ｇ／Ｌ）、NaBH₄（６ｇ／Ｌ）を用いた黒化−還元処理にて粗化面を形成させた。また、比較例２は、表層の導体回路に、硫酸銅３．２×１０^−２モル／Ｌ、硫酸ニッケル３．９×１０^−３モル／Ｌ、錯化剤５．４×１０^−２モル／Ｌ、次亜リン酸ナトリウム３．３×１０^−１モル／Ｌ、界面活性剤（日信化学工業製、サーフィール４６５）１．１×１０^−４モル／Ｌ、ｐＨ＝９からなる無電解めっき液より銅−ニッケル−リンからなる針状合金によって粗化層を形成させた。比較例１及び２のプリント配線板においても、実施例１と同様の通常配線と微細配線の部分、配線密度が疎の部分と配線密度が密の部分を設けた。
【０１４１】
比較例３
基本的に実施例２と同様であるが、表層の導体回路に、酸化浴（黒化浴）として、NaOH（10ｇ／Ｌ）、NaClＯ₂（40ｇ／Ｌ）、Na₃PO₄（６ｇ／Ｌ）を用い、還元浴として、NaOH（10ｇ／Ｌ）、NaBH₄ （６ｇ／Ｌ）を用いた黒化−還元処理にて粗化面を形成させた。この例のプリント配線板においても、実施例１と同様の通常配線と微細配線の部分、配線密度が疎の部分と配線密度が密の部分とを設けた。
【０１４２】
比較例４
基本的に実施例２と同様であるが、表層の導体回路に、硫酸銅３．２×１０^−２モル／Ｌ、硫酸ニッケル３．９×１０^−３モル／Ｌ、錯化剤５．４×１０^−２モル／Ｌ、次亜リン酸ナトリウム３．３×１０^−１モル／Ｌ、界面活性剤（日信化学工業製、サーフィール４６５）１．１×１０^−４モル／Ｌ、ｐＨ＝９からなる無電解めっき液より銅−ニッケル−リンからなる針状合金によって粗化層を形成させた。この例のプリント配線板においても、実施例１と同様の通常配線と微細配線の部分、配線密度が疎の部分と配線密度が密の部分とを設けた。
【０１４３】
ソルダーレジスト層の剥がれ試験
実施例１、比較例１及び２で製造したプリント基板について、ソルダーレジスト層形成後と信頼性試験（ヒートサイクル条件）後に、ソルダーレジスト層の剥がれを試験した。なお、導体回路間の接続不良の有無を、配線密度が疎と密の部分で比較し、開口部底部の有機残さの残りを確認した。結果を表１に示す。
【０１４４】
【表１】

【０１４５】
表１に示すように、実施例１のプリント配線板では、レジスト層の剥がれや、導体回路の接続不良の発生がなく、有機残さの残りも発見されなかった。比較例１のプリント配線板では、ヒートサイクル後に配線密度が疎の部分で剥がれが発生し、比較例２のプリント配線板では、導体回路の接続不良が発生し、開口部底部に有機残さ残りが確認された。
【０１４６】
ソルダーレジスト層の剥がれ試験及びはんだバンプの剥がれ試験
実施例２〜５、比較例３及び４で製造したプリント基板について、はんだバンプ形成後と信頼性試験（ヒートサイクル条件）後に、ソルダーレジスト層及びはんだバンプの剥がれ、クラックなどを検査し、はんだバンプのシェアー強度を測定し、また、チェッカーにて導通試験を行い、断線、短絡の有無を判定した。結果を表２に示す。
【０１４７】
【表２】

【０１４８】
表２に示すように、実施例２〜５のプリント配線板は、比較例３及び５の配線板と比べ、いずれも、ソルダーレジスト層及びはんだバンプの剥がれ、クラックがなく、導通試験及びはんだバンプのシェアー強度に優れていた。また、信頼性試験後も、ソルダーレジスト層及びはんだバンプの強度が十分に保て、断線、短絡等が無かった。
【０１４９】
【発明の効果】
上述したように、本発明のプリント配線板では、所定形状の粗化面がはんだパッド用導体回路の表面に形成されており、この粗化面を介してソルダーレジスト層が強固に密着しており、はんだバンプ形成部でソルダーレジスト層が除去されて、導体回路とソルダーレジスト層との接触面積が少なくなった場合や、導体回路が微細配線からなり、配線密度が疎の状態でも、導体回路とソルダーレジスト層との十分な密着性を確保することができる。
【０１５０】
また、本発明のプリント配線板では、はんだバンプ形成用の開口部に露出する粗化面上に、ソルダーレジスト樹脂の残さが残らず、バンプ下金属との密着性に優れ、はんだバンプ形成部に導通不良を引き起こさない。
【０１５１】
さらに、本発明のプリント配線板は、はんだパッド用導体回路の粗化面が金属層で被覆されることによって、ソルダーレジスト層との密着性やバンプ下金属との密着性に優れた形状及び強度が保持されるので、はんだバンプの強度が著しく高まり、はんだバンプの脱落を防止することができる。
【図面の簡単な説明】
【図１】 本発明にかかる一例の粗化面の図面代用写真である。
【図２】 本発明にかかる他の例の粗化面の図面代用写真である。
【図３】 本発明にかかる更に他の例の粗化面の図面代用写真である。
【図４】 本発明にかかる粗化面の摸式図である。
【図５】 本発明にかかる粗化面の摸式図である。
【図６】 本発明にかかる粗化面の摸式図である。
【図７】 本発明にかかる粗化面の摸式図である。
【図８】 本発明にかかる粗化面の摸式図である。
【図９】 本発明にかかる他の粗化面の断面図である。
【図１０】 本発明にかかる他の粗化面の断面図である。
【図１１】 本発明にかかる他の粗化面の断面図である。
【図１２】 本発明にかかる他の粗化面の断面図である。
【図１３】 本発明にかかる一例の多層プリント配線板の製造工程図である。
【図１４】 本発明にかかる一例の多層プリント配線板の製造工程図である。
【図１５】 本発明にかかる一例の多層プリント配線板の製造工程図である。
【図１６】 本発明にかかる一例の多層プリント配線板の製造工程図である。
【図１７】 本発明にかかる一例の多層プリント配線板の製造工程図である。
【図１８】 本発明にかかる一例の多層プリント配線板の製造工程図である。
【図１９】 本発明にかかる一例の多層プリント配線板の製造工程図である。
【図２０】 本発明にかかる一例の多層プリント配線板の製造工程図である。
【図２１】 本発明にかかる一例の多層プリント配線板の製造工程図である。
【図２２】 本発明にかかる一例の多層プリント配線板の製造工程図である。
【図２３】 本発明にかかる一例の多層プリント配線板の製造工程図である。
【図２４】 本発明にかかる一例の多層プリント配線板の製造工程図である。
【図２５】 本発明にかかる一例の多層プリント配線板の製造工程図である。
【図２６】 本発明にかかる一例の多層プリント配線板の製造工程図である。
【図２７】 本発明にかかる一例の多層プリント配線板の製造工程図である。
【図２８】 本発明にかかる一例の多層プリント配線板の製造工程図である。
【図２９】 本発明にかかる一例の多層プリント配線板の製造工程図である。
【図３０】 本発明にかかる一例の多層プリント配線板の製造工程図である。
【図３１】 本発明にかかる他の例の多層プリント配線板の断面図である。
【図３２】 針状合金からなる粗化層の図面代用写真である。
【符号の説明】
１ 錨状部
２ 窪み部
３ 稜線
４ 基板
５ 銅箔
６ 銅張積層板
７ ドリル孔
８ 内層銅パターン（下層導体回路）
９ スルーホール
１０，１０ａ，１１，１１ａ，２３，２４，３２ 粗化面
１２，１５，１８ 配線基板
１３，１４ 樹脂層
１６，１７ 粗化層
１９ 接着剤層
２０，２６ 黒円
２１，３５ フォトマスクフィルム
２２ 開口（バイアホール形成用開口）
２５ 無電解銅めっき膜
２７ 感光性ドライフィルム
２８ めっきレジスト
２９ 電解銅めっき膜
３０ 導体回路
３１ バイアホール
３３ ソルダーレジスト用組成物
３４ 円パターン（マスクパターン）
３６ はんだパッド部分
３７ バイアホールとそのランド部分
３８ ソルダーレジスト層
３９，４３ プリント配線板
４０，５２ ニッケルめっき層
４１，５３ 金めっき層
４２，５４ はんだバンプ（はんだ体）
５１ 金属層[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a printed wiring board, and more particularly to a printed wiring board capable of improving the adhesion between a solder pad conductor circuit and a solder resist layer, the solder pad conductor circuit and a solder bump, and the strength of the solder bump.
[0002]
[Prior art]
In recent years, so-called build-up multilayer wiring boards have attracted attention due to the demand for higher density of multilayer wiring boards. This build-up multilayer wiring board is manufactured, for example, by a method as disclosed in Patent Document 1.
[0003]
[Patent Document 1]
Japanese Patent Publication No. 4-55555
[0004]
According to this method, an insulating material made of a photosensitive electroless plating adhesive is applied onto a core substrate, dried, and then exposed and developed, whereby an interlayer insulating resin layer having a via hole opening is formed. Form. Next, the surface of the interlayer insulating resin layer is roughened by treatment with an oxidizing agent or the like, then a plating resist is provided on the roughened surface, electroless plating is applied to the resist non-forming portion, and two layers including via holes are provided. The conductor circuit pattern is formed. By repeating this process a plurality of times, a multilayered build-up wiring board can be obtained.
[0005]
Such a printed wiring board is provided with solder bumps on the surface layer, and is connected to the IC chip via the solder bumps. In this case, the printed wiring board is provided with a solder resist layer so as to protect the surface solder pad conductor circuit and prevent the solder bumps from being fused to each other.
[0006]
Further, in such a printed wiring board, the surface of the conductor circuit is roughened in order to improve the adhesion between the solder pad conductor circuit and the solder resist layer. For the roughening treatment of the conductor circuit, blackening-reduction treatment, etching with sulfuric acid-hydrogen peroxide, copper-nickel-phosphorus needle alloy plating (see, for example, Patent Document 2), and the like are used.
[0007]
[Patent Document 2]
JP-A-9-130050
[0008]
[Problems to be solved by the invention]
In recent years, a technique using fine wiring has attracted attention as a circuit pattern of a printed wiring board. This is because the conductor circuit can be densified by such fine wiring.
[0009]
However, in the miniaturized conductor circuit, the contact area between the conductor circuit and the solder resist layer is remarkably reduced, and the adhesion between the conductor circuit and the solder resist layer is lowered. In particular, when the conductor circuit is provided in a sparse state on the surface layer of the printed wiring board, the adhesion between the conductor circuit and the solder resist layer is further reduced.
[0010]
The present invention improves the adhesion between the miniaturized conductor circuit and the solder resist layer, and even in the solder bump forming portion, the conductor circuit and the solder resist layer are firmly adhered and do not peel off, and the solder bump forming portion It aims at obtaining the printed wiring board which does not cause a conduction defect.
[0011]
[Means for Solving the Problems]
The present invention comprises a solder pad conductor circuit and a solder resist layer on the solder pad conductor circuit, and in a printed wiring board in which an opening for providing a solder body is formed in the solder resist layer, The solder pad conductor circuit comprises an electroless plating film and an electrolytic plating film, and has a roughened surface treated with an etching solution containing a cupric complex and an organic acid, and the solder resist layer Are related to the printed wiring board provided on the roughened surface.
[0012]
Further, the present invention is a printed wiring board comprising a conductor circuit and a solder resist layer on the conductor circuit, wherein an opening for providing a solder body is formed in the solder resist layer. The electroless plating film and the electroplating film have a roughened surface, and the roughened surface has a plurality of ridges, depressions, and ridges, and the ridges and the depressions. And the ridge line are dispersedly formed, the adjacent ridge portions are connected by the ridge line, the recess portion is surrounded by the ridge portion and the ridge line, and the solder resist layer is formed. The present invention relates to a printed wiring board provided on the roughened surface.
[0013]
  In particular, the present invention includes a solder pad conductor circuit, a solder resist layer on the solder pad conductor circuit, and a solder bump, and an opening for providing a solder body is formed by removing the solder resist layer. The solder bump is provided in the opening, the solder pad conductor circuit comprising an electroless plating film and an electrolytic plating film, and the solder pad conductor circuit line The solder pad conductor circuit has a roughened surface treated with an etching solution containing a cupric complex and an organic acid, and the roughened surface is 0.5 to It has a maximum roughness (Rmax) of 10 μm, the roughened surface has a plurality of ridges, depressions and ridges, and the ridges, depressions and ridges are dispersedly formed. Tena The adjacent ridges are connected by the ridge line, the recess is surrounded by the ridge and the ridge line, and the solder resist layer is provided on the roughened surface. The present invention relates to a multilayer printed wiring board.
  In order to improve the adhesion between the surface layer of the multilayer printed wiring board and the solder resist layer, the present inventor has studied various methods for roughening the surface of the conductor circuit. In particular, the present inventor has responded to the desire to increase the adhesion between the conductor circuit formed of fine wiring of 50 μm or less and the solder resist layer and the strength of the solder bump, blackening-reducing treatment, sulfuric acid-peroxidation. A processing method such as etching with hydrogen and copper-nickel-phosphorus needle-like alloy plating was studied.
[0014]
However, it has been found that blackening-reducing treatment or the like is inappropriate as roughening treatment for fine wiring. In the blackening-reduction treatment and sulfuric acid-hydrogen peroxide etching treatment, when fine wiring of 50 μm or less is used and the wiring density is sparse, the conductor circuit and the solder resist layer are formed by the convex portions formed on the roughened surface. It has been found that the contact area of the solder becomes smaller and the adhesion of the solder resist layer cannot be improved. In particular, under heat cycle conditions, it was found that the wiring density was peeled off at a sparse part. In addition, the metal in the solder pad was also peeled off or cracks were generated, causing the solder bumps to fall off.
[0015]
Moreover, the roughening layer formation by copper-nickel-phosphorus needle-like alloy plating is excellent in the adhesion between the conductor circuit and the solder resist layer, and fine wiring of 50 μm or less, particularly in a sparse part composed of such wiring, It was found that sufficient adhesion was shown. However, since such a roughened layer is formed by plating, when the density of fine wiring is increased, the deposited needle-like alloy stretches on the interlayer insulating layer, connecting the conductor circuits and causing a short circuit. It was.
[0016]
In the formation of a roughened layer by copper-nickel-phosphorus needle-like alloy plating, strict management and control of the plating solution are required to prevent precipitation abnormality due to elongation of the needle-like alloy.
[0017]
Further, the solder resist layer formed from the resin is removed through exposure and development in the solder bump forming portion. At this time, in the roughened layer made of a copper-nickel-phosphorus needle-like alloy, since the needle-like protrusions are densely packed, the gap between the protrusions is narrow, and when the opening is formed, the developer and the resin residue are removed. The oxidant solution may not flow, and the resin may remain between the protrusions, leaving an organic residue of the solder resist resin at the bottom of the opening.
This residue may cause poor conduction between the conductor circuit in the opening and the metal under the bump. In addition, the residue may cause the formation of a noble metal layer in the solder pad and a formation defect, and the strength between the solder pad and the conductor circuit may be reduced.
[0018]
Under such knowledge, the present inventor has eagerly studied other roughening treatments. As a result, the roughened surface formed by treating the surface of the conductor circuit using an etching solution containing a cupric complex and an organic acid has an adhesiveness to the solder resist resin and the metal under the bump. It has been found that it is excellent in adhesion and is extremely suitable for forming solder bumps, and the present invention has been completed.
[0019]
The printed wiring board of the present invention has a roughened surface with a predetermined rough surface shape formed on the conductor circuit as formed by such an etching solution, and a solder resist layer is provided via the roughened surface. It has been. Such a roughened surface can be formed on a conductor circuit having a high wiring density composed of fine wiring of 50 μm or less without causing a conduction failure such as copper-nickel-phosphorus needle-like alloy plating.
[0020]
Also, this roughened surface has excellent adhesion to the solder resist layer, and when the solder resist layer is removed at the solder bump forming part, the contact area between the conductor circuit and the solder resist layer is reduced, or fine wiring Even in a printed wiring board having a sparse wiring density, sufficient adhesion between the conductor circuit and the solder resist layer can be ensured.
[0021]
Furthermore, when the solder resist layer is removed and an opening for forming a solder bump is provided, the roughened surface has less resin residue on the roughened surface, and has excellent adhesion to the metal under the bump. Does not cause poor conduction in the formation.
[0022]
DETAILED DESCRIPTION OF THE INVENTION
The present invention will be described in detail with reference to the drawings.
When the solder pad conductor circuit is processed with the etching solution according to the present invention, the surface thereof becomes a roughened surface having a hook-like portion as shown in FIGS. FIG. 1 is a drawing-substituting photograph of an example of a roughened surface according to the present invention. This photograph is a photograph of the roughened surface taken obliquely under an electron microscope. FIG. 2 is a drawing-substituting photograph of another example of the roughened surface according to the present invention. This photograph was also taken in the same manner as the photograph in FIG. 1, but with a higher magnification. FIG. 3 is a drawing-substituting photograph of a roughened surface of still another example according to the present invention. This photograph was taken from directly above the roughened surface under an electron microscope at the same magnification as in FIG.
[0023]
In the printed wiring board of the present invention, a solder resist layer is provided on the conductor circuit via the roughened surface of the solder pad conductor circuit as shown in the electron micrograph.
[0024]
4 to 8 are schematic views of the roughened surface. 4 is a plan view, FIG. 5 is a longitudinal sectional view taken along line AA in FIG. 4, FIG. 6 is a longitudinal sectional view taken between the bowl-shaped portion and the recessed portion, and FIG. FIG. 8 is a longitudinal sectional view cut between the ridge line and the recessed portion.
[0025]
As shown in FIGS. 4 and 5, the roughened surface according to the present invention has a plurality of ridges 1, a plurality of depressions 2, and a plurality of ridges 3, and the ridges 1 and the depressions 2. And the ridgeline 3 are dispersed. A recess 2 as shown in FIG. 6 is formed between the flange 1 and the adjacent flange 1. Moreover, the hook-shaped part 1 and the adjacent hook-shaped part 1 are mutually connected by the ridgeline 3, as shown in FIG. As shown in FIGS. 6 and 8, the hollow portion 2 is surrounded by the hook-shaped portion 1 and the ridgeline 3.
[0026]
For comparison, FIG. 32 shows a drawing-substituting photograph of a roughened layer made of a conventional acicular alloy formed by plating. In the roughened layer shown in this electron micrograph, the acicular alloys overlap with each other, and a space is formed between the acicular alloys. In such a needle-like alloy structure made of Cu-Ni-P, since the needle-like protrusions are densely packed, the gap between the protrusions is narrow, and the oxidant solution for removing the developer and the resin residue does not flow. Resin remains between the protrusions, causing a resin residue.
[0027]
On the other hand, the rough surface shape according to the present invention has a bowl-shaped part at the highest part, and a depression is formed at the lowest part around the bowl-shaped part. The part is connected by a ridge line that is lower than these bowl-shaped parts and higher than the hollow part, and exhibits a complicated uneven shape. In such a rough surface having a rough surface, the saddle-shaped portion bites into the solder resist layer, and the conductor circuit and the solder resist layer are firmly adhered to each other. Even in the state of, peeling does not occur between the conductor circuit and the solder resist layer. In addition, the roughened surface has excellent affinity with the plating solution, and the plating penetrates into the recesses of the roughened surface and turns around the wrinkled portion of the roughened surface, so that the wrinkled portion bites into the metal under the bump. The adhesion between the conductor circuit and the solder bump is not lowered.
[0028]
Further, on the roughened surface, the ridges are not dense. Moreover, the ridgeline which connects each bowl-shaped part has a shape which does not prevent the flow of resin. For this reason, on this roughened surface, the oxidant solution that removes the developer and the resin residue easily flows between the recesses and the ridges, and the solder resist resin does not easily accumulate. For this reason, the roughened surface concerning this invention does not have the resin residue after image development processing, and is excellent in adhesiveness with a metal under bump.
[0029]
Thus, the roughened surface according to the present invention prevents the resin residue after the development process while maintaining the adhesion between the conductor circuit and the solder resist layer and the adhesion between the conductor circuit and the metal under the bump. It has an optimal shape.
[0030]
The roughened surface according to the present invention can be formed, for example, by dropping the metal crystal particles on the surface of the conductor circuit with an etching solution containing a cupric complex and an organic acid. On the roughened surface, a recess (recess) is formed at a portion where the metal crystal particles are largely dropped. Such a depression can be formed in a shape in which a substantially polyhedral substance derived from metal crystal particles is scraped off. In the present invention, the substantially polyhedral shape refers to a polyhedron such as a trihedron, a tetrahedron, a pentahedron, a hexahedron, or a polyhedron formed by combining two or more of these polyhedrons. Such dents can prevent resin residue after the development process.
[0031]
Further, the ridge portion of the roughened surface can be formed by dropping off the metal crystal particles around the ridge portion. The hook-shaped part formed in this way is composed of angular protrusions, is surrounded by the depressions, and does not overlap each other. The roughened surface having such a complicated uneven shape can prevent the resin residue after the development process while maintaining the adhesion with the solder resist resin and the metal under the bump.
[0032]
Furthermore, a ridgeline can be formed on the roughened surface by dropping off adjacent metal crystal particles. The ridge line connects the hook-shaped portion and the adjacent hook-shaped portion at a position lower than the height of the hook-shaped portion. This ridge line is formed in a branched state by dropping three or more adjacent metal crystal particles. Moreover, this ridgeline can be formed in the pointed state by the adjacent metal crystal particle dropping into a substantially polyhedral shape. Such ridge lines can be formed such that the hook-shaped portions are dispersed, and the hook-shaped portions are surrounded by the recessed portions and the ridge lines. Such a roughened surface has a more complicated uneven shape, and can expand the contact surface with the resin and the metal under the bump to further improve the adhesion, and at the same time prevent the resin residue.
[0033]
Such roughened surface preferably has a maximum roughness (Rmax) of 0.5 to 10 μm. If the thickness is less than 0.5 μm, the adhesion to the solder resist layer and the adhesion to the metal under the bump are remarkably lowered. If the thickness exceeds 10 μm, a resin residue is generated after the development process, and problems such as disconnection are likely to occur.
[0034]
The roughened surface is 25 μm.²It is preferable to have an average of 2 to 100 bowl-shaped portions and an average of 2 to 100 depressions. 25 μm²On average, 2 to 100 bowl-shaped portions prevent resin residue after development while maintaining adhesion between the roughened surface and the solder resist layer and adhesion between the roughened surface and the metal under the bump. Yes, 25μm²The average of 2 to 100 indented portions prevents the crowded portions from congesting, suppresses the generation of the resin residue after the development process, and adheres to the adhesion between the roughened surface and the solder resist layer. The adhesion between the chemical surface and the metal under the bump can be maintained.
[0035]
The ridgeline according to the present invention is 25 μm.²It is desirable to form an average of 3 to 3000 per hit. The number of ridges in this range can complicate the shape of the roughened surface, widen the contact surface with the solder resist layer and the metal under the bump, and improve the adhesion with the solder resist layer, etc. This is because it is easy to remove the rest.
[0036]
In addition, the number of ridges, dents, and ridges was taken using an electron micrograph at a magnification of 5000 times as shown in FIGS. 2 and 3, and the roughened surface was photographed immediately above and obliquely from 45 °, 25 μm.²The area was arbitrarily selected and measured, and the average value was adopted.
[0037]
In the present invention, a metal layer can be coated on the roughened surface. 9 to 12 are cross-sectional views of roughened surfaces of other examples according to the present invention. 9-12, the roughened surface as shown in FIGS. 4-8 is each coat | covered with the metal layer 51. FIG.
[0038]
The metal layer 51 as shown in FIGS. 9 to 12 is a metal that does not easily oxidize or corrode, or a metal that does not impair the adhesiveness to the solder resist resin and the metal under the bump even when the metal itself is oxidized or corroded. Consists of.
[0039]
In addition, the metal layer prevents the formation of oxide film and corrosion film on the roughened surface, and covers the roughened surface while maintaining its shape, and roughens with the solder resist resin and the metal under the bump. The adhesion with the surface is not impaired.
[0040]
Such a metal layer prevents a decrease in adhesion strength between the roughened surface and the solder resist layer and a decrease in adhesion strength between the roughened surface and the metal under the bump due to peeling of the oxide film or corrosion. be able to.
[0041]
In addition, since the metal layer can increase the hardness of the metal constituting the roughened surface, metal breakdown does not occur on the roughened surface, the roughened surface and the solder resist layer, the roughened surface and the metal under the bump Is further prevented.
[0042]
The printed wiring board according to the present invention has a metal layer having a roughened surface, and it is difficult to form an oxide layer or a corrosive layer on the roughened surface. Even if an oxide layer or a corrosive layer is formed, a solder resist resin or Adhesion with the metal under the bump is maintained, and heating does not cause separation between the roughened surface and the solder resist layer or between the roughened surface and the metal under the bump.
[0043]
The metal layer is made of at least one metal selected from the group consisting of titanium, zinc, iron, indium, thallium, cobalt, nickel, tin, lead, bismuth and a noble metal.
[0044]
Such a metal is relatively difficult to oxidize or corrode, or even if the metal itself is oxidized or corroded, it does not lower the adhesion between the solder resist resin and the metal under the bump.
[0045]
In addition, the metal is a metal or noble metal whose ionization tendency is greater than that of copper and is equal to or less than titanium. If the roughened surface is covered with a layer of these metal or noble metal, the solder resist layer is locally roughened. Dissolution of the conductor circuit due to the electrode reaction can be prevented.
[0046]
Examples of the metal that is relatively difficult to oxidize or corrode include non-oxidizing metals such as nickel, tin, cobalt, and noble metals. The noble metal is preferably at least one selected from gold, silver, platinum, and palladium.
[0047]
Examples of the metal that does not deteriorate the adhesion between the metal layer and the solder resist resin even if the metal itself is oxidized or corroded include metals such as titanium, zinc, iron, indium, thallium, lead, and bismuth. it can.
[0048]
Thus, in the present invention, a metal layer of at least one metal selected from the group consisting of titanium, zinc, iron, indium, thallium, cobalt, nickel, tin, lead, bismuth and a noble metal is provided on the roughened surface. By coating, it has an optimal shape to prevent the resin residue after development processing, while the adhesion between the solder pad conductor circuit and the solder resist layer, and between the solder pad conductor circuit and the metal under the bump Adhesion and solder bump strength can be improved.
[0049]
In order to coat the metal layer on the roughened surface, plating (a method selected from electrolytic plating, electroless plating, displacement plating), vapor deposition, electrodeposition, sputtering, and the like can be used.
[0050]
The thickness of the metal layer is preferably 0.01 to 1 μm. In particular, a thickness of 0.03 to 0.5 μm is good. This is because the metal layer having such a thickness can prevent the copper conductor from being oxidized or corroded while maintaining the uneven shape of the roughened surface. When the thickness is less than 0.01 μm, the roughened surface cannot be completely covered. When the thickness exceeds 1 μm, the metal coated between the roughened surfaces may enter, and the unevenness of the roughened surface may be offset. The adhesion between the roughened surface and the solder resist layer and the adhesion between the roughened surface and the metal under the bump may be lowered.
[0051]
A method for forming a roughened surface according to the present invention will be described.
Such a roughened surface can be formed by treating a conductor circuit serving as a solder pad with an etching solution containing a cupric complex and an organic acid. Such an etching solution can dissolve the copper conductor circuit under oxygen coexisting conditions such as spraying and bubbling. It is estimated that the etching proceeds according to the following reaction formula.
[0052]
[Chemical 1]

[Wherein, A represents a complexing agent (acting as a chelating agent), and n represents a coordination number. ]
[0053]
As shown in the above reaction formula, the generated cuprous complex is dissolved by the action of an acid, is combined with oxygen to become a cupric complex, and again contributes to the oxidation of copper.
[0054]
The cupric complex used in the present invention is preferably an azole cupric complex. This type of cupric complex acts as an oxidizing agent that oxidizes metallic copper and the like. As azoles, diazole, triazole, and tetrazole are preferable. Among these, imidazole, 2-methylimidazole, 2-ethylimidazole, 2-ethyl-4-methylimidazole, 2-phenylimidazole, 2-undecylimidazole and the like are preferable. The addition amount of the cupric complex of azoles is preferably 1 to 15% by weight. It is because it is excellent in solubility and stability.
[0055]
The organic acid is blended with the cupric complex in order to dissolve the copper oxide. When using cupric complexes of azoles, the organic acids are formic acid, acetic acid, propionic acid, butyric acid, valeric acid, caproic acid, acrylic acid, crotonic acid, oxalic acid, malonic acid, succinic acid, glutaric acid, At least one selected from the group consisting of maleic acid, benzoic acid, glycolic acid, lactic acid, malic acid, and sulfamic acid is preferable. The content of the organic acid is preferably 0.1 to 30% by weight. This is to maintain the solubility of oxidized copper and to ensure dissolution stability.
[0056]
In the etching solution according to the present invention, halogen ions such as fluorine ions, chlorine ions and bromine ions may be added in order to assist the dissolution of copper and the oxidizing action of azoles. Such halogen ions can be supplied as hydrochloric acid, sodium chloride or the like. The addition amount of halogen ions is preferably 0.01 to 20% by weight. This is because the adhesion between the roughened surface formed and the solder resist layer is excellent.
[0057]
The etching solution according to the present invention can be prepared by dissolving a cupric complex of an azole and an organic acid (halogen ions as necessary) in water. Moreover, a commercially available etching liquid, for example, a product name “MEC Etch Bond” manufactured by MEC Co., Ltd. can be used.
[0058]
The average etching amount with such an etching solution is preferably 0.1 to 10 μm. If the thickness is less than 0.1 μm, the adhesion between the roughened surface and the solder resist layer is lowered. If the thickness exceeds 10 μm, a resin residue is likely to be generated, and disconnection or the like is likely to occur in a fine wiring of 50 μm or less.
[0059]
In this invention, a metal layer can be coat | covered on the roughening surface formed in this way. The metal layer is made of at least one metal selected from the group consisting of titanium, zinc, iron, indium, thallium, cobalt, nickel, tin, lead, bismuth, and a noble metal. The coating of the metal layer can be performed by any of plating, vapor deposition, electrodeposition, and sputtering. In terms of the uniformity of the film to be formed, it is preferable to carry out by plating.
[0060]
Moreover, in this invention, in order to form this metal layer uniformly, after forming a roughened surface, the metal layer can be formed after heat-treating the roughened surface. Due to the heat treatment, the etching solution and its residual components are evaporated, and the surface state of the roughened surface becomes uniform, so that the metal layer is easily formed.
[0061]
The temperature of the heat treatment can be set in various ranges depending on the shape and thickness of the roughened surface, the metal component and thickness of the conductor circuit for solder pads, and the like. In particular, the range of 50 to 250 ° C. is preferable. When the temperature is lower than 50 ° C., the effect of the heat treatment is not observed. When the temperature exceeds 250 ° C., the roughened surface is oxidized, and the formed metal layer becomes non-uniform.
[0062]
In the present invention, a solder resist layer is formed on the roughened surface having a predetermined shape formed as described above. The thickness of the solder resist layer is preferably 5 to 40 μm.
If it is too thin, the solder resist layer will not function as a solder dam, and if it is too thick, it will be difficult to form openings for solder bumps, and it will cause contact with the solder body and cause cracks in the solder body. It is.
[0063]
The solder resist layer can be formed from various resins. For example, it can be formed by curing a bisphenol A type epoxy resin or its acrylate, or a novolac type epoxy resin or its acrylate with an amine-based curing agent or an imidazole curing agent.
[0064]
In particular, when an opening is provided in the solder resist layer to form a solder bump, it is preferable to cure a novolac type epoxy resin or its acrylate with an imidazole curing agent. The solder resist layer made of such a resin has an advantage that lead migration (a phenomenon in which lead ions diffuse in the solder resist layer) is small.
[0065]
In addition, in the case of a resin obtained by curing an acrylate of a novolac type epoxy resin with an imidazole curing agent, it has excellent heat resistance and alkali resistance, and does not deteriorate even at a temperature at which the solder melts (around 200 ° C), like nickel plating or gold plating. Does not decompose with strong basic plating solution. Examples of the acrylate of the novolak type epoxy resin include an epoxy resin obtained by reacting glycidyl ether of phenol novolak or cresol novolak with acrylic acid or methacrylic acid.
[0066]
However, since the solder resist layer formed from the acrylate of a novolac type epoxy resin is made of a resin having a rigid skeleton, it is likely to peel off from the conductor circuit. The roughened surface according to the present invention can advantageously prevent such peeling.
[0067]
It is desirable that the imidazole curing agent is liquid at 25 ° C. This is because uniform mixing is easy if liquid. Examples of such curing agents include 1-benzyl-2-methylimidazole (product name: 1B2MZ), 1-cyanoethyl-2-ethyl-4-methylimidazole (product name: 2E4MZ-CN), 4-methyl-2-ethylimidazole (product name). : 2E4MZ).
[0068]
Such a resin and a curing agent are preferably dissolved in a glycol ether solvent to form a solder resist composition. When a solder resist layer is formed from such a composition, free oxygen is not generated and the copper pad surface is not oxidized. In addition, it is less harmful to the human body.
[0069]
As a glycol ether solvent, the following general formula:
CH_ThreeO- (CH₂CH₂O)_n-CH_Three(N = 1-5)
The solvent represented by these can be used.
[0070]
Particularly preferably, at least one selected from the group consisting of diethylene glycol dimethyl ether (DMDG) and triethylene glycol dimethyl ether (DMTG) is used. These solvents can completely dissolve reaction initiators such as benzophenone and Michler's ketone by heating at about 30 to 50 ° C. The amount of the solvent is preferably 10 to 40% by weight of the solder resist composition.
[0071]
The addition amount of the imidazole curing agent is desirably 1 to 10% by weight with respect to the total solid content of the solder resist composition. This is because uniform mixing is easy if the added amount is within this range.
[0072]
In addition to the above-described solder resist compositions, various antifoaming agents, leveling agents, initiators, photosensitizers, thermosetting to improve heat resistance and base resistance and impart flexibility. A photosensitive resin, a photosensitive monomer for improving resolution, and the like can be added.
[0073]
As a leveling agent, what consists of a polymer of an acrylic ester is good. Further, Irgacure I907 manufactured by Ciba Geigy is preferable as the initiator, and DETX-S manufactured by Nippon Kayaku is preferable as the photosensitizer.
[0074]
A bisphenol type epoxy resin can be used as the thermosetting resin. This bisphenol type epoxy resin includes a bisphenol A type epoxy resin and a bisphenol F type epoxy resin. When the basic resistance is important, the former is required when the viscosity is reduced (when the coating property is important). The latter is better.
[0075]
As the photosensitive monomer, a polyvalent acrylic monomer can be used. This is because the polyvalent acrylic monomer can improve the resolution. For example, polyvalent acrylic monomers such as DPE-6A manufactured by Nippon Kayaku and R-604 manufactured by Kyoeisha Chemical Co., Ltd. can be used.
[0076]
You may add a pigment | dye, a pigment, etc. to this solder resist composition. This is because the wiring pattern can be concealed. As such a dye, phthalocyanine green is desirably used.
[0077]
The solder resist composition should have a viscosity of 0.5 to 10 Pa · s, more preferably 1 to 10 Pa · s at 25 ° C. This is because it is easy to apply with a roll coater.
[0078]
An opening can be formed in the solder resist layer made of such a composition by exposure and development.
[0079]
Next, a method for producing the printed wiring board of the present invention will be described. The following method is mainly based on the semi-additive method, but the full additive method may be adopted.
[0080]
In the present invention, a wiring board is produced in which a conductor circuit to be a solder pad is formed on the surface of the board. As the substrate, a glass epoxy substrate, a polyimide substrate, a resin insulating substrate such as a bismaleimide-triazine resin substrate, a ceramic substrate, a metal substrate, or the like can be used.
[0081]
Such a wiring board may be a multilayer printed wiring board having a plurality of layers of conductor circuits formed therein. As a method for forming such a multi-layer conductor circuit, for example, an adhesive layer made of an electroless plating adhesive is formed as an interlayer insulating resin layer on a lower conductor circuit provided on a substrate, and this adhesion is performed. The surface of the agent layer is roughened to form a roughened surface, and the entire roughened surface is subjected to thin electroless plating, a plating resist is formed, and a thick electrolytic plating is applied to a portion where the plating resist is not formed. There is a method in which a resist is removed and an etching process is performed to form a two-layer conductor circuit composed of an electrolytic plating film and an electroless plating film. The conductor circuit is preferably a copper pattern.
[0082]
The most suitable electroless plating adhesive is one in which cured heat-resistant resin particles that are soluble in acids and oxidants are dispersed in an uncured heat-resistant resin that is hardly soluble in acids and oxidants. . This is because such heat-resistant resin particles are dissolved and removed by treatment with an acid or an oxidant to form a roughened surface composed of crucible-shaped anchors on the surface. Such an electroless plating adhesive may be composed of two layers having different compositions.
[0083]
The heat-resistant resin particles that are cured in acid and oxidant are agglomerated (1) heat-resistant resin powder having an average particle size of 10 μm or less and (2) a heat-resistant resin powder having an average particle size of 2 μm or less. Agglomerated particles, (3) a mixture of heat-resistant resin powder having an average particle diameter of 2 to 10 μm and heat-resistant resin powder having an average particle diameter of less than 2 μm, (4) heat-resistant resin powder having an average particle diameter of 2 to 10 μm Pseudo-particles in which at least one of a heat-resistant resin powder having an average particle size of 2 μm or less and an inorganic powder are adhered to the surface of the material, and (5) a heat-resistant resin powder having an average particle size of 0.1-0.8 μm and the average A mixture with a heat-resistant resin powder having a particle size of more than 0.8 μm and less than 2 μm, and (6) at least one particle selected from the group consisting of heat-resistant resin powders having an average particle size of 0.1 to 1.0 μm It is desirable to use it. This is because they form more complex anchors. The roughened surface obtained with these particles can have a maximum roughness (Rmax) of 0.1 to 20 μm.
[0084]
The mixing ratio of the heat-resistant resin particles is 5 to 50% by weight, preferably 10 to 40% by weight, based on the solid content of the matrix made of the heat-resistant resin. The heat-resistant resin particles may be made of an amino resin (melamine resin, urea resin, guanamine resin, etc.), an epoxy resin, or the like.
[0085]
The uncured heat-resistant resin that is hardly soluble in an acid or an oxidizing agent is preferably composed of a resin composite of a thermosetting resin and a thermoplastic resin, or a resin composite of a photosensitive resin and a thermoplastic resin. This is because the former has high heat resistance, and the latter can form a via hole opening by photolithography.
[0086]
As such a thermosetting resin, an epoxy resin, a phenol resin, a polyimide resin, or the like can be used. In the case of sensitization, the thermosetting group is acrylated with methacrylic acid or acrylic acid. In particular, acrylates of epoxy resins are optimal. As the epoxy resin, a novolak type epoxy resin such as a phenol novolak type or a cresol novolak type, a dicyclopentadiene-modified alicyclic epoxy resin, or the like can be used.
[0087]
As the thermoplastic resin, polyether sulfone (PES), polysulfone (PSF), polyphenylene sulfone (PPS), polyphenylene sulfide (PPES), polyphenyl ether (PPE), polyetherimide (PI), or the like can be used. .
[0088]
The mixing ratio of the thermosetting resin (photosensitive resin) and the thermoplastic resin is preferably thermosetting resin (photosensitive resin) / thermoplastic resin = 95/5 to 50/50. This is because high physical property values can be obtained without impairing heat resistance.
[0089]
Next, the adhesive for electroless plating is cured to form an interlayer insulating resin layer, and an opening for forming a via hole can be provided in the interlayer resin resin layer.
[0090]
When the resin matrix of the adhesive for electroless plating is a thermosetting resin, the opening for forming the via hole is perforated using laser light, oxygen plasma, or the like. And drill. In addition, after the exposure and development treatment, after placing a photomask (a glass substrate is preferable) on which a circular pattern is drawn for via hole formation so that the circular pattern side is in close contact with the photosensitive interlayer resin insulating layer, Exposure and development processing.
[0091]
Next, the surface of the interlayer resin insulation layer (adhesive layer for electroless plating) provided with via hole formation openings is roughened. In particular, the surface of the adhesive layer is roughened by dissolving and removing the heat-resistant resin particles present on the surface of the electroless plating adhesive layer with an acid or an oxidizing agent. At this time, a roughened surface is formed in the interlayer resin insulation layer.
[0092]
As the acid, inorganic acids such as phosphoric acid, hydrochloric acid and sulfuric acid, or organic acids such as formic acid and acetic acid can be used. In particular, it is desirable to use an organic acid. This is because when the roughening treatment is performed, the metal conductor layer exposed from the via hole is hardly corroded. As the oxidizing agent, it is desirable to use chromic acid or permanganate (such as potassium permanganate).
[0093]
Such roughened surface preferably has a maximum roughness (Rmax) of 0.1 to 20 μm. This is because if the layer is too thick, the layer itself is easily damaged and peeled off, and if it is too thin, the adhesion is lowered. Particularly, in the semi-additive method, 0.1 to 5 μm is preferable. This is because the electroless plating film is removed while ensuring adhesion.
[0094]
Next, a catalyst nucleus is provided on the roughened interlayer resin insulation layer, and a thin electroless plating film is formed on the entire surface. The electroless plating film is preferably electroless copper plating and has a thickness of 1 to 5 μm, more preferably 2 to 3 μm. In addition, as an electroless copper plating solution, the thing of the liquid composition employ | adopted by a conventional method can be used. For example, a liquid composition composed of copper sulfate: 10 g / L, EDTA: 50 g / L, sodium hydroxide: 8 g / L, 37% formaldehyde: 10 mL is preferable.
[0095]
Next, a photosensitive resin film (dry film) is laminated on the electroless plating film thus formed, and a photomask (a glass substrate is preferable) in which a plating resist pattern is drawn on the photosensitive resin film. Are placed in close contact with each other, exposed, and developed to form a non-conductor portion provided with a plating resist pattern.
[0096]
Next, an electrolytic plating film is formed in addition to the non-conductor portion on the electroless copper plating film, and a conductor portion serving as a conductor circuit and a via hole is provided. As the electrolytic plating, it is desirable to use electrolytic copper plating, and the thickness is preferably 5 to 20 μm.
[0097]
Next, after removing the plating resist from the non-conductor circuit part, electrolessly with a mixed solution of sulfuric acid and hydrogen peroxide or an etching solution such as sodium persulfate, ammonium persulfate, ferric chloride, cupric chloride, etc. The plating film is removed to obtain an independent conductor circuit and via hole composed of two layers of an electroless plating film and an electrolytic plating film. The catalyst nuclei on the roughened surface exposed in the non-conductor portion are dissolved and removed with a mixed solution of chromic acid, sulfuric acid and hydrogen peroxide, or the like.
[0098]
Next, the roughened surface according to the present invention is formed on the conductor circuit to be the surface solder pad. The roughened surface is formed by spraying an etching solution composed of an aqueous solution of the above-described azole cupric complex and an organic acid on the surface of the conductor circuit, or immersing the conductor circuit in the etching solution and bubbling. Can do. The conductor circuit is preferably an electroless plating film or an electrolytic plating film. This is because it is difficult to form a roughened surface in a conductor circuit obtained by etching a thick rolled copper foil.
[0099]
The roughened surface thus formed can then be further processed by etching, polishing, oxidation, oxidation-reduction, or the like, and can be covered with a plating film.
[0100]
The roughened surface can be covered with a metal layer made of at least one metal selected from the group consisting of titanium, zinc, iron, indium, thallium, cobalt, nickel, tin, lead, bismuth and noble metals. . The coating method can be performed by plating (a method selected from electrolytic plating, electroless plating, and displacement plating), vapor deposition, electrodeposition, sputtering, and the like.
[0101]
A solder resist layer as described above can be formed on a conductor circuit having a roughened surface subjected to such treatment.
[0102]
【Example】
The present invention will be described based on examples and comparative examples with reference to the drawings.
Example 1
Raw material composition for preparing electroless plating adhesive (upper layer adhesive)
[Resin composition A]
35 parts by weight of a resin solution prepared by dissolving 25% acrylate of cresol novolac type epoxy resin (manufactured by Nippon Kayaku Co., Ltd., molecular weight 2500) in DMDG at a concentration of 80 wt%, photosensitive monomer (Aronix M315, manufactured by Toagosei Co., Ltd.) 3.15 wt. Part, 0.5 part by weight of antifoaming agent (manufactured by San Nopco, S-65) and 3.6 parts by weight of NMP were obtained by stirring and mixing.
[0103]
[Resin composition B]
After mixing 12 parts by weight of polyethersulfone (PES), 7.2 parts by weight of epoxy resin particles (manufactured by Sanyo Kasei, polymer pole) with an average particle diameter of 1.0 μm, and 3.09 parts by weight with an average particle diameter of 0.5 μm, Further, 30 parts by weight of NMP was added and obtained by stirring and mixing with a bead mill.
[0104]
[Curing agent composition C]
Imidazole curing agent (Shikoku Chemicals, 2E4MZ-CN) 2 parts by weight, Photoinitiator (Ciba Geigy, Irgacure I-907) 2 parts, Photosensitizer (Nippon Kayaku, DETX-S) 0.2 parts by weight, It was obtained by stirring and mixing 1.5 parts by weight of NMP.
[0105]
Raw material composition for preparing interlayer resin insulation (adhesive for lower layer)
[Resin composition D]
35 parts by weight of a resin solution prepared by dissolving 25% acrylate of cresol novolak type epoxy resin (manufactured by Nippon Kayaku Co., Ltd., molecular weight 2500) in DMDG at a concentration of 80 wt%, photosensitive resin (Aronix M315, manufactured by Toagosei Co., Ltd.) Part, 0.5 part by weight of antifoaming agent (manufactured by San Nopco, S-65) and 3.6 parts by weight of NMP were obtained by stirring and mixing.
[0106]
[Resin composition E]
After mixing 12 parts by weight of polyethersulfone (PES) and 14.49 parts by weight of epoxy resin particles (manufactured by Sanyo Kasei, polymer pole) with an average particle size of 0.5 μm, add 30 parts by weight of NMP, and stir and mix in a bead mill. I got it.
[0107]
[Curing agent composition F]
Imidazole curing agent (Shikoku Chemicals, 2E4MZ-CN) 2 parts by weight, Photoinitiator (Ciba Geigy, Irgacure I-907) 2 parts, Photosensitizer (Nippon Kayaku, DETX-S) 0.2 parts by weight, It was obtained by stirring and mixing 1.5 parts by weight of NMP.
[0108]
Raw material composition for resin filler preparation
[Resin composition G]
Bisphenol F type epoxy monomer (Oilized shell, molecular weight 310, YL983U) 100 parts by weight, surface coated with silane coupling agent, average particle diameter 1.6μm SiO₂Spherical particles (manufactured by Admatech, CRS 1101-CE, where the maximum particle size is not more than the thickness of the inner layer copper pattern (15 μm) described later) 170 parts by weight, leveling agent (San Nopco, Perenol S4) 1.5 parts by weight By stirring and mixing, the viscosity of the mixture was adjusted to 45,000 to 49,000 cps at 23 ± 1 ° C.
[0109]
[Curing agent composition H]
6.5 parts by weight of imidazole curing agent (Shikoku Chemicals, 2E4MZ-CN).
[0110]
Manufacture of printed wiring boards
FIGS. 13 to 30 respectively show longitudinal sectional views in each step of a series of manufacturing steps when manufacturing an example of the printed wiring board according to the present invention.
(1) Starting material is a copper clad laminate 6 having 18 μm copper foil 5 laminated on both sides of a substrate 4 made of glass epoxy resin or BT (bismaleimide triazine) resin having a thickness of 1 mm as shown in FIG. It was.
[0111]
First, as shown in FIG. 14, the copper-clad laminate 6 is drilled with a drill hole 7, subjected to electroless plating treatment, and etched into a pattern to form inner layer copper patterns ( Lower layer conductor circuit) 8 and through hole 9 were formed.
[0112]
(2) The substrate on which the inner layer copper pattern 8 and the through hole 9 are formed is washed with water and dried, and then NaOH (10 g / L), NaClO as an oxidation bath (blackening bath).₂(40g / L), Na_ThreePO_Four(6 g / L), NaOH (10 g / L), NaBH as a reducing bath_FourBy the oxidation-reduction treatment using (6 g / L), the roughened surfaces 10 and 11 were provided on the surfaces of the inner layer copper pattern 8 and the through hole 9, and the wiring board 12 as shown in FIG. 14 was manufactured.
[0113]
(3) The resin composition G and the curing agent composition H are mixed and kneaded to obtain a resin filler, and this resin filler is applied to both surfaces of the substrate 12 using a roll coater within 24 hours after preparation. Thus, the resin layers 13 and 14 were formed by filling between the conductor circuits 8 or in the through holes 9 and drying at 70 ° C. for 20 minutes.
[0114]
(4) The surface of the inner layer copper pattern 8 or the land 11 of the through hole 9 is polished on one side of the substrate after the processing in (3) by belt sander polishing using # 600 belt polishing paper (manufactured by Sankyo Rikagaku). Polishing was performed so that no resin filler remained on the surface, and then buffing was performed to remove scratches caused by the belt sander polishing. Such a series of polishing was similarly performed on the other surface of the substrate.
[0115]
(5) Next, the resin filler is cured by heat treatment at 100 ° C. for 1 hour, 120 ° C. for 3 hours, 150 ° C. for 1 hour, and 180 ° C. for 7 hours. Was made. In this wiring board 15, the surface layer portion of the resin filler filled in the through-holes 9 and the like and the roughened surfaces 10 and 11 on the upper surface of the inner layer conductor circuit 8 are removed, both surfaces of the substrate are smoothed, and the resin layer 13 and the side surface of the inner layer conductor circuit 8 and the land surface of the through hole 9 are firmly adhered to each other through the roughened surfaces 10a and 11a, and the inner wall surface of the through hole 9 and the resin layer 14 form the roughened surface 11a. It is in close contact with each other. That is, by this step, the surfaces of the resin layers 13 and 14 and the surface of the inner layer copper pattern 8 are flush.
[0116]
(6) The printed circuit board 15 on which the conductor circuit is formed is subjected to alkali degreasing and soft etching, and then treated with a catalyst solution composed of paradium chloride and an organic acid to give a Pd catalyst and activate the catalyst. After that, copper sulfate 3.2 × 10^-2Mol / L, nickel sulfate 3.9 × 10^-3Mol / L, sodium citrate 5.4 × 10^-2Mol / L, sodium hypophosphite 3.3 × 10^-1Mol / L, surfactant (manufactured by Nissin Chemical Industry, Surfir 465) 1.1 × 10^-4As shown in FIG. 16, the copper conductor circuit 8 is immersed in an electroless plating solution of mol / L, pH = 9 and vibrated and swung at a rate of once every 4 seconds. The roughened layers 16 and 17 of the needle-like alloy made of Cu—Ni—P were provided on the surface of the land of the through hole 9.
[0117]
Furthermore, a Cu—Sn substitution reaction was performed under the conditions of tin borofluoride 0.1 mol / L, thiourea 1.0 mol / L, temperature 35 ° C., pH = 1.2, and the thickness of the roughened layers 16 and 17 was increased. A 0.3 μm Sn layer was provided. The Sn layer is not particularly shown.
[0118]
(7) Resin compositions D and E and curing agent composition F were mixed by stirring and adjusted to a viscosity of 1.5 Pa · s to obtain an interlayer resin insulation (for the lower layer). Next, the resin compositions A and B and the curing agent composition C were stirred and mixed, and adjusted to a viscosity of 7 Pa · s to obtain an electroless plating adhesive solution (for the upper layer).
[0119]
(8) Apply the interlayer resin insulation (for lower layer) having a viscosity of 1.5 Pa · s obtained in (7) on both surfaces of the substrate 18 in (6) with a roll coater within 24 hours after preparation; Allow to stand for 20 minutes in a horizontal state, then dry (pre-bake) for 30 minutes at 60 ° C, and then apply the photosensitive adhesive solution (for upper layer) with a viscosity of 7 Pa · s obtained in (7) above. Then, it was applied within 24 hours after the preparation, left in a horizontal state for 20 minutes, and then dried (prebaked) at 60 ° C. for 30 minutes to form an adhesive layer 19 having a thickness of 35 μm as shown in FIG. .
[0120]
(9) As shown in FIG. 18, a photomask film 21 on which a black circle 20 of 85 μmφ is printed is adhered to both surfaces of the substrate on which the adhesive layer 19 is formed in the above (8), and 500 mJ / cm²And exposed. This substrate is spray-developed with DMTG solution, and further 3000 mJ / cm with an ultra-high pressure mercury lamp.²Exposure to 100 ° C. for 1 hour, 120 ° C. for 1 hour, and then 150 ° C. for 3 hours (post-baking) to achieve the dimensional accuracy corresponding to the photomask film 21 as shown in FIG. An interlayer resin insulating layer (two-layer structure) 19 having a thickness of 35 μm and having an excellent opening (via hole forming opening) 22 of 85 μmφ was obtained. Note that the tin plating layer was partially exposed in the opening 22 serving as a via hole.
[0121]
(10) The substrate on which the opening 22 is formed is immersed in chromic acid for 19 minutes, and the epoxy resin particles present on the surface of the interlayer resin insulation layer 19 are dissolved and removed to roughen the surface of the interlayer resin insulation layer 19. 20, roughened surfaces 23 and 24 as shown in FIG. 20 were formed, and then immersed in a neutralized solution (manufactured by Shipley Co., Ltd.) and washed with water.
[0122]
Furthermore, by applying a palladium catalyst (manufactured by Atotech) to the surface of the substrate that has been roughened (roughening depth 6 μm), the surface 23 of the interlayer resin insulation layer 19 and the inner wall surface 24 of the via hole opening are formed. A catalyst nucleus was attached.
[0123]
(11) The wiring board thus formed is immersed in an electroless copper plating aqueous solution having the following composition, and an electroless copper plating film having a thickness of 0.6 μm is formed on the entire rough surface as shown in FIG. 25 was formed.

[0124]
(12) On the electroless copper plating film 25 formed in the above (11), as shown in FIG. 22, a commercially available photosensitive dry film 27 printed with a black circle 26 is attached, and a mask is placed. 100 mJ / cm²And developed with 0.8% sodium carbonate to provide a plating resist 28 having a thickness of 15 μm as shown in FIG.
[0125]
(13) Next, electrolytic copper plating was performed on the resist-unformed portion under the following conditions to form an electrolytic copper plating film 29 having a thickness of 15 μm as shown in FIG.

[0126]
(14) After stripping and removing the plating resist 28 with 5% KOH, the electroless plating film 25 under the plating resist 28 is removed by dissolution treatment by etching with a mixed solution of sulfuric acid and hydrogen peroxide. As shown, a conductor circuit 30 (including a via hole 31) having a thickness of 18 μm composed of an electroless copper plating film 25 and an electrolytic copper plating film 29 was formed.
[0127]
(15) The same treatment as in (6) was performed to form a roughened surface made of a Cu—Ni—P needle-like alloy, and Sn substitution was performed on the surface.
[0128]
(16) By repeating the steps (7) to (15), a further upper conductor circuit was formed to obtain a multilayer wiring board.
[0129]
(17) The conductor circuit on the surface layer was sprayed with an etching solution consisting of 10 parts by weight of imidazole copper (II) complex, 7 parts by weight of glycolic acid and 5 parts by weight of potassium chloride, and a trade name “MEC Etch Bond” manufactured by MEC. Then, the roughened surface 32 having a thickness of 3 μm as shown in FIG. This roughened surface was not substituted with tin.
[0130]
When this roughened surface is measured from directly above with an electron scanning microscope (× 5000), it is 25 μm.²In the range, an average of 11 hook-shaped portions 1 as shown in FIGS. 4 to 8, an average of 11 hollow portions, and an average of 22 ridge lines were confirmed.
[0131]
(18) On the other hand, 46.67g of photosensitized oligomer (molecular weight 4000) obtained by acrylating 50% of the epoxy group of 60% by weight cresol novolak type epoxy resin (manufactured by Nippon Kayaku) dissolved in DMDG, dissolved in methyl ethyl ketone. 15.0 g of 80% by weight bisphenol A epoxy resin (manufactured by Yuka Shell, Epicoat 1001), 1.6 g of imidazole curing agent (manufactured by Shikoku Chemicals, 2E4MZ-CN), polyvalent acrylic monomer (Nippon Kasei) 3 g of medicine, R604), 1.5 g of polyacrylic monomer (Kyoeisha Chemical Co., DPE6A), 0.71 g of a dispersion antifoaming agent (Sanopco, S-65) are mixed. Solder Regis with 2 g of benzophenone (manufactured by Kanto Chemical) as an initiator and 0.2 g of Michlerketone (manufactured by Kanto Chemical) as a photosensitizer and adjusted to a viscosity of 2.0 Pa · s at 25 ° C. To obtain a use composition. Viscosity was measured with a B-type viscometer (Tokyo Keiki, DVL-B type) at 60 rpm with rotor No. 4 and at 6 rpm with rotor No. 3.
[0132]
(19) As shown in FIG. 27, this solder resist composition 33 was applied to both surfaces of the multilayer wiring board obtained in (16) to a thickness of 20 μm. Next, after drying at 70 ° C. for 20 minutes and at 70 ° C. for 30 minutes, as shown in FIG. 28, a photomask film 35 having a thickness of 5 mm on which a circular pattern (mask pattern) 34 is drawn is adhered. 1000mJ / cm²Were exposed to UV light and DMTG developed. Further, heat treatment was performed under conditions of 80 ° C. for 1 hour, 100 ° C. for 1 hour, 120 ° C. for 1 hour, and 150 ° C. for 3 hours. As shown in FIG. A solder resist layer (thickness 20 μm) 38 having an opening (including a land portion 37) (opening diameter 200 μm) was formed, and a printed wiring board 39 was manufactured.
[0133]
(20) Next, the substrate 39 on which the solder resist layer 38 is formed is applied to an electroless nickel plating solution having a pH of 5 consisting of nickel chloride 30 g / L, sodium hypophosphite 10 g / L, and sodium citrate 10 g / L. As a result of immersion for 20 minutes, a nickel plating layer 40 having a thickness of 5 μm was formed in the openings 36 and 37 as shown in FIG. Further, the substrate was placed in an electroless gold plating solution composed of potassium gold cyanide 2 g / L, ammonium chloride 75 g / L, sodium citrate 50 g / L, and sodium hypophosphite 10 g / L at 93 ° C. for 23 seconds. A gold plating layer 41 having a thickness of 0.03 μm was formed on the nickel plating layer 40 by dipping.
[0134]
(21) A solder bump (solder body) 42 was formed by printing a solder paste in the opening of the solder resist layer 38 and reflowing at 200 ° C., and a printed wiring board 43 having the solder bump 42 was manufactured. . This printed wiring board is provided with a portion of normal wiring (75 μm line width) and fine wiring (50 μm line width), and in the portion of fine wiring, the wiring density is further reduced compared with a portion having a sparse (400 μm interval) portion. Dense (50 μm intervals) portions were provided.
[0135]
Example 2
FIG. 31 is a cross-sectional view of the printed wiring board of this example. In this example, it is basically the same as in Example 1, but in the step (17), the roughened surface of the surface conductor circuit (solder pad conductor circuit) is made of a metal as shown in FIGS. Coated with layer 51. Nickel was used as the metal, and electroless plating was used as the coating. The thickness of the obtained nickel layer was 0.04 μm.
[0136]
In this example, the nickel plating layer 52 on the nickel layer 51 and the gold plating layer 53 on the nickel layer 51 as shown in FIG. 31 are formed in the openings of the solder resist layer 38 by the steps (18) to (21). Then, a solder bump (solder body) 54 was formed.
[0137]
Example 3
Although basically the same as in Example 2, a tin layer formed by displacement plating was used in place of the nickel layer formed by electroless plating as the metal layer covering the roughened surface of the conductor circuit for solder pads. The tin layer had a thickness of 0.03 μm.
[0138]
Example 4
Although basically the same as in Example 2, a zinc layer formed by electroless plating was used instead of the nickel layer formed by electroless plating as the metal layer covering the roughened surface of the conductor circuit for solder pads. The zinc layer had a thickness of 0.05 μm.
[0139]
Example 5
Although basically the same as in Example 2, a metal layer formed by vapor deposition was used instead of the nickel layer formed by electroless plating as the metal layer covering the roughened surface of the conductor circuit for solder pads. This metal layer was made of iron and cobalt and had a thickness of 0.05 μm.
[0140]
Comparative Examples 1 and 2
Basically the same as in Example 1, but in Comparative Example 1, NaOH (10 g / L), NaClO was used as the oxidation bath (blackening bath) in the conductor circuit on the surface layer.₂(40g / L), Na_ThreePO_Four(6 g / L) and, as a reducing bath, NaOH (10 g / L), NaBH_FourA roughened surface was formed by blackening-reducing treatment using (6 g / L). In Comparative Example 2, copper sulfate of 3.2 × 10 6 was applied to the surface conductor circuit.^-2Mol / L, nickel sulfate 3.9 × 10^-3Mol / L, complexing agent 5.4 × 10^-2Mol / L, sodium hypophosphite 3.3 × 10^-1Mol / L, surfactant (manufactured by Nissin Chemical Industry, Surfir 465) 1.1 × 10^-4A roughened layer was formed from an electroless plating solution consisting of mol / L, pH = 9 with a needle-like alloy consisting of copper-nickel-phosphorus. The printed wiring boards of Comparative Examples 1 and 2 were also provided with the same normal wiring and fine wiring portions as in Example 1, a sparse wiring density portion and a dense wiring density portion.
[0141]
Comparative Example 3
Basically the same as in Example 2, except that the surface conductor circuit has NaOH (10 g / L), NaClO as an oxidation bath (blackening bath).₂(40g / L), Na_ThreePO_Four(6 g / L) and, as a reducing bath, NaOH (10 g / L), NaBH_Four  A roughened surface was formed by blackening-reducing treatment using (6 g / L). Also in the printed wiring board of this example, a portion of normal wiring and fine wiring, a portion having a low wiring density, and a portion having a dense wiring density were provided as in the first embodiment.
[0142]
Comparative Example 4
Basically the same as in Example 2, but copper sulfate 3.2 × 10 6 was applied to the surface conductor circuit.^-2Mol / L, nickel sulfate 3.9 × 10^-3Mol / L, complexing agent 5.4 × 10^-2Mol / L, sodium hypophosphite 3.3 × 10^-1Mol / L, surfactant (manufactured by Nissin Chemical Industry, Surfir 465) 1.1 × 10^-4A roughened layer was formed from an electroless plating solution consisting of mol / L, pH = 9 with a needle-like alloy consisting of copper-nickel-phosphorus. Also in the printed wiring board of this example, a portion of normal wiring and fine wiring, a portion having a low wiring density, and a portion having a dense wiring density were provided as in the first embodiment.
[0143]
Solder resist layer peeling test
About the printed circuit board manufactured in Example 1 and the comparative examples 1 and 2, peeling of the soldering resist layer was tested after soldering resist layer formation and a reliability test (heat cycle conditions). In addition, the presence or absence of the connection failure between conductor circuits was compared in the part where wiring density was sparse and dense, and the remainder of the organic residue of the opening part bottom part was confirmed. The results are shown in Table 1.
[0144]
[Table 1]

[0145]
As shown in Table 1, in the printed wiring board of Example 1, there was no peeling of the resist layer and poor connection of the conductor circuit, and no organic residue was found. In the printed wiring board of the comparative example 1, peeling occurs in the portion where the wiring density is sparse after the heat cycle, and in the printed wiring board of the comparative example 2, the connection failure of the conductor circuit occurs, and the organic residue remains at the bottom of the opening. confirmed.
[0146]
Solder resist layer peeling test and solder bump peeling test
For the printed circuit boards manufactured in Examples 2 to 5 and Comparative Examples 3 and 4, after solder bump formation and reliability test (heat cycle conditions), the solder resist layer and solder bumps were peeled off and cracks were inspected. The shear strength was measured, and a continuity test was performed with a checker to determine the presence or absence of disconnection or short circuit. The results are shown in Table 2.
[0147]
[Table 2]

[0148]
As shown in Table 2, the printed wiring boards of Examples 2 to 5 were not peeled off from the solder resist layer and the solder bumps and cracked as compared with the wiring boards of Comparative Examples 3 and 5, and the continuity test and the solder bumps. The shear strength was excellent. Moreover, even after the reliability test, the strength of the solder resist layer and the solder bump was sufficiently maintained, and there was no disconnection or short circuit.
[0149]
【The invention's effect】
As described above, in the printed wiring board of the present invention, the roughened surface having a predetermined shape is formed on the surface of the conductor circuit for the solder pad, and the solder resist layer is firmly adhered through the roughened surface. Even if the solder resist layer is removed at the solder bump forming part and the contact area between the conductor circuit and the solder resist layer is reduced, or the conductor circuit is composed of fine wiring and the wiring density is sparse, Sufficient adhesion with the solder resist layer can be ensured.
[0150]
In the printed wiring board of the present invention, the solder resist resin residue does not remain on the roughened surface exposed to the opening for forming the solder bump, and it has excellent adhesion to the metal under the bump, so that the solder bump forming portion Does not cause poor continuity.
[0151]
Furthermore, the printed wiring board of the present invention has a shape and strength excellent in adhesion to the solder resist layer and adhesion to the metal under the bump by covering the roughened surface of the solder pad conductor circuit with a metal layer. Therefore, the strength of the solder bump is remarkably increased, and the solder bump can be prevented from falling off.
[Brief description of the drawings]
FIG. 1 is a drawing-substituting photograph of an example of a roughened surface according to the present invention.
FIG. 2 is a drawing-substituting photograph of another example of the roughened surface according to the present invention.
FIG. 3 is a drawing-substituting photograph of a roughened surface of still another example according to the present invention.
FIG. 4 is a schematic diagram of a roughened surface according to the present invention.
FIG. 5 is a schematic diagram of a roughened surface according to the present invention.
FIG. 6 is a schematic diagram of a roughened surface according to the present invention.
FIG. 7 is a schematic diagram of a roughened surface according to the present invention.
FIG. 8 is a schematic diagram of a roughened surface according to the present invention.
FIG. 9 is a cross-sectional view of another roughened surface according to the present invention.
FIG. 10 is a cross-sectional view of another roughened surface according to the present invention.
FIG. 11 is a cross-sectional view of another roughened surface according to the present invention.
FIG. 12 is a cross-sectional view of another roughened surface according to the present invention.
FIG. 13 is a manufacturing process diagram of an example multilayer printed wiring board according to the present invention.
FIG. 14 is a manufacturing process diagram of an example multilayer printed wiring board according to the present invention.
FIG. 15 is a manufacturing process diagram of an example multilayer printed wiring board according to the present invention;
FIG. 16 is a manufacturing process diagram of an example multilayer printed wiring board according to the present invention.
FIG. 17 is a manufacturing process diagram of an example multilayer printed wiring board according to the present invention.
FIG. 18 is a manufacturing process diagram of an example multilayer printed wiring board according to the present invention.
FIG. 19 is a manufacturing process diagram of an example multilayer printed wiring board according to the present invention;
FIG. 20 is a manufacturing process diagram of an example multilayer printed wiring board according to the present invention.
FIG. 21 is a manufacturing process diagram of an example multilayer printed wiring board according to the present invention;
FIG. 22 is a manufacturing process diagram of an example multilayer printed wiring board according to the present invention;
FIG. 23 is a manufacturing process diagram of an example multilayer printed wiring board according to the present invention;
FIG. 24 is a manufacturing process diagram of an example multilayer printed wiring board according to the present invention;
FIG. 25 is a manufacturing process diagram of an example multilayer printed wiring board according to the present invention;
FIG. 26 is a manufacturing process diagram of an example multilayer printed wiring board according to the present invention;
FIG. 27 is a manufacturing process diagram of an example multilayer printed wiring board according to the present invention;
FIG. 28 is a manufacturing process diagram of an example multilayer printed wiring board according to the present invention;
FIG. 29 is a manufacturing process diagram of an example multilayer printed wiring board according to the present invention;
FIG. 30 is a manufacturing process diagram of an example multilayer printed wiring board according to the present invention;
FIG. 31 is a cross-sectional view of another example multilayer printed wiring board according to the present invention.
FIG. 32 is a drawing-substituting photograph of a roughened layer made of an acicular alloy.
[Explanation of symbols]
1 bowl
2 depressions
3 ridgelines
4 Substrate
5 Copper foil
6 Copper-clad laminate
7 Drill holes
8 Inner layer copper pattern (lower conductor circuit)
9 Through hole
10, 10a, 11, 11a, 23, 24, 32 Roughened surface
12, 15, 18 Wiring board
13,14 Resin layer
16, 17 Roughening layer
19 Adhesive layer
20, 26 black circle
21, 35 Photomask film
22 opening (opening for via hole formation)
25 Electroless copper plating film
27 Photosensitive dry film
28 Plating resist
29 Electrolytic copper plating film
30 Conductor circuit
31 Bahia Hall
33 Solder resist composition
34 Circle pattern (mask pattern)
36 Solder pad part
37 Bahiahole and its land
38 Solder resist layer
39, 43 Printed wiring board
40,52 Nickel plating layer
41,53 Gold plating layer
42,54 Solder bump (solder body)
51 metal layer

Claims (9)

A solder pad conductor circuit, a solder resist layer and a solder bump on the solder pad conductor circuit, and an opening for providing a solder body is formed by removing the solder resist layer. Is a multilayer printed wiring board provided in the opening, wherein the solder pad conductor circuit comprises an electroless plating film and an electrolytic plating film, and the solder pad conductor circuit has a line width of 50 μm or less. The solder pad conductor circuit has a roughened surface treated with an etching solution containing a cupric complex and an organic acid, and the roughened surface has a maximum roughness of 0.5 to 10 μm ( Rmax), the roughened surface has a plurality of ridges, depressions, and ridgelines, and the ridges, depressions, and ridgelines are dispersedly formed and adjacent to each other. A hook-shaped part is connected by the ridge line, the hollow part is surrounded by the hook-shaped part and the ridge line, and the solder resist layer is provided on the roughened surface. A multilayer printed wiring board. ^2. The multilayer print according to claim 1 , wherein the roughened surface has an average of 2 to 100 ridges and an average of 2 to 100 depressions per 25 μm ^2. Wiring board.   The multilayer printed wiring board according to claim 2, wherein the recess is formed by etching metal crystal particles.   The multilayer printed wiring board according to claim 2, wherein the hollow portion is bent into a substantially polyhedral shape.   The multilayer printed wiring board according to claim 2, wherein the ridgeline is formed by dropping off adjacent metal crystal particles.   The multilayer printed wiring board according to claim 2, wherein the ridge line is branched.   The multilayer printed wiring board according to claim 2, wherein the ridge line is sharp.   The multilayer printed wiring board according to claim 2, wherein the hook-shaped portion is formed by etching metal crystal particles around the hook-shaped portion.   3. The multilayer printed wiring board according to claim 2, wherein each of the hook-shaped portions is dispersed, and the hook-shaped portion is surrounded by the recess and the ridge line.

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