JP2008198846A - Multilayer wiring board and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a coreless multilayer wiring board and its manufacturing method, wherein an elastic modulus is enhanced, a joint with high reliability relative to a semiconductor chip is materialized, and a ceramic layer is formed on a board in response to a characteristic of a function part. <P>SOLUTION: The coreless multilayer wiring board 20 comprises a resin laminate composed of a lamination of a plurality of build-up resin layers which carry a wiring pattern, respectively, and further have a via plug connected to the wiring pattern. Further, on an upper face of the resin laminate, a first ceramic layer comprising at least a first and second ceramic pattern having a larger elastic modulus than that of the build-up layer is formed, and on a lower face of the resin laminate, a second ceramic layer comprising a third ceramic pattern having a larger elastic modulus than that of the build-up layer is formed. The first ceramic pattern and the second ceramic pattern have a first and second dielectric constant which differ from each other, respectively. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention generally relates to a semiconductor device, and more particularly to a resin material, a multilayer wiring board using the resin material, and a semiconductor device using the multilayer wiring board.

  In today's high-performance semiconductor devices, a resin multilayer substrate is used as a package substrate carrying a semiconductor chip. On the other hand, in recent high-performance semiconductor devices, intense heat is generated in the semiconductor chip, and the semiconductor chip has a larger elastic modulus than that of the resin substrate. Therefore, the resin multilayer substrate carrying the semiconductor chip is caused by thermal stress. Warping is likely to occur. Therefore, when such a semiconductor device is mounted on a circuit board via a solder bump or the like, a large stress is applied to the bump as the semiconductor chip generates heat, and the semiconductor chip and the package substrate or the circuit board between the package substrate and the circuit board. The problem arises that the electrical and mechanical joints are broken or damaged.

  Therefore, in order to suppress such warpage of the package substrate, a resin multilayer substrate having a high elastic modulus in which a core layer reinforced with a glass cloth is disposed at the center of the resin multilayer substrate constituting the package substrate has been conventionally used. Yes.

  On the other hand, in a package substrate having such a thick core layer, the thickness of the substrate increases, the inductance of a signal path such as a via plug formed in the substrate increases, and the transmission speed of an electric signal decreases. Occurs.

Therefore, conventionally, efforts have been made to realize an ultrathin resin multilayer substrate having a thickness of 500 μm or less except for the core layer in the resin multilayer substrate.
JP 2001-168228 A JP 2000-340895 A JP 2001-127389 A

  On the other hand, in circuit boards for high frequency applications, such as distributed constant type elements such as microstrip lines whose characteristic impedance is increased by narrowing the pattern width, and capacitors whose characteristic impedance is reduced by conversely increasing the pattern width. Lumped constant elements are used together.

  FIG. 1 shows an example of a high-frequency module substrate 100 according to the related art of the present invention.

  Referring to FIG. 1, the high-frequency module substrate 100 is configured on a resin substrate 101, a semiconductor chip 102 is flip-chip mounted, and further a spiral inductor 101A and a resistor 101B formed on the resin substrate 101, and a capacitor 101C. And a distributed constant element such as a microstrip line formed by a conductive film 101D formed on the back surface of the resin substrate 100 and a conductive film pattern 101E formed on the top surface of the resin substrate 100. Contains.

  In such a high-frequency module substrate, in the lumped constant element, in the spiral inductor 101A and the resistor 101B, parasitic capacitance is generated via the resin substrate 101 between the back surface of the substrate and the conductive film 101D serving as a ground electrode. Since the characteristics deteriorate, it is desirable that the resin substrate 101 has a small dielectric constant and a large thickness.

  On the other hand, it is desirable that the resin substrate 101 has a large dielectric constant and a small thickness in order to increase the capacitance of the capacitor even in the lumped element. Furthermore, in a distributed constant type element such as a microstrip line, the wavelength can be shortened as the dielectric constant of the resin substrate 101 is increased and the thickness thereof is decreased, so that the high-frequency module substrate can be reduced in size. It can be seen that it is preferable to form the resin substrate 101 with a large dielectric constant and a small thickness.

  As described above, in the high-frequency module substrate, there are conflicting requirements depending on the elements on the substrate, and it has been difficult to reduce the size of the high-frequency module substrate.

  In addition, since the high-frequency module substrate 100 of FIG. 1 is thin, the mechanical strength, more precisely, the elastic modulus of the entire substrate is small. For example, wiring on the semiconductor chip 102 and the resin substrate 101 is caused by deformation of the substrate. There arises a problem that the joint between the pattern and the pattern is easily broken.

  In order to solve this problem, a reinforcing member (stiffener) 100L is provided along the outer periphery of the resin substrate 101 in the configuration of FIG. 1, but only the outer peripheral portion of the substrate 101 can be reinforced by the reinforcing member 100L. It is difficult to ensure sufficient mounting reliability for the semiconductor chip 102 mounted in the substrate inner region.

  FIG. 2 shows an example of a multilayer wiring board 11 having a core according to the related art of the present invention.

Referring to FIG. 2, a core portion 11C in which core layers 11C ₁ and 11C ₂ each having a thickness of 40 to 60 μm obtained by impregnating a glass cloth 11G with resin is provided at the center of the multilayer wiring board 11. On the core portion 11C, build-up insulating films 11A and 11B having a wiring pattern 12 are formed. Also, build-up insulating films 11D and 11E having wiring patterns 12D and 12E are formed under the core portion 11C.

  Further, a through via 12C that penetrates the core portion 11C and connects the wiring layer 12A and the wiring layer 12D is formed.

  Solder resist films 13A and 13B are formed on the outermost buildup insulating films 11B and 11E, respectively. In the solder resist film 13A, an electrode pad 14A and in the solder resist film 13B, respectively. The electrode pad 14B is formed.

  The semiconductor chip 15 is mounted face down on the multilayer wiring board 11 formed in this way, and the electrode bumps 16 of the semiconductor chip 15 are bonded to the corresponding electrode pads 14A. An underfill resin layer 17 is filled between the semiconductor chip 15 and the solder resist film 13A.

  On the back side of the multilayer wiring board 11, solder bumps 18 are formed on the electrode pads 14B in order to mount a semiconductor device comprising the semiconductor chip 15 and the multilayer wiring board 11 on a circuit board.

However, in the multilayer wiring board 11 having such a core portion 11C, the total thickness of the board including the core layers 11C ₁ and 11C ₂ may exceed 500 μm. In such a case, the through via Since the length of the signal path formed by 12C from the electrode pad 14B to the corresponding electrode pad 14A still exceeds 500 μm, the signal transmitted through the long signal path is delayed by the influence of the inductance.

  On the other hand, it is conceivable to remove the core portion 11C as shown in FIG. 3 and reduce the thickness of the multilayer wiring board. However, in a so-called coreless resin board that does not include such a core, the elastic modulus is, for example, the core. The value of 20 GPa when the portion 11C is provided is reduced to about 10 GPa or less, so that the warp or deformation of the substrate described above becomes a serious problem. However, in FIG. 3, the same reference numerals are given to the parts described above, and the description thereof is omitted.

  When the multilayer wiring board carrying the semiconductor chip is warped in this way, a large stress is applied to the joint between the multilayer wiring board and the circuit board on which the semiconductor device having the multilayer wiring board is mounted. The problem of being destroyed or damaged arises.

  In the conventional coreless substrate, in order to suppress such warpage of the substrate, a reinforcing member (stiffener) 10L is provided along the outer peripheral portion. However, even if such a reinforcing member is provided, the warping is performed. Is suppressed only in the outer peripheral portion, and warping or deformation cannot be sufficiently suppressed in most regions of the substrate.

  Further, in a semiconductor device in which a semiconductor chip is mounted on such a multilayer wiring board, a decoupling capacitor made of a ceramic capacitor is provided between a power line and a ground pattern to suppress unnecessary electromagnetic radiation. Since it requires heat treatment at a high temperature, it cannot be integrated on a resin substrate, and such a decoupling capacitor requires a capacitance higher than picofarad. For example, it was mounted on the wiring board by a flip chip method. However, in such a configuration, even if the thickness of the multilayer wiring substrate is reduced by using the folded coreless resin substrate, the effect is offset. In addition, when such an external decoupling capacitor is used, it is necessary to provide wiring for that purpose, but the problem of unnecessary radiation of electromagnetic waves from such wiring cannot be avoided.

  As described above, in the high-frequency module substrate, the request for reducing the parasitic capacitance component of the lumped-constant element and the request for reducing the size of the distributed-constant element are contradictory, and conventionally, these cannot be solved simultaneously.

  Further, in such a high-frequency module substrate carrying a semiconductor chip, since the elastic modulus of the resin substrate is small, the entire substrate is likely to warp, causing a problem in the bonding reliability between the semiconductor chip and the wiring pattern on the resin substrate.

  In addition, when trying to configure a high-frequency module substrate based on a resin substrate, a large-capacity capacitor that is used to suppress unnecessary radiation of electromagnetic waves cannot be integrated in the resin substrate, so a separate capacitor must be used. However, the length of the wiring for that purpose becomes long, and the problem of unnecessary electromagnetic radiation from the wiring has occurred.

  According to one aspect, the present invention is a multilayer wiring board provided with a resin laminate comprising a plurality of build-up resin layers each carrying a wiring pattern and further having a via plug connected to the wiring pattern. Furthermore, a first ceramic layer made of at least first and second ceramic patterns having an elastic modulus larger than the elastic modulus of the buildup layer is formed on the upper surface of the resin laminate, and the resin laminate A second ceramic layer made of a third ceramic pattern having an elastic modulus larger than that of the buildup layer is formed on the lower surface of the body, and the first ceramic pattern and the second ceramic layer are formed. A multilayer wiring board characterized in that the patterns have first and second dielectric constants different from each other, and the multilayer To provide a semiconductor device having a semiconductor chip mounted on a line on the substrate.

According to another aspect, the present invention provides a method for manufacturing a multilayer wiring board comprising a resin laminate comprising a plurality of build-up resin layers each carrying a wiring pattern and having via plugs connected to the wiring pattern. And forming a first ceramic pattern having an elastic modulus larger than an elastic modulus of the build-up layer in a first region of the upper surface of the resin laminate by an aerosol deposition method; In the second region on the upper surface of the laminate, a second ceramic pattern having a modulus of elasticity larger than that of the buildup layer and having a dielectric constant different from that of the first ceramic pattern, A step of forming by an aerosol deposition method; and a third ceramic having an elastic modulus larger than that of the buildup layer on the lower surface of the resin laminate. The click layer, to provide a method of manufacturing a multilayer wiring board which comprises a step of forming by aerosol deposition.

  According to the present invention, by forming a plurality of ceramic patterns having different dielectric constants in different regions on the resin laminate by the aerosol deposition method, different functional parts are provided on the multilayer wiring board having the resin laminate. Each can be formed in an optimum state.

  Furthermore, according to the present invention, in the multilayer wiring board including the coreless multilayer wiring board provided with the resin laminate including the build-up resin layer having a low elastic modulus by using the aerosol deposition technique, the resin laminate The first and second ceramic layers whose surfaces have a large elastic modulus are reinforced from the upper and lower sides over the entire surface. Therefore, by using such a multilayer wiring board, it becomes possible to mount a semiconductor chip with high reliability. . At that time, by using at least one of the first and second ceramic layers as a capacitor, it is possible to realize a multilayer wiring board in which large-capacity ceramic capacitors are integrated and the mechanical strength is improved. . The first and second ceramic layers, like the conventional solder resist film, prevent the generation of solder bridges, the value of the amount of pick-up of solder, the prevention of contamination of the solder pot, the protection of the board during assembly, and the copper wiring pattern. It functions to prevent oxidation and corrosion, and to prevent electromigration.

  FIG. 4 is a diagram showing a configuration of the semiconductor device 40 according to the first embodiment of the present invention.

  Referring to FIG. 4, the semiconductor device 40 includes a coreless multilayer wiring board 20 and a semiconductor chip 30 flip-chip mounted on the coreless multilayer wiring board 20, and the coreless multilayer wiring board 20 is built up. It is comprised from the resin laminated body 20R which laminated | stacked the insulating films 21, 22, and 23. FIG.

  Here, the build-up insulating film 21 carries a Cu wiring pattern 20a on its lower surface and a Cu wiring pattern 21a on its upper surface, and further, a Cu via plug 21b that electrically connects the Cu wiring pattern 21a and the Cu wiring pattern 20a. Is formed.

  The build-up insulating film 22 carries the Cu wiring pattern 21a on the lower surface and the Cu wiring pattern 22a on the upper surface, and further, a Cu via plug 22b that electrically connects the Cu wiring pattern 22a and the Cu wiring pattern 21a. Is formed.

  Further, the build-up insulating film 23 carries the Cu wiring pattern 22a on the lower surface and the Cu wiring pattern 23a on the upper surface, and further, a Cu via plug 23b that electrically connects the Cu wiring pattern 23a and the Cu wiring pattern 22a. Is formed.

  In the illustrated example, the Cu via plugs 21b, 22b, and 23b have a diameter of 40 μm, and the Cu wiring patterns 21a and 22a form a 30 μm / 30 μm line and space pattern. The uppermost Cu wiring pattern 23 a has a pattern shape corresponding to a functional part formed on the multilayer wiring board 20.

In the semiconductor device 40 of the present embodiment, the resin laminate 20R carries on its lower surface a ceramic layer 20A having an elastic modulus of 100 to 200 GPa, for example 150 GPa, and a thickness of 10 to 50 μm, while its upper surface. In the first region, a high dielectric ceramic layer 20B such as SiTiO ₃ , BaTiO ₃ , (Sr, Ba) TiO ₃ , (Pb, Zr) TiO ₃ , Ta ₂ O ₅ having the same elastic modulus is used. It has a thickness of about 10 to 50 μm. In the illustrated example, the high dielectric ceramic layer 20B forms a microstrip line 20TM together with the Cu pattern 23a below it and the Cu wiring pattern 20E formed thereon.

  In the example shown in the drawing, the same material as that constituting the ceramic layer 20B is used as the ceramic layer 20A, but the ceramic layer 20A formed on the lower surface is usually used as a high elastic modulus material. You can use the materials you have. Examples of such materials include alumina, zirconia, aluminum nitride, cordierite, mullite, titania, quartz, forsterite, wollastonite, anorthite, enstatite, diopsite, akermanite, gehlenite, spinel, garnet, and the like. May include titanates such as magnesium titanate, calcium titanate, strontium titanate and barium titanate. In particular, alumina, zirconia, aluminum nitride, cordierite, mullite, etc. are preferably used from the viewpoints of insulation and strength.

The ceramic layer 20A is formed with an opening 20Ah exposing a part of the Cu wiring pattern 20a, and the Cu wiring pattern 20a exposed through the opening 20Ah forms a pad electrode. Similarly, an opening 20Bh exposing a part of the Cu wiring pattern 23a is formed in the ceramic layer 20B, and the Cu wiring pattern 23a exposed by the opening 20Bh forms a pad electrode. In addition, a capacitor C ₁ using the ceramic layer 20A as a capacitor insulating film is formed on a part of the lower surface.

  Further, the resin laminate 20R has a high Q ceramic layer 20C such as quartz having an elastic modulus of 100 to 200 GPa and a film thickness of about 10 to 50 μm formed in the second region on the upper surface thereof. 20C forms the filter 20f together with the Cu wiring pattern 23a below it and the Cu wiring pattern 20F above it.

Further, in the resin laminate 20R, a low dielectric constant ceramic layer 20D made of quartz, AlN, Al ₂ O ₃ or the like having an elastic modulus of 100 to 200 GPa and a film thickness of about 10 to 50 μm is formed in the third region on the upper surface. On the low dielectric constant ceramic layer 20D, a spiral inductor 20d is formed by a Cu pattern 20G.

  In the multilayer wiring board 20 having such a configuration, the lower surface is substantially entirely covered with the ceramic layer 20A, and the upper surface is substantially entirely covered so that the high dielectric constant ceramic layer 20B, the high Q ceramic layer 20C, The resin laminate 20R is covered with one of the low dielectric constant ceramic layers 20D, and as a result, the resin laminate 20R is reinforced from above and below over the entire surface. That is, the coreless multilayer wiring board 20 exhibits excellent mechanical strength, that is, elastic modulus, as will be described later, although each build-up layer has an elastic modulus of about 2 to 20 GPa at most. .

  In addition, by selecting such a material for the ceramic layer in accordance with the function of the element formed on the substrate 20, a distributed constant type element such as a microstrip line can be reduced in size, or a spiral inductor can be formed. The high-frequency module configured on the multilayer wiring board 20 can be reduced in size.

  In the illustrated example, in order to further increase the effect of using the low dielectric constant ceramic layer 20D, the low power supply ceramic layer 20D is formed with a film thickness larger than that of the high dielectric constant ceramic layer 20B or the high Q ceramic layer 20C. Yes.

  Further, the ceramic layers 20A to 20D formed in this way, like the conventional solder resist film, prevent the generation of solder bridges, reduce the amount of solder pickup, prevent contamination of the solder pot, protect the board during assembly, and copper wiring Functions such as prevention of pattern oxidation and corrosion, and prevention of electromigration can be achieved.

  Further, in the semiconductor device of FIG. 3, a semiconductor chip 30 is flip-chip mounted on the coreless multilayer wiring substrate 20, and a pad electrode (not shown) on the semiconductor chip 20 is connected to the ceramic layer 20 </ b> B via a bump electrode 31. Bonded to the pad electrode 23a exposed in the opening 20Bh formed therein. Further, an underfill resin layer 32 is formed between the coreless multilayer substrate 20 and the semiconductor chip 20.

  FIG. 5 is a plan view showing an example of a pattern formed on the upper surface of the multilayer wiring board 20 in the semiconductor device 40 of FIG. The plan view of FIG. 5 does not completely match the cross-sectional view of FIG.

Referring to FIG. 5, the entire upper surface of the multilayer wiring board 20 is covered with the high dielectric constant ceramic layer 20B, the high Q ceramic layer 20C, and the low dielectric constant ceramic layer 20D substantially without any gap. In the illustrated example, a capacitor Cap and an antenna ANT are formed on the high dielectric constant ceramic layer 20B, a filter F is formed on the high Q ceramic layer 20C, and a spiral is formed on the low dielectric constant ceramic layer D. Inductors L ₁ and L ₂ , a resistor R, and a transmission line TL are formed.

  In the present invention, the characteristic of each functional unit is optimized by forming an optimal ceramic layer on the resin substrate 20R according to the functional unit desired to be formed on the multilayer wiring board 20 in this way. A semiconductor device or a circuit module can be realized.

  Next, the manufacturing process of the semiconductor device 40 of FIGS.

  In the semiconductor device 40 shown in FIGS. 4 and 5, the ceramic layers 20A and 20B are formed on the resin laminate 20R by an aerosol deposition method using an aerosol deposition device 60 shown in FIG.

  Referring to FIG. 6, the aerosol deposition apparatus 60 includes a processing container 61 that is evacuated by a mechanical booster pump 62 and a vacuum pump 62A. In the processing container 61, a substrate to be processed is placed on a stage 61A. W is held by the XY stage drive mechanism 61a and the Z stage drive mechanism 61b so that it can be driven in the XYZ-θ direction.

  A nozzle 61B is provided in the processing container 61 so as to face the substrate W to be processed on the stage 61A, and the nozzle 61B is supplied with an aerosol of ceramic material together with a carrier gas, and this is supplied to the substrate to be processed. The surface of W is sprayed as a jet 61c.

  The ceramic particles constituting the aerosol sprayed in this way preferably have a particle size of 0.5 μm or less, as described above. The surface of the processing substrate W is solidified by impact to form a ceramic film.

  In order to supply the aerosol to the nozzle 61B, the aerosol deposition apparatus 60 of FIG. 4 is provided with a raw material container 63 holding a ceramic powder raw material having a particle size of preferably 0.5 μm or less. A carrier gas such as inert gas or high-purity oxygen is supplied from the high-pressure gas source 64 via the mass flow controller 64A. The raw material container 63 is held on a vibration table 63A in order to promote the generation of aerosol. The raw material container 63 is maintained in a reduced pressure state prior to the film forming step by the mechanical booster pump 62 and the vacuum pump 62A, and the moisture of the ceramic powder raw material is removed.

  Next, a manufacturing process of the semiconductor device 40 of FIGS. 4 and 5 performed using the aerosol deposition apparatus 60 of FIG. 6 will be described.

  Referring to FIG. 7A, first, a Cu wiring pattern 20a is formed on a substrate 70 made of Cu or a Cu alloy, and the first build-up insulating film 21 is formed so as to cover the Cu wiring pattern 20a. Is formed by a vacuum lamination method. For example, as the build-up insulating film 21, a resin insulating film commercially available as trade name TLF-30 from Yodogawa Paper Co., Ltd. can be used.

Further, a via hole corresponding to the plug 21b is formed in the build-up insulating film 21 by a CO ₂ laser, and the entire surface of the build-up insulating film 21 including the via hole is formed by electroless plating of Cu. A layer (not shown) is covered, and a commercially available resist film (not shown) is formed on the Cu seed layer as a trade name FOTEC RY-3229 from Hitachi Chemical Co., Ltd., for example. Further, the resist film is exposed to form an opening corresponding to the via hole, and then the via hole is filled with Cu by electrolytic plating. As a result, the Cu plug 21 b is formed in the buildup insulating film 21.

  Further, a new resist film is formed on the Cu seed layer, patterned according to a desired wiring pattern, and subjected to electrolytic plating, whereby a wiring pattern 21a is formed on the build-up insulating film 21.

  Further, after removing the Cu seed layer interposed between the wiring patterns 21a on the build-up insulating film 21 by etching, the same process is repeated, so that the base 70 is described with reference to FIG. Resin laminate 20R is formed.

  Next, in the steps of FIGS. 7B and 7C, a high elastic modulus material such as ceramics, for example, alumina (product number 160SG-4) manufactured by Showa Denko KK is placed on the resin buildup laminate 20R. Using the position device 60, a film is formed through a screen mask M1 such as a metal mask to form a high elastic modulus material pattern 20B.

  Alternatively, a high elastic modulus material layer is formed on the entire upper surface of the resin laminate 20R by an aerosol deposition method, and then a resist pattern is formed thereon by a photolithography process, and an etching solution suitable for the high elastic modulus material layer May be used for patterning.

  Further, in the step of FIG. 7C, the support member 70 is removed by etching, and in the steps of FIGS. 7D and 7E, the high elastic modulus material layer is formed on the lower surface of the resin buildup laminate 20R. A high elastic modulus material layer 20A similar to the above is formed by an aerosol deposition method using a screen mask M2 such as a metal mask.

  In the next step of FIG. 7F, the counter electrode (upper) electrode of the parallel electrode capacitor Cap is formed on the high elastic modulus material pattern 20B to form a plating seed layer (not shown) and a resist pattern (for example, Hitachi Chemical Co., Ltd.). A Cu wiring pattern is formed by the Cu electroplating method using FOTEC RY-3229) manufactured by Co., Ltd. as a mask, and simultaneously with this. Alternatively, in the step of FIG. 7F, the microstrip line 20TM as shown in FIG. 4 can be formed using the high elastic material pattern 20B.

  In the step shown in FIG. 7F, the electrode and the wiring are formed by depositing a metal material such as Cu fine powder on the high elastic modulus material pattern 20B by an aerosol deposition method. Can also be formed by executing in combination with a screen mask such as a metal mask.

  Next, in the process of FIG. 7G, a ceramic low dielectric constant material film is formed on the Cu wiring pattern 23a on the upper surface of the resin laminate 20R in combination with a screen mask M3 such as a metal mask by an aerosol deposition method. Execute to form a low dielectric constant material pattern 20D. In the step of FIG. 7G, the low dielectric constant material layer may be uniformly formed by an aerosol deposition method and then patterned by a photolithography step.

  Further, in the next step of FIG. 7H, a high dielectric constant / high Q value material such as ceramics is formed on the Cu wiring pattern 23a, and the aerosol deposition apparatus of FIG. 6 is combined with a screen mask M4 such as a metal mask. A high dielectric constant / high Q value material pattern 20C is formed. Alternatively, the pattern 20C may be formed by uniformly forming a high dielectric constant / high Q material layer by an aerosol deposition method and then patterning it by a photolithography process.

  Next, in the step of FIG. 8I, a Cu plating seed layer (not shown) is formed on the low dielectric constant material layer 20D by sputtering or the like, and a resist pattern formed on the Cu plating seed layer. As a mask, the Cu layer is electrolytically plated to form, for example, a spiral inductor 20d which is a lumped element. Alternatively, the Cu wiring pattern can be formed by using a metal material such as Cu fine powder by a aerosol deposition method and using a screen mask such as a metal mask.

  Further, after the low dielectric constant material layer 20D is formed, a Cu plating seed layer (not shown) is formed on the high dielectric constant / high Q value material layer by sputtering or the like, and then formed on the Cu plating seed layer. Using the resist pattern as a mask, Cu electroplating is performed to form, for example, a Cu wiring pattern 20F of the band-pass filter 20f. Also in this case, such a Cu wiring pattern can be formed by depositing a metal material such as Cu fine powder by an aerosol deposition method and in combination with a screen mask such as a metal mask.

When the warpage was measured in the multilayer wiring board thus formed, it was confirmed that the value of the warpage was about 50 μm for a substrate having a side of 4 cm 2. Further, looking at a region having a side of 2 cm on which a semiconductor chip is mounted, the warpage was about 20 μm, and it was confirmed that the semiconductor chip can be mounted without using a stiffener. Further, the total capacitance of the capacitor formed by using alumina having a relative dielectric constant of 10 as the dielectric material as the high elastic modulus material layer has an effective electrode area of 0.0015 m ² and a thickness of the dielectric portion of 10 μm. And was confirmed to have a value of approximately 13 nF.

  Further, a semiconductor chip is actually flip-chip mounted on the multilayer wiring board formed in this manner, and a general underfill resin layer having an elastic modulus of 10 GPa (manufactured by Sumitomo Bakelite Co., Ltd.) is provided between the semiconductor chip and the substrate. CRP-4075S3) was filled, and the thermal cycle test from −10 ° C. to 100 ° C. was repeated 300 times in a state where it was thermally cured at 150 ° C. for 30 minutes. As a result, it was confirmed that even if such a thermal cycle test was performed, defects such as peeling and disconnection did not occur between the semiconductor chip and the resin multilayer substrate.

  Further, after the semiconductor chip was mounted, the warpage of the substrate was measured, and it was confirmed that the warpage of the substrate was 100 μm or less on a substrate having a side of 4 cm, and no chip peeling or via disconnection occurred. It was done.

  The underfill resin layer may or may not have a filler added thereto.

  On the other hand, in the case of the comparative experiment in the configuration of FIG. 4, it is found that the size of warpage increases from 50 μm when the high elastic modulus material layer is not provided to 300 μm in a substrate having a side of 4 cm. It was. Also, in the chip mounting area with a side of 2 cm, the warpage size increased from about 20 μm to about 100 μm, and it was confirmed that semiconductor chip mounting was impossible unless a stiffener was provided. It was.

  In this comparative control experiment, an experiment was performed by suppressing the warpage of the substrate to about 100 μm by providing a SUS stiffener having a thickness of 1 mm around the resin multilayer wiring substrate according to the comparative control under such circumstances. After mounting a semiconductor chip in the same manner using an underfill resin, a thermal cycle test was performed 100 times between −10 ° C. and 100 ° C., and it was confirmed that a break occurred between the substrate and the chip. It was. Further, when the warpage of the substrate was measured in a chip-mounted state, the warpage reached 300 μm, and it was observed that the semiconductor chip was peeled off and the through via was disconnected.

  As described above, according to the present invention, warpage and deformation of the substrate can be effectively suppressed by mechanical reinforcement by the high elastic modulus material layer formed on the outermost surface of the coreless multilayer resin substrate.

  Furthermore, the mechanical reinforcement of the multilayer resin substrate by the high elastic modulus material layer according to the present invention is not limited to the coreless substrate, and even if the substrate having the core material shown in FIG. It is effective for a substrate having warpage and deformation that is a serious problem at μm or less.

  FIG. 8 shows a schematic cross-sectional structure of a ceramic layer formed in the aerosol deposition process of FIGS. 7 (B), (D), (G), and (H).

  Referring to FIG. 8, in such an aerosol deposition process, the supplied fine particles undergo plastic deformation on the substrate due to impact activation, and flat ceramic particles 2 as shown in FIG. The characteristic structure deposited on top can be seen. The ceramic particles 2 have a particle size of about 10 to 0.1 μm and a flatness of about 1/10 to 1/100 (height of 0.1 to 0.01 μm), depending on the particle size of the fine powder of FIG. In the ceramic layer.

  As mentioned above, although this invention was demonstrated about preferable embodiment, this invention is not limited to this specific embodiment, A various deformation | transformation and change are possible within the summary described in the claim.

(Appendix 1)
A multilayer wiring board comprising a resin laminate comprising a plurality of buildup resin layers each carrying a wiring pattern and further having via plugs connected to the wiring pattern,
Furthermore, on the upper surface of the resin laminate, a first ceramic layer made of at least first and second ceramic patterns having an elastic modulus larger than that of the buildup layer is formed,
On the lower surface of the resin laminate, a second ceramic layer made of a third ceramic pattern having an elastic modulus larger than that of the buildup layer is formed,
The multilayer wiring board according to claim 1, wherein the first ceramic pattern and the second ceramic pattern have first and second different dielectric constants, respectively.
(Appendix 2)
The first ceramic pattern has a first thickness, the second ceramic pattern has a second thickness, and the first and second thicknesses are different from each other. 1. The multilayer wiring board according to 1.
(Appendix 3)
The first dielectric constant is smaller than the second dielectric constant, and a region of the multilayer wiring board in which the first ceramic pattern is formed includes at least a transmission line, a spiral inductor, a filter, and a resistor. 1 or 2 wherein at least one of a transmission line, an antenna, a capacitor, and a filter is formed in a region of the multilayer wiring board where the second ceramic pattern is formed. 2. The multilayer wiring board according to 2.
(Appendix 4)
The multilayer wiring board according to any one of appendices 1 to 3, wherein the multilayer wiring board is a coreless multilayer wiring board.
(Appendix 5)
Additional notes 1 to 4, wherein the first ceramic layer substantially covers the entire upper surface of the resin substrate laminate, and the second ceramic layer substantially covers the entire lower surface of the resin laminate. A multilayer wiring board according to any one of the above.
(Appendix 6)
The multilayer wiring board according to any one of appendices 1 to 5, wherein the first and second ceramic layers are formed by an aerosol deposition method.
(Appendix 7)
A semiconductor device comprising the multilayer wiring board according to any one of appendices 1 to 6 and a semiconductor chip flip-chip mounted on the multilayer wiring board.
(Appendix 8)
A method for producing a multilayer wiring board comprising a resin laminate comprising a plurality of build-up resin layers each carrying a wiring pattern and further having via plugs connected to the wiring pattern,
Forming a first ceramic pattern having an elastic modulus larger than an elastic modulus of the buildup layer in a first region of the upper surface of the resin laminate by an aerosol deposition method;
A second ceramic pattern having an elastic modulus larger than the elastic modulus of the build-up layer in the second region on the upper surface of the resin laminate, and having a dielectric constant different from that of the first ceramic pattern Is formed by an aerosol deposition method,
Forming a third ceramic layer having an elastic modulus larger than that of the build-up layer on the lower surface of the resin laminate by an aerosol deposition method. Method.

It is a figure which shows the structure of the semiconductor device provided with the coreless multilayer substrate by the related technique of this invention. It is a figure which shows the structure of the semiconductor device provided with the multilayer wiring board which has a core by the related technique of this invention. It is a figure which shows the structure of the semiconductor device provided with the coreless multilayer wiring board by the related technique of this invention. It is sectional drawing which shows the structure of the semiconductor device provided with the coreless multilayer wiring board by one Embodiment of this invention. FIG. 5 is a plan view showing a part of the semiconductor device of FIG. 4. It is a figure which shows the structure of the aerosol deposition apparatus used by this invention. (A)-(J) are figures which show the manufacturing process of the semiconductor device of FIG. It is the schematic which shows the structure of the ceramic layer obtained by the aerosol deposition method.

Explanation of symbols

1 underlayer 2 ceramic particles 11 multilayer wiring board 11A, 11B, 11D, 11E buildup insulating film 11C core portion 11C _1, 11C ₂ core layer 11G glass cloth 12A, 12B, 12D, 12E wiring layer 12C through vias 13A, 13B solder resist 15 Semiconductor chip 16 Bump 17 Underfill resin layer 20 Coreless multilayer wiring board 20A, 20B, 80A, 80B High elastic ceramic layer 20Ah, 20Bh Opening 20B High dielectric constant ceramic layer 20C High Q ceramic layer 20D Low dielectric constant ceramic layer 20E, 20F, 20G Conductor pattern 20d Spiral inductor 20f Filter 21, 22, 23 Build-up insulating film 20a, 21a, 22a, 23a Cu wiring pattern 21b, 22b, 23b Cu via plug 3 Semiconductor chip 31 Bump 32 Underfill resin layer 40 Semiconductor device 60 Aerosol deposition device 61 Processing container 61A Stage 61B Nozzle 61a XY stage driving mechanism 61b Z stage driving mechanism 61c Jet 62 Mechanical booster pump 63 Raw material container 63A Shaking table 64 High pressure Gas source

Claims (6)

A multilayer wiring board comprising a resin laminate comprising a plurality of buildup resin layers each carrying a wiring pattern and further having via plugs connected to the wiring pattern,
Furthermore, on the upper surface of the resin laminate, a first ceramic layer made of at least first and second ceramic patterns having an elastic modulus larger than that of the buildup layer is formed,
On the lower surface of the resin laminate, a second ceramic layer made of a third ceramic pattern having an elastic modulus larger than that of the buildup layer is formed,
The multilayer wiring board according to claim 1, wherein the first ceramic pattern and the second ceramic pattern have first and second different dielectric constants, respectively.   The first ceramic pattern has a first thickness, the second ceramic pattern has a second thickness, and the first and second thicknesses are different from each other. Item 11. A multilayer wiring board according to Item 1.   The first dielectric constant is smaller than the second dielectric constant, and a region of the multilayer wiring board in which the first ceramic pattern is formed includes at least a transmission line, a spiral inductor, a filter, and a resistor. 2. At least one of a transmission line, an antenna, a capacitor, and a filter is formed in a region of the multilayer wiring board in which the second ceramic pattern is formed. Or the multilayer wiring board of 2.   The multilayer wiring board according to claim 1, wherein the multilayer wiring board is a coreless multilayer wiring board.   The multilayer wiring board according to any one of claims 1 to 4, wherein the first and second ceramic layers are formed by an aerosol deposition method. A method for producing a multilayer wiring board comprising a resin laminate comprising a plurality of build-up resin layers each carrying a wiring pattern and further having via plugs connected to the wiring pattern,
Forming a first ceramic pattern having an elastic modulus larger than an elastic modulus of the buildup layer in a first region of the upper surface of the resin laminate by an aerosol deposition method;
A second ceramic pattern having an elastic modulus larger than the elastic modulus of the build-up layer in the second region on the upper surface of the resin laminate, and having a dielectric constant different from that of the first ceramic pattern Is formed by an aerosol deposition method,
Forming a third ceramic layer having an elastic modulus larger than that of the build-up layer on the lower surface of the resin laminate by an aerosol deposition method. Method.

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