JP4832369B2 - Circuit board, semiconductor device, circuit board manufacturing method, and semiconductor device manufacturing method - Google Patents

Description

  The present invention generally relates to semiconductor devices, and more particularly to a multilayer circuit board using a resin material and a semiconductor device using such a multilayer circuit board.

  In today's high-performance semiconductor devices, a resin multilayer substrate is used as a package substrate carrying a semiconductor chip. On the other hand, in recent high-performance semiconductor devices, intense heat is generated in the semiconductor chip, and the semiconductor chip has a larger elastic modulus than that of the resin substrate. Therefore, the resin multilayer substrate carrying the semiconductor chip is caused by thermal stress. Warping is likely to occur. Therefore, when such a semiconductor device is mounted on a circuit board via a solder bump or the like, a large stress is applied to the bump as the semiconductor chip generates heat, and the semiconductor chip and the package substrate or the circuit board between the package substrate and the circuit board. The problem arises that the electrical and mechanical joints are broken or damaged.

Therefore, in order to suppress such warpage of the package substrate, a resin multilayer substrate having a high elastic modulus in which a core layer reinforced with a glass cloth is disposed at the center of the resin multilayer substrate constituting the package substrate has been conventionally used. Yes.
JP-A-55-011888 JP 2006-1000046 A JP 2004-200614 A

  On the other hand, a package substrate on which a semiconductor chip is mounted is provided with a heat transfer plate or a heat radiating plate in order to efficiently dissipate heat generated from the semiconductor chip to the outside. Such a heat transfer plate or heat radiating plate is generally formed of a metal such as copper or other highly heat conductive material, and is bonded to the back surface or both surfaces of a circuit board on which a semiconductor chip is mounted. Alternatively, the semiconductor chip is directly mounted on a heat transfer plate or a heat sink, or the semiconductor chip is brought into contact with a via (thermal via plug) for heat dissipation, and heat generated from the semiconductor chip is transferred from the thermal via plug. A structure that is absorbed by a hot plate is used. By dissipating the heat absorbed by the heat transfer plate from the heat dissipation plate to the outside, malfunction of the circuit due to thermal runaway of the semiconductor chip and destruction of the circuit itself are prevented, and thermal protection is achieved.

  FIG. 1 shows a configuration of a multilayer wiring board 11 provided with a thermal via plug having a conventional core.

  Referring to FIG. 1, a core portion 11C having a thickness of 40-60 μm obtained by impregnating a glass cloth with a resin is provided at the center of the multilayer wiring board 11, and on the core portion 11C, Build-up insulating films 11A and 11B having wiring patterns 12A and 12B and via plugs 13A and 13B are formed. Under the core portion 11C, build-up insulating films 11D and 11E having wiring patterns 12D and 12E and via plugs 13D and 13E are formed.

  Furthermore, a through via plug 12C that penetrates the core portion 11C and connects the wiring layer 12A and the wiring layer 12D is formed. The via plugs 13A, 13B, 13E, and 13E include a via plug 13T that functions as a thermal via plug.

  Solder resist films 14B and 14E are formed on the outermost buildup insulating films 11B and 11E, respectively. In the solder resist film 14B, an electrode pad 15A and in the solder resist film 14E. The electrode pad 15B is formed.

  The semiconductor chip 16 is mounted face down on the multilayer wiring board 11 formed in this manner, and the electrode bumps 16A of the semiconductor chip 16 are bonded to the corresponding electrode pads 15A. An underfill resin layer 16B is filled between the semiconductor chip 16 and the solder resist film 14B.

  On the back side of the multilayer wiring board 11, solder bumps (not shown) are formed on the electrode pads 15B in order to mount the semiconductor device comprising the semiconductor chip 16 and the multilayer wiring board 11 on the circuit board.

  However, in the multilayer wiring board 11 having such a core portion 11C, the thickness of the entire board including the core layer may exceed 500 μm. In such a case, the length of the through via plug 12C is long. Therefore, the signal transmitted through such a long signal path is delayed by the influence of the inductance. In addition, the length of the heat transfer path formed by the thermal via plug 13T increases, and the heat resistance of the heat transfer path increases. Further, the thermal via plug 13T generally has a via diameter of 100 μm or less, and has a problem of high heat resistance.

  On the other hand, in the configuration of FIG. 1, it is conceivable to remove the core portion 11C and reduce the thickness of the multilayer wiring board. However, when the core portion 11C is removed in this way, the elastic modulus of the entire multilayer wiring board is considered. However, it is reduced from, for example, 20 GPa to about 10 GPa or less, and warping or deformation of the substrate becomes a big problem. When the multilayer wiring board carrying the semiconductor chip 16 is warped in this way, a large stress is applied to the joint between the multilayer wiring board and the circuit board on which the semiconductor device having the multilayer wiring board is mounted. The problem arises that is destroyed or damaged.

  In the conventional coreless substrate, in order to suppress such warpage of the substrate, a reinforcing member (stiffener) 17 shown in FIG. 1 is provided along the outer peripheral portion. Even if it is provided, warpage is suppressed only in the outer peripheral portion, and warpage or deformation cannot be sufficiently suppressed in most regions in the substrate.

  In a multilayer wiring board used for a high frequency module, as shown in FIGS. 2A and 2B, a metal substrate is provided on the back surface of the coreless multilayer wiring board for heat dissipation and mechanical reinforcement. A structure in which contact is made through a via plug has been proposed. However, FIG. 2A is a diagram showing one side of the plan view of the high-frequency module 21, and FIG. 2B is a cross-sectional view of FIG.

  Referring to FIGS. 2A and 2B, the high-frequency module 21 includes an insulating resin layer 22 and conductor patterns 23A and 23B that are formed on the front and back surfaces of the insulating resin layer 22 and constitute microstrip lines. And a metal substrate 25 that functions as a heat radiating member and a mechanical reinforcing member is provided on the back surface of the insulating resin film 22.

  On the front side of the insulating resin layer 22, the semiconductor chip 24 is mounted face-down in contact with the conductor pattern 23 </ b> A by bumps 24 </ b> A. The thermal via plug 23T formed in the insulating resin layer 22 is contacted. The thermal via plug 23T penetrates through the insulating resin layer 22 and is in thermal contact with the metal substrate 25 through the conductor film 23B.

  However, in the case of the configuration of FIGS. 2A and 2B, as described above, the diameter of the thermal via plug 23T is generally 100 μm or less and the thermal resistance is high, so that the efficiency via the thermal via plug 23T is high. For efficient heat dissipation, it is necessary to reduce the film thickness of the insulating resin layer 23. However, when the film thickness of the insulating resin layer 23 is reduced, the withstand voltage is lowered, and stress is generated at the joint due to the difference in thermal expansion between the insulating resin layer 23 and the semiconductor chip 16, and the contact There arises a problem that the reliability of the system is lowered. Furthermore, in the microstrip line, the thickness of the insulating resin layer 23 cannot be reduced arbitrarily.

  By the way, in a semiconductor device for high frequency applications, a semiconductor chip is resin-sealed and an encapsulating resin is metalized for electromagnetic shielding.

  FIG. 3 shows an example in which the semiconductor device having the structure shown in FIG. 1 is applied to a high frequency application. In the configuration shown in FIG. 1, the solder resist layers 14B and 14A are removed, and the build-up insulating film 11B. On top, a sealing resin layer 17 is formed so as to cover the semiconductor chip 16, and a metallization layer 17M is formed on the surface thereof.

  4A and 4B show the configuration of another high-frequency module 21A having a microstrip line. In the configuration of FIG. 4, the configuration of FIG. 2 is mounted in the package body 25, and the upper portion is further formed. The structure is covered with a metal cap 26. However, FIG. 4 (A) is a plan view corresponding to FIG. 2 (A), and shows the high-frequency module 21A with the metal cap 26 removed, whereas FIG. A cross-sectional view of the high-frequency module 21A in a state where the metal cap 26 is provided is shown.

  However, in the high-frequency module shown in FIG. 3, a structure is formed in which a space surrounded by the metallization layer 17M is filled with a dielectric (resin region 17) surrounding the semiconductor chip 16, but internal resonance occurs in the space. In such a case, the semiconductor device cannot operate at a frequency exceeding the resonance frequency. The same applies to the configurations of FIGS. 4A and 4B.

According to one aspect, the present invention is a circuit board comprising a resin laminate in which a plurality of buildup resin layers each carrying a wiring pattern and having via plugs connected to the wiring pattern are laminated, Having first and second ceramic layers formed on the upper and lower surfaces of the resin laminate, each having an elastic modulus greater than that of the build-up layer;
At least one of the first and second ceramic layers has a concavo-convex cross section to provide a circuit board.

According to another aspect, the present invention provides a circuit board comprising a resin laminate in which a plurality of buildup resin layers each carrying a wiring pattern and having via plugs connected to the wiring pattern are laminated, and the circuit board A semiconductor device having a semiconductor chip mounted thereon,
An insulating ceramic layer that covers the circuit board and the semiconductor chip except for external connection terminal portions of the circuit board; and a conductive ceramic layer that covers the insulating ceramic layer;
A semiconductor device is provided.

  According to another aspect, the present invention includes a resin laminate in which a plurality of buildup resin layers each carrying a wiring pattern and having via plugs connected to the wiring pattern are laminated, and the upper surface of the resin laminate and A method of manufacturing a circuit board having first and second ceramic layers having elastic modulus larger than that of the build-up layer on a lower surface, wherein the first and second ceramic layers are formed by an aerosol deposition method. Thus, there is provided a method for manufacturing a circuit board, wherein at least one of the first and second ceramic layers is formed to have a concavo-convex cross section.

  According to another aspect, the present invention provides a circuit board comprising a resin laminate in which a plurality of buildup resin layers each carrying a wiring pattern and having via plugs connected to the wiring pattern are laminated, and the circuit board A semiconductor chip mounted thereon, an insulating ceramic layer covering the circuit board and the semiconductor chip except for an external connection terminal portion of the circuit board, and a conductive ceramic layer covering the insulating ceramic layer. Provided is a method for manufacturing a semiconductor device, wherein the insulating ceramic layer and the conductive ceramic layer are formed by an aerosol deposition method.

  According to the present invention, in a circuit board including a coreless circuit board provided with a resin laminate formed by laminating a build-up resin layer having a low elastic modulus, the surface of the resin laminate is provided by a ceramic layer having a large elastic modulus. By reinforcing the entire surface from above and below and further forming the concavo-convex structure with respect to the substrate plane, the sectional moment of inertia generally increases, so the strength against bending increases. Therefore, according to the present invention, it is possible to mount a semiconductor chip with high reliability by using such a circuit board. Also, high reliability can be realized when a semiconductor device including a circuit board on which such a semiconductor chip is mounted is mounted on a printed circuit board of an electronic device.

  At this time, by forming a concavo-convex structure in the ceramic layer, the surface area of the ceramic layer is increased, and even when a semiconductor chip mounted on the circuit board is operated at a high output, the ceramic layer is interposed. Heat dissipation is promoted.

  The ceramic layer can be formed on the resin laminate by an aerosol deposition method without directly heating from the outside.

  According to the present invention, in the semiconductor device in which the semiconductor chip is mounted on the circuit board made of the resin laminate, the whole is covered with the insulating ceramic layer except for the external connection terminal portion, and the insulating ceramic layer is further electrically conductive. By covering with a conductive ceramic layer, an effective electromagnetic shield can be formed. In this case, according to the present invention, since the conductive ceramic layer is formed close to the semiconductor chip, internal resonance (cavity resonance) is unlikely to occur, and no restriction is imposed on the operation speed of the semiconductor chip.

[First Embodiment]
5A to 5C show a configuration of the semiconductor device 40 according to the first embodiment of the present invention. 5A is a partially cutaway plan view of the semiconductor device 40, FIG. 5B is a longitudinal sectional view of the structure of FIG. 5A, and FIG. A part of a cross-sectional view of the structure is shown.

  Referring to FIGS. 5A to 5C, the semiconductor device 40 is flip-chip mounted on a circuit board 41 made of a resin laminate in which build-up insulating films 41A to 41E are laminated, and the circuit board 41. And a semiconductor chip 44. The build-up insulating films 41A to 41E have Cu wiring patterns 42A to 42E and Cu via plugs 43A to 43E that electrically interconnect the Cu wiring patterns 42A to 42E, respectively. It is formed through the resin laminate. A Cu wiring pattern 45 is formed on the upper surface of the resin laminate, and a similar Cu wiring pattern 46 is also formed on the lower surface of the resin laminate. In the illustrated example, the Cu via plugs 43A to 43E have a diameter of 40 μm, and the Cu wiring patterns 42A to 42E form a line and space pattern of 30 μm / 30 μm.

  On the upper surface of the resin laminate, a ceramic layer 47, 48 having a high elastic modulus and heat conductivity, such as AlN, formed by an aerosol deposition method described later, is a film having a thickness of 10 to 50 μm. It is formed with a thickness. Typically, the ceramic layers 47 and 48 have an elastic modulus of 100 to 200 GPa, for example, 150 GPa. As a result, the resin laminate is reinforced from above and below the entire surface, and the coreless circuit board 41 includes This buildup layer exhibits excellent mechanical strength, that is, elastic modulus, although it has no more than 2 to 20 GPa elastic modulus and no core layer.

  The ceramic layers 47 and 48 are formed with openings that expose portions of the Cu wiring patterns 45 and 46, and the Cu wiring patterns 45 and 46 exposed through the openings form pad electrodes 45P and 46P.

  5A to 5C, the semiconductor chip 44 is flip-chip mounted on the coreless circuit board 41, and pad electrodes (not shown) on the semiconductor chip 44 are bumped. It is joined to the pad electrode 45P through the electrode 44A. Although not shown, an underfill resin layer is formed between the coreless multilayer substrate 41 and the semiconductor chip 44.

  In the semiconductor device 40 of the present embodiment, parallel rib structures 47R and 48R are formed on the ceramic layers 47 and 48, thereby increasing the mechanical strength of the ceramic layers 47 and 48 and at the same time increasing the surface area. In particular, heat dissipation through the ceramic layer 47 is promoted.

  In relation to the heat dissipation through the ceramic layer 47, in the structure of FIGS. 5A to 5C, the Cu wiring pattern 45 is formed on a part of the Cu wiring pattern 45 formed on the upper surface of the resin laminate. A heat spreader region 45H that is wider than other portions is formed. By forming the ceramic layer 47 so as to cover the heat spreader region 45H, heat dissipation through the ceramic layer 47 is promoted.

  As a result, in the semiconductor device 40 of this embodiment, it is possible to avoid the occurrence of thermal runaway of the semiconductor device even when the semiconductor chip 44 is operated at a high output.

  As described above, in the semiconductor device 40 of FIGS. 5A to 5C, the formation of the ceramic layers 47 and 48 on the resin laminate is performed by aerosol deposition using the device shown in FIG. Perform by law.

  FIG. 6 shows the configuration of an aerosol deposition apparatus 60 used in the present invention.

  Referring to the figure, the aerosol deposition apparatus 60 includes a mechanical booster pump 62A and a processing vessel 61 that is evacuated by a vacuum pump 62. In the processing vessel 61, a substrate W to be processed is placed on a stage 61A. Is held by the XY stage driving mechanism 61b and the Z stage driving mechanism 61a so as to be driven in the XYZ-θ direction.

  The processing vessel 61 is provided with a nozzle 61B facing the substrate W to be processed on the stage 61A. The nozzle 61B is supplied with an aerosol of a ceramic material together with a carrier gas, and this is supplied to the substrate W to be processed. The surface is sprayed as a jet 61c.

  The ceramic particles constituting the aerosol sprayed in this way preferably have a particle size of 0.5 μm or less, as described above, and are solidified by impact on the surface of the substrate W to be processed. Form. The ceramic film thus obtained has a unique structure in which individual ceramic particles are deformed flat.

  In order to supply the aerosol to the nozzle 61B, the aerosol deposition apparatus 60 of FIG. 6 is provided with a raw material container 63 holding a ceramic powder raw material having a particle size of preferably 0.5 μm or less. A carrier gas such as an inert gas or high-purity oxygen is supplied from the high-pressure gas source 64 via the mass flow controller 64A. The raw material container 63 is held on a vibration table 63A in order to promote the generation of aerosol. The raw material container 63 is maintained in a reduced pressure state prior to the film forming step by the mechanical booster pump 62A and the vacuum pump 62, and the moisture of the ceramic powder raw material is removed.

  Next, the manufacturing process of the semiconductor device 40 shown in FIGS. 5A to 5C performed using the aerosol deposition apparatus will be described.

  Referring to FIG. 7A, first, Cu wiring patterns 46 and 46P are formed on a base 70 made of Cu or a Cu alloy, and the first layer build is formed so as to cover the Cu wiring patterns 46 and 46P. The up insulating film 41A is formed by a vacuum lamination method. For example, as the build-up insulating film 41A, a resin insulating film commercially available under the trade name TLF-30 from Yodogawa Paper Co., Ltd. can be used.

Further, a via hole corresponding to the via plug 43A is formed in the build-up insulating film 41A by a CO ₂ laser, and the entire surface of the build-up insulating film including the via hole is formed by Cu electroless plating. (Not shown), and a commercially available resist film (not shown) is formed on the Cu seed layer under the trade name FOTEC RY-3229 from, for example, Hitachi Chemical Co., Ltd. Further, the resist film is exposed to form an opening corresponding to the via hole, and then the via hole is filled with Cu by electrolytic plating. As a result, the Cu via plug 43A is formed in the build-up insulating film 41A.

  Further, a new resist film is formed on the Cu seed layer, patterned according to a desired wiring pattern, and subjected to electrolytic plating, thereby forming a wiring pattern 42A on the build-up insulating film 41A.

  Further, after removing the Cu seed layer interposed between the wiring patterns on the build-up insulating film by etching, the same process is repeated, so that the resin laminate described in the figure is formed on the base 70. Is formed.

  Next, in the step of FIG. 7B, the formation region of the electrode pad 45P on the resin laminate is covered with a screen mask (not shown) such as a metal mask, and in the aerosol deposition apparatus 60, AlN or the like is formed. By forming the ceramic layer 47, as shown in FIG. 7C, a structure in which the portion of the wiring pattern 45 constituting the pad electrode 45P is exposed through the opening in the ceramic layer 47 is formed. can get.

  At this time, the rib structure 47R in the ceramic layer 47 is formed again using a metal mask (not shown) on which a rib pattern is formed after, for example, first performing uniform aerosol deposition to form the first layer. It can be easily formed by performing aerosol deposition or by simply performing aerosol deposition while moving the nozzle.

  Next, in the step of FIG. 7D, the base material 70 is removed by etching. Next, a similar metal mask pattern M is formed in a predetermined electrode pad formation region on the lower surface of the resin laminate, and the aerosol deposition is performed. By performing aerosol deposition in the position device 60, the ceramic layer 48 is formed on the lower surface of the resin laminate so as to expose the electrode pad 46P as shown in FIG. A circuit board 41 is obtained. At this time, also in the formation of the ceramic layer 48, a uniform film is first formed, and then a rib portion is formed using a metal mask, so that the ceramic layer 48 is formed on the ceramic layer 48 as shown in FIG. The rib portion 48R shown in FIG.

  Further, the semiconductor device 40 described above is obtained by flip-chip mounting the semiconductor chip 44 on the coreless multilayer circuit board 41 in the step of FIG.

  7 (B) and 7 (D), the rib portions 47R and 48R are made of aerosol without using a mask pattern in the position process, and after the ceramic films 47 and 48 are uniformly formed, It is also possible to form by patterning by etching using a mask process.

  In the previous step, the ceramic layers 47 and 48 may be ceramics that are usually used as a highly elastic material and are not specified. For example, alumina, zirconia, aluminum nitride, cordierite, mullite, titania. , Quartz, forsterite, wollastonite, anorthite, enstatite, diopsite, akermanite, gelenite, spinel, garnet, etc., and titanates such as magnesium titanate, calcium titanate, strontium titanate, barium titanate, etc. Can be used.

  Among these, from the viewpoint of insulation and strength, it is preferable to use a powder having a particle diameter of 10 nm to 1 μm, such as alumina, zirconia, aluminum nitride, cordierite, mullite. Further, in the process shown in the figure or the figure, it is possible to use two or more kinds of ceramics and form the ceramic layer as, for example, a mixed film of alumina and zirconia.

  In the present embodiment, in the aerosol deposition apparatus 60 of the above figure, aluminum nitride powder commercially available from Tokuyama Co., Ltd. under the product name Shapal H grade, or alumina powder commercially available under the product name 160SG-4 from Showa Denko KK is used. Yes.

  In the semiconductor device 40, when the prepreg used for the core material, for example, impregnated with glass cloth instead of the high thermal conductive ceramic layer, the coreless multilayer circuit board 41 has a sufficient elastic modulus. Improve cannot be achieved.

  When the warp of the multilayer coreless circuit board 41 formed in this way was measured without mounting the semiconductor chip 44, the warp value was about 50 μm for a substrate with a side of 4 cm, and the semiconductor chip In a region where one side where 44 is mounted is 2 cm, it is about 20 μm, and it was confirmed that a semiconductor chip can be mounted without using a reinforcing member.

  In addition, after mounting the semiconductor chip on the coreless multilayer circuit board, the warpage of the coreless multilayer circuit board 41 was measured. As a result, the warpage was 100 μm or less on a substrate having a side of 4 cm. It was confirmed that no disconnection occurred.

  Further, the semiconductor chip 44 is actually flip-chip mounted on the coreless multilayer circuit board thus formed as described in FIGS. 5A to 5C, and the semiconductor chip 44 and the coreless multilayer circuit board are mounted. 41, a general underfill resin layer (CRP-4075S3 commercially available from Sumitomo Bakelite Co., Ltd.) having an elastic modulus of 10 GPa is filled and cured at 150 ° C. for 30 minutes, and then from −10 ° C. The thermal cycle test was repeated 300 times between 100 ° C.

  As a result, in the semiconductor device 40 using the coreless multilayer circuit board 41 having the configuration in which the high thermal conductive ceramic layers 47 and 48 are provided in the resin laminate according to the present embodiment, the separation or the separation between the semiconductor chip 44 and the coreless circuit board 41 is possible. It was confirmed that no disconnection occurred.

  5A to 5C, the underfill resin layer (not shown) may be added with a filler or may not be added with a filler.

  On the other hand, in a comparative experiment in which the high thermal conductive ceramic layer was not provided in the configuration of FIGS. 5A to 5C, a warp was 50 μm in the present embodiment on a substrate having a side of 4 cm. From the value, it was confirmed that it increased to 300 μm. At that time, in the chip mounting region having a side of 2 cm, the warpage increases from 20 μm in this embodiment to about 100 μm, and the mounting of the semiconductor chip is performed by using the reinforcing member 17 as shown in FIG. It was impossible unless it was used.

  Therefore, in the comparative experiment described above, by providing a reinforcing member made of stainless steel having a thickness of 1 mm on a coreless multilayer circuit board on which the ceramic layer is not provided, the size of the warp is suppressed to about 100 μm. After mounting and forming an underfill resin layer similar to this embodiment in the same manner, the same thermal cycle test was performed.

  As a result, in the above comparative experiment, it was confirmed that the coreless multilayer circuit board and the semiconductor chip were broken by 300 thermal cycles, and the warpage of the board in the chip mounted state reached 300 μm. confirmed. In this comparative experiment, peeling of the semiconductor chip and disconnection of the through via plug were also observed.

  Thus, according to the present invention, the coreless multilayer circuit board is effectively reinforced by forming high thermal conductive ceramic layers on the upper and lower surfaces of the coreless multilayer circuit board having a low elastic modulus, preferably by the aerosol deposition method. Thus, the reliability of the semiconductor device using such a coreless circuit board can be greatly improved. Further, at that time, by forming an uneven shape on the rib in the high thermal conductive ceramic layer, the surface area can be increased, and the heat radiation efficiency through the high thermal conductive ceramic layer can be improved.

  For example, as the rib-shaped uneven shape 47R, for example, a convex pattern or a concave pattern having a width of about 100 μm and a depth of about 100 μm may be repeated at a pitch of 100 μm, for example.

Such rib-shaped portions may be formed not only in the ceramic layer 47 but also in the ceramic layer 48 if necessary.
[Second Embodiment]
FIGS. 8A to 8C are a plan view, a longitudinal sectional view, and a transverse sectional view, respectively, showing the configuration of the semiconductor device 80 using the coreless multilayer circuit board 81 according to the second embodiment of the present invention. However, in the figure, the same reference numerals are given to the parts described above, and the description will be omitted.

  Referring to FIGS. 8A to 8C, the semiconductor device 80 has the same configuration as that of the figure in the sectional view of the figure. However, as shown in the transverse sectional view of the figure, the high thermal conductivity ceramic layer 47 is shown in FIG. This rib (unevenness) structure is not a fin shape extending in one direction but a lattice shape in two directions.

  With such a configuration, the coreless multilayer circuit board 81 resists both deformation in the X direction and the Y direction in the figure, and as a result, the elastic modulus and thermal conductivity can be further improved.

Note that the present invention is not only a coreless multilayer circuit board, but also a circuit board having a core member as shown in FIG. 1, particularly in the case where warpage and deformation are problematic at a thickness of 500 μm or less, It is also possible to apply.
[Third Embodiment]
FIG. 9 shows the concavo-convex structure of the ceramic layer 47 according to the third embodiment of the present invention.

  Referring to FIG. 9, in this embodiment, in the concavo-convex structure constituting the fin-like rib portion 47 </ b> R or the lattice-like rib portion 47 </ b> L, the base portion 47 d of the convex portion is a dense ceramic like the main portion of the ceramic layer 47. It forms as a film | membrane, Only the front-end | tip part 47p is formed as a porous ceramic film | membrane.

  Such a porous ceramic membrane can be obtained by using ceramic particles having a relatively large particle size, for example, 1.0 to 3.0 μm as a raw material in the aerosol deposition apparatus 60 of FIG. It can be formed by increasing the scanning speed from a normal speed of 0.5 mm / second to a speed of 5.0 to 10.0 mm / second.

Thus, by making only the tip 47p of the rib portion 47R or 47L porous, the heat dissipation surface area is increased, and the heat dissipation efficiency through the ceramic layer 47 is improved. At this time, since the base portion 47d is formed of a dense ceramic layer, the mechanical reinforcement effect of the ceramic layer 47 is not impaired.
[Fourth embodiment]
FIG. 10 shows a configuration of a semiconductor device 100 according to the fourth embodiment of the present invention. However, in FIG. 10, the same reference numerals are given to the parts described above, and description thereof is omitted.

  Referring to FIG. 10, in this embodiment, the surface of the resin laminate in which the build-up insulating films 41 </ b> A to 41 </ b> E are laminated has the external connection pad electrode 46 </ b> P and grounding in a state where the semiconductor chip 44 is mounted. Except for the pad electrode 45P, it is continuously covered with an insulating ceramic layer 101 similar to the ceramic layers 47 and 48, such as AlN, and a conductive ceramic layer 102 is further formed on the insulating ceramic layer 101. , Except for the external connection pad electrode 46P, and so as to be in direct contact with the semiconductor chip 44. In the configuration of FIG. 10, an underfill resin layer 44 </ b> U is formed between the resin laminate and the semiconductor chip 44.

  At that time, the conductive ceramic layer 102 is formed in contact with the ground electrode pads 45G and 46G on the circuit board made of the resin laminate, and as a result, the semiconductor device 100 has a ground potential as a whole. Covered by the conductive ceramic layer 102, an electromagnetic shield is formed. Thereby, radiation of high frequency noise is suppressed, and malfunction of the semiconductor device due to external high frequency noise is suppressed.

  At this time, in the present invention, since the conductive ceramic layer 102 is formed in close contact with the insulating ceramic layer 101, a space that causes cavity resonance around the semiconductor chip 44 is not formed, and the semiconductor The device 100 does not suffer from operating frequency limitations.

  Both the insulating ceramic layer 101 and the conductive ceramic layer 102 can be formed at a low temperature such as room temperature without heating using the aerosol deposition apparatus 60 of FIG. In this case, the insulating ceramic layer 101 is not limited to AlN, and as described above, is not specified, for example, alumina, zirconia, aluminum nitride, cordierite, mullite, titania, quartz, Use foresterite, wollastonite, anorthite, enstatite, diopsite, akermanite, gelenite, spinel, garnet, etc., and also use titanates such as magnesium titanate, calcium titanate, strontium titanate, barium titanate it can.

  On the other hand, the conductive ceramic layer 102 is used as a raw material for the insulating ceramic layer in the aerosol deposition apparatus 60 of FIG. It can be formed by using conductive ceramic powder such as TiC and AlSiC (aluminum silicon carbide), or conductive raw material powder mixed with metal fine powder. Alternatively, a plurality of nozzles and a raw material container are provided in the aerosol deposition apparatus 60 of FIG. 6, and an insulating ceramic material such as alumina and the conductive material are sprayed simultaneously or alternately from each nozzle. It can also be formed.

Since these materials have a high elastic modulus, they also function as mechanical reinforcement means for the coreless substrate, and also have excellent thermal conductivity, so that they also function as heat dissipation members.
[Fifth Embodiment]
FIG. 11 shows a configuration of a semiconductor device 120 according to the fifth embodiment of the present invention. However, in FIG. 12, the same reference numerals are assigned to portions corresponding to the portions described above, and description thereof is omitted.

  Referring to FIG. 11, in this embodiment, after the semiconductor chip 44 is flip-chip mounted, the uppermost buildup insulating film 41E is formed so as to cover the semiconductor chip 44 except for the upper portion thereof. The insulating ceramic layer 101 and the conductive ceramic layer 102 are formed on the resulting structure.

  12A to 12E are diagrams showing manufacturing steps of the semiconductor device 120 of FIG.

Referring to FIG. 12A, after the semiconductor chip 44 is flip-chip mounted on a laminate made up of the build-up insulating films 41A to 41D formed on the substrate 70, the uppermost build-up insulation is performed. A film 41E is formed, and further, a through via plug 23C and a ground pad electrode 45G are formed.

  Further, in the step of FIG. 12B, a metal mask pattern M1 is formed on the structure of FIG. 12A so as to cover the ground pad electrode 45G, and an insulating ceramic material is used with the metal mask pattern M1 as a mask. 6 is performed using the aerosol deposition apparatus 60 of FIG. 6, and the insulating ceramic film 101 is formed on the surface of the buildup insulating film 41E while avoiding the ground pad electrode 45G.

  Next, in the step of FIG. 12C, the metal mask M1 is removed, and the insulating ceramic film 101 is formed on the upper surface of the buildup insulating film 41E on the side wall surface of the stacked body of the buildup insulating films 41A to 41E. Is formed continuously.

12D, the base material 70 is removed, and a metal mask pattern M2 that covers the external connection pad electrode 46P and the ground pad electrode 46G is formed on the surface of the lowermost buildup insulating film 41A. Further, using the metal mask pattern M2 as a mask, aerosol deposition of an insulating ceramic material is performed using the aerosol deposition apparatus 60 of FIG. 6, and the insulating ceramic film 101 is formed on the surface of the build-up insulating film 41A. Is continuously formed from the side wall surface of the resin laminate.

  Further, in the step of FIG. 12E, the metal mask pattern M2 is removed, and a mask pattern M3 that selectively covers the external connection pad electrode 46P is formed on the surface of the buildup insulating film 41A. The conductive ceramic film 102 is formed by performing aerosol deposition using the ceramic raw material mixed with the conductive raw material powder in the aerosol deposition apparatus 60 of FIG. 6 using M3 as a mask.

  Alternatively, as described above, in the step of FIG. 12E, the conductive ceramic film 102 is formed by using a plurality of nozzles instead of the single nozzle 61B in the aerosol deposition apparatus 60 of FIG. Insulating ceramic raw material and conductive ceramic raw material can be formed by spraying simultaneously or alternately from the respective nozzles.

As mentioned above, although this invention was described about preferable embodiment, this invention is not limited to this specific embodiment, A various deformation | transformation and change are possible within the summary described in the claim.
(Appendix 1)
A circuit board comprising a resin laminate in which a plurality of build-up resin layers each carrying a wiring pattern and having a via plug connected to the wiring pattern are laminated,
Having first and second ceramic layers formed on the upper and lower surfaces of the resin laminate, each having an elastic modulus greater than that of the buildup layer;
At least one of the first and second ceramic layers has an uneven cross section.
(Appendix 2)
The circuit board according to appendix 1, wherein the circuit board is a coreless circuit board.
(Appendix 3)
A conductor pattern that contacts a terminal portion of a semiconductor chip is formed on the upper surface of the resin laminate so as to be covered with the first ceramic layer, and a part of the conductor pattern is formed on the upper surface of the resin laminate. The circuit board according to claim 1 or 2, wherein a heat spreader that is wider than a portion of the conductor pattern that contacts the terminal portion of the semiconductor chip is formed.
(Appendix 4)
The circuit board according to claim 3, wherein the conductor pattern is in contact with a heat radiating terminal portion of the semiconductor chip.
(Appendix 5)
The circuit board according to any one of supplementary notes 1 to 4, wherein the ceramic layer having the concavo-convex cross section has a porous portion formed on a convex portion thereof.
(Appendix 6)
The first and second ceramic layers are made of any one of AlN (aluminum nitride), Al ₂ O ₃ (alumina), and AlSiC (aluminum silicon carbide). The circuit board according to one item.
(Appendix 7)
A semiconductor device comprising: the circuit board according to any one of appendices 1 to 6; and a semiconductor chip flip-chip mounted on the circuit board.
(Appendix 8)
A circuit board having a resin laminate in which a plurality of build-up resin layers each carrying a wiring pattern and having a via plug connected to the wiring pattern are laminated;
A semiconductor device comprising a semiconductor chip mounted on the circuit board,
An insulating ceramic layer that covers the circuit board and the semiconductor chip except for external connection terminal portions of the circuit board;
A conductive ceramic layer covering the insulating ceramic layer;
A semiconductor device comprising:
(Appendix 9)
The semiconductor device according to appendix 9, wherein the conductive ceramic layer is provided in contact with a ground terminal of the circuit board.
(Appendix 10)
A resin laminate comprising a plurality of buildup resin layers each carrying a wiring pattern and having via plugs connected to the wiring pattern, and an elastic modulus of the buildup layer on the upper and lower surfaces of the resin laminate A method of manufacturing a circuit board having first and second ceramic layers having a greater elastic modulus, wherein at least the first and second ceramic layers are formed by an aerosol deposition method on the first and second ceramic layers. A method of manufacturing a circuit board, wherein one of the layers is formed to have an uneven cross section.
(Appendix 11)
A circuit board having a resin laminate in which a plurality of build-up resin layers each carrying a wiring pattern and having via plugs connected to the wiring pattern are laminated; a semiconductor chip mounted on the circuit board; A method of manufacturing a semiconductor device comprising: an insulating ceramic layer that covers a circuit board and the semiconductor chip except for an external connection terminal portion of the circuit board; and a conductive ceramic layer that covers the insulating ceramic layer. ,
The method for manufacturing a semiconductor device, wherein the insulating ceramic layer and the conductive ceramic layer are formed by an aerosol deposition method.

It is a figure which shows the structure of the semiconductor device which has the conventional multilayer circuit board. (A), (B) is a figure which shows the structure of the semiconductor device for high frequency uses which has the conventional coreless multilayer circuit board. It is a figure which shows the structure of the semiconductor device for a high frequency use which has an electromagnetic shield on a multilayer circuit board. It is a figure which shows the structure of the semiconductor device for a high frequency use which has an electromagnetic shield on a coreless multilayer circuit board. (A)-(C) are figures which show the structure of the semiconductor device by the 1st Embodiment of this invention. It is a figure which shows the structure of the aerosol deposition apparatus used by this invention. (A)-(F) are the figures explaining the manufacturing process of the semiconductor device of FIG. (A)-(C) are figures which show the structure of the semiconductor device by the 2nd Embodiment of this invention. It is a figure which shows the structure of the semiconductor device by the 3rd Embodiment of this invention. It is a figure which shows the structure of the semiconductor device by the 4th Embodiment of this invention. It is a figure which shows the structure of the semiconductor device by the 5th Embodiment of this invention. (A)-(E) is a figure explaining the manufacturing process of the semiconductor device of FIG.

Explanation of symbols

40, 80, 100, 120 Semiconductor device 41 Coreless multilayer circuit boards 41A to 41E Build-up insulating films 42A to 41E Cu wiring patterns 43A to 43E Cu via plug 44 Semiconductor chip 44A Bump 45, 46 Cu wiring pattern 45P, 46P Pad electrode 45G, 46G Ground electrode 45H Heat spreader 47, 48 Ceramic layers 47R, 48R, 47L, 48L Rib 60 Aerosol deposition device 61 Processing vessel 61A Stage 61B Nozzle 61a Z-axis drive mechanism 61b XY-axis drive mechanism 61c Jet 62 Vacuum pump 62A Mechanical booster Pump 63 Raw material container 63A Shaking table 64 High pressure gas source 64A MFC
101 Insulating Ceramic Film 102 Conductive Ceramic Film M, M1, M2, M3 Metal Mask Pattern

Claims (7)

A circuit board comprising a resin laminate in which a plurality of build-up resin layers each carrying a wiring pattern and having a via plug connected to the wiring pattern are laminated,
Having first and second ceramic layers formed on the upper and lower surfaces of the resin laminate, each having an elastic modulus greater than that of the buildup layer;
At least one of the first and second ceramic layers has an uneven cross section. A conductor pattern that contacts a terminal portion of a semiconductor chip is formed on the upper surface of the resin laminate so as to be covered with the first ceramic layer, and a part of the conductor pattern is formed on the upper surface of the resin laminate. 3. The circuit board according to claim 1 , wherein a heat spreader having a width wider than a portion of the conductor pattern that contacts the terminal portion of the semiconductor chip is formed. The circuit board according to claim 1, wherein the ceramic layer having the concavo-convex cross section has a porous portion formed on a convex portion thereof. A circuit board having a resin laminate in which a plurality of build-up resin layers each carrying a wiring pattern and having a via plug connected to the wiring pattern are laminated;
A semiconductor device comprising a semiconductor chip mounted on the circuit board,
An insulating ceramic layer that covers the circuit board and the semiconductor chip except for external connection terminal portions of the circuit board;
A conductive ceramic layer covering the insulating ceramic layer;
A semiconductor device comprising:   The semiconductor device according to claim 4, wherein the conductive ceramic layer is provided in contact with a ground terminal of the circuit board. A resin laminate comprising a plurality of buildup resin layers each carrying a wiring pattern and having via plugs connected to the wiring pattern, and an elastic modulus of the buildup layer on the upper and lower surfaces of the resin laminate A method of manufacturing a circuit board having first and second ceramic layers having a greater elastic modulus,
A method of manufacturing a circuit board, wherein the first and second ceramic layers are formed by an aerosol deposition method so that at least one of the first and second ceramic layers has an uneven cross section. A circuit board having a resin laminate in which a plurality of build-up resin layers each carrying a wiring pattern and having via plugs connected to the wiring pattern are laminated; a semiconductor chip mounted on the circuit board; A method of manufacturing a semiconductor device comprising: an insulating ceramic layer that covers a circuit board and the semiconductor chip except for an external connection terminal portion of the circuit board; and a conductive ceramic layer that covers the insulating ceramic layer. ,
The method for manufacturing a semiconductor device, wherein the insulating ceramic layer and the conductive ceramic layer are formed by an aerosol deposition method.