JP2002026171A - Method for producing multilayer wiring board and multilayer wiring board - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a multilayer wiring board, having not only rigidity but also superior heat dissipation characteristic and noise characteristic. SOLUTION: The method for manufacturing a multilayer wiring board comprises a step for forming a resist metal layer and a wiring pattern, using a metal plate as a lead for electrolytic plating; a step for removing the metal plate by etching, and a step for forming a metal frame 116 on the outermost layer of the multilayer wiring board 113 partially etching and removing a metal plate 101b which is used at formation of the outermost layer on the side of the multilayer wiring board 113, for mounting of a semiconductor chip 202.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multilayer wiring board on which a semiconductor chip is mounted, and more particularly to a method of manufacturing a multilayer wiring board for simultaneously performing electrical connection and adhesion between layers and a multilayer wiring board manufactured by the manufacturing method. It is.

[0002]

2. Description of the Related Art In recent years, with the demand for higher functionality and lighter, thinner and smaller electronic devices, high-density integration and high-density mounting of electronic components have been progressing. Semiconductor packages have been increasingly miniaturized and have more pins than ever before.

[0003] A conventional circuit board is called a printed wiring board, and after patterning copper foil adhered to a glass epoxy board made of a laminated board made of glass fiber woven fabric impregnated with epoxy resin, a plurality of sheets are stacked. The mainstream was to use a wiring board in which a through-hole was formed by bonding and drilling, a via was formed by performing copper plating on the wall surface of the hole, and a via was formed to perform electrical connection between layers. However, the mounting components have been reduced in size and density, and the wiring density of the above-described wiring boards has become insufficient, and problems have arisen in mounting components.

[0004] Against this background, recently, build-up multilayer wiring boards have been adopted. The build-up multilayer wiring board is formed while stacking an insulating layer made of only a resin and a conductor. As a via forming method, a high density is achieved by freely arranging small diameter via holes in various ways such as a laser method, a plasma method and a photo method instead of the conventional drilling. Examples of the interlayer connection portion include a blind via (Blind Via) and a buried via (Buried Via: a structure in which a via is filled with a conductor). A buried via hole capable of forming a via on a via is particularly attracting attention. ing. The buried via hole is classified into a method of filling the via hole with plating and a method of filling the via hole with a conductive paste or the like. On the other hand, as a method of forming a wiring pattern, there are a method of etching a copper foil (subtractive method), a method of electrolytic copper plating (additive method), and the like. Is starting to be.

Since a semiconductor package using such a multilayer wiring board has a very large number of pins, the multilayer wiring board is generally larger in size than the semiconductor chip. Therefore, it is natural that the multilayer wiring board needs to have rigidity from the viewpoint of the handleability of the multilayer wiring board. At present, in order to secure the rigidity of the multilayer wiring board, the rigidity of a printed wiring board (glass epoxy board such as FR-4) having an insulating layer in which resin is impregnated with a reinforcing fiber is used, Build-up layers are stacked. However, a printed wiring board having an insulating layer in which a reinforcing fiber is impregnated with a resin may cause dielectric breakdown at an interface between the reinforcing fiber and the resin, and thus has a problem in insulating properties.

[0006] On the other hand, the "prior art" of Japanese Patent Application Laid-Open No. 11-11887 describes a stiffener (reinforcing frame) of a tape BGA. It is general to attach a stiffener to the tape BGA, and the object is to secure the rigidity of the tape BGA from the viewpoint of the handling of the tape BGA. Thus, the solder balls can be smoothly mounted. Further, the tape BGA uses polyimide or the like as an insulating layer, that is, since the insulating layer is made of a resin not filled with reinforcing fibers, the tape BGA has good insulating properties. However,
Since it is difficult to multi-layer the tape BGA, the tape BGA cannot be adopted as a semiconductor package having a very high pin count. Further, in order to prevent unnecessary radiation of noise and improve heat radiation characteristics, it is preferable that the stiffener is conductively connected to the ground wiring pattern. However, the adhesive between the tape BGA and the stiffener uses an adhesive having a high insulating property and a high thermal conductivity, so that the heat radiation characteristics can be improved, but there is a problem that it is not possible to prevent unnecessary radiation.

[0007]

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems in a multilayer wiring board on which a semiconductor chip is mounted. In view of the above-mentioned problems, the multilayer wiring board not only has rigidity but also has excellent heat dissipation characteristics and noise characteristics. The purpose is to provide.

[0008]

SUMMARY OF THE INVENTION The present invention provides a multi-layer wiring comprising a step of forming a resist metal layer and a wiring pattern by electrolytic plating using a metal plate as a lead for electrolytic plating, and a step of removing the metal plate by etching. A method of manufacturing a board, in which a metal plate used when forming an outermost layer on a side on which a semiconductor chip of a multilayer wiring board is mounted is partially etched and removed, so that the outermost layer of the multilayer wiring board is removed. A method for manufacturing a multilayer wiring board, comprising a step of forming a metal frame.

The method for manufacturing a multilayer wiring board according to the present invention includes the steps of forming a resist metal layer and a wiring pattern by electrolytic plating using a metal plate as a lead for electrolytic plating, and removing the metal plate by etching. In addition, these steps are repeatedly performed, and the metal plate used when forming the outermost layer on the side on which the semiconductor chip of the multilayer wiring board is mounted is partially removed by etching, whereby the multilayer wiring board is removed. Forming a metal frame on the outermost layer of a metal plate as a lead for electrolytic plating, forming a resist metal layer and a wiring pattern by electrolytic plating, and an insulating film on the wiring pattern. Forming a via in the insulating film so that a part of the wiring pattern is exposed; and using a metal plate as a lead for electrolytic plating to form a conductor post. Forming a bonding metal material layer on at least one of the surface of the conductor post or the surface of the portion to be bonded of the connected layer; and forming at least one of the surface of the insulating film or the surface of the connected layer. A step of forming an adhesive layer on one side, and joining the conductor post and the part to be joined with the joining metal material layer via the adhesive layer,
A step of bonding the insulating film and the connected layer with an adhesive layer,
Removing the metal plate by etching, by partially etching and removing the metal plate used when forming the outermost layer on the side on which the semiconductor chip of the multilayer wiring board is mounted, It is preferable to include a step of forming a metal frame on the outermost layer of the multilayer wiring board. Further, it is preferable that the insulating film is made of a resin not filled with reinforcing fibers, and it is even more preferable that the metal frame is electrically connected to the ground wiring pattern of the multilayer wiring board.

A multilayer wiring board of the present invention is characterized by being obtained by the above-described method for manufacturing a multilayer wiring board.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described with reference to the drawings, but the present invention is not limited thereto.

FIGS. 1A to 4R are views for explaining an example of a method for manufacturing a multilayer wiring board according to an embodiment of the present invention, and FIG. 4R shows an obtained multilayer wiring board. FIG. 3 is a cross-sectional view showing the structure of FIG.

The method for producing a multilayer wiring board of the present invention includes the following:
First, a patterned plating resist 102 is formed on a metal plate 101 (FIG. 1A). The plating resist 102 can be formed, for example, by laminating an ultraviolet-sensitive dry film resist on the metal plate 101, selectively exposing it using a negative film or the like, and then developing it. The material of the metal plate 101 may be any material as long as it is suitable for the manufacturing method of the present invention. In particular, the metal plate 101 has a resistance to a used chemical solution and can be finally removed by etching. It is necessary to be. As a material of the metal plate 101, for example, copper,
Copper alloy, 42 alloy, nickel and the like can be mentioned.

Next, a resist metal layer 103 is formed by electrolytic plating using the metal plate 101 as a lead for electrolytic plating (FIG. 1B). By this electrolytic plating, the metal plate 1
A resist metal layer 103 is formed on the portion of the substrate 01 where the plating resist 102 is not formed. The material of the resist metal layer 103 may be any material as long as it is suitable for the manufacturing method of the present invention. In particular, the material is resistant to a chemical used when the metal plate 101 is finally removed by etching. It is necessary to have. As a material of the resist metal layer 103, for example, nickel, gold, tin,
Silver, solder, palladium and the like can be mentioned. The purpose of forming the resist metal layer 103 is to prevent the wiring pattern 104 shown in FIG. 1C from being eroded or corroded by a chemical used when etching the metal plate 101. Therefore, for the chemical solution used when etching the metal plate 101, the wiring pattern 1 shown in FIG.
04 is resistant, the resist metal layer 1
03 is unnecessary. Further, the resist metal layer 103 does not need to be the same pattern as the wiring pattern 104, and before forming the plating resist 102 on the metal plate 101,
A resist metal layer 103 may be formed on the entire surface of the metal plate 101.

Next, a wiring pattern 104 is formed by electrolytic plating using the metal plate 101 as a lead for electrolytic plating (FIG. 1C). By this electrolytic plating, the metal plate 10
The wiring pattern 104 is formed on the portion on which the plating resist 102 is not formed. Wiring pattern 1
The material of the material 04 may be any material as long as it is suitable for the manufacturing method of the present invention. In particular, the material of the material 04 is resistant to a chemical used when the resist metal layer 103 is finally removed by etching. It is necessary. Actually, it is advisable to select a material for the resist metal layer 103 that can be etched with a chemical solution that does not corrode or corrode the wiring pattern 104. Examples of the material of the wiring pattern 104 include copper, nickel, gold, tin, silver, and palladium. Further, by using copper, a stable wiring pattern 104 with low electric resistance can be obtained.

Next, the plating resist 102 is removed (FIG. 1D), and the insulating film 1 is formed on the formed wiring pattern 104.
05 is formed (FIG. 1E). As the resin constituting the insulating film 105, any resin suitable for the manufacturing method of the present invention can be used. In particular, reinforcing fibers (eg,
(Glass cloth) It is preferable to form an insulating film 105 made of an unfilled resin. The method for forming the insulating film 105 may be a method suitable for the resin to be used. The resin varnish may be directly applied by printing, curtain coating, bar coating, or the like, or a dry film type resin may be vacuum-laminated.
A method of laminating by a method such as a vacuum press may be used. Particularly, a commercially available resin-coated copper foil is easily available. If the copper foil is etched by embedding and embedding the unevenness of the wiring pattern 104 by vacuum lamination, the surface of the insulating film 105 becomes It becomes very flat without being affected by unevenness. Further, since the fine roughened shape of the copper foil surface is transferred to the surface of the insulating film 105,
Adhesion with the adhesive layer 109 shown in FIG. 2 (i) can be ensured.

Next, a via 106 is formed in the formed insulating film 105.
Is formed (FIG. 1F). The method for forming the via 106 is as follows.
Any method may be used as long as it is suitable for the manufacturing method of the present invention, and examples thereof include dry etching by laser and plasma, and chemical etching. In the case where the insulating film 105 is made of a photosensitive resin, the via 106 can be formed by selectively exposing and developing the insulating film 105.

Next, the conductor post 107 is formed by electrolytic plating using the metal plate 101 as a lead for electrolytic plating (FIG. 2 (g)). By this electrolytic plating, the insulating film 105 is formed.
In the portion where the via 106 is formed, the conductor post 10 is formed.
7 is formed. If the conductor post 107 is formed by electrolytic plating, the shape of the tip of the conductor post 107 can be freely controlled. The material of the conductor post 107 may be any material as long as it is suitable for the manufacturing method of the present invention, and examples thereof include copper, nickel, gold, tin, silver, and palladium. Furthermore, by using copper, the conductor post 107 which is stable with low electric resistance can be obtained.

Next, the surface (tip) of the conductor post 107
Next, a bonding metal material layer 108 is formed (FIG. 2).
(H)). Examples of a method of forming the bonding metal material layer 108 include a method of forming the metal plate 101 by electroplating as a lead for electrolytic plating, and a method of printing a paste containing the bonding metal material. Can be In the printing method, the printing mask needs to be accurately positioned with respect to the conductor post 107. However, in the method of electroless plating or electrolytic plating, the bonding metal material layer 108 is formed on the surface other than the surface of the conductor post 107. The conductor posts 107 are not miniaturized.
Easy to cope with high density. In particular, the method using electroplating is very suitable because the metal that can be plated is more diverse than the method using electroless plating and the management of the chemical solution is easy. The material of the bonding metal material layer 108 may be any material as long as it is a metal that can be metal-bonded to the portion to be bonded 112 shown in FIG.
Solder. Among the solders, Sn and In, or Sn, Ag, Cu, Zn, Bi, Sb, Pb, In,
It is preferable to use solder made of at least two kinds of Au. More preferably, it is an environment-friendly Pb-free solder. FIG. 2H illustrates an example in which the bonding metal material layer 108 is formed on the surface of the conductor post 107.
Since the purpose of forming the bonding metal material layer 108 is to perform metal bonding between the conductor post 107 and the bonded portion 112, the bonding metal material layer 108 may be formed on the bonded portion 112. Of course, it may be formed on both surfaces of the conductor post 107 and the joint 112.

Next, the adhesive layer 1 is formed on the surface of the insulating film 105.
09 (FIG. 2 (i)). The adhesive layer 109 may be formed by a method suitable for the adhesive resin to be used. A resin varnish may be directly applied by printing, curtain coating, bar coating, or the like, or a dry film type resin may be vacuum-laminated, A method of laminating by a method such as a vacuum press may be used. Although FIG. 2 (i) shows an example in which the adhesive layer 109 is formed on the surface of the insulating film 105, the connection layer 11
The adhesive layer 109 may be formed on the surface of the first substrate. Of course, it may be formed on both surfaces of the insulating film 105 and the connected layer 111.

Next, the connection layer 1 obtained by the above-described steps
10 and the connected layer 111 are aligned (FIG. 2).
(J)). For the alignment, a method of aligning the positioning marks formed on the connection layer 110 and the connected layer 111 in advance by reading with an image recognition device, a method of aligning with a positioning pin, or the like can be used. Note that the connected layer 111 shown in FIG.
1 (a) to 1 (d) can be obtained.

Next, the connecting layer 110 and the connected layer 111
Are laminated (FIG. 2 (k)). As a lamination method, for example, using a vacuum press, the conductor post 107 is pressed through the adhesive layer 109 until it is metal-bonded to the portion 112 to be bonded by the bonding metal material layer 108, and further heated to be bonded. The agent layer 109 is cured so that the connection layer 110 and the
11 can be bonded.

Next, the metal plate 101 of the connection layer 110 is removed by etching (FIG. 3 (l)). A resist metal layer 103 is formed between the metal plate 101 and the wiring pattern 104, and the resist metal layer 103
Since the resist metal layer 103 is resistant to a chemical solution used when etching the metal pattern 101 by etching, the resist metal layer 103 is not eroded or corroded even when the metal plate 101 is etched. Is not eroded or corroded. When the material of the metal plate 101 is copper and the material of the resist metal layer 103 is nickel, tin or solder, a commercially available ammonia-based etchant can be used. When the material of the metal plate 101 is copper and the material of the resist metal layer 103 is gold or silver, almost any etching solution can be used, including a ferric chloride solution and a cupric chloride solution.

Next, the resist metal layer 103 is removed by etching (FIG. 3 (m)). Wiring pattern 104
Is resistant to the chemical used when the resist metal layer 103 is removed by etching, so that the wiring pattern 104 is not eroded or corroded. for that reason,
By removing the resist metal layer 103, the wiring pattern 104 is exposed. When the material of the wiring pattern 104 is copper and the material of the resist metal layer 103 is nickel, tin, or solder, a commercially available solder / nickel release agent (for example, Pewax manufactured by Mitsubishi Gas Chemical Co., Ltd.) can be used. The material of the wiring pattern 104 is copper, the resist metal layer 1
When the material of 03 is gold, it is difficult to etch the resist metal layer 103 without eroding or corroding the wiring pattern 104. In this case, the step of etching the resist metal layer 103 may be omitted, and the resist metal layer 103 may be left.

Subsequently, the above-mentioned steps, that is, FIG.
3 (m) is repeated to obtain a multilayer wiring board 113 which is in the process of being manufactured (see FIG. 3 (m)).
Another layer can be obtained (see FIG. 3).
(N)).

The steps shown in FIGS. 3 (o) to 4 (p) are views for explaining a step of forming the outermost layer 117a of the multilayer wiring board 113. The steps shown in FIGS. 3 (o) to 4 (p) are similar to the steps shown in FIGS. 2 (j) to 2 (k) in that the alignment between the connection layer and the connected layer is performed (FIG. 3 (o) ), And a laminate of a connection layer and a connected layer (FIG. 4 (p)).

Next, the metal plate 101a is completely removed by etching, and only the portion of the metal plate 101b on which the semiconductor chip 202 is mounted is removed by etching to form a metal frame 116 (FIG. 4 (q)). ). Since the multilayer wiring board 113 has the metal frame 116, the insulating film 1
Even when 05 is made of resin not filled with reinforcing fibers (for example, glass cloth), the multilayer wiring board 113 has rigidity. The insulating film 105a is formed by directly applying a resin varnish by printing, curtain coating, bar coating, or the like, or by laminating a dry film type resin by a method such as vacuum lamination or vacuum pressing.
The insulating film 105 is formed directly on the metal plate 101b.
a and the metal frame 116 have high adhesion.

Finally, a solder resist 115 is formed on the surface of the outermost layer 117b, and a portion of the pad 114b is opened to obtain a multilayer wiring board 113 (FIG. 4).
(R)). The wiring pattern 104 is provided on the outermost layer 117b.
Is not formed and only the pad 114b is formed, there is no need to form the solder resist 115. The same applies to the other outermost layer 117a. In the case of FIG. 4 (r), since only the pad 114a is formed, it is not necessary to form a solder resist. Further, it is not necessary to remove the resist metal layers 118a and 118b used when forming the outermost layers 117a and 117b. That is, the resist metal layers 118a, 1
Reference numeral 18b is used as a plating film applied to pads 114a and 114b formed on both surfaces of the multilayer wiring board 113. The material of the resist metal layers 118a and 118b is gold,
Silver, palladium, nickel, solder, etc., gold,
A layer configuration including any two or more of each of silver, palladium, and nickel may be employed. When the wiring pattern 104 is made of copper, gold and nickel are used.
It is good to have a layer configuration. Thereby, the pads 114a, 1
It is possible to prevent the solder of the solder balls mounted on 14b from diffusing into the copper of the wiring pattern 104. Furthermore, by electrically connecting the metal frame 116 to the ground wiring pattern 119 of the multilayer wiring board 113, not only unnecessary radiation of noise from the semiconductor device 201 can be reduced, but also heat radiation characteristics of the semiconductor device 201 are improved. be able to.

Through the above steps, a multilayer wiring board having the metal frame 116 on the side of the multilayer wiring board 113 on which the semiconductor chip 202 is mounted can be manufactured.

The method for manufacturing a multilayer wiring board according to the present invention and the features of the manufactured multilayer wiring board are as follows. (1) The metal frame 116 can be formed by partially etching the metal plate 101b used at the time of manufacturing. (2) Since the multilayer wiring board 113 has the metal frame 116, even when the insulating film 105 is made of a resin that is not filled with reinforcing fibers (for example, glass cloth), the multilayer wiring board 113 can be used.
Has rigidity. (3) By conductively connecting the metal frame 116 to the ground wiring pattern 119 of the multilayer wiring board 113, not only unnecessary radiation of noise from the semiconductor device 201 can be reduced, but also heat radiation characteristics of the semiconductor device 201 are improved. be able to.

The semiconductor device 201 can be obtained by mounting the semiconductor chip 202 on the pad 114a side and mounting the solder ball 205 on the pad 114b side of the multilayer wiring board 113 obtained by the above process ( (Fig. 5).

[0032]

EXAMPLES The present invention will be described in more detail with reference to the following Examples, but it should not be construed that the invention is limited thereto.

Example of Formulation of Adhesive m, p-cresol novolak resin (Nippon Kayaku Co., Ltd.
AS-1, 100 g of OH group equivalent) and 100 g of bisphenol F type epoxy resin (RE-404 manufactured by Nippon Kayaku Co., Ltd.)
140 g of S, epoxy group equivalent 165) was dissolved in 60 g of cyclohexanone, and 0.2 g of triphenylphosphine (manufactured by Hokko Chemical Industry Co., Ltd.) was added as a curing catalyst.
An adhesive varnish was prepared.

Example (Production Example of Multilayer Wiring Board) A dry film resist (AQ-2058 manufactured by Asahi Kasei) was applied to a rolled copper plate (metal plate 101, EFTEC-64T manufactured by Furukawa Electric) having a roughened surface and having a thickness of 150 microns. Roll lamination was performed and exposed and developed using a predetermined negative film to form a plating resist (plating resist 102) necessary for forming the wiring pattern 104. Next, using a rolled copper plate as a lead for electrolytic plating, a resist metal layer made of nickel by electrolytic plating (resist metal layer 103)
Was formed, and a wiring pattern (wiring pattern 104) was formed by electrolytic copper plating. The wiring pattern had a line width / interline / thickness = 20 microns / 20 microns / 10 microns. Next, copper foil with resin (Sumitomo Bakelite A
PL) by vacuum lamination while embedding the unevenness of the wiring pattern, and etching the entire surface of the copper foil.
A micron-thick insulating film (insulating film 105) was formed. Next, a via (via 106) having a diameter of 50 microns is formed by UV-YA.
It was formed by a G laser. Next, using the rolled copper plate as a lead for electrolytic plating, the via was filled with copper by electrolytic copper plating to form a copper post (conductor post 107). next,
Using a rolled copper plate as a lead for electrolytic plating, a Sn-Pb eutectic solder layer (metallic material layer for joining 108) was formed on a copper post by electrolytic plating. Next, the above-mentioned adhesive varnish was applied to the surface of the insulating film, that is, Sn-Pb by bar coating.
After coating on the surface on which the eutectic solder was formed, it was dried at 80 ° C. for 20 minutes to form an adhesive layer (adhesive layer 109) having a thickness of 10 μm. By the steps described above, a build-up layer (connection layer 110) was obtained. On the other hand, a resist metal layer (resist metal layer 118b) is formed on a rolled copper plate by electrolytic nickel / gold plating, and a wiring pattern is formed by electrolytic copper plating in the same manner as in the above-described process.
A connected layer (connected layer 111) having (12) was obtained. Next, the positioning marks formed in advance on the build-up layer and the connection layer obtained in the above-described steps were read by an image recognition device, the two were aligned, and pre-pressed at a temperature of 100 ° C. This was heated and pressurized at a temperature of 220 ° C. by a press, so that the copper post penetrated the adhesive layer and joined to the land by soldering, and the build-up layer was bonded to the connected layer by the adhesive layer. Next, the rolled copper plate of the build-up layer is removed by etching using an ammonia-based etchant, and a solder / nickel release agent (Mitsubishi Gas Chemical Co., Ltd.
ewtax) to remove the nickel by etching. Further, the above steps were repeated, and another buildup layer was laminated. However, the outermost layers (outermost layers 117a,
The resist metal layer (resist metal layers 118a and 118b) used in forming 17b) was a two-layer structure of nickel / gold. Subsequently, a metal frame (metal frame 116) was formed by etching the rolled copper plate on the side on which the semiconductor chip was mounted, and the entire surface was removed by etching the rolled copper plate on the connected layer side. Finally, a solder resist (solder resist 115) was formed. Through the above steps, a multilayer wiring board (multilayer wiring board 113) having a metal frame and having an insulating film made of a resin not filled with reinforcing fibers could be obtained.

[0035]

The multilayer wiring board obtained by the present invention has a metal frame, so even when the insulating film is made of a resin not filled with reinforcing fibers, it has rigidity, so that handling properties can be ensured. Further, the insulation characteristics can be significantly improved. In addition, by conductively connecting the ground wiring pattern to the metal frame, the heat radiation characteristics of the semiconductor device can be significantly improved, and unnecessary radiation from the semiconductor device can be prevented, and high-speed operation can be supported. A multilayer wiring board can be manufactured.

[Brief description of the drawings]

FIG. 1 is a sectional view illustrating an example of a method for manufacturing a multilayer wiring board according to an embodiment of the present invention.

FIG. 2 is a sectional view showing an example of a method for manufacturing a multilayer wiring board according to the embodiment of the present invention (continuation of FIG. 1).

FIG. 3 is a sectional view showing an example of the method for manufacturing a multilayer wiring board according to the embodiment of the present invention (continuation of FIG. 2).

FIG. 4 is a sectional view showing an example of the method for manufacturing a multilayer wiring board according to the embodiment of the present invention (continuation of FIG. 3).

FIG. 5 is a sectional view showing an example of a semiconductor device manufactured using the multilayer wiring board according to the embodiment of the present invention.

[Explanation of symbols]

 REFERENCE SIGNS LIST 101 metal plate 101 a metal plate 101 b metal plate 102 plating resist 103 resist metal layer 104 wiring pattern 105 insulating film 106 via 107 conductor post 108 bonding metal material layer 109 adhesive layer 110 connection layer 111 connected layer 112 bonded part 113 multilayer Wiring board 114a Pad 114b Pad 115 Solder resist 116 Metal frame 117a Outermost layer 117b Outermost layer 118a Resist metal layer 118b Resist metal layer 201 Semiconductor device 202 Semiconductor chip 203 Bump 204 Underfill 205 Solder ball

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H05K 3/46 H01L 23/12 JN (72) Inventor Takeshi August Satoshi 2-Higashishinagawa, Shinagawa-ku, Tokyo No. 5-8 Sumitomo Bakelite Co., Ltd. (72) Inventor Hiroyuki Sawai 2-5-8 Higashishinagawa, Shinagawa-ku, Tokyo Sumitomo Bakelite Co., Ltd. (72) Inventor Masaaki Kato 2-5-Higashishinagawa, Shinagawa-ku, Tokyo No. 8 Sumitomo Bakelite Co., Ltd. (72) Inventor Hideki Hara 2-5-8 Higashishinagawa, Shinagawa-ku, Tokyo Sumitomo Bakelite Co., Ltd. F term (reference) 5E315 AA09 BB01 DD15 DD16 DD17 GG01 5E346 AA03 AA12 AA15 AA32 AA43 CC02 CC04 CC08 CC32 CC33 CC37 CC38 CC39 CC40 CC55 DD03 DD24 EE12 EE15 EE19 FF07 FF08 FF09 FF10 FF14 FF27 GG15 GG26 GG27 GG28 HH01 HH06 HH 11 HH18

Claims (5)

[Claims] A method of manufacturing a multilayer wiring board, comprising: a step of forming a resist metal layer and a wiring pattern by electrolytic plating using a metal plate as a lead for electrolytic plating; and a step of removing the metal plate by etching. Forming a metal frame on the outermost layer of the multilayer wiring board by partially etching and removing a metal plate used for forming the outermost layer on the side on which the semiconductor chip of the multilayer wiring board is mounted; A method for manufacturing a multilayer wiring board, comprising the steps of: 2. A step of forming a resist metal layer and a wiring pattern by electrolytic plating using a metal plate as a lead for electrolytic plating, a step of forming an insulating film on the wiring pattern, and a part of the wiring pattern is exposed. Forming a via in the insulating film, forming a conductive post by electrolytic plating using the metal plate as a lead for electrolytic plating, and forming a conductive post on the surface of the conductive post or the surface of the portion to be joined of the layer to be connected. Forming a bonding metal material layer on at least one of the surfaces, forming an adhesive layer on at least one of the surface of the insulating film and the surface of the connected layer, and forming the conductive post and the bonded portion together. A multi-layer structure including a step of bonding with the bonding metal material layer via an adhesive layer, bonding the insulating film and the layer to be connected with the adhesive layer, and removing the metal plate by etching; A method of manufacturing a wiring board, wherein a metal plate used for forming an outermost layer on a side on which a semiconductor chip of the multilayer wiring board is mounted is partially removed by etching, thereby forming the multilayer wiring board. A method for manufacturing a multilayer wiring board, comprising a step of forming a metal frame on an outer layer. 3. The method for manufacturing a multilayer wiring board according to claim 2, wherein said insulating film is made of a resin not filled with reinforcing fibers. 4. The method for manufacturing a multilayer wiring board according to claim 1, wherein said metal frame is conductively connected to a ground wiring pattern of the multilayer wiring board. 5. A multilayer wiring board obtained by the method for manufacturing a multilayer wiring board according to any one of claims 1 to 4.