JP2003204011A - Multilayer wiring board and manufacturing method there for - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a multilayer wiring board with not only rigidity but also excellent heat radiation characteristics/noise characteristics. <P>SOLUTION: The multilayer wiring board is provided with a stiffener on the outermost layer. The stiffener is composed of a metal frame obtained by partially etching a metal layer as a power feed layer for forming a multilayer wiring pattern of the outermost layer, and a plating film or a resin film covering at least a part of a metal frame surface. Further, the multilayer wiring board is connected by a conductor post. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multilayer wiring board and a method for manufacturing the multilayer wiring board. More specifically, the present invention relates to a multilayer wiring board having a rigid property for mounting a semiconductor chip, and more particularly to a multilayer wiring board for simultaneously performing electrical connection and adhesion between layers and a method for manufacturing the same.

[0002]

2. Description of the Related Art With the recent demand for high functionality, lightness, thinness, shortness, and miniaturization of electronic devices, high-density integration and further high-density mounting of electronic parts have been advanced, and they are used in these electronic devices. Semiconductor packages are becoming smaller and more pins than ever before.

A conventional circuit board is called a printed wiring board, and after patterning a copper foil attached to a glass epoxy board made of a laminated board in which a woven cloth of glass fiber is impregnated with an epoxy resin, a plurality of layers are laminated and laminated. The mainstream method is to use a wiring board that is bonded and drilled with a through hole, and the wall surface of this hole is copper-plated to form a via to electrically connect layers. However, the miniaturization and high densification of mounted components have progressed, and the wiring density of the above-described wiring board is insufficient, causing a problem in mounting components.

Under these circumstances, build-up multilayer wiring boards have been adopted in recent years. The build-up multilayer wiring board is formed by stacking an insulating layer composed only of resin and a conductor. As a method of forming vias, a laser method, a plasma method, a photo method, or the like is used in place of conventional drilling, and a via hole having a small diameter is freely arranged to achieve high density. As the interlayer connection portion, there are a blind via (Blind Via), a buried via (Buried Via: a structure in which a via is filled with a conductor), and the like, and a stacked via hole capable of forming a via on the via is particularly noted. ing. Barry via holes are classified into a method of filling the via holes with plating and a method of filling the via holes with a conductive paste or the like. On the other hand, as a method for forming a wiring pattern, there are a method of etching a copper foil (subtractive method), a method of electrolytic copper plating (additive method), etc. Is being started.

Since a semiconductor package using such a multilayer wiring board has a very large number of pins, the multilayer wiring board is generally larger in size than a semiconductor chip. Therefore, from the viewpoint of handleability of the multilayer wiring board, it is natural that the multilayer wiring board needs to have rigidity. At present, in order to secure the rigid property of a multilayer wiring board, the rigid property of a printed wiring board (a glass epoxy substrate such as FR-4) having an insulating layer in which a reinforcing fiber is impregnated with a resin is used, and both surfaces are used. Build-up layers are laminated. However, a printed wiring board having an insulating layer in which a reinforcing fiber is impregnated with a resin may cause dielectric breakdown at the interface between the reinforcing fiber and the resin, which leaves a problem in the insulating property.

On the other hand, from the viewpoint of handling property of the tape BGA, there is an example in which a stiffener (reinforcing frame) is provided on the tape BGA in order to secure the rigid property of the tape BGA, which allows the solder balls to be mounted smoothly. Will be able to. In addition, polyimide or the like is used for the tape BGA as an insulating layer, that is, the insulating layer is made of a resin not filled with reinforcing fibers, and thus has good insulating properties. However, the tape BGA cannot be used as a super-multi-pin semiconductor package because it is difficult to form multiple layers. In addition, in order to prevent unnecessary radiation of noise and improve heat dissipation characteristics, it is preferable to electrically connect the stiffener to the ground wiring pattern. However, since an adhesive having a high insulating property and a high thermal conductivity is used for bonding the tape BGA and the stiffener, there is a problem in that it is possible to improve the heat radiation characteristics but it is impossible to prevent unnecessary radiation.

[0007]

SUMMARY OF THE INVENTION In view of such problems in a multilayer wiring board on which a semiconductor chip is mounted, the present invention not only has a rigid property but also a multilayer wiring board excellent in heat dissipation characteristics and noise characteristics. The purpose is to provide.

[0008]

Means for Solving the Problems That is, the present invention provides (1)
A multilayer wiring board having a stiffener as an outermost layer, wherein the stiffener has at least one of a metal frame obtained by partially etching a metal layer as a power feeding layer for forming an outermost wiring pattern and a metal frame surface. A multilayer wiring board characterized by comprising a plating coating or a resin coating for covering a portion, (2) the multilayer wiring board according to the above (1), wherein the multilayer wiring boards are interconnected by conductor posts, (3) a multilayer The multilayer wiring board according to the above (1) or (2), wherein the wiring board has an insulating layer made of a resin not filled with reinforcing fibers.
(4) The multilayer wiring board according to any one of (1) to (3), wherein the metal frame is conductively connected to the ground wiring pattern of the multilayer wiring board, and (5) the metal layer for electrolytic plating. The step of forming a wiring pattern by electroplating as a lead and the outermost layer of the multilayer wiring board by partially etching and removing the metal layer as a power supply layer for forming the outermost wiring pattern of the multilayer wiring board A method of manufacturing a multilayer wiring board, comprising: a step of forming a metal frame on top; and a step of forming a plating film or a resin film on at least a part of the surface of the metal frame, (6) Wiring pattern A step of forming an insulating layer on the top, a step of forming a via in the insulating layer so that a part of the wiring pattern is exposed, and a step of forming a conductor post by electrolytic plating using the metal layer as a lead for electrolytic plating. Including The method for manufacturing a multilayer wiring board according to the item (5), (7) comprising a step of adhering a connection layer and a layer to be connected via an adhesive layer, and a step of performing interlayer connection by a conductor post ( (5) or the method for manufacturing a multilayer wiring board according to (6), (8) The multilayer wiring board according to (6) or (7) above, wherein the insulating layer is made of a resin not filled with reinforcing fibers. (9) The metal frame is conductively connected to the ground wiring pattern of the multilayer wiring board,
(10) A method for manufacturing a multilayer wiring board according to any one of (1) to (8), (10) A method for manufacturing a multilayer wiring board according to any of (5) to (9) above. A multilayer wiring board, characterized in that

[0009]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings, but the present invention is not limited thereto.

1 (a) to 4 (s) show a first embodiment of the present invention.
FIG. 4 (s) is a cross-sectional view showing the structure of the obtained multilayer wiring board, which is a view for explaining an example of the method for manufacturing the multilayer wiring board which is the embodiment of FIG.

The method of manufacturing the multilayer wiring board of the present invention includes:
First, a patterned plating resist 102 is formed on the metal layer 101 (FIG. 1A). The plating resist 102 can be formed, for example, by laminating an ultraviolet-sensitive dry film resist on the metal layer 101, selectively exposing it with a negative film or the like, and then developing it. The material of the metal layer 101 may be any material as long as it is suitable for the manufacturing method of the present invention, but in particular, it has resistance to the chemical solution used and can be finally removed by etching. It is necessary to be. Examples of the material of the metal layer 101 include copper, copper alloy, 42 alloy, nickel and the like. Further, the metal layer 101 may have any thickness as long as it is suitable for the manufacturing method of the present invention. Metal layer 1
As 01, a metal plate, a metal foil, or the like can be used. In particular, the 42 alloy plate, the copper plate, the copper alloy plate, and the copper foil are commercially available in various thicknesses, so that they are not only inexpensive and easily available, but also easy to handle. Very suitable for the method.

Next, using the metal layer 101 as a lead for electrolytic plating, a resist metal layer 103 is formed by electrolytic plating (FIG. 1 (b)). By this electroplating, the metal layer 1
A resist metal layer 103 is formed on the area on 01 where the plating resist 102 is not formed. The material of the resist metal layer 103 may be any material as long as it is suitable for the manufacturing method of the present invention. In particular, the resist metal layer 103 has a resistance to a chemical solution used when finally removing the metal layer 101 by etching. It is necessary to have. Examples of the material of the resist metal layer 103 include nickel, gold, tin,
Examples include silver, solder, palladium and the like. The purpose of forming the resist metal layer 103 is to prevent the wiring pattern 104 shown in FIG. 1C from being corroded or corroded by the chemical solution used for etching the metal layer 101. Therefore, the wiring pattern 1 shown in FIG. 1C is used for the chemical solution used for etching the metal layer 101.
When 04 is resistant, this resist metal layer 1
03 is unnecessary. The resist metal layer 103 does not have to have the same pattern as the wiring pattern 104, and before forming the plating resist 102 on the metal layer 101,
The resist metal layer 103 may be formed on the entire surface of the metal layer 101.

Next, the wiring pattern 104 is formed by electrolytic plating using the metal layer 101 as a lead for electrolytic plating (FIG. 1C). By this electrolytic plating, the metal layer 10
The wiring pattern 104 is formed on the portion on which the plating resist 102 is not formed. Wiring pattern 1
As the material of 04, any material may be used as long as it is suitable for the manufacturing method of the present invention, but in particular, it has resistance to a chemical solution used when finally removing the resist metal layer 103 by etching. It is necessary. In practice, it is a good idea to select a material for the resist metal layer 103 that can be etched with a chemical solution that does not corrode or corrode the wiring pattern 104. Examples of the material of the wiring pattern 104 include copper, nickel, gold, tin, silver, palladium and the like. Furthermore, by using copper, a stable wiring pattern 104 with low electric resistance can be obtained.

Next, the plating resist 102 is removed (FIG. 1D), and the insulating layer 1 is formed on the formed wiring pattern 104.
05 is formed (FIG. 1E). As the resin forming the insulating layer 105, any resin can be used as long as it is suitable for the manufacturing method of the present invention. In particular, reinforcing fibers (eg,
It is preferable to form the insulating layer 105 made of a glass cloth) unfilled resin. The method for forming the insulating layer 105 may be a method suitable for the resin used, for example, a resin varnish may be directly applied by a method such as printing, curtain coating or bar coating, or a dry film type resin may be vacuum laminated,
A method of laminating by a method such as vacuum pressing may be used. In particular, a commercially available resin-coated copper foil is easily available. If the copper foil with resin is formed by vacuum laminating while embedding the unevenness of the wiring pattern 104, and the copper foil is finally etched, the surface of the insulating layer 105 becomes the wiring pattern 104. It becomes very flat without being affected by irregularities. Further, since the fine roughened shape of the copper foil surface is transferred to the surface of the insulating layer 105,
Adhesion with the adhesive layer 109 shown in FIG. 2 (i) can be secured.

Next, a via 106 is formed in the formed insulating layer 105.
Are formed (FIG. 1 (f)). The via 106 is formed by
Any method may be used as long as it is suitable for the manufacturing method of the present invention, and examples thereof include dry etching with laser and plasma, and chemical etching. Further, when the insulating layer 105 is made of a photosensitive resin, the via 106 can be formed by selectively exposing the insulating layer 105 to light and developing it.

Next, the conductor post 107 is formed by electrolytic plating using the metal layer 101 as a lead for electrolytic plating (FIG. 1 (g)). By this electrolytic plating, the insulating layer 105
Of the conductor post 10 at the portion where the via 106 of
7 is formed. If the conductor post 107 is formed by electrolytic plating, the shape of the tip of the conductor post 107 can be freely controlled. The conductor post 107 may be made of any material as long as it is suitable for the manufacturing method of the present invention, and examples thereof include copper, nickel, gold, tin, silver and palladium. Furthermore, by using copper, a stable conductor post 107 with low electric resistance can be obtained.

Next, the surface (tip) of the conductor post 107.
The metal material layer for bonding 108 is formed on the surface (FIG. 2).
(H)). Examples of the method of forming the bonding metal material layer 108 include a method of forming by electroless plating, a method of forming the metal layer 101 as a lead for electrolytic plating by electrolytic plating, and a method of printing a paste containing a bonding metal material. To be In the printing method, it is necessary to accurately align the printing mask with the conductor post 107. However, in the electroless plating method or the electrolytic plating method, the bonding metal material layer 108 is formed on the surface other than the surface of the conductor post 107. Therefore, the conductor post 107 is miniaturized.
Easy to handle high density. In particular, the electrolytic plating method is very suitable because it has a wider variety of metals that can be plated and the chemical solution is easier to manage than the electroless plating method. The material of the joining metal material layer 108 may be any metal as long as it can be metal-joined to the joined portion 112 shown in FIG. 2 (j).
Solder is an example. Among solders, Sn or In, or Sn, Ag, Cu, Zn, Bi, Sb, Pb, In,
It is preferable to use solder composed of at least two kinds of Au. More preferably, it is an environment-friendly Pb-free solder. Although FIG. 2H shows an example in which the bonding metal material layer 108 is formed on the surface of the conductor post 107,
Since the purpose of forming the joining metal material layer 108 is to join the conductor post 107 and the joined portion 112 by metal, the joining metal material layer 108 may be formed on the joined portion 112. Of course, it may be formed on both surfaces of the conductor post 107 and the joined portion 112. Further, there is a method of forming the conductor post 107 itself with a bonding metal material, but in that case, it is not necessary to form the bonding metal material layer 108. The various configurations of the conductor post 107 and the bonding metal material layer 108 as described above are included in the present invention.

Next, the adhesive layer 1 is formed on the surface of the insulating layer 105.
09 is formed (FIG. 2 (i)). The adhesive layer 109 may be formed by a method suitable for the adhesive resin used, for example, a resin varnish may be directly applied by a method such as printing, curtain coating or bar coating, or a dry film type resin may be vacuum laminated, A method of laminating by a method such as vacuum pressing may be used. 2 (i) shows an example in which the adhesive layer 109 is formed on the surface of the insulating layer 105, the connected layer 11
The adhesive layer 109 may be formed on the surface of No. 1. Of course, it may be formed on both surfaces of the insulating layer 105 and the layer to be connected 111.

Next, the connection layer 1 obtained by the above steps
10 and the layer to be connected 111 are aligned (see FIG. 2).
(J)). The alignment can be performed by a method of aligning the positioning marks formed in advance on the connecting layer 110 and the layer to be connected 111 with an image recognition device, a method of aligning with a pin for alignment, or the like. The connected layer 111 shown in FIG.
It can be obtained by the steps similar to the steps shown in (a) to FIG.

Next, the connection layer 110 and the layer to be connected 111 are laminated (FIG. 2 (k)). As a stacking method, for example,
Using a vacuum press, the conductor posts 107 are bonded to the adhesive layer 1
09, pressure is applied until the metal is joined to the joined portion 112 by the joining metal material layer 108, and further heating is performed to cure the adhesive layer 109, so that the connection layer 110 and the connected layer 111.
And can be glued together.

Next, the metal layer 101 of the connection layer 110 is removed by etching (FIG. 2 (l)). A resist metal layer 103 is formed between the metal layer 101 and the wiring pattern 104, and the resist metal layer 103 is the metal layer 1
Since the resist metal layer 103 is resistant to a chemical solution used for removing 01 by etching, the resist metal layer 103 is not corroded or corroded even when the metal layer 101 is etched, and as a result, the wiring pattern 104 is formed. Is not eroded or corroded. When the material of the metal layer 101 is copper and the material of the resist metal layer 103 is nickel, tin, or solder, a commercially available ammonia-based etching solution can be used. When the material of the metal layer 101 is copper and the material of the resist metal layer 103 is gold or silver, most etching solutions including a ferric chloride solution and a cupric chloride solution can be used.

Next, the resist metal layer 103 is removed by etching (FIG. 3 (m)). Wiring pattern 104
Has resistance to a chemical solution used when removing the resist metal layer 103 by etching, so that the wiring pattern 104 is not corroded or corroded. for that reason,
By removing the resist metal layer 103, the wiring pattern 104 is exposed. When the material of the wiring pattern 104 is copper and the material of the resist metal layer 103 is nickel, tin, or solder, a commercially available solder / nickel release agent (for example, Pewtax manufactured by Mitsubishi Gas Chemical Co., Inc.) can be used. The material of the wiring pattern 104 is copper, and the resist metal layer 1
When the material of 03 is gold, it is difficult to etch the resist metal layer 103 without eroding / corroding the wiring pattern 104. In this case, the step of etching the resist metal layer 103 may be omitted and the resist metal layer 103 may be left as it is.

Then, the above-mentioned steps, that is, FIG.
By repeating FIG. 3M, it is possible to obtain another multilayer wiring board 113a which is in the process of being manufactured (see FIG. 3M) and is laminated by another layer (FIG. 3).
(N)).

The steps shown in FIGS. 3 (o) to 3 (p) are diagrams for explaining the step of forming the outermost layer 117a of the multilayer wiring board 113a. The steps shown in FIGS. 3 (o) to 3 (p) are similar to the steps shown in FIGS. 2 (j) to 2 (k).
The connection layer and the layer to be connected are aligned (FIG. 3 (o)), and the connection layer and the layer to be connected are laminated (FIG. 3 (p)).

Next, the semiconductor chip 20 of the metal layer 101b
2 is removed by etching to form a metal frame 120a (FIG. 4 (q)).
Forming a plating film 121a on the surface of the
(R)). As a result, the outermost layer 1 of the multilayer wiring board 113a is
The stiffener 122a is formed on the surface of 17a. The purpose of forming the plating film 121a is a rust preventive film when the metal frame 120a is made of a material that easily corrodes, such as copper or a copper alloy, or a protective film against damage due to contact. Examples of the method for forming the plating film 121a include a method using electroless plating and a method using electrolytic plating. In either method, it is preferable to perform a plating after applying a protective mask or the like so that the plating film is not formed on the pad 114a. Plating film 121
Examples of the material of a include gold, silver, palladium, chromium, nickel, solder and tin.

The multilayer wiring board 113a is the stiffener 122a.
With the above, even when the insulating layer 105 is made of a resin not filled with reinforcing fibers (for example, glass cloth), the multilayer wiring board 113a has a rigid property. The insulating layer 105a is directly coated with a resin varnish by a method such as printing, curtain coating, or bar coating, or a dry film type resin is laminated by a method such as vacuum lamination or vacuum pressing to directly form a metal layer. 101
The insulating layer 105a and the metal frame 120a are formed on the insulating layer 105a.
Adhesion with

Finally, the metal layer 101a is completely removed by etching, the solder resist 115 is formed on the surface of the outermost layer 117b, and the pad 114b is opened to obtain the multilayer wiring board 113a (see FIG. Four
(S)). When the wiring pattern is not formed on the outermost layer 117b and only the pad 114b is formed, it is not necessary to form the solder resist 115. The same applies to the other outermost layer 117a.
In the case of FIG. 4 (s), since only the pad 114a is formed, it is not necessary to form the solder resist. Further, it is not necessary to remove the resist metal layers 118a and 118b used when forming the outermost layers 117a and 117b. That is, the resist metal layers 118a and 118b
Are pads 1 formed on both surfaces of the multilayer wiring board 113a.
It is used as an outer layer plating film applied to 14a and 114b. The material of the resist metal layers 118a and 118b is gold,
Examples include silver, palladium, nickel, solder, gold,
The layer structure may include any two or more of silver, palladium, and nickel. In addition, when the wiring pattern 104 is made of copper, two of gold and nickel are used.
A layered structure is preferable. As a result, the pads 114a, 1
It is possible to prevent the solder of the solder balls mounted on 14b from diffusing into the copper of the wiring pattern 104. Furthermore, by conductively connecting the metal frame 120a to the ground wiring pattern 119 of the multilayer wiring board 113a, not only unnecessary radiation of noise from the semiconductor device 201 can be reduced but also the heat dissipation characteristic of the semiconductor device 201 is improved. be able to.

Through the above steps, the stiffener 122a is attached to the side of the multilayer wiring board 113a on which the semiconductor chip 202 is mounted.
It is possible to manufacture a multilayer wiring board having

Next, a method of manufacturing a multilayer wiring board according to a second embodiment of the present invention will be described in detail with reference to FIG. 5 (q ′) to (s ′) show the second embodiment of the present invention.
FIG. 5A is a cross-sectional view for explaining the method for manufacturing the multilayer wiring board of FIG. 4, for explaining the process performed in place of FIGS. 4 (q) to 4 (s). Therefore, here, a part different from the manufacturing method of the first multilayer wiring board will be described in detail, and the description of the same part will be basically omitted.

In FIG. 5 (q '), a plating film 121b is formed on the surface of the metal layer 101b. Plating film 12
Examples of the method of forming 1b include a method by electroless plating and a method by electrolytic plating. For electroplating,
Electroplating can be performed by using the metal layer 101b as a lead for electrolytic plating to form the plated coating 121b. When the plating film 121b is formed by electrolytic plating or electroless plating, a plating resist (not shown) is formed so that the plating film 121b is formed only in a necessary portion, and the plating resist is formed after the plating is completed. Of course, it needs to be removed.

Next, in FIG. 5 (r '), the metal layer 101b is etched by using the plating film 121b as an etching mask to form the metal frame 120b. Finally, in FIG. 5 (s ′), the multilayer wiring board 113b can be obtained by etching the metal layer 101c and forming the solder resist 115.

In FIG. 5 (q '), even if the plating film 121b is changed to a resin film, it is effective as a rust preventive treatment for the metal frame 120b. Examples of the method for forming the resin film include a printing method and a method using a photosensitive resin.

The characteristics of the method for manufacturing a multilayer wiring board and the manufactured multilayer wiring board according to the present invention are as follows. (1) The metal frames 120a and 120b can be formed by partially etching the metal layer 101b used during manufacturing. (2) The stiffener 12 is the multilayer wiring boards 113a and 113b.
By including 2a and 122b, even when the insulating layer 105 is made of a resin not filled with reinforcing fibers (for example, glass cloth), the multilayer wiring boards 113a and 113b have rigidity. (3) The metal frames 120a and 120b are connected to the multilayer wiring board 113.
By conductively connecting to the ground wiring pattern 119 of a and 113b, not only unnecessary radiation of noise from the semiconductor device 201 can be reduced, but also the heat dissipation characteristic of the semiconductor device 201 can be improved.

The solder bumps 203 are formed on the pads 114a of the multilayer wiring board 113a obtained by the above process.
The semiconductor device 201 can be obtained by mounting the semiconductor chip 202 and the semiconductor chip 202, providing the underfill 204 in the gap between the multilayer wiring board 113a and the semiconductor chip 202, and mounting the solder ball 205 on the pad 114b side (FIG. 6).

[0035]

EXAMPLES Hereinafter, the present invention will be described in more detail by way of examples, but the present invention is not limited thereto.

Preparation Example of Adhesive m, p-cresol novolac resin (P manufactured by Nippon Kayaku Co., Ltd.)
100 g of AS-1, OH group equivalent 120) and bisphenol F type epoxy resin (RE-404 manufactured by Nippon Kayaku Co., Ltd.)
140 g of S and epoxy group equivalent 165) are dissolved in 60 g of cyclohexanone, and 0.2 g of triphenylphosphine (manufactured by Kitako Chemical Industry Co., Ltd.) is added as a curing catalyst.
An adhesive varnish was prepared.

Example (Production Example of Multilayer Wiring Board) A surface-roughened rolled copper sheet having a thickness of 150 μm (metal layer 1)
01. Furukawa Electric Co., Ltd. EFTEC-64T) is roll-laminated with a dry film resist (AQ-2058 manufactured by Asahi Kasei), exposed and developed using a predetermined negative film, and a plating resist (plating required for forming the wiring pattern 104 A resist 102) was formed. Next, using a rolled copper plate as a lead for electrolytic plating, a resist metal layer (resist metal layer 103) made of nickel was formed by electrolytic plating, and a wiring pattern (wiring pattern 104) was further formed by electrolytic copper plating. Wiring pattern is line width /
Line spacing / thickness = 20 μm / 20 μm / 10 μm. Next, a resin-coated copper foil (APL manufactured by Sumitomo Bakelite) was formed by vacuum lamination while embedding irregularities in the wiring pattern, and the entire surface of the copper foil was etched to form a 25 μm thick insulating layer (insulating layer 105). Next, a via having a diameter of 50 μm (via 106) was formed by a UV-YAG laser. Next, using the rolled copper plate as a lead for electrolytic plating, the via was filled with copper by electrolytic copper plating to form a copper post (conductor post 107). Next, using a rolled copper plate as a lead for electrolytic plating, Sn-P was deposited on the copper posts by electrolytic plating.
A eutectic solder layer (bonding metal material layer 108) was formed.
Then, the above-mentioned adhesive varnish is applied to the surface of the insulating layer, that is, the surface on which the Sn-Pb eutectic solder is formed, by bar coating, and then dried at 80 ° C for 20 minutes to obtain a 10 μm thick adhesive layer ( The adhesive layer 109) was formed. The build-up layer (connection layer 110) was obtained by the steps so far. On the other hand, similarly to the above process, a resist metal layer (resist metal layer 118b) is formed on the rolled copper plate by electrolytic nickel / gold plating, and a wiring pattern is further formed by electrolytic copper plating, and a land (bonded portion 112) is formed. A layer to be connected (layer to be connected 111) was obtained. Next, the positioning marks formed in advance on the build-up layer and the layer to be connected, which were obtained in the above steps, were read by an image recognition device, the both were aligned, and temporary pressure bonding was performed at a temperature of 100 ° C. This is heated and pressed at a temperature of 220 ° C. by a press, and the copper posts are
The buildup layer was bonded to the layer to be connected by the adhesive layer by soldering to the land through the adhesive layer. Next, the rolled copper plate of the build-up layer was etched and removed using an ammonia-based etching solution, and the nickel was removed by etching using a solder / nickel release agent (Pewtax manufactured by Mitsubishi Gas Chemical Co., Inc.). Further, the above steps were repeated to stack another buildup layer. However, the resist metal layers (resist metal layers 118a and 118b) used when forming the outermost layers (outermost layers 117a and 117b) had a two-layer structure of nickel / gold. Then, the rolled copper plate on which the semiconductor chip is mounted is etched to form a metal frame (metal frame 120a), and a gold film (plating film 121a) is formed by electrolytic gold plating to form a multilayer wiring board (multilayer wiring). A stiffener (stiffener 122a) was formed on the outermost layer of the plate 113a). Finally, the rolled copper plate on the layer to be connected side was etched to completely remove it, and then a solder resist (solder resist 115) was formed. Through the above steps, a multilayer wiring board having a stiffener and an insulating layer made of a resin not filled with reinforcing fibers could be obtained.

[0038]

Since the multilayer wiring board obtained by the present invention has the stiffener, even if the insulating layer is made of the resin not filled with the reinforcing fiber, it has the rigid property and therefore the handling property can be secured. Can significantly improve the insulation characteristics. Further, by conductively connecting the ground wiring pattern to the metal frame, the heat dissipation characteristics of the semiconductor device can be greatly improved, and further, unnecessary radiation from the semiconductor device can be prevented and high speed operation can be supported. A multilayer wiring board can be manufactured.

[Brief description of drawings]

FIG. 1 is a sectional view showing an example of a method for manufacturing a multilayer wiring board according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view showing an example of a method for manufacturing a multilayer wiring board according to an embodiment of the present invention (sequel to FIG. 1).

FIG. 3 is a cross-sectional view showing an example of a method for manufacturing a multilayer wiring board according to an embodiment of the present invention (sequel to FIG. 2).

FIG. 4 is a cross-sectional view showing an example of a method for manufacturing a multilayer wiring board according to an embodiment of the present invention (sequel to FIG. 3).

FIG. 5 is a cross-sectional view showing another example of the method for manufacturing the multilayer wiring board according to the embodiment of the present invention.

FIG. 6 is a sectional view showing an example of a semiconductor device manufactured using the multilayer wiring board according to the embodiment of the present invention.

[Explanation of symbols]

101, 101a, 101b Metal layer 102 plating resist 103, 118a, 118b Resist metal layer 104 wiring pattern 105 insulating layer 106 vias 107 Conductor post 108 Metal Material Layer for Bonding 109 adhesive layer 110 connection layer 111 Connected layer 112 Joined part 113a, 113b Multilayer wiring board 114a, 114b pads 115 Solder resist 117a, 117b Outermost layer 120a, 120b metal frame 121a, 121b plating film 122a, 122b stiffener 201 Semiconductor device 202 semiconductor chips 203 bump 204 underfill 205 solder ball

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) H05K 3/46 H01L 23/12 NF term (reference) 5E338 AA03 AA16 BB03 BB19 BB63 BB72 CC01 CC04 CC06 CD11 EE02 EE13 EE26 5E346 AA01 AA11 AA12 AA15 AA43 AA60 BB02 BB03 BB04 BB06 CC08 CC32 CC54 DD03 DD24 EE31 FF14 FF35 FF36 GG15 GG17 GG22 GG28 HH01 HH11 HH17

Claims (10)

[Claims] 1. A multi-layer wiring board having a stiffener as an outermost layer, wherein the stiffener has a metal frame obtained by partially etching a metal layer as a power feeding layer for forming an outermost wiring pattern, and a metal. A multilayer wiring board comprising a plating coating or a resin coating covering at least a part of the frame surface. 2. The multilayer wiring board according to claim 1, wherein the multilayer wiring boards are interconnected by conductor posts. 3. The multilayer wiring board according to claim 1 or 2, wherein the multilayer wiring board has an insulating layer made of a resin not filled with reinforcing fibers. 4. The multilayer wiring board according to claim 1, wherein the metal frame is electrically connected to the ground wiring pattern of the multilayer wiring board. 5. A step of forming a wiring pattern by electrolytic plating using the metal layer as a lead for electrolytic plating, and a step of partially etching the metal layer as a power supply layer for forming the outermost wiring pattern of the multilayer wiring board. By removing, a multilayer including a step of forming a metal frame on the outermost layer of the multilayer wiring board and a step of forming a plating film or a resin film on at least a part of the surface of the metal frame. Wiring board manufacturing method. 6. A step of forming an insulating layer on a wiring pattern, a step of forming a via in the insulating layer so that a part of the wiring pattern is exposed, an electroplating of a conductor post using a metal layer as a lead for electrolytic plating. The method for manufacturing a multilayer wiring board according to claim 5, further comprising the step of forming by plating. 7. The method for manufacturing a multilayer wiring board according to claim 5, further comprising a step of adhering the connection layer and the layer to be connected via an adhesive layer, and a step of connecting the layers by a conductor post. 8. The method for manufacturing a multilayer wiring board according to claim 6, wherein the insulating layer is made of a resin not filled with reinforcing fibers. 9. The method for manufacturing a multilayer wiring board according to claim 5, wherein the metal frame is conductively connected to the ground wiring pattern of the multilayer wiring board. 10. A multilayer wiring board obtained by the method for manufacturing a multilayer wiring board according to claim 5.