WO2003100851A1 - Semiconductor device mounting board, method for producing the same, method for inspecting board, and semiconductor package - Google Patents

Semiconductor device mounting board, method for producing the same, method for inspecting board, and semiconductor package Download PDF

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Publication number
WO2003100851A1
WO2003100851A1 PCT/JP2003/006526 JP0306526W WO03100851A1 WO 2003100851 A1 WO2003100851 A1 WO 2003100851A1 JP 0306526 W JP0306526 W JP 0306526W WO 03100851 A1 WO03100851 A1 WO 03100851A1
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WO
WIPO (PCT)
Prior art keywords
forming
electrode pattern
semiconductor device
insulator film
metal support
Prior art date
Application number
PCT/JP2003/006526
Other languages
French (fr)
Japanese (ja)
Inventor
Katsumi Kikuchi
Tadanori Shimoto
Kazuhiro Baba
Original Assignee
Nec Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nec Corporation filed Critical Nec Corporation
Publication of WO2003100851A1 publication Critical patent/WO2003100851A1/en
Priority to US10/975,061 priority Critical patent/US7474538B2/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/16—Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68345—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during the manufacture of self supporting substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05568—Disposition the whole external layer protruding from the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05573—Single external layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16235—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a via metallisation of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01019—Potassium [K]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01046—Palladium [Pd]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01057—Lanthanum [La]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor

Definitions

  • the present invention relates to a semiconductor device mounting substrate, a method for manufacturing the same, a method for detecting the substrate, and a semiconductor package
  • the present invention relates to a semiconductor device mounting board used for mounting various devices such as a semiconductor device at a high density and realizing a high-density and high-speed high-frequency module or system, a manufacturing method thereof, a board inspection method thereof, (5) Related to semiconductor packages.
  • Conventional technology such as a semiconductor device at a high density and realizing a high-density and high-speed high-frequency module or system, a manufacturing method thereof, a board inspection method thereof, (5) Related to semiconductor packages.
  • mounting substrates that are often used include a ceramic substrate, a build-up substrate, and a tape substrate.
  • the ceramic substrate is composed of an insulating substrate made of alumina or the like and a wiring made of a high melting point such as W or Mo formed on the surface, as disclosed in Japanese Patent Application Laid-Open No. 8-330474. And a conductor.
  • the build-up substrate is formed by using an organic resin as an insulating material on a printed circuit board. It is used to form a fine circuit with copper wiring by etching and plating to form a multilayer structure.
  • the tape substrate is formed by forming a copper wiring on a polyimide-based film or the like disclosed in Japanese Patent Application Laid-Open No. 2000-58701. Problems to be solved by the invention
  • the ceramic substrate has a problem in that the ceramic constituting the insulating substrate is hard and brittle, so that damage such as chipping and cracking is likely to occur in the manufacturing process and the transport process, and the yield is reduced.
  • the ceramic substrate is manufactured by printing wiring on a green sheet before firing, laminating each sheet, and firing.
  • the fired substrate has a problem that shape defects such as warpage, deformation, and dimensional variation are likely to occur. Due to the occurrence of such a shape defect, there is a problem that it is not possible to sufficiently cope with the strict flatness required for a substrate such as a high-density circuit board and a flip chip. That is, such a shape defect hinders the increase in the number of pins, the density, and the miniaturization of the circuit, and the flatness of the mounting portion of the semiconductor device is lost. There is a problem that cracks and peeling are apt to occur in the connected portions, and the reliability of the semiconductor device is reduced.
  • the substrate is warped due to the difference in thermal expansion between the print substrate used for the core material and the insulating resin film formed on the surface layer.
  • This warping also becomes an obstacle when connecting semiconductor devices with a large number of pins, and as described above, hinders circuit densification and miniaturization, and also reduces the yield of build-up substrates.
  • the present invention has been made in view of the above problems, and can improve a conventional wiring board, realize high density and miniaturization corresponding to a narrow pitch, and have excellent mounting reliability. It is an object of the present invention to provide a semiconductor device mounting substrate, a method of manufacturing the same, a method of inspecting the substrate, and a semiconductor package. Disclosure of the invention
  • the present invention employs the following semiconductor device mounting substrate, a method of manufacturing the same, a method of inspecting the substrate, and a semiconductor package.
  • the electrode pattern is provided on one side, the periphery of the side of the electrode pattern is in contact with the insulating layer, and at least the lower surface of the electrode pattern is provided without being in contact with the insulating layer, and the insulating layer surface and the electrode pattern lower surface are on the same plane.
  • a first electrode pattern (13) including an insulating layer (14) and a wiring layer (15) alternately stacked, and an electrode pattern is formed of the wiring structure film.
  • the electrode pattern is provided on one side, the periphery of the side of the electrode pattern is in contact with the insulating layer, and at least the lower surface of the electrode pattern is provided without being in contact with the insulating layer, and the insulating layer surface and the electrode pattern lower surface are on the same plane.
  • a first electrode pattern (13) including an insulating
  • An insulator film (12) provided with an opening pattern located below the first electrode pattern
  • each layer of the wiring layer (15) is connected to each other via a via provided in the insulating layer (14),
  • the second electrode pattern (17) is connected to the first electrode pattern (13) via the wiring layer (15) and the via. Sign.
  • a conductor pattern (18) is provided between and around the first electrode pattern (13), and the conductor pattern (18) is provided on the wiring layer. (15) and is connected by the via.
  • the metal support (11) and the conductor pattern (18) are connected by a via (19) formed in the insulator film (12). It is characterized by having been done.
  • the insulating layer (14) has a film strength of 70 MPa or more, a breaking elongation of 5% or more, a glass transition temperature of 150 ° C or more, and heat. It is characterized by being made of an insulating material having an expansion coefficient of 60 ppm / ° C or less.
  • the insulating layer (14) has an elastic modulus of 10 GPa or more, a thermal expansion coefficient of 30 ppm / ° C or less, and a glass transition temperature of 150 °. It is characterized by being made of an insulating material of C or more. Furthermore, the semiconductor device mounting substrate according to claim 7 is characterized in that the insulator film (12) has a function as a solder resist. Further, the semiconductor device mounting substrate according to claim 8 is characterized in that the insulator film (12) is made of the same material as the insulating layer (14).
  • the semiconductor device mounting board further comprising: a dielectric layer (20) formed on an upper surface of the first electrode pattern (13); and a wiring formed on an upper surface of the dielectric layer (20).
  • a capacitor (22) comprising a structural film (16) and a conductive layer (21) in conduction is provided.
  • the metal support (11) is at least one metal selected from the group consisting of stainless steel, iron, nickel, and copper aluminum. Or an alloy thereof.
  • the metal support (11) is provided on the entire lower surface of the insulator film (12), and the first electrode pattern (13) is provided. And a projection (24) that is in contact with the substrate.
  • the protrusion (24) is formed by one or a combination of plating, etching, conductive paste, and machining.
  • a semiconductor package according to a fifteenth aspect is characterized in that at least one semiconductor device is mounted on the semiconductor device mounting substrate according to any one of the first to fourteenth aspects. I do.
  • a semiconductor package according to claim 16 is characterized in that a semiconductor device is mounted on at least one surface.
  • the semiconductor package according to claim 17 is characterized in that the semiconductor device is flip-chip connected by using any one of a low melting point metal and a conductive resin.
  • the method for manufacturing a semiconductor device mounting substrate according to claim 19 includes a step of forming a plurality of projections (24) at desired positions on the surface of the metal support (11).
  • the method includes a step of adjusting the shape of the opening of the insulator film. Also, the method for manufacturing a semiconductor device mounting substrate according to claim 20 includes a step of forming a plurality of projections (24) at desired positions on the surface of the metal support (11);
  • first electrode pattern (13) on the insulator film; forming a conductor pattern (18) between and around the first electrode pattern;
  • the method includes a step of adjusting the shape of the opening of the insulator film.
  • the method includes a step of adjusting the shape of the opening of the insulator film.
  • a method of manufacturing a semiconductor device mounting substrate according to claim 22 is characterized in that the first electrode pattern and the conductor pattern are formed in the same step.
  • the method further comprises a step of forming a thin film capacitor on at least one of the first electrode patterns.
  • a concave portion (29) is formed in a region where the first opening is to be formed. It is characterized by having a step of performing.
  • the method for manufacturing a semiconductor device mounting substrate according to claim 25, comprises a step of forming a plurality of protrusions (24) at desired positions on both surfaces of the metal support (11);
  • first electrode pattern (13) Forming a first electrode pattern (13) on the insulator film; and contacting a periphery of a side surface of the first electrode pattern (13), and a lower surface of the first electrode pattern (13).
  • the method includes a step of adjusting the shape of the opening of the insulator film.
  • first electrode pattern (13) on the insulator film; forming a conductor pattern (18) between and around the first electrode pattern;
  • the method includes a step of adjusting the shape of the opening of the insulator film.
  • the method includes a step of adjusting the shape of the opening of the insulator film. Further, the method of manufacturing a semiconductor device mounting substrate according to claim 28, comprises bonding two first and second metal supports,
  • the first and second metal supports are in contact with the periphery of the side surface of each first electrode pattern (13), and the lower surface is flush with the lower surface of the first electrode pattern (13).
  • the method includes a step of adjusting the shape of the opening of the insulator film. Also, the method for manufacturing a semiconductor device mounting board according to claim 29 includes a step of bonding two first and second metal supports,
  • the first and second metal supports are in contact with the periphery of the side surface of each first electrode pattern (13), and the lower surface is flush with the lower surface of the first electrode pattern (13).
  • the method includes a step of adjusting the shape of the opening of the insulator film. Further, the method for manufacturing a semiconductor device mounting substrate according to claim 30 includes a step of bonding two first and second metal supports,
  • the conductor pattern (18) is provided between and around the first electrode patterns on the first and second metal supports and so that the conductor pattern (18) can be connected to the metal support by the via. )
  • the first and second metal supports are in contact with the periphery of the side surface of each first electrode pattern (13), and the lower surface is flush with the lower surface of each first electrode pattern (13).
  • the insulator film and the protrusion are exposed on the first and second metal supports. Forming a first opening to project out;
  • a step of adjusting the shape of the opening of the insulator film The method of manufacturing a semiconductor device mounting substrate according to claim 31, wherein the first opening is formed before the step of bonding the first and second metal supports (11 a, lib). Forming a concave portion (29) in a region where a portion is to be formed.
  • the method of manufacturing a semiconductor device mounting substrate according to claim 32 further comprising: forming the first electrode pattern (13); and forming a wiring structure on the first electrode pattern.
  • a step of forming a thin film capacitor on at least one of the first electrode patterns is provided.
  • the method for manufacturing a semiconductor device mounting substrate according to claim 33 includes a step of forming a solder ball or a connection pin so that the first electrode pattern is connected at a desired position of the second electrode pattern. It is characterized.
  • the metal support is at least one metal selected from the group consisting of stainless steel, iron, nickel, copper, and aluminum. It is characterized by being made of the alloy.
  • the projection is formed by one or a combination of plating, etching, conductive paste, and machining. It is characterized by that.
  • a method for manufacturing a semiconductor package according to claim 36 is characterized in that at least one surface of the semiconductor device mounting substrate manufactured by the method according to any one of claims 19 to 35 is provided with a semiconductor device. Are connected.
  • the semiconductor device is characterized in that the semiconductor device is made of a material having a low melting point or a conductive resin. It is characterized by being chip-connected.
  • the method for inspecting a semiconductor device mounting substrate according to claim 38 is a method for inspecting a semiconductor mounting substrate manufactured by the method according to any one of claims 19 to 35. After an electrode pattern is formed and the metal support is selectively removed, continuity detection is performed using the contact terminal without removing the protrusion.
  • FIG. 1A and 1B are diagrams showing a first embodiment of a semiconductor device mounting substrate and a semiconductor package according to the present invention, wherein FIG. 1A is a schematic sectional view, and FIG. FIG.
  • FIG. 2 is a schematic sectional view showing a modified example of the first embodiment of the semiconductor device mounting board and the semiconductor package of the present invention.
  • FIG. 3 is a schematic sectional view showing a flat conductor device mounting substrate and a semiconductor package according to a second embodiment of the present invention.
  • FIG. 4 is a schematic cross-sectional view showing a modification of the second embodiment of the semiconductor device mounting board and the semiconductor package of the present invention.
  • FIG. 5 is a schematic cross-sectional view showing a third embodiment of the semiconductor device mounting board and the semiconductor package of the present invention.
  • FIG. 6 is a schematic sectional view showing a semiconductor device mounting board and a semiconductor package according to a fourth embodiment of the present invention.
  • FIG. 7 is a schematic sectional view showing a modified example of the fourth embodiment of the semiconductor device mounting board and the semiconductor package of the present invention.
  • FIG. 8 is a schematic sectional view showing a semiconductor device mounting substrate and a semiconductor package according to a fifth embodiment of the present invention.
  • FIG. 9 is a partial cross-sectional view illustrating a first embodiment of a method for manufacturing a semiconductor device mounting board and a semiconductor package according to the present invention.
  • FIG. 10 is a partial cross-sectional view showing a second embodiment of a method for manufacturing a semiconductor device mounting substrate and a semiconductor package according to the present invention.
  • FIG. 11 is a partial cross-sectional view showing a modification of the second embodiment of the method for manufacturing a semiconductor device mounting board and a semiconductor package of the present invention.
  • FIG. 12 is a partial cross-sectional view showing a third embodiment of the method for manufacturing a semiconductor device mounting board and a semiconductor package according to the present invention.
  • FIG. 13 is a partial cross-sectional view showing a modification of the third embodiment of the method for manufacturing a semiconductor device mounting board and a semiconductor package of the present invention.
  • FIG. 14 is a partial cross-sectional view showing a fourth embodiment of the method for manufacturing a semiconductor device mounting board and a semiconductor package according to the present invention.
  • FIG. 15 is a partial cross-sectional view showing a fifth embodiment of the method for manufacturing a semiconductor device mounting board and a semiconductor package according to the present invention.
  • FIG. 16 is a partial cross-sectional view showing a sixth embodiment of the method for manufacturing a semiconductor device mounting board and a semiconductor package of the present invention.
  • FIG. 17 is a partial cross-sectional view showing a seventh embodiment of a method for manufacturing a semiconductor device mounting board and a semiconductor package according to the present invention.
  • FIG. 18 is a partial cross-sectional view showing an eighth embodiment of a method for manufacturing a semiconductor device mounting board and a semiconductor package according to the present invention.
  • FIG. 19 is a partial cross-sectional view showing a ninth embodiment of a method for manufacturing a semiconductor device mounting board and a semiconductor package according to the present invention.
  • FIG. 20 is a partial cross-sectional view showing a modification of the ninth embodiment of the method of manufacturing a semiconductor device mounting board and a semiconductor package of the present invention.
  • FIG. 21 is a partial cross-sectional view showing a modification of the ninth embodiment of the method for manufacturing a semiconductor device mounting board and a semiconductor package of the present invention.
  • FIG. 22 is a partial cross-sectional view showing a tenth embodiment of a method for manufacturing a semiconductor device mounting board and a semiconductor package of the present invention.
  • FIG. 23 is a partial cross-sectional view showing a modification of the tenth embodiment of the method for manufacturing a semiconductor device mounting board and a semiconductor package of the present invention.
  • FIG. 24 is a partial cross-sectional view for explaining the method of inspecting a semiconductor mounting board according to the present invention.
  • Reference numeral 11 denotes a metal support.
  • Reference numeral 11a is a metal support.
  • Reference numeral 11b is a metal support.
  • Reference numeral 12 denotes an insulator film.
  • Reference numeral 13 is a first electrode pattern.
  • Reference numeral 14 denotes an insulating layer.
  • Reference numeral 15 is a wiring layer.
  • Reference numeral 16 denotes a wiring structure film.
  • Reference numeral 1 1 denotes a second electrode pattern.
  • Reference numeral 18 is a conductor pattern.
  • Reference numeral 19 is a via.
  • Reference numeral 20 denotes a dielectric layer.
  • Reference numeral 21 denotes a conductor layer.
  • Reference numeral 22 denotes a capacitor.
  • Reference numeral 23 is a solder resist.
  • Reference numeral 24 is a protrusion.
  • Reference numeral 25 denotes a semiconductor device.
  • Reference numeral 26 denotes a pad.
  • Reference numeral 27 is a metal bump.
  • Reference numeral 28 denotes an underfill resin.
  • Reference numeral 29 denotes a concave portion.
  • Reference numeral 30 denotes a mold resin.
  • Reference numeral 31 is a spacer.
  • Reference numeral 32 denotes a heat spreader.
  • Reference numeral 3 denotes an inspection needle.
  • mounting substrate the semiconductor device mounting substrate and a semiconductor package according to the present invention.
  • the semiconductor device mounting substrate is referred to as “mounting substrate” as appropriate.
  • FIG. 1 is a diagram showing a configuration of a semiconductor device mounting board according to the present embodiment
  • FIG. 1 (a) is a schematic sectional view
  • FIG. 1 (b) is a schematic bottom view from the metal support 11 side.
  • the mounting substrate shown in FIGS. 1 (a) and 1 (b) has a first electrode pattern 13 on one side of a wiring structure film 16 composed of an insulating layer 14 and a wiring layer 15 and a second electrode pattern on the opposite side. 17, an insulating film 12 on a surface of the first electrode pattern not in contact with the wiring structure film 16, and a metal support 11 on a lower surface of the insulating film 12.
  • the periphery of the side surface is in contact with the insulating layer 14, and the lower surface of the first electrode pattern 13 is in the same plane as the lower surface of the insulating layer 14. It is in. That is, the lower surface of the first electrode pattern 13 is embedded in the insulating layer 14 without being in contact with the insulating layer 14.
  • the wiring structure film 16 is formed by alternately laminating wiring layers 15 composed of wiring having a predetermined pattern and an insulating material filled between the wirings, and insulating layers 14 composed of the insulating material. I have.
  • the wiring structure film 16 is laminated by a subtractive method, a semi-additive method, a full additive method, or the like used in the build-up method.
  • the subtractive method is a method of etching a copper foil on a substrate or a resin to form a circuit pattern, as disclosed in, for example, Japanese Patent Application Laid-Open No. H10-5111.
  • a circuit is formed by depositing electrolytic plating in a resist after forming a power supply layer and etching the power supply layer after removing the resist. It is a method to make a pattern.
  • a pattern is formed with a resist after activating the surface of a substrate or a resin, and the resist is used as an insulating layer as an electroless film. This is a method of forming a circuit pattern by the plating method.
  • the insulating layer 14 is one selected from the group consisting of epoxy resin, epoxy acrylate resin, urethane acrylate resin, polyester resin, phenol resin, polyimide resin, BCB (benzocyclobutene) and FB0 (polybenzoxazole). Or, it is formed of two or more kinds of organic resins.
  • an insulating material having a film strength of 70 MPa or more, an elongation at break of 5% or more, a glass transition temperature of 150 ° C or more, and a thermal expansion coefficient of 60 ppm / or less (hereinafter abbreviated as “insulating material A” as appropriate)
  • an insulating material with an elastic modulus of 10 GPa or more, a coefficient of thermal expansion of 30 P PmZ ° C or less, and a glass transition temperature of 150 ° C or more hereinafter abbreviated as “insulating material B” as appropriate).
  • the thickness of one insulating layer 14 is preferably 8 ⁇ m or more.
  • the elastic modulus and the elongation at break are values measured by a tensile test of an insulating material in accordance with JISK 7161 (tensile property test), and the elastic modulus is a strain 0 based on the result of the tensile test. This is the value calculated from the intensity at 1%.
  • the coefficient of thermal expansion is a value measured by the TMA method based on JISC6481
  • the glass transition temperature is a value measured by the DMA method based on JISC6481.
  • the insulating material A examples include an epoxy resin (manufactured by Hitachi Chemical; MC F-7000 LX), a polyimide resin (manufactured by Nitto Denko: AP-6832C), and a benzocycloptene resin (manufactured by Dow Chemical: Cyc 1 otene 4000 series), poly (vinylene ether resin) (made by Asahi Kasei; Xiapan), liquid crystal polymer film (made by Kuraray; LCP-A), stretched porous fluororesin impregnated thermosetting resin (Japan GATEX) And Ml CROLAM 600).
  • an epoxy resin manufactured by Hitachi Chemical; MC F-7000 LX
  • a polyimide resin manufactured by Nitto Denko: AP-6832C
  • a benzocycloptene resin manufactured by Dow Chemical: Cyc 1 otene 4000 series
  • poly (vinylene ether resin) made by Asahi Kasei; Xiapan
  • Examples of the insulating material B include epoxy resin impregnated with glass cloth (manufactured by Hitachi Chemical; MC L-E-679), epoxy resin impregnated with nonwoven fabric (manufactured by Shin Kobe Electric Co., Ltd .; EA-541), and impregnated with expanded porous fluorine resin Thermosetting resin (manufactured by Japan Gore-Tex; MICROL AM400) is suitable.
  • the insulating layer 14 one of these organic resins may be used for all the insulating layers 14 between the wiring layers 15, or two or more layers of the organic resin may be mixed. It may be arranged between the wiring layers 15.
  • the insulating layer 14 is formed of, for example, polyimide resin.
  • the lowermost insulating layer 14 is formed of polyimide resin, and the second and subsequent layers are formed of epoxy resin. It may be formed.
  • Copper is the most suitable metal for wiring in the wiring layer 15 from the viewpoint of cost, but at least one metal selected from the group consisting of gold, silver, aluminum and nickel or its alloy can also be used. It is.
  • the wiring in the wiring layer 15 is made of copper.
  • the insulator film 12 has an opening in the insulator film 12 so as to be in contact with the lower surface of the first electrode pattern 13 and to fit within the first electrode pattern, and a metal support is provided on the lower surface of the insulator film 12. 11 is provided and has a function as a solder resist.
  • As a material of the insulator film 12 there is no problem as long as it is an insulating material having a function as a solder resist. Further, the same material as the material used for the insulating layer 14 can be used.
  • the second electrode pattern 17 is connected to the uppermost layer of the wiring layer 15, and each layer of the wiring layer 15 is connected to each other via a via in the insulating layer 14, and the wiring ⁇ 15 Is connected to the first electrode pattern 13 via a via in the insulating layer 14.
  • the second electrode pattern 17 is described as being formed in the insulating layer 14; however, even if the second electrode pattern 17 is formed on the insulating layer 14 as shown in FIG. 2 (a). No problem. Further, as shown in FIG. 2 (b), a solder resist 23 may be provided on the second electrode pattern 17 formed on the insulating layer 14.
  • the metal support 11 is provided to reinforce the mounting substrate. By providing the metal support 11 on the mounting board, deformation such as warpage and undulation of the mounting board can be suppressed, and the mounting reliability of the semiconductor device (device) on the mounting board and the mounting board on an external board etc. Alternatively, the mounting reliability of the semiconductor package can be ensured.
  • the metal support 11 may be provided in a grid shape or a mesh shape as long as the first electrode pattern 13 is exposed, in addition to the frame shape as shown in FIG. 1 (b).
  • the metal support 11 is desirably a metal that can impart sufficient strength to the mounting substrate and has heat resistance enough to withstand heat treatment during mounting of the mounting substrate or the semiconductor package.
  • This material can be composed of at least one metal or an alloy thereof selected from the group consisting of stainless steel, iron, nickel, copper and aluminum, but stainless steel and copper alloys are the most suitable for handling. Suitable. Further, the thickness of the metal support 11 is preferably 0.1 to 1.5 mm. are doing. Since the metal support 11 is a metal and has conductivity, it can be energized.
  • the first electrode pattern 13 is embedded in the insulating layer 14, stress and strain on the first electrode pattern 13 are relaxed, and the concentration of stress can be reduced. Since the film 12 functions as a solder resist, it is possible to prevent the ball from being displaced when solder balls are placed, and to improve workability. Due to these effects, the stress concentration at the joints can be reduced after installation, and a mounting board with excellent installation stability and reliability of mounting to an external board can be obtained.
  • FIG. 3 is a schematic sectional view showing the configuration of the semiconductor device mounting board according to the present embodiment.
  • the conductor pattern 18 is provided between and around the first electrode patterns 13, and the conductor pattern 18 is connected to the wiring layer 15 in the wiring structure film 16 by vias. This is the same as the mounting board of the first embodiment.
  • Copper is the most suitable metal for the conductor pattern 18 from the viewpoint of cost, but at least one metal selected from the group consisting of gold, silver, aluminum and nickel or an alloy thereof can also be used. .
  • the wiring in conductor pattern 18 is made of copper.
  • the metal support 11 is metal and can be used electrically, a structure in which the conductor pattern 18 and the metal support 11 are connected via the via 19 may be used.
  • the insulating film 12 since the insulating film 12 is provided, it is possible to stably provide an electric circuit (especially a power supply or a ground) using the conductor pattern 18 on the plane on which the first electrode pattern 13 is formed. This increases the degree of freedom in designing an electric circuit, improves the electrical characteristics, and has the effect of reducing the number of layers when the mounting substrate is a multilayer.
  • FIG. 5 is a schematic sectional view showing the configuration of the semiconductor device mounting board according to the present embodiment.
  • the configuration other than having the capacitor 22 including the dielectric layer 20 provided on the upper surface of the first electrode pattern 13 and the conductive layer 21 electrically connected to the wiring structure film 16 on the upper surface of the dielectric layer 20 is as follows. This is the same as the mounting board according to the first embodiment or the second embodiment.
  • the dielectric layer 20 of the capacitor 22 is formed by a sputtering method, an evaporation method, a CVD method, an anodic oxidation method, or the like.
  • Material constituting the capacitor 22 is titanium oxide, tantalum oxide, A 1 2 0 3, S i 0 2, Nb 2 O 5, B ST (B a x S r! _ X T i O 3), P ZT (P b Z r x T i preparative x 0 3), PLZT (P b!
  • the material is a metal-based material.
  • the capacitor 22 may be made of an organic resin or the like that can realize a desired dielectric constant.
  • FIG. 6 is a schematic sectional view showing the configuration of the semiconductor device mounting board according to the present embodiment.
  • the first embodiment except that the metal support 11 has a projection 24, is provided on the entire lower surface of the insulator film 12, and the upper part of the projection 24 is in contact with the first electrode pattern 13. This is the same as the mounting board of the second embodiment or the third embodiment.
  • the protrusions 24 are formed by one or a combination of plating, etching, conductive paste, and machining.
  • a configuration in which the continuity between the metal support 11 and the conductor pattern 18 can be provided by the protrusion 24 is also possible. It is.
  • the protrusion 24 and the conductor pattern 18 are electrically stable. A connection is required. Further, even in a configuration in which the metal support 11 shown in FIG. 7 (b) is selectively removed and the insulating film 12 is opened, conduction between the metal support 11 and the conductor pattern 18 is obtained by the projection 24. Configuration is also available.
  • the present invention electrical continuity between the metal support 11 and the first electrode pattern 13 and the conductor pattern 18 is ensured, and a circuit open inspection of the mounting substrate can be performed.
  • the entire lower surface of the mounting substrate is made of a metal support 11 so that the semiconductor device can be mounted on the mounting substrate using a solder ball, a low melting point metal, wire bonding, or the like so that the second electrode pattern 17 can be conducted.
  • the flatness of the mounting substrate is more sufficiently ensured, and the mounting reliability of the semiconductor device can be improved.
  • the entire lower surface is a metal support 11, it is not possible to perform a pass / fail judgment on the mounting substrate before mounting the semiconductor device, so that only the necessary projections 24 are made of metal so as not to contact the metal support 11. By selectively removing the support 11, it can be exposed and used for inspection.
  • the flatness of the metal support 11 can be ensured, and the mounting substrate can be selected for pass / fail.
  • the first electrode pattern 13 is attached to the metal support 13. 1 1 Does not cause damage when removing.
  • the metal support 11 and protrusions 24 are selectively removed in the form of a frame, so that the first electrode pattern 1 is removed. 3 can be exposed. When removing the metal support 11, if the semiconductor package formed has sufficient strength to ensure sufficient mounting reliability on an external board without the metal support 11, the metal support 1 1 may be completely removed.
  • FIG. 8 is a schematic sectional view showing the configuration of a semiconductor package using a flip chip according to the present embodiment.
  • the semiconductor package of the present invention may be mounted on the semiconductor package according to the first, second, third, or fourth embodiment of the present invention.
  • the semiconductor device 25 can be formed on a substrate.
  • the electrical connection portion such as the pad of the semiconductor device 25 can be electrically connected to the wiring of the mounting board by various methods, for example, a flip chip, a wire bonding, and a tape bonding. .
  • the semiconductor package of the present invention may have a form in which the metal support 11 is provided on the entire lower surface of the mounting substrate.
  • the metal support 11 and the protrusion 24 are removed so that the first electrode pattern 13 is exposed.
  • the metal support 11 is processed into a frame shape, a grid shape or a mesh shape with the insulator film 12 on the lower surface. It can be used for reinforcing semiconductor packages. If the metal support 11 has a sufficient strength without forming such a reinforcement, the metal support 11 may be entirely removed to obtain the form shown in FIG. 8 (c).
  • the semiconductor device 25 is mounted on the first electrode pattern 13. Can also be taken. At this time, the metal support 11 functions to reinforce the semiconductor package and suppress the warpage and undulation of the mounting substrate by applying tension to the insulator film 12 and the wiring structure film 16. Further, if necessary, the semiconductor device 25 may be mounted on both sides of the mounting board as shown in FIG. 8 (e).
  • the semiconductor package of the present invention includes a pad 26 provided on a semiconductor device 25 and a first electrode pattern 13 or a second electrode of a mounting substrate of the present invention.
  • the pattern 17 can be electrically connected, for example, via a metal bump 27.
  • the space between the semiconductor device 25 and the mounting substrate can be filled with an underfill resin 28 if necessary.
  • the semiconductor device 25 may be sealed with the mold resin 30 or may have a form in which a heat spreader 32 and a heat sink for improving heat dissipation are attached. Furthermore, the first electrode pattern 1 3 When the semiconductor device 25 is mounted on the device, the metal support 11 may be used as a spacer 31 with a heat sink.
  • FIGS. 9A to 9C are partial cross-sectional views illustrating a method of manufacturing the mounting board according to the first embodiment of the present invention in the order of steps.
  • the present embodiment is for manufacturing the mounting substrate according to the first embodiment (FIG. 1) of the present invention. Note that cleaning and heat treatment are appropriately performed between each step.
  • the surface of a metal support 11 having a thickness of 0.1 to 1.5 mm is formed by plating, etching, conductive paste, or mechanical machining.
  • the metal support 11 is made of a copper alloy plate (Koto Steel: KFC series), and the projections 24 are formed of nickel by a plating method.
  • the projections 24 are formed by laminating a plating resist with a thickness of 30 ⁇ m on the metal support 11 and planning the projections 24 by exposure, current image, or laser, which is one photolithography technology.
  • An opening pattern of the plating resist was formed on the ground, and 25 m of electrolytic nickel plating was deposited.
  • FIG. 9 (b) an insulator film 12 and a first electrode pattern 13 are formed.
  • the insulating film 12 is formed by a spin coating method, a die coating method, a curtain coating method, a printing method, or the like if the resin for the insulating film 12 is in a liquid state. If the film is a dry film or a copper foil with a resin, it is laminated by a lamination method or the like and then solidified by drying or the like. At this time, since the vertices of the protrusions 24 need to appear on the surface of the insulator film 12, in the case of a liquid resin, if photosensitive, photolithography is used to perform buttering. If the resolution is insufficient even with non-photosensitive or photosensitive, adjust by polishing.
  • a cushion on the carrier side of the film so that the top of the protrusion 24 protrudes during lamination.
  • it may be polished after lamination.
  • the first electrode pattern 13 is formed by a subtractive method, a semi-additive method, a full-additive method, or the like.
  • the resin of the copper foil with resin is used as the insulating film 12
  • the copper foil used as the carrier can be patterned by a subtractive method.
  • a copper foil with a resin (Sumitomo Bei-Cryte; APL-4501; copper foil thickness, 18 m) is used to form an insulator film 12 and a copper foil by a subtractive method.
  • the foil was patterned to form a first electrode pattern 13.
  • an insulating layer 14 and a wiring layer 15 are formed.
  • the method of forming the insulating layer 14 is as follows: if the insulating resin constituting the insulating layer 14 is in a liquid state, the insulating resin is laminated by a spin coating method, a die coating method, a curtain coating method, a printing method, or the like. In the case of dry film, after insulating resin is laminated by a laminating method or the like, the insulating resin is hardened by performing a treatment such as drying.
  • the insulating resin is photosensitive, a photolithography process or the like is used. If the insulating resin is non-photosensitive, a via hole is formed by patterning the insulating resin by a laser processing method or the like. The insulating resin is cured by curing to form an insulating layer 14. Next, a wiring pattern is formed by a subtractive method, a semi-additive method, a full-additive method, or the like, and a wiring layer 15 is formed.
  • a pole pattern 17 is formed.
  • an epoxy resin impregnated with nonwoven nonwoven fabric manufactured by Shin-Kobe Electric; EA-541
  • EA-541 is used for the insulating layer 13
  • the wiring layer 14 has a 2 m-thick electroless copper plating as the power supply layer.
  • the semi-additive method used was used.
  • the metal support 11 is selectively removed by etching.
  • an etching resist that has an opening at the place to be etched is formed. If the etching resist is liquid, the etching resist is laminated by a spin coating method, a die coating method, a force coating method, a printing method, or the like, and if the etching resist is a dry film, the etching resist is laminated. After that, the etching resist is hardened by drying or other treatment, and the etching resist is photosensitive by a photolithographic process or the like if it is photosensitive, or by a laser processing method if the etching resist is non-photosensitive. Pattern the etching resist.
  • the metal support 11 is etched until the insulator film 11 and the projections 24 are exposed.
  • the copper alloy plate is selectively removed using an alkaline copper etching solution containing ammonia as a main component (Meltex; A process).
  • the protrusion 24 is selectively removed by etching or laser.
  • a laser may be used to adjust the shape of the opening after etching.
  • the exposed surface of the first electrode pattern 13 is normalized to obtain a mounting substrate.
  • This mounting board is the same as the mounting board according to the first embodiment of the present invention, and according to the above-described manufacturing method, this mounting board can be manufactured efficiently. Further, according to the manufacturing method according to the present embodiment, the wiring structure film 16 is stacked using the flat metal support 11 as a substrate, so that the flatness of the wiring structure film 16 can be improved. Because of stable lamination Becomes possible.
  • the flatness of the metal support 11 is reduced as in the effect of the mounting substrate shown in the fourth embodiment of the present invention.
  • the quality of the mounting substrate is indispensable, it is impossible to mount the semiconductor device using the flatness of the metal support 11 by the method without the projections 24.
  • 10 (a) to 10 (d) are partial cross-sectional views illustrating a method of manufacturing a mounting board according to the second embodiment of the present invention in the order of steps.
  • the present embodiment is for manufacturing a mounting board according to a second embodiment (FIG. 3) of the present invention. Cleaning and heat treatment are appropriately performed between each step.
  • the conductor pattern 18 is provided between and around the first electrode patterns 13, and the conductor pattern 18 is connected to the wiring layer 15 in the wiring structure film 16 by a via, except for the present invention. This is the same as the method of manufacturing the mounting board according to the first embodiment.
  • the surface of a metal support 11 having a thickness of 0.1 to 1.5 mm is selected from the group consisting of plating, etching, conductive paste, and machining.
  • the projections 24 are formed by one or a composite method. When the protrusions 24 are removed by etching, any one of gold, silver, platinum, and palladium is formed on the uppermost layer of the protrusions 24 to serve as an etching barrier to the first electrode pattern 13. It is also possible.
  • the metal support 11 is a copper alloy plate (Kobe Steel: KFC series), and the projections 24 are formed of nickel by a plating method.
  • the projections 24 can be formed by laminating a plating resist on the metal support 11 with a thickness of 30 m, and using photolithography technology such as exposure, current imaging, or laser to place the projections 24 on the planned location. Open plating register A mouth pattern was formed and electrolytic nickel plating was deposited by 25 m. Next, as shown in FIG. 10B, an insulator film 12 and a first electrode pattern 13 are formed.
  • the resin for the insulating film 12 is liquid, it is laminated by a spin coating method, a die coating method, a curtain coating method, a printing method, or the like. If it is a dry film or a resin-coated copper foil, it is laminated by a lamination method or the like and then solidified by drying or the like. At this time, since the vertices of the projections 24 need to appear on the surface of the insulator film 12, in the case of a liquid resin, if photosensitive, photolithography is used to perform buttering. If the resolution is insufficient even for photosensitive or photosensitive, prepare by polishing.
  • the first electrode pattern 13 is formed by a subtractive method, a semi-additive method, a full-additive method, or the like.
  • the resin of the copper foil with resin is used as the insulating film 12
  • the copper foil used as the carrier can be patterned by a subtractive method.
  • the thickness of the copper foil is as thin as 2 / m or less, patterning by the semi-additive method using this copper foil as the power supply layer is also possible.
  • a resin-coated copper foil (Sumitomo Bei-Client; APL-4501; copper foil thickness, 18 m) is used to form the insulator film 12 and the subtractive method.
  • the first electrode pattern 13 was formed by patterning the copper foil.
  • a conductor pattern 18 is formed between and around the first electrode patterns 13.
  • the conductor pattern 18 is formed by a subtractive method, a semi-additive method, a full-additive method, or the like.
  • a semi-additive method is used in which 2 m of electroless copper plating is deposited after forming the first electrode pattern 13 and this is used as a power supply layer. Formed.
  • an insulating layer 14 and a wiring layer 15 are formed.
  • the method of forming the insulating layer 14 is that, if the insulating resin constituting the insulating layer 14 is liquid, the insulating resin is laminated by a spin coating method, a die coating method, a force coating method, a printing method, or the like. If the resin is a dry film, after laminating the insulating resin by a lamination method or the like, a treatment such as drying is performed to solidify the insulating resin.
  • the insulating resin is photosensitive, a photolithography process or the like is used. If the insulating resin is non-photosensitive, a via hole is formed by patterning the insulating resin by a laser processing method or the like. The insulating resin is cured by curing to form an insulating layer 14.
  • a wiring pattern is formed by a subtractive method, a semi-additive method, a full-additive method, or the like, and a wiring layer 15 is formed.
  • the insulating layer 13 is made of epoxy resin impregnated with aramide non-woven fabric (manufactured by Shin-Kobe Electric Co., Ltd .; EA-541), and the wiring layer 14 has a 2 m thick electroless copper plating.
  • the semi-additive method used as the power supply layer was used. Subsequent steps are the same as the steps after FIG. 9D of the first embodiment of the present invention.
  • FIGS. 11 (a) and 11 (b) the first electrode pattern 13 and the conductor pattern 18 may be formed simultaneously.
  • FIG. 11 shows only steps different from those in FIG. This method has an effect of improving alignment accuracy between the first electrode pattern 13 and the conductor pattern 18 and an effect of reducing cost by reducing the number of steps.
  • the surface of a metal support 11 having a thickness of 0.1 to 1.5 mm is selected from the group consisting of plating, etching, conductive paste, and machining.
  • the projections 24 are formed by one or a composite method. When the projections 24 are removed by etching, one of gold, silver, platinum, and palladium is formed on the uppermost layer of the projections 24 to provide an etching barrier to the first electrode pattern 13. It is also possible.
  • the metal support 11 is a copper alloy plate (Kobe Steel: KFC series), and the projections 24 are formed of nickel by a plating method.
  • the projections 24 are formed by laminating a plating resist on the metal support 11 with a thickness of 30 m, and using a photolithography technique such as exposure, current image, or laser to plan the locations of the projections 24.
  • An opening pattern of the plating resist was formed on the substrate, and 25 m of electrolytic nickel plating was deposited.
  • an insulator film 12, a first electrode pattern 13 and a conductor pattern 18 are formed.
  • the insulating film 12 is formed by a spin coating method, a die coating method, a force coating method, a printing method, or the like if the resin for the insulating film 12 is liquid.
  • the first electrode pattern 13 and the conductor pattern 18 are formed by a subtractive method, a semi-additive method, a full-additive method, or the like.
  • the resin of the copper foil with resin is used as the insulating film 12
  • the copper foil used as the carrier can be patterned by a subtractive method. If the thickness of the copper foil is as thin as 2 m or less, the semi-additive method using this copper foil as the power supply layer is also possible.
  • a resin-coated copper foil (Sumitomo Bei-Client; APL-4501; copper foil thickness, 18 mm) is used to form an insulating film 12 and a copper foil by a subtractive method.
  • APL-4501 APL-4501
  • copper foil thickness 18 mm
  • a body pattern 18 was formed.
  • This mounting board is the same as the mounting board according to the second embodiment of the present invention, and according to the above-described manufacturing method, this mounting board can be manufactured efficiently.
  • the mounting substrate has the same effect as in the first embodiment of the present invention as it is, and further has the effect of further increasing the wiring density and reducing the number of stacked layers by forming the conductor pattern 18. .
  • 12 (a) to 12 (c) are partial cross-sectional views illustrating a method of manufacturing a mounting board according to the third embodiment of the present invention in the order of steps.
  • the present embodiment is for manufacturing a mounting substrate according to the second embodiment (FIG. 4) of the present invention. Cleaning and heat treatment are appropriately performed between each step.
  • the configuration other than that the conductor pattern 18 is connected to the metal support 11 and the via 19 is the same as the method of manufacturing the mounting board according to the second embodiment of the present invention.
  • the surface of a metal support 11 having a thickness of 0.1 to 1.5 mm is selected from the group consisting of plating, etching, conductive paste, and machining.
  • the projections 24 are formed by one or a combined method. When etching the projections 24, any one of gold, silver, platinum, and palladium metal should be formed on the uppermost layer of the projections 24 to provide an etching barrier to the first electrode pattern 13. Is also possible.
  • the metal support 11 is a copper alloy plate (Kobe Steel: KFC series), and the projections 24 are formed of nickel by a plating method.
  • the method of forming the projections 24 is as follows. A plating resist is laminated on the metal support 11 with a thickness of 30 and is exposed to the photolithography technology, a current image, or a laser. An opening pattern was formed, and 25 m of electrolytic nickel plating was deposited.
  • an insulator film 12, a first electrode pattern 13 and a via 19 are formed.
  • the insulating film 12 is formed by spin coating, die coating, curtain coating or printing if the resin for the insulating film 12 is liquid. If it is a dry film or a resin-coated copper foil, it is laminated by a lamination method or the like, and then solidified by drying or the like. At this time, since the apexes of the protrusions 24 need to appear on the surface of the insulator film 12, in the case of a liquid resin, if photosensitive, patterning is performed by photolithography, and If the resolution is not enough, adjust by polishing.
  • a cushion on the carrier side of the film so that the top of the protrusion 24 protrudes during lamination.
  • it may be polished after lamination.
  • the first electrode pattern 13 is formed by a subtractive method, a semi-additive method, a full-additive method, or the like.
  • the resin of the copper foil with resin is used as the insulating film 12
  • the copper foil used as the carrier can be patterned by a subtractive method. If the thickness of the copper foil is as thin as 2 m or less, patterning by the semi-additive method using this copper foil as the power supply layer is also possible.
  • a via 19 is formed so as to expose the metal support 11 by using a method such as photolithography, laser, or dry etching.
  • the vias 19 may be simultaneously patterned by photolithography if photosensitive, or by laser or dry etching if non-photosensitive.
  • a copper foil with a resin (Sumitomo Bei-Client; APL-4501; copper foil thickness, 18 m) is used to form an insulating film 12 and a copper foil by a subtractive method.
  • a first electrode pattern 13 was formed, and a via 19 having a via diameter of 80 ⁇ m was formed using a carbon dioxide laser.
  • a conductor pattern 18 is formed between and around the first electrode patterns 13 so as to be connected to the metal support 11 via vias 19.
  • the conductor pattern 18 is formed by a subtractive method, a semi-additive method, a full-additive method, or the like.
  • 2 m of electroless copper plating was deposited after the formation of the first electrode pattern 13, and was formed using a semi-additive method using this as a power supply layer.
  • the first electrode pattern 13 and the conductor pattern 18 may be formed simultaneously. This method has an effect of improving alignment accuracy between the first electrode pattern 13 and the conductor pattern 18 and an effect of reducing cost by reducing the number of steps.
  • the surface of a metal support 11 having a thickness of 0.1 to 1.5 mm is selected from the group consisting of plating, etching, conductive paste, and machining.
  • the projections 24 are formed by one or a composite method. When the protrusions 24 are removed by etching, any one of gold, silver, platinum, and palladium is formed on the uppermost layer of the protrusions 24 to serve as an etching barrier to the first electrode pattern 13. It is also possible.
  • the metal support 11 is a copper alloy plate (Kobe Steel: KFC series), and the projections 24 are formed of nickel by a plating method.
  • the projections 24 are formed by depositing a plating resist with a thickness of 30 m on the metal support 11 and planning the projections 24 by photolithography, an exposure, current image, or laser. An opening pattern of the plating resist was formed on the ground, and 25 electrolytic nickel plating was deposited.
  • an insulator film 12 via 19 is formed.
  • the insulating film 12 is formed by a spin coating method, a die coating method, a curtain coating method, a printing method, or the like if the resin for the insulating film 12 is liquid. If the film is a dry film or a resin-coated copper foil, it is laminated by lamination or the like, and then solidified by drying or the like. At this time, the top of the projection 2 4 Must be exposed on the surface of the insulator film 12, so in the case of a liquid resin, if photosensitivity is used, patterning is performed by photolithography, and even if it is non-photosensitive or photosensitive, the resolution is insufficient. If so, prepare by polishing.
  • a cushion on the carrier side of the film so that the top of the protrusion 24 protrudes during lamination.
  • it may be polished after lamination.
  • a via 19 is formed so as to expose the metal support 11 by using a method such as photolithography, laser, or dry etching.
  • the vias 19 may be simultaneously patterned by photolithography if photosensitive, or by laser or dry etching if non-photosensitive.
  • the via 19 is formed by etching the copper foil and then using a laser.
  • the insulating film 12 and the copper foil are etched using a resin-coated copper foil (Sumitomo Bei-Client; APL-4501; copper foil thickness, 18 m). Then, a via 19 having a via diameter of 80 m was formed using a carbon dioxide laser.
  • the first electrode pattern 13 and the conductor pattern 18 are formed by a subtractive method, a semi-additive method, a full-additive method, or the like.
  • the electroless copper plating is deposited with a thickness of 2 m and formed using a semi-additive method using this as a power supply layer.
  • the state formed in this step is the same as that in FIG. 10 (c), and the subsequent steps are the steps after FIG. 10 (d).
  • This mounting board is the same as the mounting board according to the second embodiment of the present invention, and according to the above-described manufacturing method, this mounting board can be manufactured efficiently.
  • the mounting board inherits the effects of the first and second embodiments of the present invention as it is, and furthermore, the conductor pattern 18 is connected to the metal support 11 to support the metal.
  • Body 1 1 Since it is used as an air circuit, it has the effects of improving the wiring density and reducing the number of stacked layers as compared with the second embodiment of the present invention.
  • FIGS. 14A to 14C are partial cross-sectional views illustrating a method of manufacturing a mounting board according to the fourth embodiment of the present invention in the order of steps.
  • the present embodiment is for manufacturing a mounting substrate according to a fourth embodiment (FIG. 7) of the present invention. Cleaning and heat treatment are appropriately performed between each step.
  • the configuration other than that the via 19 connecting the conductor pattern 18 to the metal support 11 uses the protrusion 24 is the same as the manufacturing method of the mounting board according to the second embodiment of the present invention.
  • the surface of a metal support 11 having a thickness of 0.1 to 1.5 mm is selected from the group consisting of plating, etching, conductive paste, and machining.
  • the projections 24 are formed by one or a composite method. When etching the projections 24, one of gold, silver, platinum, and palladium metal should be formed on the top layer of the projections 24 in order to etch the first electrode patterns 13 Is also possible.
  • the metal support 11 is a copper alloy plate (Kobe Steel: KFC series), and the projections 24 are formed of nickel by a plating method.
  • the projections 24 are formed by laminating a plating resist on the metal support 11 with a thickness of 30 m, and using a photolithography technique such as exposure, current image, or laser to plan the locations of the projections 24.
  • An opening pattern of the plating resist was formed on the surface, and electrolytic nickel plating was deposited for 25 jim.
  • an insulator film 12, a first electrode pattern 13 and a conductor pattern 18 are formed.
  • the insulating film 12 is formed by a spin coating method, a die coating method, a curtain coating method, a printing method, or the like if the resin for the insulating film 12 is liquid.
  • the resin for the insulating film 12 is liquid.
  • it is cured by drying or the like.
  • photolithography Patterning is performed by lithography, and if the resolution is insufficient even with non-photosensitive or photosensitive, polishing is used to prepare it.
  • the first electrode pattern 13 and the conductor pattern 18 are formed by a subtractive method, a semi-additive method, a full-additive method, or the like.
  • the resin of the copper foil with resin is used as the insulating film 12
  • the copper foil used as the carrier can be patterned by a subtractive method.
  • the first electrode pattern 13 and the conductor pattern 18 may be formed in separate steps or may be formed in the same step. If they are formed separately, the yield will be improved by adapting the process to the pattern to be formed.If they are formed simultaneously, the accuracy of alignment between the first electrode pattern 13 and the conductor pattern 18 will be improved and the number of steps will be reduced. effective.
  • a resin-coated copper foil (Sumitomo Bei-Client; APL-4501: copper foil thickness, 18 1m) is used to form an insulating film 12 and a copper foil by a subtractive method.
  • APL-4501 copper foil thickness, 18 1m
  • an insulating layer 14 and a wiring layer 15 are formed.
  • the method for forming the insulating layer 14 is as follows: if the insulating resin constituting the insulating layer 14 is liquid, the insulating resin is laminated by a spin coating method, a die coating method, a curtain coating method, a printing method, or the like. If the resin is a dry film, an insulating resin is laminated by a laminating method or the like, and then a treatment such as drying is performed to solidify the insulating resin.
  • the insulating resin is photosensitive, a photolithography process or the like is used. Alternatively, if the insulating resin is non-photosensitive, the insulating resin is patterned by a laser processing method or the like to form a via hole, and cured to cure the insulating resin to form an insulating layer 14. .
  • a wiring pattern is formed by a subtractive method, a semi-additive method, a full-additive method, or the like, and a wiring layer 15 is formed.
  • the insulating layer 13 is made of epoxy resin impregnated with aramide non-woven fabric (manufactured by Shin-Kobe Electric; EA-541), and the wiring layer 14 has a two-layer electroless copper plating.
  • the semi-additive method was used.
  • the state formed in this step is the same as that in FIG. 10 (c), and the subsequent steps are the steps after FIG. 10 (d).
  • This mounting board is the same as the mounting board according to the fourth embodiment of the present invention, and according to the above-described manufacturing method, this mounting board can be manufactured efficiently.
  • the mounting substrate inherits the effects of the first, second, and third embodiments of the present invention as it is, and the conductor pattern 18 and the metal support 11 are formed with protrusions 24. Since the connection is made by the method described above, the number of steps can be reduced as compared with the third embodiment of the present invention, which is effective in terms of cost and yield.
  • FIGS. 15A to 15D are partial cross-sectional views illustrating a method of manufacturing a mounting board according to the fifth embodiment of the present invention in the order of steps.
  • the present embodiment is for manufacturing a mounting substrate according to the third embodiment (FIG. 5) of the present invention. Cleaning and heat treatment are appropriately performed between each step.
  • the configuration other than that the capacitor 22 is formed by providing the dielectric layer 20 and the conductor layer 21 on at least one or more first electrode patterns 13 is the same as the first embodiment of the present invention. It is the same as the manufacturing method of the mounting board.
  • FIG. 15 uses the embodiment of the first embodiment of the present invention
  • FIGS. 10 (b), (c) and 11 (b) of the second embodiment of the present invention use the same.
  • FIG. 14 (b) of the embodiment may be substituted for FIG. 15 (b).
  • the surface of a metal support 11 having a thickness of 0.1 to 1.5 mm is formed by any one of plating, etching, conductive paste, and machining.
  • the projections 24 are formed by one or a combined method. When the protrusions 24 are removed by etching, any one of gold, silver, platinum, and palladium is formed on the uppermost layer of the protrusions 24 to serve as an etching barrier to the first electrode pattern 13. It is also possible.
  • the metal support 11 is made of a copper alloy plate (Kobe Steel: KFC series), and the projections 24 are formed of nickel by a plating method.
  • the projections 24 are formed by laminating a plating resist on the metal support 11 with a thickness of 30 m, and using a photolithography technique such as exposure, current image, or laser to plan the locations of the projections 24.
  • An opening pattern of a plating resist was formed on the substrate, and electrolytic nickel plating was deposited to a thickness of 25 ⁇ m.
  • an insulator film 12 and a first electrode pattern 13 are formed.
  • the insulating film 12 is formed by spin coating, die coating, curtain coating, printing, or the like if the resin for the insulating film 12 is liquid. If the film is a dry film or a resin-coated copper foil, it is laminated by a laminating method or the like, and then dried and hardened. At this time, since the vertices of the projections 24 need to appear on the surface of the insulator film 12, in the case of a liquid resin, if photosensitive, photolithography is used to perform buttering. If the resolution is insufficient even for photosensitive or photosensitive, prepare by polishing.
  • the first electrode pattern 13 is formed by a subtractive method, a semi-additive method, a full-additive method, or the like.
  • the carrier is It is also possible to pattern the copper foil used as a layer by the subtractive method.
  • the first electrode is formed by using a polyimide resin (manufactured by Nitto Denko; AP-6832C), using an insulator film 12 and a semi-additive method in which a power supply layer is provided by sputtering. Pattern 13 was formed.
  • the dielectric layer 20 and the conductor layer 21 are formed on at least one or more first electrode patterns 13.
  • the first electrode pattern 13 forming the capacitor also has a portion electrically connected as a pad for use as a decoupling capacitor.
  • the dielectric layer 20 is formed on the first electrode pattern 13 by a sputtering method, an evaporation method, a CVD method, an anodic oxidation method, or the like.
  • Materials that make up the capacitor titanium oxide, tantalum oxide, A 1 2 0 3, S i 0 2, Nb 2 O 5, BST (B a x S r X _ X T i 0 3), P ZT (P b Z r X T ij _ x O 3), PL ZT (P b! _ y L a y Z r X T i! _ x 0 3) or pair of such S r B i 2 T a 2 O 9
  • BST B a x S r X _ X T i 0 3
  • P ZT P b Z r X T ij _ x O 3
  • PL ZT P b! _ y L a y Z r X T
  • the dielectric layer 20 may be made of an organic resin or the like that can realize a desired dielectric constant.
  • the conductive layer 21 is formed on the dielectric layer 20 by a sputtering method, a CVD method, a subtractive method, a semi-additive method, a full-additive method, or the like.
  • a metal mask is used to deposit 20 nm of BST on a required electrode pattern 13 by a sputtering method, and further, 80 nm of white gold is deposited thereon as a conductive layer 21 by a sputtering method.
  • an insulating layer 14 and a wiring layer 15 are formed.
  • the method of forming the insulating layer 14 is as follows. If the insulating resin is liquid, the insulating resin is laminated by a spin coating method, a die coating method, a curtain coating method, a printing method, or the like. If the insulating resin is a dry film, the insulating resin is laminated by a laminating method or the like. The insulating resin is hardened by performing a treatment such as drying.
  • the insulating resin is photosensitive, a photolithography process or the like is used. If the insulating resin is non-photosensitive, a via hole is formed by patterning the insulating resin by a laser processing method or the like. The insulating resin is cured by curing to form an insulating layer 14.
  • a wiring pattern is formed by a subtractive method, a semi-additive method, a full-additive method, or the like, and a wiring layer 15 is formed.
  • the insulating layer 13 is made of epoxy resin impregnated with aramide non-woven fabric (manufactured by Shin-Kobe Electric Co., Ltd .; EA-541), and the wiring layer 14 has a 2 m thick electroless copper plating.
  • the semi-additive method used as the power supply layer was used.
  • the state formed in this step is the same as that in FIG. 9 (c), and the subsequent steps are the steps after FIG. 9 (d).
  • This mounting board is the same as the mounting board according to the third embodiment of the present invention, and according to the above-described manufacturing method, this mounting board can be manufactured efficiently. By forming such a capacitor, transmission noise can be reduced, and an optimal mounting board for high-speed operation can be obtained.
  • FIGS. 16 (a) to 16 (f) are partial cross-sectional views illustrating a method of manufacturing a mounting substrate according to the sixth embodiment of the present invention in the order of steps. Cleaning and heat treatment are appropriately performed between each step.
  • the configuration is the same as that of the method of manufacturing the mounting board according to the first embodiment of the present invention, except that the portion to be removed from the metal support 11 is previously formed as the concave portion 29.
  • the method of manufacturing the mounting substrate of FIG. 16 is the same as that of the first embodiment of the present invention, but is different from the second embodiment, the third embodiment, the fourth embodiment, and the fifth embodiment.
  • the mounting substrate may be formed according to the above embodiment.
  • a metal support 11 having a thickness of 0.1 to 1.5 mm, a place to be etched and removed is formed as a recess 29.
  • etching, machining, or a combined method is used.
  • the metal support 11 may be formed by bonding a frame-shaped metal plate to a flat metal plate.
  • the projections 24 are formed on the surface of the metal support 11 by one or a combination of plating, etching, conductive base, and machining.
  • the uppermost layer of the protrusion 24 is made of one of gold, silver, platinum, and palladium to provide an etching barrier to the first electrode pattern 13. It is also possible to keep it.
  • the metal support 11 is a copper alloy plate (Kobe Steel: KFC series), and the projections 24 are formed of nickel by a plating method.
  • the projections 24 are formed by depositing a plating resist with a thickness of 30 m on the metal support 11 and planning the projections 24 by photolithography, an exposure, current image, or laser. An opening pattern of the plating resist was formed on the ground, and electrolytic nickel plating was deposited to 25 ⁇ m.
  • an insulator film 12 and a first electrode pattern 13 are formed.
  • the insulating film 12 is formed by spin coating, die coating, curtain coating, printing, or the like if the resin for the insulating film 12 is liquid.
  • the first electrode pattern 13 is formed by a subtractive method, a semi-additive method, a full-additive method, or the like.
  • the resin of the copper foil with resin is used as the insulating film 12
  • the copper foil used as the carrier can be patterned by a subtractive method.
  • the thickness of the copper foil is as thin as 2 m or less, patterning by the semi-additive method using this copper foil as the power supply layer is also possible.
  • a resin-coated copper foil (Sumitomo Bei-Cry; APL-4501; copper foil thickness, 18 m) is used to form an insulator film 12 and a copper film by a subtractive method. The foil was patterned to form a first electrode pattern 13.
  • an insulating layer 14 and a wiring layer 15 are formed.
  • the method of forming the insulating layer 14 is as follows: if the insulating resin forming the insulating layer 14 is liquid, the insulating resin is laminated by a spin coating method, a die coating method, a curtain coating method, a printing method, or the like. If the film is a dry film, the insulating resin is laminated by a laminating method or the like, and then subjected to a treatment such as drying to harden the insulating resin.
  • the insulating resin is photosensitive, a photolithography process or the like is used. If the insulating resin is non-photosensitive, a via hole is formed by patterning the insulating resin by a laser processing method or the like. The insulating resin is cured by curing to form an insulating layer 14. Next, a wiring pattern is formed by a subtractive method, a semi-additive method, a full-additive method, or the like, and a wiring layer 15 is formed.
  • the process of forming the insulating layer 13 and the process of forming the wiring layer 14 by a subtractive method, a semi-additive method, a full additive method, or the like are repeated to form a wiring structure film. 16 and a second electrode pattern 17 are formed on the surface layer.
  • the insulating layer 13 is made of epoxy resin impregnated with aramide non-woven fabric (manufactured by Shin-Kobe Electric; EA-541).
  • EA-541 Shin-Kobe Electric
  • a semi-additive method using a 2 m-thick electroless copper plating as a power supply layer was used.
  • the metal support 11 is selectively removed by etching.
  • an etching resist having an opening at a portion to be etched is formed. If the etching resist is liquid, the etching resist is laminated by a spin coating method, a die coating method, a force coating method, a printing method, or the like. After etching, the etching resist is hardened by drying and other treatments. If the etch resist is photosensitive, a photolithography process is used.If the etch resist is non-photosensitive, the laser processing method is used. The etching resist is patterned by the above method.
  • the metal support 11 is etched until the insulator film 11 and the projections 24 are exposed. Further, since the concave portion 29 is formed, it is possible to perform etching without using an etching resist.
  • the copper alloy plate was selectively removed without using an etching resist by using an alkali copper etching solution containing ammonia as a main component (Meltex; A process).
  • the protrusions 24 are etched or selectively removed by laser.
  • a laser may be used to adjust the shape of the opening after etching.
  • the exposed surface of the first electrode pattern 13 is normalized to obtain a mounting substrate.
  • the nickel formed as the protrusions 24 was removed using an etching solution in which sulfuric acid: aqueous hydrogen peroxide: pure water was mixed at a ratio of 1: 1: 10.
  • the mounting substrate can be manufactured efficiently. Further, according to the manufacturing method of the present embodiment, the first embodiment, the second embodiment, the third embodiment, the fourth embodiment, and the fifth embodiment of the present invention are described. Since each of the above forms can be handled, the respective advantages can be used. Furthermore, the place where the metal support 1 is to be etched is Since it is set to 9, the amount of etching can be reduced, and it has the effect of improving the etching accuracy and yield.
  • FIGS. 17 (a) to 17 (e) are partial cross-sectional views illustrating a method of manufacturing a mounting substrate according to the seventh embodiment of the present invention in the order of steps. Cleaning and heat treatment are appropriately performed between each step. Except for forming the mounting substrate on both surfaces of the metal support 11 and then dividing the metal support 11 into two parts in the horizontal direction, the method of manufacturing the mounting substrate according to the first embodiment of the present invention Is the same as The method of manufacturing the mounting board shown in FIG. 17 is the same as that of the first embodiment of the present invention, but the second embodiment, the third embodiment, the fourth embodiment, A mounting substrate may be formed according to the fifth embodiment.
  • a metal support 11 having a thickness of 0.2 to 3.0 mm and a thickness corresponding to a margin is added.
  • the thickness of the metal support 11 after being divided in the horizontal direction is 0.1 to 1.5 mm.
  • both surfaces of the metal support 11 are attached by one of the following methods: etching, conductive paste, and machining.
  • the projections 24 are formed.
  • any one of gold, silver, platinum, and palladium may be formed on the uppermost layer of the projections 24 to provide an etching barrier to the first electrode pattern 13. It is possible.
  • the metal support 11 is a copper alloy plate (Kobe Steel: KFC series), and the projections 24 are formed of nickel by a plating method.
  • the projections 24 are formed by laminating a plating resist on the metal support 11 with a thickness of 30 m, and using a photolithography technique such as exposure, current image, or laser to plan the locations of the projections 24.
  • An opening pattern of a plating resist was formed on the substrate, and 25 ⁇ m of electrolytic nickel plating was deposited.
  • the insulating film 12 is formed by spin coating, die coating, curtain coating, printing, or the like if the resin for the insulating film 12 is liquid.
  • a cushion on the carrier side of the film so that the top of the protrusion 24 protrudes during lamination.
  • it may be polished after lamination.
  • the first electrode pattern 13 is formed by a subtractive method, a semi-additive method, a full-additive method, or the like.
  • the resin of the copper foil with resin is used as the insulating film 12
  • the copper foil used as the carrier can be patterned by a subtractive method.
  • the thickness of the copper foil is as thin as 2 m or less, patterning by the semi-additive method using this copper foil as the power supply layer is also possible.
  • a copper foil with a resin (Sumitomo Bei-Client; APL-4501; copper foil thickness, 18 m) is used to form an insulating film 12 and a copper foil by a subtractive method.
  • the first electrode pattern 13 was formed by patterning.
  • an insulating layer 14 and a wiring layer 15 are formed.
  • the method of forming the insulating layer 14 is as follows: if the insulating resin forming the insulating layer 14 is liquid, the insulating resin is laminated by a spin coating method, a die coating method, a curtain coating method, a printing method, or the like. If the film is a dry film, an insulating resin is laminated by a laminating method or the like, and then a treatment such as drying is performed to solidify the insulating resin.
  • the insulating resin is photosensitive, a photolithography process or the like is used. If the insulating resin is non-photosensitive, a via hole is formed by patterning the insulating resin by a laser processing method or the like. The insulating resin is cured by curing to form an insulating layer 14.
  • a wiring pattern is formed by a subtractive method, a semi-additive method, a full-additive method, or the like, and a wiring layer 15 is formed. Further, the process of forming the insulating layer 13 and the process of forming the wiring layer 14 by a subtractive method, a semi-additive method, a full-additive method, or the like are repeated to form the second electrode pattern 17 on the wiring structure film 16 and the surface layer.
  • the insulating layer 13 is made of epoxy resin impregnated with aramide non-woven fabric (manufactured by Shin Kobe Electric; EA-541), and the wiring layer 14 has a 2 m-thick electroless copper plated power supply layer. The semi-additive method was used.
  • the metal support 11 is divided into two at the center in the horizontal direction to form a second surface.
  • a method of dividing, cut with a slicer, water cutter or the like As a method of dividing, cut with a slicer, water cutter or the like.
  • the state formed in this step is the same as that in FIG. 9D, and the subsequent steps are the steps after FIG. 9E.
  • the mounting substrate can be manufactured efficiently. Further, according to the manufacturing method of the present embodiment, the first embodiment, the second embodiment, the third embodiment, the fourth embodiment, and the fifth embodiment of the present invention are described. Since each of the above forms can be handled, the respective advantages can be used. Furthermore, since both surfaces of the metal support 11 are used, the number of productions is doubled, which has the effect of improving productivity.
  • FIGS. 18 (a) to 18 (e) are partial cross-sectional views illustrating a method of manufacturing a mounting board according to the eighth embodiment of the present invention in the order of steps. Cleaning and heat treatment are appropriately performed between each step.
  • the configuration other than that two metal supports 11 are attached to each other to form a mounting substrate on both surfaces and then the metal support 11 is divided is the first embodiment of the present invention. This is the same as the method of manufacturing the mounting board according to the embodiment.
  • the method of manufacturing the mounting board of FIG. 18 is the same as that of the first embodiment of the present invention, but is different from the second embodiment, the third embodiment, the fourth embodiment, and the fourth embodiment.
  • the mounting substrate may be formed according to the fifth embodiment and the sixth embodiment. In particular, in the case of a shape in which the concave portion 29 is provided in the metal support 11, both sides can be formed only by bonding according to the present invention.
  • the metal support 11a and the metal support 11b are laminated to a thickness of 0.1 to 1.5 mm. Further, it is also possible to use the metal support 11 having the concave portion 29 formed thereon for lamination. Lamination is performed on the entire surface or at the end using an adhesive, welding, or the like, by forming fine irregularities on the surface where the metal support 11a and the metal support 11b are bonded. Considering the division shown in Fig. 18 (e), it is more appropriate to bond at the end.
  • the metal support 11 is attached to both surfaces by one of the following methods: etching, conductive paste, and machining.
  • the projections 24 are formed.
  • an uppermost layer of the protrusions 24 should be made of one of gold, silver, platinum, and palladium, as an etching barrier to the first electrode pattern 13. Is also possible.
  • the metal support 11 is a copper alloy plate (Kobe Steel: KFC series), and is formed of nickel by the projection 24 mounting method.
  • the projections 24 can be formed by laminating a plating resist with a thickness of 30 m on the metal support 11 and applying photolithography techniques such as exposure, development, or laser to the intended location of the projections 24. An opening pattern of the plating resist was formed, and electrolytic nickel plating was deposited to a thickness of 25 ⁇ m.
  • an insulator film 12 and a first electrode pattern 13 are formed.
  • the insulating film 12 is formed by spin coating, die coating, curtain coating, printing, or the like if the resin for the insulating film 12 is liquid.
  • Drift film or copper foil with resin After laminating by the minate method etc., it is hardened by applying processing such as drying.
  • processing such as drying.
  • the vertices of the projections 24 need to appear on the surface of the insulator film 12, in the case of a liquid resin, if photosensitive, photolithography is used to perform buttering. If the resolution is insufficient even for photosensitive or photosensitive, prepare by polishing.
  • a cushion on the carrier side of the film so that the top of the protrusion 24 protrudes during lamination.
  • it may be polished after lamination.
  • the first electrode pattern 13 is formed by a subtractive method, a semi-additive method, a full-additive method, or the like.
  • the resin of the copper foil with resin is used as the insulating film 12
  • the copper foil used as the carrier can be patterned by a subtractive method.
  • the thickness of the copper foil is as thin as 2 m or less, patterning by the semi-additive method using this copper foil as the power supply layer is also possible.
  • a copper foil with resin (Sumitomo Bei-Cry; APL-4501; copper foil thickness, 18 m) is used to form an insulator film 12 and a copper film by a subtractive method. The foil was patterned to form a first electrode pattern 13.
  • an insulating layer 14 and a wiring layer 15 are formed.
  • the method of forming the insulating layer 14 is as follows: if the insulating resin forming the insulating layer 14 is liquid, the insulating resin is laminated by a spin coating method, a die coating method, a curtain coating method, a printing method, or the like. If the film is a dry film, the insulating resin is laminated by a lamination method or the like, and then subjected to a treatment such as drying to harden the insulating resin.
  • the insulating resin is photosensitive, a photolithography process or the like is used. If the insulating resin is non-photosensitive, a via hole is formed by patterning the insulating resin by a laser processing method or the like. The insulating resin is cured by curing to form an insulating layer 14. Next, a wiring pattern is formed by a subtractive method, a semi-additive method, a full-additive method, or the like, and a wiring layer 15 is formed.
  • the process of forming the insulating layer 13 and the process of forming the wiring layer 14 by a subtractive method, a semi-additive method, a full-additive method, or the like are repeated to form a second electrode pattern on the wiring structure film 16 and the surface layer.
  • Form 17 In this embodiment, an epoxy resin impregnated with nonwoven nonwoven fabric (manufactured by Shin-Kobe Electric; EA-541) is used for the insulating layer 13, and the wiring layer 14 is a 2-layer electroless copper-plated power supply layer. The semi-additive method was used.
  • the metal support 11 on which the metal support 11 is bonded to the entire surface is cut at its center with a slicer, a water cutter, or the like, and the metal support 11 a and the metal support 11 a are cut.
  • Support 1 Divide into 1b The metal support 11 with the end bonded is divided into a metal support 11a and a metal support 11b by cutting the bonded end.
  • the mounting substrate can be manufactured efficiently.
  • the first embodiment, the second embodiment, the third embodiment, the fourth embodiment, and the fifth embodiment of the present invention are provided. Since each of the embodiments and the sixth embodiment can be applied, the respective advantages can be utilized. Furthermore, since the metal support 11 can be bonded after being processed, the degree of freedom in processing the metal support 11 is high, and the production number is doubled because both surfaces are used. This has the effect of improving productivity.
  • FIGS. 19A to 19D are partial cross-sectional views illustrating a method of manufacturing a semiconductor package according to a ninth embodiment of the present invention in the order of steps.
  • This embodiment is for manufacturing a mounting substrate according to the fifth embodiment of the present invention (FIGS. 8A, 8B, and 8C). Note that cleaning and heat treatment are appropriately performed between each step.
  • connections are made by flip-chip using solder balls as the metal bumps 27.
  • the metal bump 27 a metal made of gold, copper, tin, solder, or the like is preferably used.
  • wire bonding or tape bonding can be used as the connection between the pad 26 and the second electrode pattern 17.
  • the first embodiment, the second embodiment, the third embodiment, the fourth embodiment, and the fifth embodiment of the present invention According to the sixth embodiment, the seventh embodiment, and the eighth embodiment, the wiring structure film 16 and the second electrode pattern 17 are formed (for example, FIG. 9 (d)). Form) is prepared.
  • the second electrode pattern 17 is connected to the pad 26 of the semiconductor device 25 by a metal bump 27.
  • underfill resin 28 may be filled. In the present embodiment, connection is made using solder balls, and the underfill resin 28 is filled.
  • the first electrode pattern 13 is exposed by selectively removing the metal support 11 and the protrusion 24.
  • the removal of the metal support 11 is performed by etching, and the removal of the protrusions 24 is performed by etching, laser, or a combined method.
  • a step of converting the state of FIG. 19 (b) with the semiconductor device 25 mounted thereon into a semiconductor package sealed with the mold resin 30 as shown in FIG. 20 may be taken.
  • the first embodiment, the second embodiment, the third embodiment, the fourth embodiment, and the fifth embodiment of the present invention The sixth embodiment, the seventh embodiment, and the eighth embodiment
  • a mounting substrate having a configuration in which the wiring structure film 16 and the second electrode pattern 17 are further formed (for example, the configuration in FIG. 9D) is prepared, and the semiconductor device 25 is flip-chip connected, and an under-mount is formed.
  • FIG. 20B sealing is performed with a mold resin 30.
  • the first electrode pattern 13 is exposed by selectively removing the metal support 11 and the protrusion 24.
  • the removal of the metal support 11 is performed by etching, and the removal of the protrusions 24 is performed by etching, laser, or a combined method.
  • the entire metal support 11 may be removed as shown in FIG. 20 (d).
  • a step of forming a semiconductor package having the heat spreader 32 attached thereto using a spacer 31 may be taken.
  • the wiring structure film 16 and the second electrode pattern 17 are formed (for example, FIG. 9D
  • the mounting substrate of the above is prepared, and the semiconductor device 25 is flip-chip connected, and the underfill resin 28 is filled.
  • the spacer 31 is attached.
  • the spacer 31 is a reinforcing frame for mounting the heat spreader 32 and the heat sink on the semiconductor device 25.
  • Stainless steel or copper is used as the material, but if it has the strength required for reinforcement, it may be formed of resin.
  • a heat spreader 32 for mounting a heat sink is attached.
  • the semiconductor device 25 and the heat spreader 32 are bonded with a heat conductive metal paste.
  • An adhesive between the spacer 31 and the heat spreader 32 is used.
  • the first electrode pattern 13 is exposed by selectively removing the metal support 11 and the protrusion 24.
  • the metal support 11 is removed by etching, and the protrusions 24 are removed by etching, laser, or a combined method.
  • This mounting board is the same as the semiconductor package according to the fifth embodiment of the present invention, and according to the above-described manufacturing method, this mounting board can be manufactured efficiently.
  • deformation such as warpage or undulation of the mounting substrate in each process of mounting the semiconductor device 25, filling the underfill 28, filling the mold resin 30, filling the spacer 31, and the heat spreader 32, is eliminated.
  • Mounting reliability and assembly yield are improved because it is suppressed by the metal support 11.
  • FIGS. 22 (a) to 22 (d) are partial cross-sectional views sequentially showing a method of manufacturing a semiconductor package according to the tenth embodiment of the present invention.
  • This embodiment is for manufacturing a mounting substrate according to the fifth embodiment (FIGS. 8B, 8C, and 8D) of the present invention. Note that cleaning and heat treatment are appropriately performed between each step.
  • connection is made by flip-chip using a solder pole as the metal bump 27.
  • a metal made of gold, copper, tin, solder, or the like is preferably used.
  • wire bonding or tape bonding can be used.
  • the first embodiment of the present invention Formed by the second embodiment, the third embodiment, the fourth embodiment, the fifth embodiment, the sixth embodiment, the seventh embodiment, and the eighth embodiment Prepare the mounted mounting board.
  • the second electrode pattern 17 is connected to the pad 26 of the semiconductor device 25 by the metal bump 27.
  • underfill resin 28 may be filled. In the present embodiment, connection is made using a solder pole, and the underfill resin 28 is filled.
  • the semiconductor package shown in FIG. 22 (c) is obtained. If the strength of the semiconductor package obtained in FIG. 22 (b) is sufficient, all of the metal support 11 attached as reinforcement may be removed, and the configuration shown in FIG. 22 (c) may be used. Absent.
  • the semiconductor device 25 mounting side is sealed with a mold resin 30 or, as shown in FIG. 22 (e), a heat spreader using a spacer 31 is used. It may be a semiconductor package to which 32 is attached.
  • FIGS. 22 (d) and (e) both show the shape in which the metal support 11 remains, but the metal support 11 may be removed if the strength is sufficient for a semiconductor package.
  • FIG. 23 (a) the first embodiment, the second embodiment, the third embodiment, the fourth embodiment, the fifth embodiment, A mounting substrate formed according to the sixth embodiment, the seventh embodiment, and the eighth embodiment is prepared.
  • the heat spreader 32 is attached.
  • the thickness of the metal support 11 substantially coincides with the thickness of the mounted semiconductor device 25 from the mounting substrate.
  • the heat spreader 32 is not attached, and is sealed with the mold resin 30 (FIG. 23 (d)).
  • the thickness of the metal support 11 and the mounting thickness of the semiconductor device 25 do not necessarily have to match.
  • This mounting board is the same as the semiconductor package according to the fifth embodiment of the present invention, and according to the above-described manufacturing method, this mounting board can be manufactured efficiently.
  • the semiconductor device 25 can be mounted after the quality of the mounted substrate is determined.
  • the spacer 31 as the metal support 11 the number of semiconductor package assembling steps can be reduced.
  • FIGS. 24 (a) to 24 (c) are partial cross-sectional views showing an example of the mounting board inspection method according to the tenth embodiment of the present invention.
  • FIG. 24 (a) is performed in the form of a mounting board before removing the metal support 11 and the protrusion 24.
  • the first embodiment of the present invention (the embodiment of FIG. 9 (d)) is used, but the second, third, and fourth embodiments of the present invention are used.
  • the mounting substrate formed according to the embodiment, the fifth embodiment, the sixth embodiment, the seventh embodiment, and the eighth embodiment may be used.
  • This inspection enables an open inspection (continuity failure) of the circuit on the mounting board.
  • a pattern search is performed using an image recognition measurement device or the like to check for each layer.
  • a short circuit detection of the circuit of the mounting board may be performed.
  • the semiconductor device 25 can be mounted after the quality of the mounting substrate used in the ninth embodiment of the present invention is determined.
  • FIG. 24 (b) shows a state in which the metal support 11 is selectively removed and the protrusions 24 are not removed, and the circuit of the mounting board is opened and shorted using the second electrode patterns 17 and the protrusions 24. Perform both tests.
  • FIG. 24 (b) uses the first embodiment of the present invention (the embodiment of FIG. 9 (e)), the second embodiment, the third embodiment, and the fourth embodiment
  • the mounting substrate formed according to the embodiment, the fifth embodiment, the sixth embodiment, the seventh embodiment, and the eighth embodiment may be used.
  • FIG. 24 (c) an opening is formed so as not to touch the protrusion 24 for inspecting the metal support 11, and the protrusion 24 in the opening and the second electrode pattern 1 ⁇ form the circuit of the mounting board. Perform both open and short inspections.
  • FIG. 24 (b) uses the first embodiment of the present invention (forming an opening from the embodiment of FIG. 9 (d)), the second embodiment and the third embodiment
  • the mounting substrate formed according to the embodiment, the fourth embodiment, the fifth embodiment, the sixth embodiment, the seventh embodiment, and the eighth embodiment may be used.
  • the quality of the mounting substrate used in the ninth embodiment of the present invention can be electrically and completely selected, and almost all of the metal support 11 remains.
  • the mounting reliability described in the embodiment can be maintained. Industrial applicability
  • the present invention it is possible to realize a high density and fine wiring of a mounting substrate corresponding to an increase in the number of terminals and a narrow pitch of a semiconductor device, and to correspond to a miniaturization and a high density of a system.
  • the present invention can provide a mounting substrate having excellent mounting reliability, and can realize a semiconductor package having high performance and excellent reliability.

Abstract

A semiconductor device mounting board in which high density packaging and fining can be realized in response to smaller pitches while ensuring excellent reliability of package by improving a conventional wiring board, its producing method and inspecting method, and a semiconductor package. The semiconductor device mounting board in characterized by comprising a wiring structure film consisting of an insulation layer and a wiring layer, a first electrode pattern provided on one surface of the wiring structure film such that at least the side circumference thereof touches the insulation layer but at least the lower surface thereof does not touch the insulation layer and the surface of the insulation layer provided with the first electrode pattern is coplanar with the lower surface of the first electrode pattern, a second electrode pattern formed on the surface opposite to the first electrode pattern, an insulator film provided with an opening pattern being confined in the first electrode pattern, and a metal support provided on the surface of the insulator film.

Description

明細: 半導体装置搭載基板とその製造方法およびその基板検查法、 並びに半 導体パッケージ 技術分野  The present invention relates to a semiconductor device mounting substrate, a method for manufacturing the same, a method for detecting the substrate, and a semiconductor package
本発明は、 半導体デバイス等の各種デバイスを高密度で搭載し、 高 密度かつ高速おょぴ高周波のモジュールやシステムを実現するために 用いる半導体装置搭載基板とその製造方法およびその基板検査法、 並 ぴに半導体パッケージに関する。 従来技術  The present invention relates to a semiconductor device mounting board used for mounting various devices such as a semiconductor device at a high density and realizing a high-density and high-speed high-frequency module or system, a manufacturing method thereof, a board inspection method thereof, (5) Related to semiconductor packages. Conventional technology
近年、 半導体デバイスの高速、 高集積化による端子の増加や狭ピッ チ化に伴い、 これら半導体デバイスを搭載する実装用配線基板におい ても、 さらなる高密度化、 微細化が求められている。 現在、 よく用い られている実装用基板の例として、 セラミ ック基板、 ビルドアップ基 板、 テープ ¾板がある。  In recent years, with the increase in the number of terminals and the narrower pitch due to the higher speed and higher integration of semiconductor devices, there is a demand for even higher densification and miniaturization of wiring boards for mounting these semiconductor devices. At present, examples of mounting substrates that are often used include a ceramic substrate, a build-up substrate, and a tape substrate.
セラミ ツク基板は、 特開平 8— 3 3 0 4 7 4号公報に開示されてい るような、 アルミナ等からなる絶縁基板と、 その表面に形成された W や M oなどの高融点からなる配線導体とから構成されている。  The ceramic substrate is composed of an insulating substrate made of alumina or the like and a wiring made of a high melting point such as W or Mo formed on the surface, as disclosed in Japanese Patent Application Laid-Open No. 8-330474. And a conductor.
また、 ビルドアップ基板は、 特開平 1 1— 1 7 0 5 8号公報及び特 許第 2 6 7 9 6 8 1号公報に開示されているように、 プリント基板上 に有機樹脂を絶縁材料に使用しエッチング法及びめつき法により銅配 線による微細な回路を形成して多層化している。  Further, as disclosed in Japanese Patent Application Laid-Open No. 11-17058 and Japanese Patent No. 2769681, the build-up substrate is formed by using an organic resin as an insulating material on a printed circuit board. It is used to form a fine circuit with copper wiring by etching and plating to form a multilayer structure.
更に、 テープ基板は、 特開 2 0 0 0— 5 8 7 0 1号公報に示されて いるポリイ ミ ド系等のフィルムに銅配線を形成したものである。 発明が解決しょうとする課題  Further, the tape substrate is formed by forming a copper wiring on a polyimide-based film or the like disclosed in Japanese Patent Application Laid-Open No. 2000-58701. Problems to be solved by the invention
しかしながら、 従来の技術には下記に示すような問題がある。 セラミ ツク基板は、 絶縁基板を構成するセラミ ックが硬くて脆い性 質を有することから、 製造工程及び搬送工程において欠け及び割れ等 の損傷が発生しやすく、 歩留まり低下を起こす問題点がある。 However, the conventional technology has the following problems. The ceramic substrate has a problem in that the ceramic constituting the insulating substrate is hard and brittle, so that damage such as chipping and cracking is likely to occur in the manufacturing process and the transport process, and the yield is reduced.
また、 セラミ ック基板は、 焼成前のグリーンシート上に配線を印刷 し、 各シートを積層して焼成させて製造される。 この製造工程におい て、高温での焼成により収縮が生じるために、焼成後の基板には反り、 変形及び寸法ばらつき等の形状不良が発生しやすい問題点がある。 こ の様な形状不良の発生により、 高密度化された回路基板及ぴフリ ップ チップ等の基板に要求される厳しい平坦度にたいして、 十分対応でき ないという問題がある。 即ち、 この様な形状不良により、 回路の多ピ ン化、 高密度化及び微細化が阻害されると共に、 半導体デバイスの搭 載部の平坦性が失われるため、 半導体デバイスと基板との間の接続さ れた部分にクラック及ぴ剥がれ等が発生しやすく、 半導体デバイスの 信頼性を低下させるという問題がある。  In addition, the ceramic substrate is manufactured by printing wiring on a green sheet before firing, laminating each sheet, and firing. In this manufacturing process, since shrinkage is caused by firing at a high temperature, the fired substrate has a problem that shape defects such as warpage, deformation, and dimensional variation are likely to occur. Due to the occurrence of such a shape defect, there is a problem that it is not possible to sufficiently cope with the strict flatness required for a substrate such as a high-density circuit board and a flip chip. That is, such a shape defect hinders the increase in the number of pins, the density, and the miniaturization of the circuit, and the flatness of the mounting portion of the semiconductor device is lost. There is a problem that cracks and peeling are apt to occur in the connected portions, and the reliability of the semiconductor device is reduced.
更に、 ビルドアップ基板においては、 コア材に使用しているプリ ン ト基板と表層に形成される絶縁樹脂膜との熱膨張差から基板の反りが 発生する。 この反りも多ピン化している半導体デバイスを接続する際 の障害となり、 前述の如く、 回路の高密度化、 微細化を阻害すると共 に、 ビルドアップ基板の歩留まりを低下させている。  Further, in the build-up substrate, the substrate is warped due to the difference in thermal expansion between the print substrate used for the core material and the insulating resin film formed on the surface layer. This warping also becomes an obstacle when connecting semiconductor devices with a large number of pins, and as described above, hinders circuit densification and miniaturization, and also reduces the yield of build-up substrates.
更にまた、 ポリイミ ド系等のテープを使用する基板においては、 半 導体デバィスを搭載する際のテープ基材の伸縮による位置ずれが大き く、 回路の高密度化対応が十分にできないという問題点がある。  Furthermore, there is a problem that a substrate using a tape of polyimide or the like has a large displacement due to expansion and contraction of the tape base material when mounting a semiconductor device, and it is not possible to sufficiently cope with a high density circuit. is there.
そこで、 これらの問題点を解決するため、 特開 2 0 0 0— 3 9 8 0 号公報に開示されている様な、 金属板からなるベース基材にビルドア ップ構造を形成した実装用配線基板が提案されている。 しかしながら、 外部端子をエッチングにより形成しているため、 エッチング時のサイ ドエッチング量制御の限界から狭ピッチな外部端子とすることが困難 である問題点がある。 また、 この実装用配線基板を外部の基板や装置 に実装したときに、 構造上、 外部端子と絶縁体膜の界面に応力が集中 0306526 Therefore, in order to solve these problems, a wiring for mounting in which a build-up structure is formed on a base material made of a metal plate as disclosed in Japanese Patent Application Laid-Open No. 2000-39080. Substrates have been proposed. However, since the external terminals are formed by etching, there is a problem that it is difficult to form the external terminals with a narrow pitch due to the limitation of the side etching amount control during the etching. Also, when this wiring board for mounting is mounted on an external substrate or device, stress is concentrated on the interface between the external terminal and the insulator film due to its structure. 0306526
3 Three
し、 オープン不良となるため、 十分な実装信頼性が得られないことと なる。 However, since open failure occurs, sufficient mounting reliability cannot be obtained.
本発明は係る問題点に鑑みてなされたもめであって、 従来の配線基 板を改良し、 狭ピッチ化に対応した高密度化、 微細化を実現すること ができ、 しかも実装信頼性に優れた半導体装置搭載基板とその製造方 法およびその基板検査法、 並びに半導体パッケージを提供することを 目的とする。 発明の開示  The present invention has been made in view of the above problems, and can improve a conventional wiring board, realize high density and miniaturization corresponding to a narrow pitch, and have excellent mounting reliability. It is an object of the present invention to provide a semiconductor device mounting substrate, a method of manufacturing the same, a method of inspecting the substrate, and a semiconductor package. Disclosure of the invention
上記目的を達成するため、 本発明は次のような半導体装置搭載基板 とその製造方法およびその基板検査法、 並びに半導体パッケージを採 用した。  In order to achieve the above object, the present invention employs the following semiconductor device mounting substrate, a method of manufacturing the same, a method of inspecting the substrate, and a semiconductor package.
即ち、 請求項 1に記載の半導体装置搭載基板は、 交互に積層された 絶縁層 （14) と配線層 （15) からなる配線構造膜 （1 6) と、 電極のパターンが前記配線構造膜の片面に設けられ、 該電極パター ン側面周囲が前記絶縁層に接し、 かつ、 少なく とも前記電極パターン 下面が前記絶縁層に接することなく設けられ、 前記絶縁層面と電極パ ターン下面が同一平面上にある第 1電極パターン （13) と、  That is, the semiconductor device mounting substrate according to claim 1, wherein a wiring structure film (16) including an insulating layer (14) and a wiring layer (15) alternately stacked, and an electrode pattern is formed of the wiring structure film. The electrode pattern is provided on one side, the periphery of the side of the electrode pattern is in contact with the insulating layer, and at least the lower surface of the electrode pattern is provided without being in contact with the insulating layer, and the insulating layer surface and the electrode pattern lower surface are on the same plane. A first electrode pattern (13),
前記第 1電極パターンの反対側の面に形成された第 2電極パターン (1 7) と、  A second electrode pattern (17) formed on a surface opposite to the first electrode pattern,
前記第 1電極パタ一ンの下部に位置する開口パターンを設けた絶縁 体膜 （12) と、  An insulator film (12) provided with an opening pattern located below the first electrode pattern;
前記絶縁体膜下表面に設けられた金属支持体 （1 1) と  A metal support (11) provided on the lower surface of the insulator film;
を有することを特徴とする。  It is characterized by having.
さらに、 請求項 2に記載の半導体装置搭載基板は、 前記配線層 （1 5) の各層は、 前記絶縁層 （14) 内に設けられたビアを介して互い に接続され、  Furthermore, in the semiconductor device mounting board according to claim 2, each layer of the wiring layer (15) is connected to each other via a via provided in the insulating layer (14),
前記第 2電極パターン （17) は、 前記配線層 （15) 及び前記ビ ァを介して前記第 1電極パターン （1 3) に接続されていることを特 徴とする。 The second electrode pattern (17) is connected to the first electrode pattern (13) via the wiring layer (15) and the via. Sign.
さらに、 請求項 3に記載の半導体装置搭載基板は、 前記第 1電極パ ターン （ 1 3) の間及び周囲に導体パターン （ 1 8) が設けられ、 該導体パターン （1 8) は前記配線層 （ 1 5) と前記ビアにより接 続されていることを特徴とする。  Furthermore, in the semiconductor device mounting board according to claim 3, a conductor pattern (18) is provided between and around the first electrode pattern (13), and the conductor pattern (18) is provided on the wiring layer. (15) and is connected by the via.
さらに、 請求項 4に記載の半導体装置搭載基板は、 前記金属支持体 ( 1 1 ) と前記導体パターン （ 1 8) が前記絶縁体膜 （ 1 2) に形成 されたビア （ 1 9) により接続されていることを特徴とする。  Further, in the semiconductor device mounting board according to claim 4, the metal support (11) and the conductor pattern (18) are connected by a via (19) formed in the insulator film (12). It is characterized by having been done.
さらに、 請求項 5に記載の半導体装置搭載基板は、 前記絶縁層 （ 1 4) は、 膜強度が 70MP a以上、 破断伸び率が 5%以上、 ガラス転 移温度が 1 50°C以上、 熱膨張係数が 60 p pm/°C以下の絶縁材料 からなることを特徴とする。  Further, in the semiconductor device mounting board according to claim 5, the insulating layer (14) has a film strength of 70 MPa or more, a breaking elongation of 5% or more, a glass transition temperature of 150 ° C or more, and heat. It is characterized by being made of an insulating material having an expansion coefficient of 60 ppm / ° C or less.
さらに、 請求項 6に記載の半導体装置搭載基板は、 前記絶縁層 （ 1 4)は、弾性率が 1 0 GP a以上、熱膨張係数が 30 p p m/°C以下、 ガラス転移温度が 1 50 °C以上の絶縁材料からなることを特徴とする。 さらに、請求項 7に記載の半導体装置搭載基板は、前記絶縁体膜（ 1 2) は、 ソルダーレジス トとしての機能を有することを特徴とする。 さらに、請求項 8に記載の半導体装置搭載基板は、前記絶縁体膜（ 1 2) が、 前記絶縁層 （ 1 4) と同一の材料からなることを特徴とする。 さらに、 請求項 9に記載の半導体装置搭載基板は、 前記第 1電極パ ターン （ 1 3) の上面に形成された誘電体層 （20) と、 該誘電体層 (20) の上面に前記配線構造膜（ 1 6) と導通している導電体層 （2 1 ) とからなるコンデンサ （22). が設けられていることを特徴とす る。  Furthermore, in the semiconductor device mounting substrate according to claim 6, the insulating layer (14) has an elastic modulus of 10 GPa or more, a thermal expansion coefficient of 30 ppm / ° C or less, and a glass transition temperature of 150 °. It is characterized by being made of an insulating material of C or more. Furthermore, the semiconductor device mounting substrate according to claim 7 is characterized in that the insulator film (12) has a function as a solder resist. Further, the semiconductor device mounting substrate according to claim 8 is characterized in that the insulator film (12) is made of the same material as the insulating layer (14). The semiconductor device mounting board according to claim 9, further comprising: a dielectric layer (20) formed on an upper surface of the first electrode pattern (13); and a wiring formed on an upper surface of the dielectric layer (20). A capacitor (22) comprising a structural film (16) and a conductive layer (21) in conduction is provided.
さらに、 請求項 1 0に記載の半導体装置搭載基板は、 前記金属支持 体 （1 1 ) は、 ステンレス、 鉄、 ニッケル、 銅おょぴアルミニウムか らなる群から選択された少なく とも 1種の金属又はその合金からなる ことを特徴とする。  The semiconductor device mounting board according to claim 10, wherein the metal support (11) is at least one metal selected from the group consisting of stainless steel, iron, nickel, and copper aluminum. Or an alloy thereof.
さらに、 請求項 1 1に記載の半導体装置搭載基板は、 前記金属支持 体 （1 1) は、 前記絶縁体膜 （12) 表面が露出するように前記絶縁 体膜 （1 2) の下面に設けられていることを特徴とする。 Further, the semiconductor device mounting board according to claim 11, wherein the metal support The body (11) is provided on the lower surface of the insulator film (12) such that the surface of the insulator film (12) is exposed.
さらに、 請求項 1 2に記載の半導体装置搭載基板は、 前記金属支持 体 （1 1) は、 前記絶縁体膜 （12) の下面全体に設けられ、 かつ前 記第 1電極パターン （1 3) と接している突起 （24) を有している ことを特徴とする。  Further, in the semiconductor device mounting board according to claim 12, the metal support (11) is provided on the entire lower surface of the insulator film (12), and the first electrode pattern (13) is provided. And a projection (24) that is in contact with the substrate.
さらに、 請求項 1 3に記載の半導体装置搭載基板は、 前記導体バタ —ン （1 8) と前記金属支持体 （1 1) が、 前記突起 （24) により 接続されていることを特徴とする。  Furthermore, the semiconductor device mounting board according to claim 13, wherein the conductor pattern (18) and the metal support (11) are connected by the projection (24). .
さらに、 請求項 14に記載の半導体装置搭載基板は、 前記突起 （2 4) は、 めっき法、 エッチング、 導電性ペース ト、 機械加工のいずれ かの 1つもしくは複合した方法により形成されることを特徴とする。 又、 請求項 15に記載の半導体パッケージは、 請求項 1 ~ 14のい ずれか一つに記載の半導体装置搭載基板に少なく とも 1つ以上の半導 体装置が搭載されてなることを特徴とする。  Furthermore, in the semiconductor device mounting substrate according to claim 14, the protrusion (24) is formed by one or a combination of plating, etching, conductive paste, and machining. Features. A semiconductor package according to a fifteenth aspect is characterized in that at least one semiconductor device is mounted on the semiconductor device mounting substrate according to any one of the first to fourteenth aspects. I do.
さらに、 請求項 1 6に記載の半導体パッケージは、 少なく とも一面 に半導体装置が搭載されたことを特徴とする。  Further, a semiconductor package according to claim 16 is characterized in that a semiconductor device is mounted on at least one surface.
さらに、 請求項 1 7に記載の半導体パッケージは、 前記半導体装置 が、 低融点金属又は導電性樹脂のいずれかの材料によりフリ ップチッ プ接続されていることを特徴とする。  Furthermore, the semiconductor package according to claim 17 is characterized in that the semiconductor device is flip-chip connected by using any one of a low melting point metal and a conductive resin.
さらに、 請求項 1 8に記載の半導体パッケージは、 前記半導体装置 が、 低融点金属、 有機樹脂又は金属混入樹脂からなる群から選択され た少なく とも 1種の材料により連結されていることを特徴とする。 又、 請求項 1 9に記載の半導体装置搭載基板の製造方法は、 金属支 持体 （1 1) の表面の所望の位置に複数個の突起 （24) を形成する 工程と、  Furthermore, the semiconductor package according to claim 18, wherein the semiconductor device is connected by at least one material selected from the group consisting of a low melting point metal, an organic resin, and a metal-mixed resin. I do. In addition, the method for manufacturing a semiconductor device mounting substrate according to claim 19 includes a step of forming a plurality of projections (24) at desired positions on the surface of the metal support (11).
前記金属支持体表面の前記突起形成領域を除く領域に絶縁体膜 （ 1 2) を形成する工程と、  Forming an insulator film (12) in a region other than the protrusion formation region on the surface of the metal support;
前記絶縁体膜上に第 1電極パターン （13) を形成する工程と、 該第 1電極パターン （13) の側面周囲に接し、 かつ下面が前記第 1電極パターン （1 3) 下面と同一平面上になるように絶縁層 （14) を形成する工程と、 Forming a first electrode pattern (13) on the insulator film; Forming an insulating layer (14) so as to be in contact with the side surface of the first electrode pattern (13) and the lower surface is flush with the lower surface of the first electrode pattern (13);
第 1電極パターン （13) の片面に配線層 （1 5) を形成する工程 と、  Forming a wiring layer (15) on one side of the first electrode pattern (13);
前記第 1電極パターンの反対側の面に第 2電極パターン （17) を 形成する工程と、  Forming a second electrode pattern (17) on a surface opposite to the first electrode pattern;
前記金属支持体に前記絶縁体膜と前記突起が露出するように第 1の 開口部を形成する工程と、  Forming a first opening in the metal support so that the insulator film and the protrusion are exposed;
前記突起を除去して、 前記第 1電極パターンが露出するように第 2 の開口部を前記絶縁体膜に形成する工程と、  Removing the protrusion and forming a second opening in the insulator film so that the first electrode pattern is exposed;
前記絶縁体膜の開口部形状を整える工程を含むことを特徴とする。 又、 請求項 20に記載の半導体装置搭載基板の製造方法は、 金属支 持体 （1 1) の表面の所望の位置に複数個の突起 （24) を形成する 工程と、  The method includes a step of adjusting the shape of the opening of the insulator film. Also, the method for manufacturing a semiconductor device mounting substrate according to claim 20 includes a step of forming a plurality of projections (24) at desired positions on the surface of the metal support (11);
前記金属支持体表面の前記突起形成領域を除く領域に絶縁体膜 （ 1 An insulator film (1)
2) を形成する工程と、 2) forming
前記絶縁体膜上に第 1電極パターン （13) を形成する工程と、 前記第 1電極パターンの間及び周囲に導体パターン （1 8) を形成 する工程と、  Forming a first electrode pattern (13) on the insulator film; forming a conductor pattern (18) between and around the first electrode pattern;
該第 1電極パターン （13) の側面周囲に接し、 かつ下面が前記第 1電極パターン （13) 下面と同一平面上になるように絶縁層 （14) を形成する工程と、  Forming an insulating layer (14) so as to be in contact with the side surface of the first electrode pattern (13) and the lower surface is flush with the lower surface of the first electrode pattern (13);
前記第 1電極パターン （1 3) の片面に配線層 （1 5) を形成する 工程と、  Forming a wiring layer (15) on one surface of the first electrode pattern (13);
前記第 1電極パターンの反対側の面に第 2電極パターン （1 7) を 形成する工程と、  Forming a second electrode pattern (17) on a surface opposite to the first electrode pattern;
前記金属支持体に前記絶縁体膜と前記突起が露出するように第 1の 開口部を形成する工程と、 前記突起を除去して、 前記第 1電極パターンが露出するように第 2 の開口部を前記絶縁体膜に形成する工程と、 Forming a first opening in the metal support so that the insulator film and the protrusion are exposed; Removing the protrusion and forming a second opening in the insulator film so that the first electrode pattern is exposed;
前記絶縁体膜の開口部形状を整える工程を含むことを特徴とする。 又、 請求項 21に記載の半導体装置搭載基板の製造方法は、 金属支 持体 （1 1) の表面の所望の位置に複数個の突起 （24) を形成する 工程と、  The method includes a step of adjusting the shape of the opening of the insulator film. The method of manufacturing a semiconductor device mounting substrate according to claim 21, further comprising: forming a plurality of protrusions (24) at desired positions on the surface of the metal support (11).
前記金属支持体表面の前記突起形成領域を除く領域に絶縁体膜 （ 1 An insulator film (1)
2) を形成する工程と、 2) forming
前記絶縁体膜上に第 1電極パターン （13) を形成する工程と、 前記金属支持体の一部が露出するようにビア （1 9) を形成するェ 程と、  Forming a first electrode pattern (13) on the insulator film; and forming a via (19) such that a part of the metal support is exposed;
前記第 1電極パターンの間及び周囲に、 かつ導体パターン （1 8) が前記ビアにより前記金属支持体と接続できるように前記導体パター ン （1 8) を形成する工程と、  Forming the conductor pattern (18) between and around the first electrode pattern and so that the conductor pattern (18) can be connected to the metal support by the via;
該第 1電極パターン （13) の側面周囲に接し、 かつ下面が前記第 1電極パターン （ 13) 下面と同一平面上になるように絶縁層 （14) を形成する工程と、  Forming an insulating layer (14) so as to be in contact with the side surface of the first electrode pattern (13) and the lower surface is flush with the lower surface of the first electrode pattern (13);
前記第 1電極パターン （13) の片面に配線層 （1 5) を形成する 工程と、  Forming a wiring layer (15) on one surface of the first electrode pattern (13);
前記第 1電極パターンの反対側の面に第 2電極パターン （17) を 形成する工程と、  Forming a second electrode pattern (17) on a surface opposite to the first electrode pattern;
前記金属支持体に前記絶縁体膜と前記突起が露出するように第 1の 開口部を形成する工程と、  Forming a first opening in the metal support so that the insulator film and the protrusion are exposed;
前記突起を除去して、 前記第 1電極パターンが露出するように第 2 の開口部を前記絶縁体膜に形成する工程と、  Removing the protrusion and forming a second opening in the insulator film so that the first electrode pattern is exposed;
前記絶縁体膜の開口部形状を整える工程を含むことを特徴とする。 さらに、 請求項 22に記載の半導体装置搭載基板の製造方法は、 前 記第 1電極パターンと前記導体パターンが同一の工程で形成されるこ とを特徴とする。 さらに、 請求項 23に記載の半導体装置搭載基板の製造方法は、 前 記第 1電極パターンを形成する工程と、 前記第 1電極パターン上に配 線層 （1 5) を形成する工程との間に、 少なく とも 1個の前記第 1電 極パターン上に薄膜コンデンサを形成する工程を有することを特徴と する。 The method includes a step of adjusting the shape of the opening of the insulator film. Further, a method of manufacturing a semiconductor device mounting substrate according to claim 22 is characterized in that the first electrode pattern and the conductor pattern are formed in the same step. The method of manufacturing a semiconductor device mounting substrate according to claim 23, further comprising: a step of forming the first electrode pattern and a step of forming a wiring layer (15) on the first electrode pattern. Preferably, the method further comprises a step of forming a thin film capacitor on at least one of the first electrode patterns.
さらに、 請求項 24に記載の半導体装置搭載基板の製造方法は、 前 記第 1電極パターンを形成する工程の前に、 前記第 1の開口部を形成 する予定の領域に凹部 （29) を形成する工程を有することを特徴と する。  Furthermore, in the method of manufacturing a semiconductor device mounting substrate according to claim 24, before the step of forming the first electrode pattern, a concave portion (29) is formed in a region where the first opening is to be formed. It is characterized by having a step of performing.
又、 請求項 25に記載の半導体装置搭載基板の製造方法は、 金属支 持体 （1 1) の両表面の所望の位置に複数個の突起 （24) を形成す る工程と、  Also, the method for manufacturing a semiconductor device mounting substrate according to claim 25, comprises a step of forming a plurality of protrusions (24) at desired positions on both surfaces of the metal support (11);
前記金属支持体両表面の前記突起形成領域を除く領域に絶縁体膜 (1 2) を形成する工程と、  Forming an insulator film (1 2) in a region excluding the protrusion formation region on both surfaces of the metal support;
前記絶縁体膜上に第 1電極パターン （1 3) を形成する工程と、 該第 1電極パターン （13) の側面周囲に接し、 かつ下面が前記第 Forming a first electrode pattern (13) on the insulator film; and contacting a periphery of a side surface of the first electrode pattern (13), and a lower surface of the first electrode pattern (13).
1電極パターン （1 3)下面と同一平面上になるように絶縁層 （14) を形成する工程と、 (1) forming an insulating layer (14) so as to be flush with the lower surface of the electrode pattern (13);
第 1電極パターン （13) の片面に配線層 （1 5) を形成する工程 と、  Forming a wiring layer (15) on one side of the first electrode pattern (13);
前記第 1電極パターンの反対側の面に第 2電極パターン （1 7) を 形成する工程と、  Forming a second electrode pattern (17) on a surface opposite to the first electrode pattern;
前記金属支持体を水平方向で半分に分割して第 1及び第 2の金属支 持体 （1 1 a, l i b ) を形成する工程と、  Dividing the metal support in half in the horizontal direction to form first and second metal supports (11a, lib);
前記第 1及び前記第 2の金属支持体に前記各絶縁体膜と前記各突起 が露出するように第 1の開口部を形成する工程と、  Forming a first opening in the first and second metal supports so that the insulator films and the projections are exposed;
前記突起を除去して、 前記第 1電極パターンが露出するように第 2 の開口部を前記絶縁体膜に形成する工程と、  Removing the protrusion and forming a second opening in the insulator film so that the first electrode pattern is exposed;
前記絶縁体膜の開口部形状を整える工程を含むことを特徴とする。 306526 The method includes a step of adjusting the shape of the opening of the insulator film. 306526
9 9
又、 請求項 26に記載の半導体装置搭載基板の製造方法は、 金属支 持体 （1 1) の両表面の所望の位置に複数個の突起 （24) を形成す る工程と、  The method for manufacturing a semiconductor device mounting substrate according to claim 26, further comprising: forming a plurality of protrusions (24) at desired positions on both surfaces of the metal support (11);
前記金属支持体両表面の前記突起形成領域を除く領域に絶縁体膜 (12) を形成する工程と、  Forming an insulator film (12) in a region excluding the protrusion formation region on both surfaces of the metal support;
前記絶縁体膜上に第 1電極パターン （1 3) を形成する工程と、 前記第 1電極パターンの間及び周囲に導体パターン （18) を形成 する工程と、  Forming a first electrode pattern (13) on the insulator film; forming a conductor pattern (18) between and around the first electrode pattern;
該第 1電極パターン （13) の側面周囲に接し、 かつ下面が前記第 1電極パターン （1 3) 下面と同一平面上になるように絶縁層 （14) を形成する工程と、  Forming an insulating layer (14) so as to be in contact with the side surface of the first electrode pattern (13) and the lower surface is flush with the lower surface of the first electrode pattern (13);
前記第 1電極パターンの片面に配線層 （1 5) を形成する工程と、 前記第 1電極パターンの反対側の面に第 2電極パターン （17) を 形成する工程と、  Forming a wiring layer (15) on one surface of the first electrode pattern; and forming a second electrode pattern (17) on a surface opposite to the first electrode pattern;
前記金属支持体を水平方向で半分に分割して第 1及び第 2の金属支 持体 （1 1 a, l i b) を形成する工程と、  Splitting the metal support in half in the horizontal direction to form first and second metal supports (11a, lib);
前記第 1及び前記第 2の金属支持体に前記各絶縁体膜と前記各突起 が露出するように第 1の開口部を形成する工程と、  Forming a first opening in the first and second metal supports so that the insulator films and the projections are exposed;
前記突起を除去して、 前記第 1電極パターンが露出するように第 2 の開口部を前記絶縁体膜に形成する工程と、  Removing the protrusion and forming a second opening in the insulator film so that the first electrode pattern is exposed;
前記絶縁体膜の開口部形状を整える工程を含むことを特徴とする。 又、 請求項 27に記載の半導体装置搭載基板の製造方法は、 金属支 持体 （1 1) の両表面の所望の位置に複数個の突起 （24) を形成す る工程と、  The method includes a step of adjusting the shape of the opening of the insulator film. A method for manufacturing a semiconductor device mounting substrate according to claim 27, further comprising: forming a plurality of protrusions (24) at desired positions on both surfaces of the metal support (11);
前記金属支持体両表面の前記突起形成領域を除く領域に絶縁体膜 (1 2) を形成する工程と、  Forming an insulator film (1 2) in a region excluding the protrusion formation region on both surfaces of the metal support;
前記絶縁体膜上に第 1電極パターン （13) を形成する工程と、 前記金属支持体の一部が露出するようにビア （1 9) を形成するェ 程と、 前記第 1電極パターンの間及び周囲に、 かつ導体パターン （ 1 8) が前記ビアにより前記金属支持体と接続できるように前記導体パタ一 ン （ 1 8) を形成する工程と、 Forming a first electrode pattern (13) on the insulator film; and forming a via (19) such that a part of the metal support is exposed; Forming the conductor pattern (18) between and around the first electrode pattern and so that the conductor pattern (18) can be connected to the metal support by the via;
該第 1電極パターン （ 1 3) の側面周囲に接し、 かつ下面が前記第 1電極パターン （ 1 3) 下面と同一平面上になるように絶縁層 （ 1 4) を形成する工程と、  Forming an insulating layer (14) so as to be in contact with the side surface of the first electrode pattern (13) and the lower surface is flush with the lower surface of the first electrode pattern (13);
第 1電極パターン （ 1 3) の片面に配線層 （ 1 5) を形成する工程 と、  Forming a wiring layer (15) on one side of the first electrode pattern (13);
前記第 1電極パターンの反対側の面に第 2電極パターン （1 7) を 形成する工程と、  Forming a second electrode pattern (17) on a surface opposite to the first electrode pattern;
前記金属支持体を水平方向で半分に分割して第 1及び第 2の金属支 持体 （ 1 1 a, l i b) を形成する工程と、  Dividing the metal support in half in the horizontal direction to form first and second metal supports (11a, lib);
前記第 1及び前記第 2の金属支持体に前記各絶縁体膜と前記各突起 が露出するように第 1の開口部を形成する工程と、  Forming a first opening in the first and second metal supports so that the insulator films and the projections are exposed;
前記突起を除去して、 前記第 1電極パターンが露出するように第 2 の開口部を前記絶縁体膜に形成する工程と、  Removing the protrusion and forming a second opening in the insulator film so that the first electrode pattern is exposed;
前記絶縁体膜の開口部形状を整える工程を含むことを特徴とする。 又、 請求項 28に記載の半導体装置搭載基板の製造方法は、 第 1及 び第 2の金属支持体を 2枚張り合わせる工程と、  The method includes a step of adjusting the shape of the opening of the insulator film. Further, the method of manufacturing a semiconductor device mounting substrate according to claim 28, comprises bonding two first and second metal supports,
前記第 1及び前記第 2の金属支持体 （ 1 1 a, l i b) の表面の所 望の位置に複数個の突起 （24) を形成する工程と、  Forming a plurality of protrusions (24) at desired positions on the surface of the first and second metal supports (11a, lib);
前記第 1及び前記第 2の金属支持体表面の前記突起形成領域を除く 領域に絶縁体膜 （ 1 2) を形成する工程と、  Forming an insulator film (12) in a region excluding the protrusion formation region on the first and second metal support surfaces;
前記第 1及び前記第 2の金属支持体における前記各絶縁体膜上に第 1電極パターン （ 1 3) を形成する工程と、  Forming a first electrode pattern (13) on each of the insulator films in the first and second metal supports;
前記第 1及び前記第 2の金属支持体における前記各第 1電極パター ン （1 3) の側面周囲に接し、 かつ下面が前記第 1電極パターン （ 1 3)下面と同一平面上になるように絶縁層（ 1 4)を形成する工程と、 前記第 1及び前記第 2の金属支持体における前記各第 1電極パター ン （13) の片面に配線層 （15) を形成する工程と、 前記第 1電極パターンの反対側の面に第 2電極パターン （1 7) を 形成する工程と、 The first and second metal supports are in contact with the periphery of the side surface of each first electrode pattern (13), and the lower surface is flush with the lower surface of the first electrode pattern (13). Forming an insulating layer (14); and forming the first electrode patterns on the first and second metal supports. Forming a wiring layer (15) on one surface of the first electrode pattern (13); and forming a second electrode pattern (17) on a surface opposite to the first electrode pattern.
前記第 1及び前記第 2の金属支持体を水平方向で半分に分割するェ 程と、  Splitting the first and second metal supports in half in the horizontal direction;
前記第 1及び前記第 2の金属支持体に前記各絶縁体膜と前記各突起 が露出するように第 1の開口部を形成する工程と、  Forming a first opening in the first and second metal supports so that the insulator films and the projections are exposed;
前記突起を除去して、 前記第 1電極パターンが露出するように第 2 の開口部を前記絶縁体膜に形成する工程と、  Removing the protrusion and forming a second opening in the insulator film so that the first electrode pattern is exposed;
前記絶縁体膜の開口部形状を整える工程を含むことを特徴とする。 又、 請求項 29に記載の半導体装置搭載基板の製造方法は、 第 1及 ぴ第 2の金属支持体を 2枚張り合わせる工程と、  The method includes a step of adjusting the shape of the opening of the insulator film. Also, the method for manufacturing a semiconductor device mounting board according to claim 29 includes a step of bonding two first and second metal supports,
前記第 1及び前記第 2の金属支持体 （1 1 a, l i ) の表面の所 望の位置に複数個の突起 （24) を形成する工程と、  Forming a plurality of protrusions (24) at desired positions on the surface of the first and second metal supports (11a, l i);
前記第 1及び前記第 2の金属支持体表面の前記突起形成領域を除く 領域に絶縁体膜 （12) を形成する工程と、  Forming an insulator film (12) in a region excluding the protrusion formation region on the first and second metal support surfaces;
前記第 1及び前記第 2の金属支持体における前記各絶縁体膜上に第 1電極パターン （13) を形成する工程と、  Forming a first electrode pattern (13) on each of the insulator films of the first and second metal supports;
前記第 1及び前記第 2の金属支持体における前記各第 1電極パ夕一 ンの間及び周囲に導体パターン （18) を形成する工程と、  Forming a conductor pattern (18) between and around each of the first electrode patterns on the first and second metal supports;
前記第 1及び前記第 2の金属支持体における前記各第 1電極パター ン （1 3) の側面周囲に接し、 かつ下面が前記第 1電極パターン （1 3)下面と同一平面上になるように絶縁層（14)を形成する工程と、 前記第 1及び前記第 2の金属支持体における前記各第 1電極パター ン （1 3) の片面に配線層 （15) を形成する工程と、  The first and second metal supports are in contact with the periphery of the side surface of each first electrode pattern (13), and the lower surface is flush with the lower surface of the first electrode pattern (13). A step of forming an insulating layer (14); and a step of forming a wiring layer (15) on one surface of each of the first electrode patterns (13) in the first and second metal supports.
前記第 1電極パターンの反対側の面に第 2電極パターン （1 7) を 形成する工程と、  Forming a second electrode pattern (17) on a surface opposite to the first electrode pattern;
前記第 1及び前記第 2の金属支持体を水平方向で半分に分割するェ 程と、 前記第 1及び前記第 2の金属支持体に前記各絶縁体膜と前記各突起 が露出するように第 1の開口部を形成する工程と、 Splitting the first and second metal supports in half in the horizontal direction; Forming a first opening in the first and second metal supports so that the insulator films and the projections are exposed;
前記突起を除去して、 前記第 1電極パターンが露出するように第 2 の開口部を前記絶縁体膜に形成する工程と、  Removing the protrusion and forming a second opening in the insulator film so that the first electrode pattern is exposed;
前記絶縁体膜の開口部形状を整える工程を含むことを特徴とする。 又、 請求項 30に記載の半導体装置搭載基板の製造方法は、 第 1及 ぴ第 2の金属支持体を 2枚張り合わせる工程と、  The method includes a step of adjusting the shape of the opening of the insulator film. Further, the method for manufacturing a semiconductor device mounting substrate according to claim 30 includes a step of bonding two first and second metal supports,
前記第 1及び前記第 2の金属支持体 （1 1 a, l i b ) の表面の所 望の位置に複数個の突起 （24) を形成する工程と、  Forming a plurality of protrusions (24) at desired positions on the surface of the first and second metal supports (11a, lib);
前記第 1及び前記第 2の金属支持体両表面の前記突起形成領域を除 く領域に絶縁体膜 （1 2) を形成する工程と、  Forming an insulator film (12) in a region excluding the protrusion formation region on both surfaces of the first and second metal supports;
前記第 1及び前記第 2の金属支持体における前記各絶縁体膜上に第 1電極パターン （1 3) を形成する工程と、  Forming a first electrode pattern (13) on each of the insulator films of the first and second metal supports;
前記第 1及び前記第 2の金属支持体の一部が露出するようにビア (1 9) を形成する工程と、  Forming a via (19) such that a part of the first and second metal supports is exposed;
前記第 1及び前記第 2の金属支持体における前記各第 1電極パター ンの間及び周囲に、 かつ導体パターン （18) が前記ビアにより前記 金属支持体と接続できるように前記導体パターン （1 8) を形成する 工程と、  The conductor pattern (18) is provided between and around the first electrode patterns on the first and second metal supports and so that the conductor pattern (18) can be connected to the metal support by the via. )
前記第 1及び前記第 2の金属支持体における前記各第 1電極パター ン （ 1 3)の側面周囲に接し、 かつ下面が前記各第 1電極パターン （ 1 3)下面と同一平面上になるように絶縁層（14)を形成する工程と、 前記第 1及び前記第 2の金属支持体における前記各第 1電極パター ン （1 3) の片面に配線層 （15) を形成する工程と、  The first and second metal supports are in contact with the periphery of the side surface of each first electrode pattern (13), and the lower surface is flush with the lower surface of each first electrode pattern (13). Forming a wiring layer (15) on one surface of each of the first electrode patterns (13) in the first and second metal supports;
前記各第 1電極パターンの反対側の面に第 2電極パターン （1 7) を形成する工程と、  Forming a second electrode pattern (17) on a surface opposite to each of the first electrode patterns;
前記第 1及び前記第 2の金属支持体を水平方向で半分に分割するェ 程と、  Splitting the first and second metal supports in half in the horizontal direction;
前記第 1及び前記第 2の金属支持体に前記絶縁体膜と前記突起が露 出するように第 1の開口部を形成する工程と、 The insulator film and the protrusion are exposed on the first and second metal supports. Forming a first opening to project out;
前記突起を除去して、 前記第 1電極パターンが露出するように第 2 の開口部を前記絶縁体膜に形成する工程と、  Removing the protrusion and forming a second opening in the insulator film so that the first electrode pattern is exposed;
前記絶縁体膜の開口部形状を整える工程を含むことを特徴とする。 さらに、 請求項 3 1 に記載の半導体装置搭載基板の製造方法は、 前 記第 1及び前記第 2の金属支持体 （ 1 1 a , l i b ) が張り合わせる 工程の前に、 前記第 1 の開口部を形成する予定の領域に凹部 （2 9 ) を形成する工程を有することを特徴とする。  A step of adjusting the shape of the opening of the insulator film. The method of manufacturing a semiconductor device mounting substrate according to claim 31, wherein the first opening is formed before the step of bonding the first and second metal supports (11 a, lib). Forming a concave portion (29) in a region where a portion is to be formed.
さらに、 請求項 3 2に記載の半導体装置搭載基板の製造方法は、 前 記第 1電極パターン （ 1 3 ) を形成する工程と、 前記第 1電極パター ン上に配線構造を形成する工程との間に、 少なく とも 1個の前記第 1 電極パターン上に薄膜コンデンサを形成する工程を有することを特徴 とする。  The method of manufacturing a semiconductor device mounting substrate according to claim 32, further comprising: forming the first electrode pattern (13); and forming a wiring structure on the first electrode pattern. In the method, a step of forming a thin film capacitor on at least one of the first electrode patterns is provided.
さらに、 請求項 3 3に記載の半導体装置搭載基板の製造方法は、 前 記第 1電極パターンが前記第 2電極パターンの所望の位置で接続する ように半田ボール又は接続ピンを形成する工程を有することを特徴と する。  Furthermore, the method for manufacturing a semiconductor device mounting substrate according to claim 33 includes a step of forming a solder ball or a connection pin so that the first electrode pattern is connected at a desired position of the second electrode pattern. It is characterized.
さらに、 請求項 3 4に記載の半導体装置搭載基板の製造方法は、 前 記金属支持体は、 ステン レス、 鉄、 ニッケル、 銅およびアルミ ニウム からなる群から選択された少なく とも 1種の金属又はその合金からな ることを特徴とする。  Further, in the method of manufacturing a semiconductor device mounting substrate according to claim 34, the metal support is at least one metal selected from the group consisting of stainless steel, iron, nickel, copper, and aluminum. It is characterized by being made of the alloy.
さらに、 請求項 3 5に記載の半導体装置搭載基板の製造方法は、 前 記突起が、 めっき法、 エッチング、 導電性ペース ト、 機械加工のいず れかの 1つもしくは複合した方法により形成されることを特徴とする。 又、 請求項 3 6に記載の半導体パッケージの製造方法は、 請求項 1 9〜3 5のいずれか 1項に記載の方法により製造された半導体装置搭 載基板の少なく とも 1面に、半導体装置を接続することを特徴とする。  Further, in the method of manufacturing a semiconductor device mounting substrate according to claim 35, the projection is formed by one or a combination of plating, etching, conductive paste, and machining. It is characterized by that. In addition, a method for manufacturing a semiconductor package according to claim 36 is characterized in that at least one surface of the semiconductor device mounting substrate manufactured by the method according to any one of claims 19 to 35 is provided with a semiconductor device. Are connected.
さらに， 請求項 3 7に記載の半導体パッケージの製造方法は、 前記 半導体装置が、 低融点金属又は導電性樹脂のいずれかの材料にフ リ ッ プチップ接続されていることを特徴とする。 Further, in the method for manufacturing a semiconductor package according to claim 37, the semiconductor device is characterized in that the semiconductor device is made of a material having a low melting point or a conductive resin. It is characterized by being chip-connected.
又、 請求項 3 8に記載の半導体装置搭載基板の検査方法は、 請求項 1 9〜3 5のいずれか一つに記載の方法により製造された半導体搭載 基板の前記金属支持体上に第 2電極パターンを形成し、 前記金属支持 体を選択除去した後、 突起を除去せずに接触端子として用いて導通検 查を行うことを特徴とする。 図面の簡単な説明  In addition, the method for inspecting a semiconductor device mounting substrate according to claim 38 is a method for inspecting a semiconductor mounting substrate manufactured by the method according to any one of claims 19 to 35. After an electrode pattern is formed and the metal support is selectively removed, continuity detection is performed using the contact terminal without removing the protrusion. BRIEF DESCRIPTION OF THE FIGURES
図 1は、 本発明の半導体装置搭載基板及び半導体パッケージの第 1 の実施の形態を示す図であって、 （a ) は概略断面図、 （b ) は金属 支持体 1 1側からの下面概略図である。  1A and 1B are diagrams showing a first embodiment of a semiconductor device mounting substrate and a semiconductor package according to the present invention, wherein FIG. 1A is a schematic sectional view, and FIG. FIG.
図 2は、 本発明の半導体装置搭載基板及び半導体パッケージの第 1 の実施の形態の変更例を示す概略断面図である。  FIG. 2 is a schematic sectional view showing a modified example of the first embodiment of the semiconductor device mounting board and the semiconductor package of the present invention.
図 3は、 本発明の平導体装置搭載基板及び半導体パッケージの第 2 の実施の形態を示す概略断面図である。  FIG. 3 is a schematic sectional view showing a flat conductor device mounting substrate and a semiconductor package according to a second embodiment of the present invention.
図 4は、 本発明の半導体装置搭載基板及び半導体パッケージの第 2 の実施の形態の変更例を示す概略断面図である。  FIG. 4 is a schematic cross-sectional view showing a modification of the second embodiment of the semiconductor device mounting board and the semiconductor package of the present invention.
図 5は、 本発明の半導体装置搭載基板及び半導体パッケージの第 3 の実施の形態を示す概略断面図である。  FIG. 5 is a schematic cross-sectional view showing a third embodiment of the semiconductor device mounting board and the semiconductor package of the present invention.
図 6は、 本発明の半導体装置搭載基板及び半導体パッケージの第 4 の実施の形態を示す概略断面図である。  FIG. 6 is a schematic sectional view showing a semiconductor device mounting board and a semiconductor package according to a fourth embodiment of the present invention.
図 7は、 本発明の半導体装置搭載基板及び半導体パッケージの第 4 の実施の形態の変更例を示す概略断面図である。  FIG. 7 is a schematic sectional view showing a modified example of the fourth embodiment of the semiconductor device mounting board and the semiconductor package of the present invention.
図 8は、 本発明の半導体装置搭載基板及び半導体パッケージの第 5 の実施の形態を示す概略断面図である。  FIG. 8 is a schematic sectional view showing a semiconductor device mounting substrate and a semiconductor package according to a fifth embodiment of the present invention.
図 9は、 本発明の半導体装置搭載基板及び半導体パッケージの製造 方法の第 1 の実施の形態を示す部分断面図である。  FIG. 9 is a partial cross-sectional view illustrating a first embodiment of a method for manufacturing a semiconductor device mounting board and a semiconductor package according to the present invention.
図 1 0は、 本発明の半導体装置搭載基板及び半導体パッケージの製 造方法の第 2の実施の形態を示す部分断面図である。 図 1 1は、 本発明の半導体装置搭載基板及び半導体パッケージの製 造方法の第 2の実施の形態の変更例を示す部分断面図である。 FIG. 10 is a partial cross-sectional view showing a second embodiment of a method for manufacturing a semiconductor device mounting substrate and a semiconductor package according to the present invention. FIG. 11 is a partial cross-sectional view showing a modification of the second embodiment of the method for manufacturing a semiconductor device mounting board and a semiconductor package of the present invention.
図 1 2は、 本発明の半導体装置搭載基板及び半導体パッケージの製 造方法の第 3の実施の形態を示す部分断面図である。  FIG. 12 is a partial cross-sectional view showing a third embodiment of the method for manufacturing a semiconductor device mounting board and a semiconductor package according to the present invention.
図 1 3は、 本発明の半導体装置搭載基板及び半導体パッケージの製 造方法の第 3の実施の形態の変更例を示す部分断面図である。  FIG. 13 is a partial cross-sectional view showing a modification of the third embodiment of the method for manufacturing a semiconductor device mounting board and a semiconductor package of the present invention.
図 1 4は、 本発明の半導体装置搭載基板及び半導体パッケージの製 造方法の第 4の実施の形態を示す部分断面図である。  FIG. 14 is a partial cross-sectional view showing a fourth embodiment of the method for manufacturing a semiconductor device mounting board and a semiconductor package according to the present invention.
図 1 5は、 本発明の半導体装置搭載基板及び半導体パッケージの製 造方法の第 5の実施の形態を示す部分断面図である。  FIG. 15 is a partial cross-sectional view showing a fifth embodiment of the method for manufacturing a semiconductor device mounting board and a semiconductor package according to the present invention.
図 1 6は、 本発明の半導体装置搭載基板及び半導体パッケージの製 造方法の第 6の実施の形態を示す部分断面図である。  FIG. 16 is a partial cross-sectional view showing a sixth embodiment of the method for manufacturing a semiconductor device mounting board and a semiconductor package of the present invention.
図 1 7は、 本発明の半導体装置搭載基板及び半導体パッケージの製 造方法の第 7の実施の形態を示す部分断面図である。  FIG. 17 is a partial cross-sectional view showing a seventh embodiment of a method for manufacturing a semiconductor device mounting board and a semiconductor package according to the present invention.
図 1 8は、 本発明の半導体装置搭載基板及び半導体パッケージの製 造方法の第 8の実施の形態を示す部分断面図である。  FIG. 18 is a partial cross-sectional view showing an eighth embodiment of a method for manufacturing a semiconductor device mounting board and a semiconductor package according to the present invention.
図 1 9は、 本発明の半導体装置搭載基板及び半導体パッケージの製 造方法の第 9の実施の形態を示す部分断面図である。  FIG. 19 is a partial cross-sectional view showing a ninth embodiment of a method for manufacturing a semiconductor device mounting board and a semiconductor package according to the present invention.
図 2 0は、 本発明の半導体装置搭載基板及び半導体パッケージの製 造方法の第 9の実施の形態の変更例を示す部分断面図である。  FIG. 20 is a partial cross-sectional view showing a modification of the ninth embodiment of the method of manufacturing a semiconductor device mounting board and a semiconductor package of the present invention.
図 2 1は、 本発明の半導体装置搭載基板及び半導体パッケージの製 造方法の第 9の実施の形態の変更例を示す部分断面図である。  FIG. 21 is a partial cross-sectional view showing a modification of the ninth embodiment of the method for manufacturing a semiconductor device mounting board and a semiconductor package of the present invention.
図 2 2は、 本発明の半導体装置搭載基板及び半導体パッケージの製 造方法の第 1 0の実施の形態を示す部分断面図である。  FIG. 22 is a partial cross-sectional view showing a tenth embodiment of a method for manufacturing a semiconductor device mounting board and a semiconductor package of the present invention.
図 2 3は、 本発明の半導体装置搭載基板及び半導体パッケージの製 造方法の第 1 0の実施の形態の変更例を示す部分断面図である。 図 2 4は、 本発明による半導体搭載基板の検査法を説明するための 部分断面図である。  FIG. 23 is a partial cross-sectional view showing a modification of the tenth embodiment of the method for manufacturing a semiconductor device mounting board and a semiconductor package of the present invention. FIG. 24 is a partial cross-sectional view for explaining the method of inspecting a semiconductor mounting board according to the present invention.
符号 1 1 は、金属支持体である。符号 1 1 aは、金属支持体である。 符号 1 1 bは、 金属支持体である。 符号 1 2は、 絶縁体膜である。 符 号 1 3は、 第 1電極パターンである。 符号 1 4は、 絶縁層である。 符 号 1 5は、 配線層である。 符号 1 6は、 配線構造膜である。 符号 1 Ί は、 第 2電極パターンである。 符号 1 8は、 導体パターンである。 符 号 1 9は、 ビアである。 符号 2 0は、 誘電体層である。 符号 2 1 は、 導電体層である。 符号 2 2は、 コンデンサである。 符号 2 3は、 ソル ダーレジス トである。 符号 2 4は、 突起である。 符号 2 5は、 半導体 装置である。 符号 2 6は、 パッ ドである。 符号 2 7は、 金属バンプで ある。 符号 2 8は、 アンダーフ ィル樹脂である。 符号 2 9は、 凹部で ある。 符号 3 0は、 モールド樹脂である。 符号 3 1は、 スぺーサであ る。 符号 3 2は、 ヒートスプレッダである。 符号 3 3は、 検査針であ る。 発明を実施するための最良の形態 Reference numeral 11 denotes a metal support. Reference numeral 11a is a metal support. Reference numeral 11b is a metal support. Reference numeral 12 denotes an insulator film. Reference numeral 13 is a first electrode pattern. Reference numeral 14 denotes an insulating layer. Reference numeral 15 is a wiring layer. Reference numeral 16 denotes a wiring structure film. Reference numeral 1 1 denotes a second electrode pattern. Reference numeral 18 is a conductor pattern. Reference numeral 19 is a via. Reference numeral 20 denotes a dielectric layer. Reference numeral 21 denotes a conductor layer. Reference numeral 22 denotes a capacitor. Reference numeral 23 is a solder resist. Reference numeral 24 is a protrusion. Reference numeral 25 denotes a semiconductor device. Reference numeral 26 denotes a pad. Reference numeral 27 is a metal bump. Reference numeral 28 denotes an underfill resin. Reference numeral 29 denotes a concave portion. Reference numeral 30 denotes a mold resin. Reference numeral 31 is a spacer. Reference numeral 32 denotes a heat spreader. Reference numeral 3 denotes an inspection needle. BEST MODE FOR CARRYING OUT THE INVENTION
以下、図面を参照し、本発明の実施の形態について詳細に説明する。 まず、 本発明に係る半導体装置搭載基板及び半導体パッケージの実施 の形態について説明する。 半導体装置搭載基板は、 以下、 適宜 「搭載 基板」 という。  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. First, an embodiment of a semiconductor device mounting substrate and a semiconductor package according to the present invention will be described. Hereinafter, the semiconductor device mounting substrate is referred to as “mounting substrate” as appropriate.
本発明搭載基板及び半導体パッケージの第 1の実施の形態について 説明する。 図 1 は本実施の形態に係る半導体装置搭載基板の構成を示 す図であり、 図 1 ( a ) は概略断面図であり、 図 1 ( b ) は金属支持 体 1 1側からの下面概略図である。  A first embodiment of the mounting board and the semiconductor package of the present invention will be described. FIG. 1 is a diagram showing a configuration of a semiconductor device mounting board according to the present embodiment, FIG. 1 (a) is a schematic sectional view, and FIG. 1 (b) is a schematic bottom view from the metal support 11 side. FIG.
図 1 ( a ) 、 （b ) に示す搭載基板は、 絶縁層 1 4と配線層 1 5か らなる配線構造膜 1 6の片面に第 1電極パターン 1 3と、 反対面に第 2電極パターン 1 7と、 第 1電極パターンの配線構造膜 1 6に接して いない面に絶縁体膜 1 2と、 絶縁体膜 1 2の下面に金属支持体 1 1 を 有する。  The mounting substrate shown in FIGS. 1 (a) and 1 (b) has a first electrode pattern 13 on one side of a wiring structure film 16 composed of an insulating layer 14 and a wiring layer 15 and a second electrode pattern on the opposite side. 17, an insulating film 12 on a surface of the first electrode pattern not in contact with the wiring structure film 16, and a metal support 11 on a lower surface of the insulating film 12.
本実施の形態の第 1電極パターン 1 3は、 側面周囲が絶縁層 1 4に 接し、 第 1電極パターン 1 3の下面が絶縁層 1 4の下面と同一平面内 にある。 即ち、 第 1電極パターン 1 3はその下面が絶縁層 1 4と接す ることなく絶縁層 1 4に埋め込まれている。 In the first electrode pattern 13 of the present embodiment, the periphery of the side surface is in contact with the insulating layer 14, and the lower surface of the first electrode pattern 13 is in the same plane as the lower surface of the insulating layer 14. It is in. That is, the lower surface of the first electrode pattern 13 is embedded in the insulating layer 14 without being in contact with the insulating layer 14.
配線構造膜 1 6は、 所定のパターンを有する配線及びこの配線間に 充填された絶縁材料とから構成される配線層 1 5と、 絶縁材料からな る絶縁層 1 4とが交互に積層されている。 この配線構造膜 1 6は、 ビ ルドアップ工法で使用されているサブトラクティブ法、 セミアディテ イブ法又はフルアディティブ法等により積層される。  The wiring structure film 16 is formed by alternately laminating wiring layers 15 composed of wiring having a predetermined pattern and an insulating material filled between the wirings, and insulating layers 14 composed of the insulating material. I have. The wiring structure film 16 is laminated by a subtractive method, a semi-additive method, a full additive method, or the like used in the build-up method.
サブトラクティブ法は、 例えば特開平 1 0— 5 1 1 05号公報に開 示されているように、 基板又は樹脂上の銅箔をエツチングして回路パ タ一ンとする方法である。  The subtractive method is a method of etching a copper foil on a substrate or a resin to form a circuit pattern, as disclosed in, for example, Japanese Patent Application Laid-Open No. H10-5111.
セミアディティブ法は、 例えば特開平 9 - 64493号公報に開示 されているように、 給電層を形成した後にレジス ト内に電解めつきを 析出させ、 レジス トを除去後に給電層をエッチングして回路パターン とする方法である。  In the semi-additive method, for example, as disclosed in Japanese Patent Application Laid-Open No. 9-64493, a circuit is formed by depositing electrolytic plating in a resist after forming a power supply layer and etching the power supply layer after removing the resist. It is a method to make a pattern.
フルアディティブ法は、 例えば特開平 6— 334334号公報に開 示されているように、 基板又は樹脂の表面を活性化させた後にレジス トでパターンを形成し、 このレジス トを絶縁層として無電解めつき法 により回路パターンを形成する方法である。  In the full additive method, as disclosed in, for example, JP-A-6-334334, a pattern is formed with a resist after activating the surface of a substrate or a resin, and the resist is used as an insulating layer as an electroless film. This is a method of forming a circuit pattern by the plating method.
絶縁層 1 4は、 エポキシ樹脂、 エポキシァクリ レート樹脂、 ウレタ ンァク リ レート樹脂、 ポリエステル樹脂、 フヱノール樹脂、 ポリイ ミ ド樹脂、 B C B (b e n z o c y c l o b u t e n e)及ぴ F B 0 (p o l y b e n z o x a z o l e) からなる群から選択された 1種又は 2種以上の有機樹脂により形成されている。 特に、 膜強度が 70MP a以上、 破断伸び率が 5%以上、 ガラス転移温度が 1 50°C以上、 熱 膨張係数が 60 p p m /で以下の絶縁材料 （以下、 適宜 「絶縁材料 A」 と略する。 ） 、 あるいは弾性率が 1 0 GP a以上、 熱膨張係数が 30 P PmZ°C以下、 ガラス転移温度が 1 50°C以上の絶縁材料 （以下、 適宜 「絶縁材料 B」 と略する。 ） を有することが好ましい。 絶縁層 1 4の一層あたりの厚みとしては、 8〃m以上にすることが好ましい。 ここで、 弾性率及び破断伸び率は、 J I S K 7 1 6 1 (引張特 性試験） に準拠した絶縁材料の引っ張り試験による測定値であり、 弾 性率は、 この引っ張り試験結果に基づいた歪み 0. 1 %における強度 からの算出値である。 熱膨張率は J I S C 648 1に準拠した T M A法による測定値であり、 ガラス転移温度は J I S C 648 1 に準拠した DMA法による測定値である。 The insulating layer 14 is one selected from the group consisting of epoxy resin, epoxy acrylate resin, urethane acrylate resin, polyester resin, phenol resin, polyimide resin, BCB (benzocyclobutene) and FB0 (polybenzoxazole). Or, it is formed of two or more kinds of organic resins. In particular, an insulating material having a film strength of 70 MPa or more, an elongation at break of 5% or more, a glass transition temperature of 150 ° C or more, and a thermal expansion coefficient of 60 ppm / or less (hereinafter abbreviated as “insulating material A” as appropriate) Or an insulating material with an elastic modulus of 10 GPa or more, a coefficient of thermal expansion of 30 P PmZ ° C or less, and a glass transition temperature of 150 ° C or more (hereinafter abbreviated as “insulating material B” as appropriate). ) Is preferable. The thickness of one insulating layer 14 is preferably 8 μm or more. Here, the elastic modulus and the elongation at break are values measured by a tensile test of an insulating material in accordance with JISK 7161 (tensile property test), and the elastic modulus is a strain 0 based on the result of the tensile test. This is the value calculated from the intensity at 1%. The coefficient of thermal expansion is a value measured by the TMA method based on JISC6481, and the glass transition temperature is a value measured by the DMA method based on JISC6481.
絶縁材料 Aとしては、 例えば、 エポキシ系樹脂 （日立化成製 ； MC F- 7000 LX) 、 ポリイ ミ ド系樹脂 （日東電工製 ： A P— 683 2 C) 、 ベンゾシクロプテン樹脂 （ダウ ' ケミカル製 ： C y c 1 o t e n e 4000シリーズ） 、 ポリフ ヱニレンエーテル樹脂 （旭化成製 ； ザィ口ン） 、 液晶ポリマーフ ィ ルム （クラ レ製 ； L C P— A) 、 延伸 多孔質フッ素樹脂含浸熱硬化性樹脂 （ジャパンゴァテックス製 ； M l CROLAM 600) などが好適である。  Examples of the insulating material A include an epoxy resin (manufactured by Hitachi Chemical; MC F-7000 LX), a polyimide resin (manufactured by Nitto Denko: AP-6832C), and a benzocycloptene resin (manufactured by Dow Chemical: Cyc 1 otene 4000 series), poly (vinylene ether resin) (made by Asahi Kasei; Xiapan), liquid crystal polymer film (made by Kuraray; LCP-A), stretched porous fluororesin impregnated thermosetting resin (Japan GATEX) And Ml CROLAM 600).
絶縁材料 Bとしては、 例えば、 ガラスクロス含浸エポキシ樹脂 （日 立化成製 ； MC L— E— 679) 、 ァラミ ド不織布含浸エポキシ樹脂 (新神戸電機製 ； E A— 54 1 ) 、 延伸多孔質フッ素樹脂含浸熱硬化 性樹脂 （ジャパンゴァテッ クス製 ； M I CROL AM400) などが 好適である。  Examples of the insulating material B include epoxy resin impregnated with glass cloth (manufactured by Hitachi Chemical; MC L-E-679), epoxy resin impregnated with nonwoven fabric (manufactured by Shin Kobe Electric Co., Ltd .; EA-541), and impregnated with expanded porous fluorine resin Thermosetting resin (manufactured by Japan Gore-Tex; MICROL AM400) is suitable.
絶縁層 1 4は、 これらの有機樹脂のうちの 1種を配線層 1 5間の全 ての絶縁層 1 4に使用してもよいし、 前記有機樹脂の 2種以上の層を 混在させて配線層 1 5間に配置してもよい。本実施の形態においては、 絶縁層 1 4は例えばポリイ ミ ド樹脂により形成するが、 例えば、 最下 層の絶縁層 1 4をポリイ ミ ド樹脂により形成し、 2層目以降をェポキ シ樹脂により形成してもよい。  As the insulating layer 14, one of these organic resins may be used for all the insulating layers 14 between the wiring layers 15, or two or more layers of the organic resin may be mixed. It may be arranged between the wiring layers 15. In this embodiment, the insulating layer 14 is formed of, for example, polyimide resin.For example, the lowermost insulating layer 14 is formed of polyimide resin, and the second and subsequent layers are formed of epoxy resin. It may be formed.
配線層 1 5における配線を構成する金属は、 コストの観点から銅が 最適であるが、 金、 銀、 アルミニウム及びニッケルからなる群から選 択された少なく とも 1種の金属又はその合金も使用可能である。 本実 施の形態においては、 配線層 1 5における配線は銅から構成されてい る。 絶縁体膜 1 2は、 第 1電極パターン 1 3の下面と接しかつ第 1電極 パターン内に収まるように絶縁体膜 1 2に開口部があり、 さらに絶縁 体膜 1 2の下面に金属支持体 1 1が設けられ、 ソルダーレジス トとし ての機能を有している。 絶縁体膜 1 2の材料としては、 ソルダーレジ ス ト としての機能を有する絶縁材料であれば問題はない。 また、 絶縁 層 1 4に用いる材料と同じ材料を適応することも可能である。 Copper is the most suitable metal for wiring in the wiring layer 15 from the viewpoint of cost, but at least one metal selected from the group consisting of gold, silver, aluminum and nickel or its alloy can also be used. It is. In the present embodiment, the wiring in the wiring layer 15 is made of copper. The insulator film 12 has an opening in the insulator film 12 so as to be in contact with the lower surface of the first electrode pattern 13 and to fit within the first electrode pattern, and a metal support is provided on the lower surface of the insulator film 12. 11 is provided and has a function as a solder resist. As a material of the insulator film 12, there is no problem as long as it is an insulating material having a function as a solder resist. Further, the same material as the material used for the insulating layer 14 can be used.
また、 第 2電極パターン 1 7は配線層 1 5の最上層に接続されてお り、 配線層 1 5の各層は絶縁層 1 4内のビアを介して互いに接続され ており、 配線曆 1 5の最下層は絶縁層 1 4内のビアを介して第 1電極 パターン 1 3に接続されている。  Further, the second electrode pattern 17 is connected to the uppermost layer of the wiring layer 15, and each layer of the wiring layer 15 is connected to each other via a via in the insulating layer 14, and the wiring 曆 15 Is connected to the first electrode pattern 13 via a via in the insulating layer 14.
図 1 ( a ) では、 第 2電極パターン 1 7が絶縁層 1 4内に形成され た形で記載しているが、 図 2 ( a ) に示すとおり絶縁層 1 4上に形成 されていても問題はない。 さらに、 図 2 ( b ) に示すとおり、 絶縁層 1 4上に形成された第 2電極パターン 1 7の上にソルダーレジス ト 2 3を設けても良い。  In FIG. 1 (a), the second electrode pattern 17 is described as being formed in the insulating layer 14; however, even if the second electrode pattern 17 is formed on the insulating layer 14 as shown in FIG. 2 (a). No problem. Further, as shown in FIG. 2 (b), a solder resist 23 may be provided on the second electrode pattern 17 formed on the insulating layer 14.
金属支持体 1 1は、 搭載基板を補強するために設けられる。 搭載基 板に金属支持体 1 1 を設けることにより、 搭載基板の反りやうねりな どの変形を抑えることができ、 搭載基板へ半導体装置 （デバイス） の 搭載信頼性や、 外部ボードなどへの搭載基板あるいは半導体パッケ一 ジの実装信頼性を確保できる。 金属支持体 1 1 は、 図 1 ( b ) に示す ようなフレーム状の他、第 1電極パターン 1 3が露出する形であれば、 格子状ゃメ ッシュ状として設けても良い。  The metal support 11 is provided to reinforce the mounting substrate. By providing the metal support 11 on the mounting board, deformation such as warpage and undulation of the mounting board can be suppressed, and the mounting reliability of the semiconductor device (device) on the mounting board and the mounting board on an external board etc. Alternatively, the mounting reliability of the semiconductor package can be ensured. The metal support 11 may be provided in a grid shape or a mesh shape as long as the first electrode pattern 13 is exposed, in addition to the frame shape as shown in FIG. 1 (b).
金属支持体 1 1 としては、 搭載基板に十分な強度を付与でき、 搭載 基板あるいは半導体パッケージの実装時における熱処理に耐えられる 耐熱性を有する金属であることが望ましい。  The metal support 11 is desirably a metal that can impart sufficient strength to the mounting substrate and has heat resistance enough to withstand heat treatment during mounting of the mounting substrate or the semiconductor package.
この材料として、 ステン レス、 鉄、 ニッケル、 銅及びアルミニゥム からなる群から選択された少なく とも 1種の金属又はその合金から構 成されることができるが、 ステンレス及び銅合金が取り扱いの面で最 適である。 また、 金属支持体 1 1の厚さは 0 . 1乃至 1 . 5 m mが適 している。 金属支持体 1 1は、 金属であるため導電性を有しているた め通電が可能である。 This material can be composed of at least one metal or an alloy thereof selected from the group consisting of stainless steel, iron, nickel, copper and aluminum, but stainless steel and copper alloys are the most suitable for handling. Suitable. Further, the thickness of the metal support 11 is preferably 0.1 to 1.5 mm. are doing. Since the metal support 11 is a metal and has conductivity, it can be energized.
本発明によれば、 第 1電極パターン 1 3が絶縁層 1 4に埋め込まれ ているので、 第 1電極パターン 1 3への応力やひずみが緩和され応力 の集中を低減することができ、 絶縁体膜 1 2がソルダ一レジス トとし て機能するため、 半田ボール設置の際にボールの位置ずれを防止でき 作業性を高めることができる。 これらの効果により、 設置後において は接合部での応力集中を低減でき、 設置安定性と外部ボードとの実装 信頼性が優れた搭載基板を得ることができる。  According to the present invention, since the first electrode pattern 13 is embedded in the insulating layer 14, stress and strain on the first electrode pattern 13 are relaxed, and the concentration of stress can be reduced. Since the film 12 functions as a solder resist, it is possible to prevent the ball from being displaced when solder balls are placed, and to improve workability. Due to these effects, the stress concentration at the joints can be reduced after installation, and a mounting board with excellent installation stability and reliability of mounting to an external board can be obtained.
次に、 本発明に係る搭載基板及び半導体パッケージの第 2の実施の 形態について説明する。 図 3は本実施の形態に係る半導体装置搭載基 板の構成を示す概略断面図である。 第 1電極パターン 1 3の間及び周 囲に導体パターン 1 8が設けられ、 導体パターン 1 8は配線構造膜 1 6内の配線層 1 5とビアにより接続されていること以外の構成は、 第 1 の実施の形態の搭載基板と同一である。  Next, a second embodiment of the mounting substrate and the semiconductor package according to the present invention will be described. FIG. 3 is a schematic sectional view showing the configuration of the semiconductor device mounting board according to the present embodiment. The conductor pattern 18 is provided between and around the first electrode patterns 13, and the conductor pattern 18 is connected to the wiring layer 15 in the wiring structure film 16 by vias. This is the same as the mounting board of the first embodiment.
導体パターン 1 8を構成する金属は、 コス トの観点から銅が最適で あるが、 金、 銀、 アルミニウム及びニッケルからなる群から選択され た少なく とも 1種の金属又はその合金も使用可能である。 本実施の形 態においては、 導体パターン 1 8における配線は銅から構成されてい る。  Copper is the most suitable metal for the conductor pattern 18 from the viewpoint of cost, but at least one metal selected from the group consisting of gold, silver, aluminum and nickel or an alloy thereof can also be used. . In the present embodiment, the wiring in conductor pattern 18 is made of copper.
また、 図 4に示すとおり、 金属支持体 1 1 は金属であり電気的に利 用できるため、 ビア 1 9を介して導体パターン 1 8と金属支持体 1 1 が接続されている構造もとれる。  Further, as shown in FIG. 4, since the metal support 11 is metal and can be used electrically, a structure in which the conductor pattern 18 and the metal support 11 are connected via the via 19 may be used.
本発明によれば、 絶縁体膜 1 2を有するため、 第 1電極パターン 1 3が形成されている平面上に安定して導体パターン 1 8による電気的 回路 （特に電源やグランド） を設けることができ、 電気回路の設計自 由度が増え、 電気特性を向上することができ、 搭載基板が多層積層の 場合において積層数を低減できる効果がある。  According to the present invention, since the insulating film 12 is provided, it is possible to stably provide an electric circuit (especially a power supply or a ground) using the conductor pattern 18 on the plane on which the first electrode pattern 13 is formed. This increases the degree of freedom in designing an electric circuit, improves the electrical characteristics, and has the effect of reducing the number of layers when the mounting substrate is a multilayer.
次に、本発明に係る搭載基板の第 3の実施の形態について説明する。 06526 Next, a third embodiment of the mounting board according to the present invention will be described. 06526
21 twenty one
図 5は本実施の形態に係る半導体装置搭載基板の構成を示す概略断面 図である。第 1電極パターン 1 3の上面に設けられた誘電体層 20と、 誘電体層 20の上面に配線構造膜 1 6と導通した導電体層 2 1 とから なるコンデンサ 22を有すること以外の構成は、 第 1の実施の形態ま たは第 2の実施の形態の搭載基板と同一である。 FIG. 5 is a schematic sectional view showing the configuration of the semiconductor device mounting board according to the present embodiment. The configuration other than having the capacitor 22 including the dielectric layer 20 provided on the upper surface of the first electrode pattern 13 and the conductive layer 21 electrically connected to the wiring structure film 16 on the upper surface of the dielectric layer 20 is as follows. This is the same as the mounting board according to the first embodiment or the second embodiment.
コンデンサ 22の誘電体層 20はスパッタ法、 蒸着法、 CVD又は 陽極酸化法等により形成する。このコンデンサ 22を構成する材料は、 酸化チタン、 酸化タンタル、 A 1203、 S i 02、 Nb 2O5、 B ST (B a x S r !_XT i O3) 、 P ZT (P b Z r xT i ト x03) 、 P L Z T (P b !_y L a y Z r xT i ,_xO 3) 又は S r B i 2T a 2〇9等の ぺロブスカイ ト系材料であることが好ましい。 但し、 前記化合物のい ずれについても、 0≤x≤ l、 0 <y < lである。 また、 コンデンサ 22は、 所望の誘電率を実現することができる有機樹脂等により構成 されてもよい。 The dielectric layer 20 of the capacitor 22 is formed by a sputtering method, an evaporation method, a CVD method, an anodic oxidation method, or the like. Material constituting the capacitor 22 is titanium oxide, tantalum oxide, A 1 2 0 3, S i 0 2, Nb 2 O 5, B ST (B a x S r! _ X T i O 3), P ZT (P b Z r x T i preparative x 0 3), PLZT (P b! _ y L a y Z r x T i, _ x O 3) or S r B i 2 T a 2 〇 9 like Bae Robusukai It is preferable that the material is a metal-based material. However, for any of the above compounds, 0 ≦ x ≦ l and 0 <y <l. Further, the capacitor 22 may be made of an organic resin or the like that can realize a desired dielectric constant.
本発明によれば、 この様なコンデンサを形成することにより、 伝送 ノィズを低減することができ、 高速化に最適な搭載基板を得ることが できる。  According to the present invention, by forming such a capacitor, transmission noise can be reduced, and a mounting board optimal for high-speed operation can be obtained.
次に、 本発明に係る搭載基板及び半導体パッケージの第 4の実施の 形態について説明する。 図 6は本実施の形態に係る半導体装置搭載基 板の構成を示す概略断面図である。金属支持体 1 1が突起 24を有し、 絶縁体膜 1 2の下面全体に設けられかつ突起 24の上部が第 1電極パ ターン 1 3と接していること以外は第 1の実施の形態、 第 2の実施の 形態または第 3の実施の形態の搭載基板と同一である。  Next, a fourth embodiment of the mounting substrate and the semiconductor package according to the present invention will be described. FIG. 6 is a schematic sectional view showing the configuration of the semiconductor device mounting board according to the present embodiment. The first embodiment, except that the metal support 11 has a projection 24, is provided on the entire lower surface of the insulator film 12, and the upper part of the projection 24 is in contact with the first electrode pattern 13. This is the same as the mounting board of the second embodiment or the third embodiment.
突起 24は、 めっき法、 エッチング、 導電性ペース ト、 機械加工の いずれかの 1つもしくは複合した方法により形成される。 また、 図 7 (a) 、 （b) に示すとおり、 導体パターン 1 8を有する搭載基板に おいて、 金属支持体 1 1 と導体パターン 1 8との導通を突起 24によ り得る構成も可能である。  The protrusions 24 are formed by one or a combination of plating, etching, conductive paste, and machining. In addition, as shown in FIGS. 7A and 7B, in the mounting substrate having the conductor pattern 18, a configuration in which the continuity between the metal support 11 and the conductor pattern 18 can be provided by the protrusion 24 is also possible. It is.
この構成の際は、 突起 24と導体パターン 1 8は電気的に安定した 接続が必要となる。 さらに、 図 7 ( b ) に示す金属支持体 1 1 を選択 除去し絶縁体膜 1 2を開口させた構成でも、 金属支持体 1 1 と導体パ ターン 1 8との導通を突起 2 4で取る構成も取れる。 In this configuration, the protrusion 24 and the conductor pattern 18 are electrically stable. A connection is required. Further, even in a configuration in which the metal support 11 shown in FIG. 7 (b) is selectively removed and the insulating film 12 is opened, conduction between the metal support 11 and the conductor pattern 18 is obtained by the projection 24. Configuration is also available.
本発明によれば、 金属支持体 1 1 と第 1電極パターン 1 3および導 体パターン 1 8の電気的導通が確保され、 搭載基板の回路オープン検 査が可能となる。 また、 搭載基板の下面全体が金属支持体 1 1 とする ことで、 搭載基板の第 2電極パターン 1 7と導通が取れるよう半田ボ —ル、 低融点金属、 ワイヤーボンディ ングなどによる半導体装置の搭 載時において搭載基板の平坦性がより十分に確保され半導体装置の搭 載信頼性が向上できる。 さらに、 下面全体が金属支持体 1 1 となって いると半導体装置搭載前に搭載基板の良否選別を行うことができない ため、 必要な突起 2 4のみを金属支持体 1 1 と接触しないように金属 支持体 1 1 を選択除去することで露出させて検査に用いることができ る。  According to the present invention, electrical continuity between the metal support 11 and the first electrode pattern 13 and the conductor pattern 18 is ensured, and a circuit open inspection of the mounting substrate can be performed. In addition, the entire lower surface of the mounting substrate is made of a metal support 11 so that the semiconductor device can be mounted on the mounting substrate using a solder ball, a low melting point metal, wire bonding, or the like so that the second electrode pattern 17 can be conducted. At the time of mounting, the flatness of the mounting substrate is more sufficiently ensured, and the mounting reliability of the semiconductor device can be improved. Furthermore, if the entire lower surface is a metal support 11, it is not possible to perform a pass / fail judgment on the mounting substrate before mounting the semiconductor device, so that only the necessary projections 24 are made of metal so as not to contact the metal support 11. By selectively removing the support 11, it can be exposed and used for inspection.
この方法を用いれば、 金属支持体 1 1 による平坦性を確保した上、 搭載基板は良否選別を行うことができ、 さらに突起 2 4を使用するた め第 1電極パターン 1 3へは金属支持体 1 1除去時のダメージを与え ずにすむ。 また、 良否選別を行う方法の使用、 未使用に関わらず、 半 導体パッケージを形成した後、 フ レーム状などに金属支持体 1 1 と突 起 2 4を選択除去することで第 1電極パターン 1 3を露出させること ができる。 金属支持体 1 1 の除去に際して、 形成される半導体パッケ —ジが金属支持体 1 1が無くても外部ボードへの十分な実装信頼性を 確保できる強度を保有していれば、 金属支持体 1 1を完全除去しても かまわない。  Using this method, the flatness of the metal support 11 can be ensured, and the mounting substrate can be selected for pass / fail. In addition, since the projections 24 are used, the first electrode pattern 13 is attached to the metal support 13. 1 1 Does not cause damage when removing. In addition, regardless of whether a pass / fail sorting method is used or not, after forming a semiconductor package, the metal support 11 and protrusions 24 are selectively removed in the form of a frame, so that the first electrode pattern 1 is removed. 3 can be exposed. When removing the metal support 11, if the semiconductor package formed has sufficient strength to ensure sufficient mounting reliability on an external board without the metal support 11, the metal support 1 1 may be completely removed.
次に、 本発明に係る搭載基板及び半導体パッケージの第 5の実施の 形態について説明する。 図 8は本実施の形態に係るフリ ップチップに よる半導体パッケージの構成を示す概略断面図である。  Next, a fifth embodiment of the mounting substrate and the semiconductor package according to the present invention will be described. FIG. 8 is a schematic sectional view showing the configuration of a semiconductor package using a flip chip according to the present embodiment.
本発明の半導体パッケージは、 本発明の第 1の実施の形態、 第 2の 実施の形態、 第 3の実施の形態または第 4の実施の形態に記載の搭載 基板に半導体装置 2 5を搭載して形成することができる。 半導体装置 2 5のパッ ドなど電気的接続部と搭載基板の配線とは、 種々の方式で 電気的に導通することが可能であり、 たとえば、 フリ ップチップ、 ヮ ィヤーボンディ ング、 テープボンディ ングがあげられる。 The semiconductor package of the present invention may be mounted on the semiconductor package according to the first, second, third, or fourth embodiment of the present invention. The semiconductor device 25 can be formed on a substrate. The electrical connection portion such as the pad of the semiconductor device 25 can be electrically connected to the wiring of the mounting board by various methods, for example, a flip chip, a wire bonding, and a tape bonding. .
本発明の半導体パッケージは、 図 8 ( a ) に示すように、 搭載基板 の下面全体に金属支持体 1 1を備えた形態とすることができる。 この 形態で他のポードなどに実装する際、 第 1電極パターン 1 3が露出す るように金属支持体 1 1 と突起 2 4を除去する。 第 1電極パターン 1 3が露出した形態としては、 図 8 ( b ) に示すように絶縁体膜 1 2を 下面に、 フ レーム状あるいは格子状やメ ッシュ状に金属支持体 1 1 を 加工して残し、 半導体パッケージ補強に用いることができる。 このよ うな補強を形成しなくても十分な強度を有する場合は、 金属支持体 1 1 をすベて除去して、 図 8 ( c ) に示す形態としてもよい。  As shown in FIG. 8A, the semiconductor package of the present invention may have a form in which the metal support 11 is provided on the entire lower surface of the mounting substrate. When mounting to another port or the like in this mode, the metal support 11 and the protrusion 24 are removed so that the first electrode pattern 13 is exposed. As a form in which the first electrode pattern 13 is exposed, as shown in FIG. 8 (b), the metal support 11 is processed into a frame shape, a grid shape or a mesh shape with the insulator film 12 on the lower surface. It can be used for reinforcing semiconductor packages. If the metal support 11 has a sufficient strength without forming such a reinforcement, the metal support 11 may be entirely removed to obtain the form shown in FIG. 8 (c).
また、 図 8 ( d ) に示した様に、 金属支持体 1 1 を選択除去して第 1電極パターン 1 3を露出させた後、 第 1電極パターン 1 3に半導体 装置 2 5を搭載した形態も取れる。 この際、 金属支持体 1 1は半導体 パッケージの補強と、 絶縁体膜 1 2と配線構造膜 1 6にテンショ ンを かけた状態として搭載基板の反り、うねりを抑える働きを持っている。 さらに、 必要であれば図 8 ( e ) にある様に半導体装置 2 5を搭載基 板両側に搭載してもよい。  Further, as shown in FIG. 8 (d), after the metal support 11 is selectively removed to expose the first electrode pattern 13, the semiconductor device 25 is mounted on the first electrode pattern 13. Can also be taken. At this time, the metal support 11 functions to reinforce the semiconductor package and suppress the warpage and undulation of the mounting substrate by applying tension to the insulator film 12 and the wiring structure film 16. Further, if necessary, the semiconductor device 25 may be mounted on both sides of the mounting board as shown in FIG. 8 (e).
また、 本発明の半導体パッケージは、 図 8に示す形態の様に、 半導 体装置 2 5に設けられたパッ ド 2 6と、 本発明の搭載基板の第 1電極 パターン 1 3もしくは第 2電極パターン 1 7とは、 例えば金属バンプ 2 7を介して電気的に接続することができる。 その際、 半導体装置 2 5と搭載基板との間には必要によりアンダーフィル樹脂 2 8を充填す ることができる。  Further, as shown in FIG. 8, the semiconductor package of the present invention includes a pad 26 provided on a semiconductor device 25 and a first electrode pattern 13 or a second electrode of a mounting substrate of the present invention. The pattern 17 can be electrically connected, for example, via a metal bump 27. At that time, the space between the semiconductor device 25 and the mounting substrate can be filled with an underfill resin 28 if necessary.
また、半導体装置 2 5はモールド樹脂 3 0による封止を行うことや、 放熱性を高めるためのヒートスプレッダ 3 2およびヒートシンクを取 り付けた形態を取ってもかまわない。 さらに、 第 1電極パターン 1 3 に半導体装置 2 5を搭載した際は、 金属支持体 1 1 をヒートシンクと のスぺーサ 3 1 として使用してもよい。 Further, the semiconductor device 25 may be sealed with the mold resin 30 or may have a form in which a heat spreader 32 and a heat sink for improving heat dissipation are attached. Furthermore, the first electrode pattern 1 3 When the semiconductor device 25 is mounted on the device, the metal support 11 may be used as a spacer 31 with a heat sink.
以下、 本発明に係る半導体装置搭載基板及び半導体パッケージの製 造方法の実施の形態について説明する。 図 9 ( a ) から （ί ) は、 本 発明の第 1の実施の形態に係る搭載基板の製造方法を工程順に示す部 分断面図である。 本実施の形態は、 本発明の第 1 の実施の形態 （図 1 ) に係る搭載基板を製造するためのものである。 なお、 各工程間におい て適宜洗浄及び熱処理を行う。  Hereinafter, embodiments of a method for manufacturing a semiconductor device mounting substrate and a semiconductor package according to the present invention will be described. FIGS. 9A to 9C are partial cross-sectional views illustrating a method of manufacturing the mounting board according to the first embodiment of the present invention in the order of steps. The present embodiment is for manufacturing the mounting substrate according to the first embodiment (FIG. 1) of the present invention. Note that cleaning and heat treatment are appropriately performed between each step.
先ず、 図 9 ( a ) に示すように、 厚さ 0 . 1乃至 1 . 5 m mの金属 支持体 1 1の表面にめっき法、 エッチング、 導電性ペースト、 機械加 ェのいずれかの 1つもしくは複合した方法により突起 2 4を形成する, 突起 2 4をエッチング除去する際に、 第 1電極パターン 1 3へのエツ チングバリアのため、 突起 2 4の最上層に金、 銀、 白金、 パラジウム のいずれか一つの金属を構成させておく ことも可能である。  First, as shown in FIG. 9 (a), the surface of a metal support 11 having a thickness of 0.1 to 1.5 mm is formed by plating, etching, conductive paste, or mechanical machining. Forming projections 24 by a combined method, when etching and removing projections 24, any of gold, silver, platinum, and palladium on top layer of projections 24 because of etching barrier to first electrode pattern 13 It is also possible to make up one metal.
本実施の形態では、 金属支持体 1 1 は銅合金板 （祌戸製鋼： K F C シリーズ） を用い、 突起 2 4はめつき法によりニッケルで形成してい る。 突起 2 4を形成する方法は、 めっきレジス トを金属支持体 1 1上 に 3 0 〃 m厚みで積層し、 フォ ト リソグラフィ一技術である露光、 現 像、 もしくは、 レーザにより突起 2 4の予定地にめっきレジス トの開 ロパタ一ンを形成し、 電解二ッケルめっきを 2 5 m析出させた。 次に、 図 9 ( b ) に示すように、 絶縁体膜 1 2と第 1電極パターン 1 3を形成する。 絶縁体膜 1 2の形成は、 絶縁体膜 1 2用の樹脂が液 状ならばスピンコート法、 ダイコート法、 カーテンコート法又は印刷 法等で積層する。 また、 ドライ フ ィ ルム、 樹脂付き銅箔であればラ ミ ネート法等で積層した後、 乾燥等の処理を施して固める。 この際、 突 起 2 4の頂点が絶縁体膜 1 2の表面上に現れている必要があるため、 液状樹脂の場合'は、 感光性であればフオ ト リソグラフィ一によりバタ 一二ングを行い、 非感光性もしくは感光性でも解像度が不足している 場合は、 研磨により整える。 また、 ドライフ ィ ルム、 樹脂付き銅箔の場合は、 ラミネート時に突 起 2 4の頂点が飛び出す様にフイルムのキヤ リァ側にクッションを入 れておく とよい。 ドライフィルムの場合は、 ラミネート後に研磨で整 えてもかまわない。 In the present embodiment, the metal support 11 is made of a copper alloy plate (Koto Steel: KFC series), and the projections 24 are formed of nickel by a plating method. The projections 24 are formed by laminating a plating resist with a thickness of 30 μm on the metal support 11 and planning the projections 24 by exposure, current image, or laser, which is one photolithography technology. An opening pattern of the plating resist was formed on the ground, and 25 m of electrolytic nickel plating was deposited. Next, as shown in FIG. 9 (b), an insulator film 12 and a first electrode pattern 13 are formed. The insulating film 12 is formed by a spin coating method, a die coating method, a curtain coating method, a printing method, or the like if the resin for the insulating film 12 is in a liquid state. If the film is a dry film or a copper foil with a resin, it is laminated by a lamination method or the like and then solidified by drying or the like. At this time, since the vertices of the protrusions 24 need to appear on the surface of the insulator film 12, in the case of a liquid resin, if photosensitive, photolithography is used to perform buttering. If the resolution is insufficient even with non-photosensitive or photosensitive, adjust by polishing. In the case of a dry film or a resin-coated copper foil, it is preferable to insert a cushion on the carrier side of the film so that the top of the protrusion 24 protrudes during lamination. In the case of dry film, it may be polished after lamination.
絶縁体膜 1 2を形成した後、 第 1電極パターン 1 3をサブトラクテ ィブ法、 セミアディティブ法又はフルアディティブ法等により形成す る。 特に、 樹脂付き銅箔の樹脂を絶縁体膜 1 2とした場合は、 キヤ リ ァとして用いている銅箔をサブトラクティブ法でパターニングするこ とも可能である。  After the formation of the insulator film 12, the first electrode pattern 13 is formed by a subtractive method, a semi-additive method, a full-additive method, or the like. In particular, when the resin of the copper foil with resin is used as the insulating film 12, the copper foil used as the carrier can be patterned by a subtractive method.
また、 銅箔の厚みが 2 以下と薄い場合は、 この銅箔を給電層と したセミアディティブ法でのパターニングも可能である。 本実施の形 態では、 樹脂付き銅箔 (住友べ一クライ ト ； A P L— 4 5 0 1 ； 銅箔 厚み、 1 8 m) を使用して絶縁体膜 1 2と、 サブトラクティブ法に より銅箔をパターニングして第 1電極パターン 1 3を形成した。  When the thickness of the copper foil is as thin as 2 or less, patterning by the semi-additive method using this copper foil as the power supply layer is also possible. In this embodiment, a copper foil with a resin (Sumitomo Bei-Cryte; APL-4501; copper foil thickness, 18 m) is used to form an insulator film 12 and a copper foil by a subtractive method. The foil was patterned to form a first electrode pattern 13.
次に、 図 9 ( c ) に示すように、 絶縁層 1 4と配線層 1 5を形成す る。 絶縁層 1 4を形成する方法は、 絶縁層 1 4を構成する絶縁樹脂が 液状ならば、 スピンコート法、 ダイコート法、 カーテンコート法又は 印刷法等により絶縁樹脂を積層し、 また、 絶縁樹脂がドライフ ィ ルム であればラミネート法等により絶縁樹脂を積層した後、 乾燥等の処理 を施して前記絶縁樹脂を固める。  Next, as shown in FIG. 9C, an insulating layer 14 and a wiring layer 15 are formed. The method of forming the insulating layer 14 is as follows: if the insulating resin constituting the insulating layer 14 is in a liquid state, the insulating resin is laminated by a spin coating method, a die coating method, a curtain coating method, a printing method, or the like. In the case of dry film, after insulating resin is laminated by a laminating method or the like, the insulating resin is hardened by performing a treatment such as drying.
そして、 前記絶縁樹脂が感光性であればフォ ト リソプロセス等によ り、 また、 前記絶縁樹脂が非感光性であればレーザ加工法等により、 前記絶縁樹脂をパターニングしてビアホールを形成し、 キュアを行つ て絶縁樹脂を硬化させて絶縁層 1 4を形成する。 次に、 配線パターン をサブトラクティプ法、 セミアディティブ法又はフルアディティプ法 等により形成し、 配線層 1 5を形成する。  If the insulating resin is photosensitive, a photolithography process or the like is used.If the insulating resin is non-photosensitive, a via hole is formed by patterning the insulating resin by a laser processing method or the like. The insulating resin is cured by curing to form an insulating layer 14. Next, a wiring pattern is formed by a subtractive method, a semi-additive method, a full-additive method, or the like, and a wiring layer 15 is formed.
次に、 図 9 ( d ) に示すように、 サブトラクティブ法、 セミアディ ティブ法又はフルアディティブ法等による絶縁層 1 3の形成工程及び 配線層 1 4の形成工程を繰り返して、 配線構造膜 1 6と表層に第 2電 26 Next, as shown in FIG. 9 (d), the process of forming the insulating layer 13 and the process of forming the wiring layer 14 by a subtractive method, a semi-additive method, a full-additive method, or the like are repeated to form the wiring structure film 16. And the second layer on the surface 26
極パターン 1 7を形成する。 本実施の形態では、 絶縁層 1 3にァラミ ド不織布含浸エポキシ樹脂（新神戸電機製； E A— 5 4 1 ) を使用し、 配線層 1 4は 2 m厚みの無電解銅めつきを給電層としたセミアディ ティプ法を用いた。 A pole pattern 17 is formed. In the present embodiment, an epoxy resin impregnated with nonwoven nonwoven fabric (manufactured by Shin-Kobe Electric; EA-541) is used for the insulating layer 13, and the wiring layer 14 has a 2 m-thick electroless copper plating as the power supply layer. The semi-additive method used was used.
次に、 図 9 ( e ) に示すように、 金属支持体 1 1をエッチングによ り選択除去する。 除去法としては、 エッチングするところが開口して いるエツチングレジス トを形成する。 形成方法は、 エッチングレジス 卜が液状ならばスピンコート法、 ダイコート法、 力一テンコート法又 は印刷法等によりェツチングレジス トを積層し、 エッチングレジス ト がドライフィルムであればラミネート法等でエッチングレジス トを積 層した後、 乾燥等の処理を施してエッチングレジス トを固め、 エッチ ングレジス トが感光性であればフォ ト リソプロセス等により、 エッチ ングレジス トが非感光性であればレーザ加工法等によりエッチングレ ジス トをパターニングする。  Next, as shown in FIG. 9E, the metal support 11 is selectively removed by etching. As for the removal method, an etching resist that has an opening at the place to be etched is formed. If the etching resist is liquid, the etching resist is laminated by a spin coating method, a die coating method, a force coating method, a printing method, or the like, and if the etching resist is a dry film, the etching resist is laminated. After that, the etching resist is hardened by drying or other treatment, and the etching resist is photosensitive by a photolithographic process or the like if it is photosensitive, or by a laser processing method if the etching resist is non-photosensitive. Pattern the etching resist.
その後、 このエッチングレジス トをマスクとして、 金属支持体 1 1 を絶縁体膜 1 1 と突起 2 4が露出するまでエッチングする。 本実施の 形態では、 アンモニアを主成分とするアルカリ銅エッチング液 （メル テックス ； エープロセス） を用いて銅合金板を選択除去した。  Thereafter, using the etching resist as a mask, the metal support 11 is etched until the insulator film 11 and the projections 24 are exposed. In the present embodiment, the copper alloy plate is selectively removed using an alkaline copper etching solution containing ammonia as a main component (Meltex; A process).
次に、 図 9 ( f ) に示すように、 突起 2 4をエッチング、 もしくは レーザにより選択除去する。 エッチングを行った後に開口部の形状を 整えるため、 レーザを使用してもかまわない。 突起 2 4除去後に第 1 電極パターン 1 3の露出表面を正常化して搭載基板を得る。 本実施の 形態では、 突起 2 4としたニッケルを硫酸：過酸化水素水：純水 = 1 ： 1 ： 1 0の比率で混合したエッチング液を用いて除去した。  Next, as shown in FIG. 9 (f), the protrusion 24 is selectively removed by etching or laser. A laser may be used to adjust the shape of the opening after etching. After removing the projections 24, the exposed surface of the first electrode pattern 13 is normalized to obtain a mounting substrate. In the present embodiment, the nickel formed as the projections 24 was removed using an etching solution in which sulfuric acid: hydrogen peroxide solution: pure water = 1: 1: 10 was mixed.
この搭載基板は、 本発明の第 1の実施の形態に係る搭載基板と同じ ものであり、 上述の製造方法によれば、 この搭載基板を効率よく製造 することができる。 また、 本実施の形態に係る製造方法によれば、 平 坦な金属支持体 1 1を基板として配線構造膜 1 6を積層するため、 配 線構造膜 1 6の平坦性を向上させることができるため、 安定した積層 が可能となる。 This mounting board is the same as the mounting board according to the first embodiment of the present invention, and according to the above-described manufacturing method, this mounting board can be manufactured efficiently. Further, according to the manufacturing method according to the present embodiment, the wiring structure film 16 is stacked using the flat metal support 11 as a substrate, so that the flatness of the wiring structure film 16 can be improved. Because of stable lamination Becomes possible.
また、 突起 2 4を形成しなく とも搭載基板を形成することは可能で あるが、 本発明の第 4の実施の形態に示した搭載基板の効果にあるよ うに、 金属支持体 1 1の平坦性を利用して第 2電極パターン 1 7上に 半導体装置を搭載する前に、 搭載基板の良否選別が不可能となる。 搭 載基板としては、 良否選別が不可欠であるため、 突起 2 4を無く した 方法では、 金属支持体 1 1の平坦性を利用した半導体装置搭載はでき ない。  Although it is possible to form the mounting substrate without forming the projections 24, the flatness of the metal support 11 is reduced as in the effect of the mounting substrate shown in the fourth embodiment of the present invention. Before mounting the semiconductor device on the second electrode pattern 17 by utilizing the characteristics, it is impossible to determine the quality of the mounting substrate. Since the quality of the mounting substrate is indispensable, it is impossible to mount the semiconductor device using the flatness of the metal support 11 by the method without the projections 24.
次に、 本発明に係る半導体装置搭載基板及び半導体パッケージの製 造方法の第 2の実施の形態を説明する。 図 1 0 ( a ) から （d ) は、 本発明の第 2の実施の形態に係る搭載基板の製造方法を工程順に示す 部分断面図である。  Next, a second embodiment of the method for manufacturing a semiconductor device mounting substrate and a semiconductor package according to the present invention will be described. 10 (a) to 10 (d) are partial cross-sectional views illustrating a method of manufacturing a mounting board according to the second embodiment of the present invention in the order of steps.
本実施の形態は、 本発明の第 2の実施の形態 （図 3 ) に係る搭載基 板を製造するためのものである。 なお、 各工程間において適宜洗浄及 ぴ熱処理を行う。 第 1電極パターン 1 3の間及び周囲に導体パターン 1 8が設けられ、 導体パターン 1 8は配線構造膜 1 6内の配線層 1 5 とビアにより接続されていること以外の構成は、 本発明の第 1 の実施 の形態の搭載基板の製造方法と同一である。  The present embodiment is for manufacturing a mounting board according to a second embodiment (FIG. 3) of the present invention. Cleaning and heat treatment are appropriately performed between each step. The conductor pattern 18 is provided between and around the first electrode patterns 13, and the conductor pattern 18 is connected to the wiring layer 15 in the wiring structure film 16 by a via, except for the present invention. This is the same as the method of manufacturing the mounting board according to the first embodiment.
先ず、 図 1 0 ( a ) に示すように、 厚さ 0 . 1乃至 1 . 5 m mの金 属支持体 1 1の表面にめつき法、 エッチング、 導電性ペース ト、 機械 加工のいずれかの 1つも しくは複合した方法により突起 2 4を形成す る。 突起 2 4をエッチング除去する際に、 第 1電極パターン 1 3への エッチングバリアのため、 突起 2 4の最上層に金、 銀、 白金、 パラジ ゥムのいずれか一つの金属を構成させておく ことも可能である。  First, as shown in Fig. 10 (a), the surface of a metal support 11 having a thickness of 0.1 to 1.5 mm is selected from the group consisting of plating, etching, conductive paste, and machining. The projections 24 are formed by one or a composite method. When the protrusions 24 are removed by etching, any one of gold, silver, platinum, and palladium is formed on the uppermost layer of the protrusions 24 to serve as an etching barrier to the first electrode pattern 13. It is also possible.
本実施の形態では、 金属支持体 1 1 は銅合金板 （神戸製鋼 ： K F C シリーズ） を用い、 突起 2 4はめつき法によりニッケルで形成してい る。 突起 2 4を形成する方法は、 めっきレジス トを金属支持体 1 1上 に 3 0 m厚みで積層し、 フォ ト リソグラフィー技術である露光、 現 像、 もしくは、 レーザにより突起 2 4の予定地にめっきレジス トの開 口パターンを形成し、 電解ニッケルめつきを 2 5 m析出させた。 次に、 図 1 0 ( b ) に示すように、 絶縁体膜 1 2と第 1電極パター ン 1 3を形成する。 絶縁体膜 1 2の形成ば、 絶縁体膜 1 2用の樹脂が 液状ならばスピンコート法、 ダイ コート法、 カーテンコート法又は印 刷法等で積層する。 また、 ドライフ ィ ルム、 樹脂付き銅箔であればラ ミネート法等で積層した後、 乾燥等の処理を施して固める。 この際、 突起 2 4の頂点が絶縁体膜 1 2の表面上に現れている必要があるため、 液状樹脂の場合は、 感光性であればフォ ト リソグラフィ一によりバタ 一二ングを行い、 非感光性もしくは感光性でも解像度が不足している 場合は、 研磨により整える。 In the present embodiment, the metal support 11 is a copper alloy plate (Kobe Steel: KFC series), and the projections 24 are formed of nickel by a plating method. The projections 24 can be formed by laminating a plating resist on the metal support 11 with a thickness of 30 m, and using photolithography technology such as exposure, current imaging, or laser to place the projections 24 on the planned location. Open plating register A mouth pattern was formed and electrolytic nickel plating was deposited by 25 m. Next, as shown in FIG. 10B, an insulator film 12 and a first electrode pattern 13 are formed. When the insulating film 12 is formed, if the resin for the insulating film 12 is liquid, it is laminated by a spin coating method, a die coating method, a curtain coating method, a printing method, or the like. If it is a dry film or a resin-coated copper foil, it is laminated by a lamination method or the like and then solidified by drying or the like. At this time, since the vertices of the projections 24 need to appear on the surface of the insulator film 12, in the case of a liquid resin, if photosensitive, photolithography is used to perform buttering. If the resolution is insufficient even for photosensitive or photosensitive, prepare by polishing.
また、 ドライフ ィ ルム、 樹脂付き銅箔の場合は、 ラミネート時に突 起 2 4の頂点が飛び出す様にフイルムのキヤリァ側にクッションを入 れておく とよい。 ドライフィルムの場合は、 ラミネート後に研磨で整 えてもかまわない。  In the case of dry film or copper foil with resin, it is preferable to insert a cushion on the carrier side of the film so that the top of the protrusion 24 protrudes during lamination. In the case of dry film, it may be polished after lamination.
絶縁体膜 1 2を形成した後、 第 1電極パターン 1 3をサブトラクテ ィブ法、 セミアディティブ法又はフルアディティブ法等により形成す る。 特に、 樹脂付き銅箔の樹脂を絶縁体膜 1 2とした場合は、 キヤ リ ァとして用いている銅箔をサブトラクティブ法でパターニングするこ とも可能である。  After the formation of the insulator film 12, the first electrode pattern 13 is formed by a subtractive method, a semi-additive method, a full-additive method, or the like. In particular, when the resin of the copper foil with resin is used as the insulating film 12, the copper foil used as the carrier can be patterned by a subtractive method.
また、 銅箔の厚みが 2 / m以下と薄い場合は、 この銅箔を給電層と したセミアディティブ法でのパターニングも可能である。 本実施の形 態では、 樹脂付き銅箔 （住友べ一クライ ト ； A P L— 4 5 0 1 ； 銅箔 厚み、 1 8 m) を使用して絶縁体膜 1 2と、 サブトラタティブ法に より銅箔をパターニングして第 1電極パターン 1 3を形成した。  If the thickness of the copper foil is as thin as 2 / m or less, patterning by the semi-additive method using this copper foil as the power supply layer is also possible. In this embodiment, a resin-coated copper foil (Sumitomo Bei-Client; APL-4501; copper foil thickness, 18 m) is used to form the insulator film 12 and the subtractive method. The first electrode pattern 13 was formed by patterning the copper foil.
次に、 図 1 0 ( c ) に示すように、 第 1電極パターン 1 3の間と周 囲に導体パターン 1 8を形成する。 導体パターン 1 8は、 サブトラク ティブ法、 セミアディティブ法又はフルアディティブ法等により形成 する。 本実施の形態では、 第 1電極パターン 1 3形成後に無電解銅め つきを 2 m析出させ、 これを給電層としたセミアディティブ法を用 いて形成した。 Next, as shown in FIG. 10C, a conductor pattern 18 is formed between and around the first electrode patterns 13. The conductor pattern 18 is formed by a subtractive method, a semi-additive method, a full-additive method, or the like. In the present embodiment, a semi-additive method is used in which 2 m of electroless copper plating is deposited after forming the first electrode pattern 13 and this is used as a power supply layer. Formed.
次に、 図 1 0 ( d ) に示すように、 絶縁層 1 4と配線層 1 5を形成 する。 絶縁層 1 4を形成する方法は、 絶縁層 1 4を構成する絶縁樹脂 が液状ならば、 スピンコート法、 ダイコート法、 力一テンコート法又 は印刷法等により絶縁樹脂を積層し、 また、 絶縁樹脂がドライフィル ムであればラミネ一ト法等により絶縁樹脂を積層した後、 乾燥等の処 理を施して前記絶縁樹脂を固める。  Next, as shown in FIG. 10 (d), an insulating layer 14 and a wiring layer 15 are formed. The method of forming the insulating layer 14 is that, if the insulating resin constituting the insulating layer 14 is liquid, the insulating resin is laminated by a spin coating method, a die coating method, a force coating method, a printing method, or the like. If the resin is a dry film, after laminating the insulating resin by a lamination method or the like, a treatment such as drying is performed to solidify the insulating resin.
そして、 前記絶縁樹脂が感光性であればフォ ト リソプロセス等によ り、 また、 前記絶縁樹脂が非感光性であればレーザ加工法等により、 前記絶縁樹脂をパターニングしてビアホールを形成し、 キュアを行つ て絶縁樹脂を硬化させて絶縁層 1 4を形成する。  If the insulating resin is photosensitive, a photolithography process or the like is used.If the insulating resin is non-photosensitive, a via hole is formed by patterning the insulating resin by a laser processing method or the like. The insulating resin is cured by curing to form an insulating layer 14.
次に、 配線パターンをサブトラクティブ法、 セミアディティブ法又 はフルアディティブ法等により形成し、 配線層 1 5を形成する。 本実 施の形態では、 絶縁層 1 3にァラミ ド不織布含浸エポキシ樹脂 （新神 戸電機製 ； E A— 5 4 1 ) を使用し、 配線層 1 4は 2 m厚みの無電 解銅めつきを給電層としたセミアディティブ法を用いた。 これ以降の 工程は、 本発明の第 1の実施の形態の図 9 ( d ) 以降の工程と同一と なる。  Next, a wiring pattern is formed by a subtractive method, a semi-additive method, a full-additive method, or the like, and a wiring layer 15 is formed. In the present embodiment, the insulating layer 13 is made of epoxy resin impregnated with aramide non-woven fabric (manufactured by Shin-Kobe Electric Co., Ltd .; EA-541), and the wiring layer 14 has a 2 m thick electroless copper plating. The semi-additive method used as the power supply layer was used. Subsequent steps are the same as the steps after FIG. 9D of the first embodiment of the present invention.
一方、 図 1 1 ( a ) 、 （b ) に示す通り、 第 1電極パターン 1 3と 導体パターン 1 8を同時に形成してもかまわない。 図 1 1では図 1 0 と異なる工程のみ示している。 この方法では、 第 1電極パターン 1 3 と導体パターン 1 8間の目合わせ精度がよくなる効果と工程数を減ら してコス トを低減する効果を有している。  On the other hand, as shown in FIGS. 11 (a) and 11 (b), the first electrode pattern 13 and the conductor pattern 18 may be formed simultaneously. FIG. 11 shows only steps different from those in FIG. This method has an effect of improving alignment accuracy between the first electrode pattern 13 and the conductor pattern 18 and an effect of reducing cost by reducing the number of steps.
先ず、 図 1 1 ( a ) に示すように、 厚さ 0 . 1乃至 1 . 5 m mの金 属支持体 1 1の表面にめつき法、 エッチング、 導電性ペース ト、 機械 加工のいずれかの 1つもしくは複合した方法により突起 2 4を形成す る。 突起 2 4をエツチング除去する際に、 第 1電極パターン 1 3への エッチングバリアのため、 突起 2 4の最上層に金、 銀、 白金、 パラジ ゥムのいずれか一つの金属を構成させておく ことも可能である。 本実施の形態では、 金属支持体 1 1は銅合金板 （神戸製鋼 ： K F C シリーズ） を用い、 突起 2 4はめつき法によりニッケルで形成してい る。 突起 2 4を形成する方法は、 めっきレジス トを金属支持体 1 1上 に 3 0 m厚みで積層し、 フォ ト リソグラフィ一技術である露光、 現 像、 もしくは、 レーザにより突起 2 4の予定地にめっきレジス トの開 口パターンを形成し、 電解二ッケルめっきを 2 5 m析出させた。 次に、 図 1 1 ( b ) に示すように、 絶縁体膜 1 2、 第 1電極パター ン 1 3、 導体パターン 1 8を形成する。 絶縁体膜 1 2の形成は、 絶縁 体膜 1 2用の樹脂が液状ならばスピンコート法、 ダイコート法、 力一 テンコート法又は印刷法等で積層する。 また、 ドライフィルム、 樹脂 付き銅箔であればラミネート法等で積層した後、 乾燥等の処理を施し て固める。 この際、 突起 2 4の頂点が絶縁体膜 1 2の表面上に現れて いる必要があるため、 液状樹脂の場合は、 感光性であればフォ ト リソ グラフィ一によりパターニングを行い、 非感光性もしくは感光性でも 解像度が不足している場合は、 研磨により整える。 First, as shown in Fig. 11 (a), the surface of a metal support 11 having a thickness of 0.1 to 1.5 mm is selected from the group consisting of plating, etching, conductive paste, and machining. The projections 24 are formed by one or a composite method. When the projections 24 are removed by etching, one of gold, silver, platinum, and palladium is formed on the uppermost layer of the projections 24 to provide an etching barrier to the first electrode pattern 13. It is also possible. In the present embodiment, the metal support 11 is a copper alloy plate (Kobe Steel: KFC series), and the projections 24 are formed of nickel by a plating method. The projections 24 are formed by laminating a plating resist on the metal support 11 with a thickness of 30 m, and using a photolithography technique such as exposure, current image, or laser to plan the locations of the projections 24. An opening pattern of the plating resist was formed on the substrate, and 25 m of electrolytic nickel plating was deposited. Next, as shown in FIG. 11 (b), an insulator film 12, a first electrode pattern 13 and a conductor pattern 18 are formed. The insulating film 12 is formed by a spin coating method, a die coating method, a force coating method, a printing method, or the like if the resin for the insulating film 12 is liquid. In the case of a dry film or a copper foil with a resin, after laminating by a laminating method or the like, a treatment such as drying is performed to harden. At this time, since the vertices of the projections 24 need to appear on the surface of the insulator film 12, in the case of a liquid resin, if photosensitive, patterning is performed by photolithography, and non-photosensitive Or, if the resolution is insufficient even with photosensitive, adjust by polishing.
また、 ドライフ ィ ルム、 樹脂付き銅箔の場合は、 ラミネート時に突 起 2 4の頂点が飛び出す様にフィルムのキヤ リァ側にクッションを入 れておく とよい。 ドライフィルムの場合は、 ラミネート後に研磨で整 えてもかまわない。  In the case of dry film or copper foil with resin, it is preferable to insert a cushion on the carrier side of the film so that the tops of the protrusions 24 protrude during lamination. In the case of dry film, it may be polished after lamination.
絶縁体膜 1 2を形成した後、 第 1電極パターン 1 3、 導体パターン 1 8をサブトラクティブ法、 セミアディティブ法又はフルアディティ ブ法等により形成する。 特に、 樹脂付き銅箔の樹脂を絶縁体膜 1 2と した場合は、 キャ リアとして用いている銅箔をサブトラクティブ法で パターニングすることも可能である。 また、 銅箔の厚みが 2 m以下 と薄い場合は、 この銅箔を給電層としたセミアディティブ法でのバタ —ニングも可能である。  After the insulator film 12 is formed, the first electrode pattern 13 and the conductor pattern 18 are formed by a subtractive method, a semi-additive method, a full-additive method, or the like. In particular, when the resin of the copper foil with resin is used as the insulating film 12, the copper foil used as the carrier can be patterned by a subtractive method. If the thickness of the copper foil is as thin as 2 m or less, the semi-additive method using this copper foil as the power supply layer is also possible.
本実施の形態では、 樹脂付き銅箔 （住友べ一クライ ト ； A P L— 4 5 0 1 ；銅箔厚み、 1 8〃m) を使用して絶縁体膜 1 2と、 サブトラ クティブ法により銅箔をパターニングして第 1電極パターン 1 3、 導 6526 In this embodiment, a resin-coated copper foil (Sumitomo Bei-Client; APL-4501; copper foil thickness, 18 mm) is used to form an insulating film 12 and a copper foil by a subtractive method. To the first electrode pattern 13 6526
31 31
体パターン 1 8を形成した。 A body pattern 18 was formed.
この工程で形成されている状態は、 図 1 0 (c) と同一となり、 こ れ以降の工程は図 1 0 (d) 以降の工程となる。  The state formed in this step is the same as that in FIG. 10 (c), and the subsequent steps are the steps after FIG. 10 (d).
この搭載基板は、 本発明の第 2の実施の形態に係る搭載基板と同じ ものであり、 上述の製造方法によれば、 この搭載基板を効率よく製造 することができる。 また、 この搭載基板は本発明の第 1の実施の形態 における効果をそのまま引き継いだ上、 導体パターン 1 8が形成され ていることにより、 さらなる配線密度向上と積層数低減の効果を有し ている。  This mounting board is the same as the mounting board according to the second embodiment of the present invention, and according to the above-described manufacturing method, this mounting board can be manufactured efficiently. In addition, the mounting substrate has the same effect as in the first embodiment of the present invention as it is, and further has the effect of further increasing the wiring density and reducing the number of stacked layers by forming the conductor pattern 18. .
次に、 本発明に係る半導体装置搭載基板及び半導体パッケージの製 造方法の第 3の実施の形態を説明する。 図 1 2 (a) から （c) は、 本発明の第 3の実施の形態に係る搭載基板の製造方法を工程順に示す 部分断面図である。 本実施の形態は、 本発明の第 2の実施の形態 （図 4) に係る搭載基板を製造するためのものである。 なお、 各工程間に おいて適宜洗浄及び熱処理を行う。 導体パターン 1 8が金属支持体 1 1 とビア 1 9により接続されていること以外の構成は、 本発明の第 2 の実施の形態の搭載基板の製造方法と同一である。  Next, a third embodiment of the method for manufacturing a semiconductor device mounting substrate and a semiconductor package according to the present invention will be described. 12 (a) to 12 (c) are partial cross-sectional views illustrating a method of manufacturing a mounting board according to the third embodiment of the present invention in the order of steps. The present embodiment is for manufacturing a mounting substrate according to the second embodiment (FIG. 4) of the present invention. Cleaning and heat treatment are appropriately performed between each step. The configuration other than that the conductor pattern 18 is connected to the metal support 11 and the via 19 is the same as the method of manufacturing the mounting board according to the second embodiment of the present invention.
先ず、 図 1 2 (a) に示すように、 厚さ 0. 1乃至 1. 5mmの金 属支持体 1 1の表面にめつき法、 エッチング、 導電性ペース ト、 機械 加工のいずれかの 1つもしくは複合した方法により突起 24を形成す る。 突起 24をエッチング除去する際に、 第 1電極パターン 1 3への エツチングバリァのため、 突起 24の最上層に金、 銀、 白金、 パラジ ゥムのいずれか一つの金属を構成させておく ことも可能である。  First, as shown in Fig. 12 (a), the surface of a metal support 11 having a thickness of 0.1 to 1.5 mm is selected from the group consisting of plating, etching, conductive paste, and machining. The projections 24 are formed by one or a combined method. When etching the projections 24, any one of gold, silver, platinum, and palladium metal should be formed on the uppermost layer of the projections 24 to provide an etching barrier to the first electrode pattern 13. Is also possible.
本実施の形態では、 金属支持体 1 1は銅合金板 （神戸製鋼 ： KF C シリーズ） を用い、 突起 24はめつき法によりニッケルで形成してい る。 突起 24を形成する方法は、 めっきレジス トを金属支持体 1 1上 に 30 厚みで積層し、 フォ ト リソグラフィ一技術である露光、 現 像、 もしくは、 レーザにより突起 24の予定地にめっきレジス トの開 口パターンを形成し、 電解ニッケルめつきを 25 m析出させた。 雇 26 In the present embodiment, the metal support 11 is a copper alloy plate (Kobe Steel: KFC series), and the projections 24 are formed of nickel by a plating method. The method of forming the projections 24 is as follows. A plating resist is laminated on the metal support 11 with a thickness of 30 and is exposed to the photolithography technology, a current image, or a laser. An opening pattern was formed, and 25 m of electrolytic nickel plating was deposited. Hire 26
32 32
次に、 図 1 2 ( b ) に示すように、 絶縁体膜 1 2、 第 1電極パター ン 1 3、 ビア 1 9を形成する。 絶縁体膜 1 2の形成は、 絶縁体膜 1 2 用の樹脂が液状ならばスピンコート法、 ダイコート法、 カーテンコー ト法又は印刷法等で積層する。 また、 ドライフ ィ ルム、 樹脂付き銅箔 であればラミネー ト法等で積層した後、乾燥等の処理を施して固める。 この際、 突起 2 4の頂点が絶縁体膜 1 2の表面上に現れている必要が あるため、 液状樹脂の場合は、 感光性であればフォ ト リソグラフィー によりパターニングを行い、 非感光性もしくは感光性でも解像度が不 足している場合は、 研磨により整える。  Next, as shown in FIG. 12 (b), an insulator film 12, a first electrode pattern 13 and a via 19 are formed. The insulating film 12 is formed by spin coating, die coating, curtain coating or printing if the resin for the insulating film 12 is liquid. If it is a dry film or a resin-coated copper foil, it is laminated by a lamination method or the like, and then solidified by drying or the like. At this time, since the apexes of the protrusions 24 need to appear on the surface of the insulator film 12, in the case of a liquid resin, if photosensitive, patterning is performed by photolithography, and If the resolution is not enough, adjust by polishing.
また、 ドライフィルム、 樹脂付き銅箔の場合は、 ラミネート時に突 起 2 4の頂点が飛び出す様にフイルムのキヤリァ側にクッショ ンを入 れておく とよい。 ドライフィルムの場合は、 ラミネート後に研磨で整 えてもかまわない。  In the case of a dry film or a copper foil with a resin, it is preferable to insert a cushion on the carrier side of the film so that the top of the protrusion 24 protrudes during lamination. In the case of dry film, it may be polished after lamination.
絶縁体膜 1 2を形成した後、 第 1電極パターン 1 3をサブトラクテ ィブ法、 セミアディティブ法又はフルアディティブ法等により形成す る。 特に、 樹脂付き銅箔の樹脂を絶縁体膜 1 2とした場合は、 キヤ リ ァとして用いている銅箔をサブトラクティブ法でパターニングするこ とも可能である。 また、 銅箔の厚みが 2 m以下と薄い場合は、 この 銅箔を給電層としたセミアディティブ法でのパターニングも可能であ る。  After the formation of the insulator film 12, the first electrode pattern 13 is formed by a subtractive method, a semi-additive method, a full-additive method, or the like. In particular, when the resin of the copper foil with resin is used as the insulating film 12, the copper foil used as the carrier can be patterned by a subtractive method. If the thickness of the copper foil is as thin as 2 m or less, patterning by the semi-additive method using this copper foil as the power supply layer is also possible.
さらに、 ビア 1 9をフォ ト リソグラフィー、 レーザ、 ドライエッチ ングなどの方法を用いて金属支持体 1 1が露出するよう形成する。 絶 縁体膜 1 2のパターニング時に、 感光性であればフォ ト リソグラフィ 一により、 非感光性であればレーザ、 ドライエッチングにより、 ビア 1 9も同時にパターニングしてもよい。  Further, a via 19 is formed so as to expose the metal support 11 by using a method such as photolithography, laser, or dry etching. When patterning the insulator film 12, the vias 19 may be simultaneously patterned by photolithography if photosensitive, or by laser or dry etching if non-photosensitive.
本実施の形態では、 樹脂付き銅箔 （住友べ一クライ ト ； A P L— 4 5 0 1 ； 銅箔厚み、 1 8 m) を使用して絶縁体膜 1 2と、 サブトラ クティブ法により銅箔をパターニングして第 1電極パターン 1 3を、 炭酸ガスレーザを用いてビア径 8 0〃 mのビア 1 9を形成した。 細 26 In this embodiment, a copper foil with a resin (Sumitomo Bei-Client; APL-4501; copper foil thickness, 18 m) is used to form an insulating film 12 and a copper foil by a subtractive method. By patterning, a first electrode pattern 13 was formed, and a via 19 having a via diameter of 80 μm was formed using a carbon dioxide laser. Fine 26
33 33
次に、 図 1 2 ( c ) に示すように、 第 1電極パターン 1 3の間と周 囲に導体パターン 1 8をビア 1 9により金属支持体 1 1 と接続できる ように形成する。 導体パターン 1 8は、 サブトラクティブ法、 セミア ディ ティブ法又はフルアディティブ法等により形成する。 本実施の形 態では、 第 1電極パターン 1 3形成後に無電解銅めつきを 2 m析出 させ、 これを給電層としたセミアディティブ法を用いて形成した。  Next, as shown in FIG. 12 (c), a conductor pattern 18 is formed between and around the first electrode patterns 13 so as to be connected to the metal support 11 via vias 19. The conductor pattern 18 is formed by a subtractive method, a semi-additive method, a full-additive method, or the like. In this embodiment, 2 m of electroless copper plating was deposited after the formation of the first electrode pattern 13, and was formed using a semi-additive method using this as a power supply layer.
この工程で形成されている状態は、 図 1 0 ( c ) と同一となり、 こ れ以降の工程は図 1 0 ( d ) 以降の工程となる。  The state formed in this step is the same as that in FIG. 10 (c), and the subsequent steps are the steps after FIG. 10 (d).
また、 図 1 3に示すように、 第 1電極パターン 1 3と導体パターン 1 8を同時に形成してもよい。 この方法では、 第 1電極パターン 1 3 と導体パターン 1 8間の目合わせ精度がよくなる効果と工程数を減ら してコス トを低減する効果を有している。  Further, as shown in FIG. 13, the first electrode pattern 13 and the conductor pattern 18 may be formed simultaneously. This method has an effect of improving alignment accuracy between the first electrode pattern 13 and the conductor pattern 18 and an effect of reducing cost by reducing the number of steps.
先ず、 図 1 3 ( a ) に示すように、 厚さ 0 . 1乃至 1 . 5 m mの金 属支持体 1 1の表面にめつき法、 エッチング、 導電性ペース ト、 機械 加工のいずれかの 1つもしくは複合した方法により突起 2 4を形成す る。 突起 2 4をエッチング除去する際に、 第 1電極パターン 1 3への エッチングバリアのため、 突起 2 4の最上層に金、 銀、 白金、 パラジ ゥムのいずれか一つの金属を構成させておく ことも可能である。  First, as shown in Fig. 13 (a), the surface of a metal support 11 having a thickness of 0.1 to 1.5 mm is selected from the group consisting of plating, etching, conductive paste, and machining. The projections 24 are formed by one or a composite method. When the protrusions 24 are removed by etching, any one of gold, silver, platinum, and palladium is formed on the uppermost layer of the protrusions 24 to serve as an etching barrier to the first electrode pattern 13. It is also possible.
本実施の形態では、 金属支持体 1 1 は銅合金板 （神戸製鋼 ： K F C シリーズ） を用い、 突起 2 4はめつき法によりニッケルで形成してい る。 突起 2 4を形成する方法は、 めっきレジス トを金属支持体 1 1上 に 3 0 m厚みで積層し、 フ ォ ト リソグラフィ一技術である露光、 現 像、 もしくは、 レーザにより突起 2 4の予定地にめっきレジス トの開 口パターンを形成し、 電解ニッケルめっきを 2 5 析出させた。  In the present embodiment, the metal support 11 is a copper alloy plate (Kobe Steel: KFC series), and the projections 24 are formed of nickel by a plating method. The projections 24 are formed by depositing a plating resist with a thickness of 30 m on the metal support 11 and planning the projections 24 by photolithography, an exposure, current image, or laser. An opening pattern of the plating resist was formed on the ground, and 25 electrolytic nickel plating was deposited.
次に、 図 1 3 ( b ) に示すように、 絶縁体膜 1 2ビア 1 9を形成す る。 絶縁体膜 1 2の形成は、 絶縁体膜 1 2用の樹脂が液状ならばスピ ンコート法、 ダイ コート法、 カーテンコート法又は印刷法等で積層す る。 また、 ドライ フ ィ ルム、 樹脂付き銅箔であればラミネート法等で 積層した後、 乾燥等の処理を施して固める。 この際、 突起 2 4の頂点 が絶縁体膜 1 2の表面上に現れている必要があるため、 液状樹脂の場 合は、 感光性であればフオ ト リソグラフィ一によりパターニングを行 い、 非感光性もしくは感光性でも解像度が不足している場合は、 研磨 により整える。 Next, as shown in FIG. 13 (b), an insulator film 12 via 19 is formed. The insulating film 12 is formed by a spin coating method, a die coating method, a curtain coating method, a printing method, or the like if the resin for the insulating film 12 is liquid. If the film is a dry film or a resin-coated copper foil, it is laminated by lamination or the like, and then solidified by drying or the like. At this time, the top of the projection 2 4 Must be exposed on the surface of the insulator film 12, so in the case of a liquid resin, if photosensitivity is used, patterning is performed by photolithography, and even if it is non-photosensitive or photosensitive, the resolution is insufficient. If so, prepare by polishing.
また、 ドライフィルム、 樹脂付き銅箔の場合は、 ラミネート時に突 起 2 4の頂点が飛び出す様にフィルムのキヤ リァ側にクッションを入 れておく とよい。 ドライフィルムの場合は、 ラミネート後に研磨で整 えてもかまわない。  In the case of a dry film or a copper foil with resin, it is preferable to insert a cushion on the carrier side of the film so that the top of the protrusion 24 protrudes during lamination. In the case of dry film, it may be polished after lamination.
さらに、 ビア 1 9をフォ ト リソグラフィ 一、 レーザ、 ドライエッチ ングなどの方法を用いて金属支持体 1 1が露出するよう形成する。 絶 縁体膜 1 2パターニング時に、 感光性であればフオ ト リソグラフィ ー により、 非感光性であればレーザ、 ドライエッチングにより、 ビア 1 9も同時にパターニングしてもよい。 樹脂付き銅箔の場合は、 銅箔を エッチングしてからレーザによりビア 1 9を形成する。  Further, a via 19 is formed so as to expose the metal support 11 by using a method such as photolithography, laser, or dry etching. At the time of patterning the insulator film 12, the vias 19 may be simultaneously patterned by photolithography if photosensitive, or by laser or dry etching if non-photosensitive. In the case of a copper foil with a resin, the via 19 is formed by etching the copper foil and then using a laser.
本実施の形態では、 樹脂付き銅箔 （住友べ一クライ ト ； A P L— 4 5 0 1 ； 銅箔厚み、 1 8 m) を使用して絶縁体膜 1 2と、 銅箔をェ ツチングしてから炭酸ガスレーザを用いてビア径 8 0 mのビア 1 9 を形成した。  In this embodiment, the insulating film 12 and the copper foil are etched using a resin-coated copper foil (Sumitomo Bei-Client; APL-4501; copper foil thickness, 18 m). Then, a via 19 having a via diameter of 80 m was formed using a carbon dioxide laser.
次に、 図 1 3 ( c ) に示すように、 第 1電極パターン 1 3と導体パ ターン 1 8をサブトラクティブ法、 セミアディティブ法又はフルアデ ィ ティブ法等により形成する。 本実施の形態では、 無電解銅めつきを 2 m厚みで析出させ、 これを給電層としたセミアディティブ法を用 いて形成した。 この工程で形成されている状態は、 図 1 0 ( c ) と同 一となり、 これ以降の工程は図 1 0 ( d ) 以降の工程となる。  Next, as shown in FIG. 13C, the first electrode pattern 13 and the conductor pattern 18 are formed by a subtractive method, a semi-additive method, a full-additive method, or the like. In the present embodiment, the electroless copper plating is deposited with a thickness of 2 m and formed using a semi-additive method using this as a power supply layer. The state formed in this step is the same as that in FIG. 10 (c), and the subsequent steps are the steps after FIG. 10 (d).
この搭載基板は、 本発明の第 2の実施の形態に係る搭載基板と同じ ものであり、 上述の製造方法によれば、 この搭載基板を効率よく製造 することができる。また、この搭載基板は本発明の第 1の実施の形態、 第 2の実施の形態の効果をそのまま引き継いだ上、 導体パターン 1 8 が金属支持体 1 1 と接続されていることにより、 金属支持体 1 1 も電 気回路として利用するため、 本発明の第 2の実施の形態よりさらに配 線密度向上と積層数低減の効果を有している。 This mounting board is the same as the mounting board according to the second embodiment of the present invention, and according to the above-described manufacturing method, this mounting board can be manufactured efficiently. In addition, the mounting board inherits the effects of the first and second embodiments of the present invention as it is, and furthermore, the conductor pattern 18 is connected to the metal support 11 to support the metal. Body 1 1 Since it is used as an air circuit, it has the effects of improving the wiring density and reducing the number of stacked layers as compared with the second embodiment of the present invention.
次に、 本発明に係る半導体装置搭載基板及び半導体パッケージの製 造方法の第 4の実施の形態を説明する。 図 1 4 ( a ) から （c ) は、 本発明の第 4の実施の形態に係る搭載基板の製造方法を工程順に示す 部分断面図である。 本実施の形態は、 本発明の第 4の実施の形態 （図 7 ) に係る搭載基板を製造するためのものである。 なお、 各工程間に おいて適宜洗浄及び熱処理を行う。 導体パターン 1 8が金属支持体 1 1 とをつなぐビア 1 9が突起 2 4を用いていること以外の構成は、 本 発明の第 2の実施の形態の搭載基板の製造方法と同一である。  Next, a fourth embodiment of the method for manufacturing a semiconductor device mounting substrate and a semiconductor package according to the present invention will be described. FIGS. 14A to 14C are partial cross-sectional views illustrating a method of manufacturing a mounting board according to the fourth embodiment of the present invention in the order of steps. The present embodiment is for manufacturing a mounting substrate according to a fourth embodiment (FIG. 7) of the present invention. Cleaning and heat treatment are appropriately performed between each step. The configuration other than that the via 19 connecting the conductor pattern 18 to the metal support 11 uses the protrusion 24 is the same as the manufacturing method of the mounting board according to the second embodiment of the present invention.
先ず、 図 1 4 ( a ) に示すように、 厚さ 0 . 1乃至 1 . 5 m mの金 属支持体 1 1の表面にめつき法、 エッチング、 導電性ペース ト、 機械 加工のいずれかの 1つもしくは複合した方法により突起 2 4を形成す る。 突起 2 4をエッチング除去する際に、 第 1電極パターン 1 3への ェッチングバリァのため、 突起 2 4の最上層に金、 銀、 白金、 パラジ ゥムのいずれか一つの金属を構成させておく ことも可能である。  First, as shown in Fig. 14 (a), the surface of a metal support 11 having a thickness of 0.1 to 1.5 mm is selected from the group consisting of plating, etching, conductive paste, and machining. The projections 24 are formed by one or a composite method. When etching the projections 24, one of gold, silver, platinum, and palladium metal should be formed on the top layer of the projections 24 in order to etch the first electrode patterns 13 Is also possible.
本実施の形態では、 金属支持体 1 1 は銅合金板 （神戸製鋼： K F C シリーズ） を用い、 突起 2 4はめつき法によりニッケルで形成してい る。 突起 2 4を形成する方法は、 めっきレジス トを金属支持体 1 1上 に 3 0 m厚みで積層し、 フォ ト リソグラフィ一技術である露光、 現 像、 もしくは、 レーザにより突起 2 4の予定地にめっきレジス トの開 口パターンを形成し、 電解ニッケルめつきを 2 5 ji m析出させた。 次に、 図 1 4 ( b ) に示すように、 絶縁体膜 1 2、 第 1電極パター ン 1 3、 導体パターン 1 8を形成する。 絶縁体膜 1 2の形成は、 絶縁 体膜 1 2用の樹脂が液状ならばスピンコート法、 ダイコート法、 カー テンコート法又は印刷法等で積層する。 また、 ドライフ ィルム、 樹脂 付き銅箔であればラミネ一ト法等で積層した後、 乾燥等の処理を施し て固める。 この際、 突起 2 4の頂点が絶縁体膜 1 2の表面上に現れて いる必要があるため、 液状樹脂の場合は、 感光性であればフォ ト リソ グラフィ一によりパターニングを行い、 非感光性もしくは感光性でも 解像度が不足している場合は、 研磨により整える。 In this embodiment, the metal support 11 is a copper alloy plate (Kobe Steel: KFC series), and the projections 24 are formed of nickel by a plating method. The projections 24 are formed by laminating a plating resist on the metal support 11 with a thickness of 30 m, and using a photolithography technique such as exposure, current image, or laser to plan the locations of the projections 24. An opening pattern of the plating resist was formed on the surface, and electrolytic nickel plating was deposited for 25 jim. Next, as shown in FIG. 14 (b), an insulator film 12, a first electrode pattern 13 and a conductor pattern 18 are formed. The insulating film 12 is formed by a spin coating method, a die coating method, a curtain coating method, a printing method, or the like if the resin for the insulating film 12 is liquid. In the case of dry film or copper foil with resin, after laminating by a laminating method or the like, it is cured by drying or the like. At this time, since the vertices of the projections 24 need to appear on the surface of the insulator film 12, in the case of a liquid resin, if it is photosensitive, photolithography Patterning is performed by lithography, and if the resolution is insufficient even with non-photosensitive or photosensitive, polishing is used to prepare it.
また、 ドライフ ィ ルム、 樹脂付き銅箔の場合は、 ラミネート時に突 起 2 4の頂点が飛び出す様にフィルムのキヤ リァ側にクッションを入 れておく とよい。 ドライフ ィ ルムの場合は、 ラミネート後に研磨で整 えてもかまわない。  In the case of dry film or copper foil with resin, it is preferable to insert a cushion on the carrier side of the film so that the tops of the protrusions 24 protrude during lamination. In the case of dry film, it may be polished after lamination.
絶縁体膜 1 2を形成した後、 第 1電極パターン 1 3、 導体パターン 1 8をサブトラクティブ法、 セミアディティブ法又はフルアディティ 'ブ法等により形成する。 特に、 樹脂付き銅箔の樹脂を絶縁体膜 1 2と した場合は、 キャ リアとして用いている銅箔をサブトラクティブ法で パターニングすることも可能である。  After the insulator film 12 is formed, the first electrode pattern 13 and the conductor pattern 18 are formed by a subtractive method, a semi-additive method, a full-additive method, or the like. In particular, when the resin of the copper foil with resin is used as the insulating film 12, the copper foil used as the carrier can be patterned by a subtractive method.
また、 銅箔の厚みが 2 m以下と薄い場合は、 この銅箔を給電層と したセミアディティブ法でのパターニングも可能である。 また、 第 1 電極パターン 1 3と導体パターン 1 8を別々の工程での形成、 もしく は同じ工程での形成のどちらを行ってもよい。別々に形成する場合は、 形成するパターンに合わせたプロセスの適応により歩留まりの向上が、 同時に形成する場合は、 第 1電極パターン 1 3と導体パターン 1 8と の目合わせ精度向上と工程数低減の効果がある。  When the thickness of the copper foil is as thin as 2 m or less, patterning by the semi-additive method using this copper foil as the power supply layer is also possible. Further, the first electrode pattern 13 and the conductor pattern 18 may be formed in separate steps or may be formed in the same step. If they are formed separately, the yield will be improved by adapting the process to the pattern to be formed.If they are formed simultaneously, the accuracy of alignment between the first electrode pattern 13 and the conductor pattern 18 will be improved and the number of steps will be reduced. effective.
本実施の形態では、 樹脂付き銅箔 (住友べ一クライ ト ； A P L— 4 5 0 1 ； 銅箔厚み、 1 8〃m) を使用して絶縁体膜 1 2と、 サブトラ クティブ法により銅箔をパターニングして第 1電極パターン 1 3、 導 体パターン 1 8を形成した。  In this embodiment, a resin-coated copper foil (Sumitomo Bei-Client; APL-4501: copper foil thickness, 18 1m) is used to form an insulating film 12 and a copper foil by a subtractive method. Was patterned to form a first electrode pattern 13 and a conductor pattern 18.
次に、 図 1 4 ( c ) に示すように、 絶縁層 1 4と配線層 1 5を形成 する。 絶縁層 1 4を形成する方法は、 絶縁層 1 4を構成する絶縁樹脂 が液状ならば、 スピンコート法、 ダイ コート法、 カーテンコート法又 は印刷法等により絶縁樹脂を積層し、 また、 絶縁樹脂がドライフィル ムであればラミネート法等により絶縁樹脂を積層した後、 乾燥等の処 理を施して前記絶縁樹脂を固める。  Next, as shown in FIG. 14C, an insulating layer 14 and a wiring layer 15 are formed. The method for forming the insulating layer 14 is as follows: if the insulating resin constituting the insulating layer 14 is liquid, the insulating resin is laminated by a spin coating method, a die coating method, a curtain coating method, a printing method, or the like. If the resin is a dry film, an insulating resin is laminated by a laminating method or the like, and then a treatment such as drying is performed to solidify the insulating resin.
そして、 前記絶縁樹脂が感光性であればフォ ト リソプロセス等によ り、 また、 前記絶縁樹脂が非感光性であればレーザ加工法等により、 前記絶縁樹脂をパターニングしてビアホールを形成し、 キュアを行つ て絶縁樹脂を硬化させて絶縁層 1 4を形成する。 If the insulating resin is photosensitive, a photolithography process or the like is used. Alternatively, if the insulating resin is non-photosensitive, the insulating resin is patterned by a laser processing method or the like to form a via hole, and cured to cure the insulating resin to form an insulating layer 14. .
次に、 配線パターンをサブトラクティブ法、 セミアディティブ法又 はフルアディティブ法等により形成し、 配線層 1 5を形成する。 本実 施の形態では、 絶縁層 1 3にァラミ ド不織布含浸エポキシ樹脂 （新神 戸電機製 ； EA— 54 1 ) を使用し、 配線層 1 4は 2 厚みの無電 解銅めつきを給電層としたセミアディティブ法を用いた。 この工程で 形成されている状態は、 図 1 0 (c) と同一となり、 これ以降の工程 は図 1 0 (d) 以降の工程となる。  Next, a wiring pattern is formed by a subtractive method, a semi-additive method, a full-additive method, or the like, and a wiring layer 15 is formed. In the present embodiment, the insulating layer 13 is made of epoxy resin impregnated with aramide non-woven fabric (manufactured by Shin-Kobe Electric; EA-541), and the wiring layer 14 has a two-layer electroless copper plating. The semi-additive method was used. The state formed in this step is the same as that in FIG. 10 (c), and the subsequent steps are the steps after FIG. 10 (d).
この搭載基板は、 本発明の第 4の実施の形態に係る搭載基板と同じ ものであり、 上述の製造方法によれば、 この搭載基板を効率よく製造 することができる。また、この搭載基板は本発明の第 1の実施の形態、 第 2の実施の形態、第 3の実施の形態の効果をそのまま引き継いだ上、 導体パターン 1 8と金属支持体 1 1が突起 24により接続されている ため、本発明の第 3の実施の形態に比べ、工数を低減することができ、 コス ト、 歩留まりの面で効果がある。  This mounting board is the same as the mounting board according to the fourth embodiment of the present invention, and according to the above-described manufacturing method, this mounting board can be manufactured efficiently. The mounting substrate inherits the effects of the first, second, and third embodiments of the present invention as it is, and the conductor pattern 18 and the metal support 11 are formed with protrusions 24. Since the connection is made by the method described above, the number of steps can be reduced as compared with the third embodiment of the present invention, which is effective in terms of cost and yield.
次に、 本発明に係る半導体装置搭載基板及び半導体パッケージの製 造方法の第 5の実施の形態を説明する。 図 1 5 (a) から （d) は、 本発明の第 5の実施の形態に係る搭載基板の製造方法を工程順に示す 部分断面図である。 本実施の形態は、 本発明の第 3の実施の形態 （図 5) に係る搭載基板を製造するためのものである。 なお、 各工程間に おいて適宜洗浄及び熱処理を行う。 少なく とも一つ以上の第 1電極パ ターン 1 3に誘電体層 20と導電体層 2 1を設けてコンデンサ 22を 形成していること以外の構成は、 本発明の第 1の実施の形態の搭載基 板の製造方法と同一である。  Next, a fifth embodiment of the method for manufacturing a semiconductor device mounting substrate and a semiconductor package according to the present invention will be described. FIGS. 15A to 15D are partial cross-sectional views illustrating a method of manufacturing a mounting board according to the fifth embodiment of the present invention in the order of steps. The present embodiment is for manufacturing a mounting substrate according to the third embodiment (FIG. 5) of the present invention. Cleaning and heat treatment are appropriately performed between each step. The configuration other than that the capacitor 22 is formed by providing the dielectric layer 20 and the conductor layer 21 on at least one or more first electrode patterns 13 is the same as the first embodiment of the present invention. It is the same as the manufacturing method of the mounting board.
また、図 1 5では本発明の第 1の実施の形態の形態を用いているが、 本発明の第 2の実施の形態における図 1 0 (b)や（c)、図 1 1 (b)、 第 3の実施の形態の図 1 2 (b) や （c) 、 図 1 3 (c) 、 第 4の実 施の形態の図 1 4 ( b ) を図 1 5 ( b ) の代わりとしてもよい。 Although FIG. 15 uses the embodiment of the first embodiment of the present invention, FIGS. 10 (b), (c) and 11 (b) of the second embodiment of the present invention use the same. FIGS. 12 (b) and (c) of the third embodiment, FIG. 13 (c), and the fourth embodiment. FIG. 14 (b) of the embodiment may be substituted for FIG. 15 (b).
先ず、 図 1 5 ( a ) に示すように、 厚さ 0 . 1乃至 1 . 5 m mの金 属支持体 1 1の表面にめっき法、 エッチング、 導電性ペース ト、 機械 加工のいずれかの 1つもしくは複合した方法により突起 2 4を形成す る。 突起 2 4をエッチング除去する際に、 第 1電極パターン 1 3への エッチングバリアのため、 突起 2 4の最上層に金、 銀、 白金、 パラジ ゥムのいずれか一つの金属を構成させておく ことも可能である。  First, as shown in FIG. 15 (a), the surface of a metal support 11 having a thickness of 0.1 to 1.5 mm is formed by any one of plating, etching, conductive paste, and machining. The projections 24 are formed by one or a combined method. When the protrusions 24 are removed by etching, any one of gold, silver, platinum, and palladium is formed on the uppermost layer of the protrusions 24 to serve as an etching barrier to the first electrode pattern 13. It is also possible.
本実施の形態では、 金属支持体 1 1は銅合金板 （神戸製鋼 ： K F C シリーズ） を用い、 突起 2 4はめつき法によりニッケルで形成してい る。 突起 2 4を形成する方法は、 めっきレジス トを金属支持体 1 1上 に 3 0 m厚みで積層し、 フォ ト リソグラフィ一技術である露光、 現 像、 もしくは、 レーザにより突起 2 4の予定地にめっきレジス トの開 口パターンを形成し、 電解二ッケルめっきを 2 5 〃m析出させた。 次に、 図 1 5 ( b ) に示すように、 絶縁体膜 1 2と第 1電極パター ン 1 3を形成する。 絶縁体膜 1 2の形成は、 絶縁体膜 1 2用の樹脂が 液状ならばスピンコート法、 ダイコート法、 カーテンコート法又は印 刷法等で積層する。 また、 ドライフ ィ ルム、 樹脂付き銅箔であればラ ミネ一ト法等で積層した後、 乾燥等の処理を施して固める。 この際、 突起 2 4の頂点が絶縁体膜 1 2の表面上に現れている必要があるため、 液状樹脂の場合は、 感光性であればフオ ト リソグラフィ一によりバタ 一二ングを行い、 非感光性もしくは感光性でも解像度が不足している 場合は、 研磨により整える。  In this embodiment, the metal support 11 is made of a copper alloy plate (Kobe Steel: KFC series), and the projections 24 are formed of nickel by a plating method. The projections 24 are formed by laminating a plating resist on the metal support 11 with a thickness of 30 m, and using a photolithography technique such as exposure, current image, or laser to plan the locations of the projections 24. An opening pattern of a plating resist was formed on the substrate, and electrolytic nickel plating was deposited to a thickness of 25 μm. Next, as shown in FIG. 15 (b), an insulator film 12 and a first electrode pattern 13 are formed. The insulating film 12 is formed by spin coating, die coating, curtain coating, printing, or the like if the resin for the insulating film 12 is liquid. If the film is a dry film or a resin-coated copper foil, it is laminated by a laminating method or the like, and then dried and hardened. At this time, since the vertices of the projections 24 need to appear on the surface of the insulator film 12, in the case of a liquid resin, if photosensitive, photolithography is used to perform buttering. If the resolution is insufficient even for photosensitive or photosensitive, prepare by polishing.
また、 ドライフ ィ ルム、 樹脂付き銅箔の場合は、 ラミネート時に突 起 2 4の頂点が飛び出す様にフイルムのキヤ リァ側にクッシヨンを入 れておく とよい。 ドライフィルムの場合は、 ラミネート後に研磨で整 えてもかまわない。  In the case of dry film or copper foil with resin, it is preferable to insert a cushion on the carrier side of the film so that the top of the protrusion 24 protrudes during lamination. In the case of dry film, it may be polished after lamination.
絶縁体膜 1 2を形成した後、 第 1電極パターン 1 3をサブトラクテ イブ法、 セミアディティブ法又はフルアディティブ法等により形成す る。 特に、 樹脂付き銅箔の樹脂を絶縁体膜 1 2とした場合は、 キヤ リ ァとして用いている銅箔をサブトラクティプ法でパターニングするこ とも可能である。 After the formation of the insulator film 12, the first electrode pattern 13 is formed by a subtractive method, a semi-additive method, a full-additive method, or the like. In particular, when the resin of copper foil with resin is used as the insulator film 12, the carrier is It is also possible to pattern the copper foil used as a layer by the subtractive method.
また、 銅箔の厚みが 2 m以下と薄い場合は、 この銅箔を給電層と したセミアディティブ法でのパターニングも可能である。 本実施の形 態では、 ポリイ ミ ド系樹脂 （日東電工製 ； AP— 6832 C) を使用 して絶縁体膜 1 2と、 スパッタ法により給電層を設けたセミアディテ イブ法を用いて第 1電極パターン 1 3を形成した。  When the thickness of the copper foil is as thin as 2 m or less, patterning by the semi-additive method using this copper foil as the power supply layer is also possible. In the present embodiment, the first electrode is formed by using a polyimide resin (manufactured by Nitto Denko; AP-6832C), using an insulator film 12 and a semi-additive method in which a power supply layer is provided by sputtering. Pattern 13 was formed.
次に、 図 1 5 ( c ) に示すように、 少なく とも一つ以上の第 1電極 パターン 1 3上に誘電体層 20と導電体層 2 1を形成する。 特に図示 してはいないが、 デカップリングコンデンサとして用いるため、 コン デンサを形成する第 1電極パターン 1 3はパッ ドとして電気的接続さ れている部位も有している。  Next, as shown in FIG. 15 (c), the dielectric layer 20 and the conductor layer 21 are formed on at least one or more first electrode patterns 13. Although not particularly shown, the first electrode pattern 13 forming the capacitor also has a portion electrically connected as a pad for use as a decoupling capacitor.
誘電体層 20はスパッタ法、 蒸着法、 CVD又は陽極酸化法等によ り第 1電極パターン 1 3上に形成する。 このコンデンサ 22を構成す る材料は、 酸化チタン、 酸化タンタル、 A 1 203、 S i 02、 Nb 2 O5、 B S T (B a x S r X_XT i 03) 、 P ZT (P b Z r XT i j _ x O 3) 、 P L ZT (P b !_yL a y Z r XT i !_x03) 又は S r B i 2 T a 2O9等のぺロブスカイ ト系材 The dielectric layer 20 is formed on the first electrode pattern 13 by a sputtering method, an evaporation method, a CVD method, an anodic oxidation method, or the like. Materials that make up the capacitor 22, titanium oxide, tantalum oxide, A 1 2 0 3, S i 0 2, Nb 2 O 5, BST (B a x S r X _ X T i 0 3), P ZT (P b Z r X T ij _ x O 3), PL ZT (P b! _ y L a y Z r X T i! _ x 0 3) or pair of such S r B i 2 T a 2 O 9 Lobskite-based materials
料であることが好ましい。 但し、 前記化合物のいずれについても、 0 ≤ X≤ 1 , 0 < y < lである。 It is preferably a material. However, for any of the above compounds, 0 ≦ X ≦ 1 and 0 <y <l.
また、 誘電体層 20は、 所望の誘電率を実現することができる有機 樹脂等により構成されてもよい。 また、 誘電体層 20上に導電体層 2 1をスパッタ法、 C V D法、 サブトラクティブ法、 セミアディティブ 法又はフルアディティブ法等により形成する。 本実施の形態では、 メ タルマスクを用いて必要な電極パターン 1 3上にスパッタ法により B S Tを 20 nm、 さらにその上に導電体層 2 1 としてスパッタ法で白 金を 80 nmを積層した。  In addition, the dielectric layer 20 may be made of an organic resin or the like that can realize a desired dielectric constant. The conductive layer 21 is formed on the dielectric layer 20 by a sputtering method, a CVD method, a subtractive method, a semi-additive method, a full-additive method, or the like. In the present embodiment, a metal mask is used to deposit 20 nm of BST on a required electrode pattern 13 by a sputtering method, and further, 80 nm of white gold is deposited thereon as a conductive layer 21 by a sputtering method.
次に、 図 1 5 (d) に示すように、 絶縁層 1 4と配線層 1 5を形成 する。 絶縁層 1 4を形成する方法は、 絶縁層 1 4を構成する絶縁樹脂 が液状ならば、 スピンコート法、 ダイコート法、 カーテンコート法又 は印刷法等により絶縁樹脂を積層し、 また、 絶縁樹脂がドライフ ィ ル ムであればラミネート法等により絶縁樹脂を積層した後、 乾燥等の処 理を施して前記絶縁樹脂を固める。 Next, as shown in FIG. 15D, an insulating layer 14 and a wiring layer 15 are formed. The method of forming the insulating layer 14 is as follows. If the insulating resin is liquid, the insulating resin is laminated by a spin coating method, a die coating method, a curtain coating method, a printing method, or the like.If the insulating resin is a dry film, the insulating resin is laminated by a laminating method or the like. The insulating resin is hardened by performing a treatment such as drying.
そして、 前記絶縁樹脂が感光性であればフォ ト リ ソプロセス等によ り、 また、 前記絶縁樹脂が非感光性であればレーザ加工法等により、 前記絶縁樹脂をパターニングしてビアホールを形成し、 キュアを行つ て絶縁樹脂を硬化させて絶縁層 1 4を形成する。  If the insulating resin is photosensitive, a photolithography process or the like is used.If the insulating resin is non-photosensitive, a via hole is formed by patterning the insulating resin by a laser processing method or the like. The insulating resin is cured by curing to form an insulating layer 14.
次に、 配線パターンをサブトラクティブ法、 セミアディティブ法又 はフルアディティブ法等により形成し、 配線層 1 5を形成する。 本実 施の形態では、 絶縁層 1 3にァラミ ド不織布含浸エポキシ樹脂 （新神 戸電機製 ； E A— 5 4 1 ) を使用し、 配線層 1 4は 2 m厚みの無電 解銅めつきを給電層としたセミアディティプ法を用いた。 この工程で 形成されている状態は、 図 9 ( c ) と同一となり、 これ以降の工程は 図 9 ( d ) 以降の工程となる。  Next, a wiring pattern is formed by a subtractive method, a semi-additive method, a full-additive method, or the like, and a wiring layer 15 is formed. In the present embodiment, the insulating layer 13 is made of epoxy resin impregnated with aramide non-woven fabric (manufactured by Shin-Kobe Electric Co., Ltd .; EA-541), and the wiring layer 14 has a 2 m thick electroless copper plating. The semi-additive method used as the power supply layer was used. The state formed in this step is the same as that in FIG. 9 (c), and the subsequent steps are the steps after FIG. 9 (d).
この搭載基板は、 本発明の第 3の実施の形態に係る搭載基板と同じ ものであり、 上述の製造方法によれば、 この搭載基板を効率よく製造 することができる。 この様なコンデンサを形成することにより、 伝送 ノィズを低減することができ、 高速化に最適な搭載基板を得ることが できる。  This mounting board is the same as the mounting board according to the third embodiment of the present invention, and according to the above-described manufacturing method, this mounting board can be manufactured efficiently. By forming such a capacitor, transmission noise can be reduced, and an optimal mounting board for high-speed operation can be obtained.
次に、 本発明に係る半導体装置搭載基板及び半導体パッケージの製 造方法の第 6の実施の形態を説明する。 図 1 6 ( a ) から （ f ) は、 本発明の第 6の実施の形態に係る搭載基板の製造方法を工程順に示す 部分断面図である。 なお、 各工程間において適宜洗浄及び熱処理を行 う。 金属支持体 1 1 に除去する予定部分をあらかじめ凹部 2 9として いる以外の構成は、 本発明の第 1の実施の形態の搭載基板の製造方法 と同一である。 図 1 6の搭載基板の製造方法は、 本発明の第 1の実施 の形態と同一で示したが、 第 2の実施の形態、 第 3の実施の形態、 第 4の実施の形態、第 5の実施の形態により搭載基板を形成してもよい。 先ず、 図 1 6 ( a ) に示すように、 厚さ 0 . 1乃至 1 . 5 m mの金 属支持体 1 1 の裏面に、 エッチング除去される予定地を凹部 2 9とし て形成する。 形成方法としては、 エッチング、 機械加工のいずれかも しくは複合した方法により行われる。 また、 フ レーム状とした金属板 を平坦な金属板と張り合わせることで金属支持体 1 1 を形成してもよ い。 Next, a sixth embodiment of the method for manufacturing a semiconductor device mounting board and a semiconductor package according to the present invention will be described. FIGS. 16 (a) to 16 (f) are partial cross-sectional views illustrating a method of manufacturing a mounting substrate according to the sixth embodiment of the present invention in the order of steps. Cleaning and heat treatment are appropriately performed between each step. The configuration is the same as that of the method of manufacturing the mounting board according to the first embodiment of the present invention, except that the portion to be removed from the metal support 11 is previously formed as the concave portion 29. The method of manufacturing the mounting substrate of FIG. 16 is the same as that of the first embodiment of the present invention, but is different from the second embodiment, the third embodiment, the fourth embodiment, and the fifth embodiment. The mounting substrate may be formed according to the above embodiment. First, as shown in FIG. 16 (a), on the back surface of a metal support 11 having a thickness of 0.1 to 1.5 mm, a place to be etched and removed is formed as a recess 29. As a forming method, etching, machining, or a combined method is used. Further, the metal support 11 may be formed by bonding a frame-shaped metal plate to a flat metal plate.
その後、 金属支持体 1 1の表面にめっき法、 エッチング、 導電性べ 一ス ト、 機械加工のいずれかの 1つもしくは複合した方法により突起 2 4を形成する。 突起 2 4をエッチング除去する際に、 第 1電極パタ ーン 1 3へのエツチングバリァのため、 突起 2 4の最上層に金、 銀、 白金、 パラジウムのいずれか一つの金属を構成させておく ことも可能 である。  After that, the projections 24 are formed on the surface of the metal support 11 by one or a combination of plating, etching, conductive base, and machining. When the protrusion 24 is removed by etching, the uppermost layer of the protrusion 24 is made of one of gold, silver, platinum, and palladium to provide an etching barrier to the first electrode pattern 13. It is also possible to keep it.
本実施の形態では、 金属支持体 1 1は銅合金板 （神戸製鋼： K F C シリーズ） を用い、 突起 2 4はめつき法によりニッケルで形成してい る。 突起 2 4を形成する方法は、 めっきレジス トを金属支持体 1 1上 に 3 0 m厚みで積層し、 フ ォ ト リソグラフィ一技術である露光、 現 像、 もしくは、 レーザにより突起 2 4の予定地にめっきレジス トの開 口パターンを形成し、 電解二ッケルめつきを 2 5 〃 m析出させた。 次に、 図 1 6 ( b ) に示すように、 絶縁体膜 1 2と第 1電極パター ン 1 3を形成する。 絶縁体膜 1 2の形成は、 絶縁体膜 1 2用の樹脂が 液状ならばスピンコート法、 ダイコート法、 カーテンコート法又は印 刷法等で積層する。 また、 ドライフィルム、 樹脂付き銅箔であればラ ミネート法等で積層した後、 乾燥等の処理を施して固める。 この際、 突起 2 4の頂点が絶縁体膜 1 2の表面上に現れている必要があるため、 液状樹脂の場合は、 感光性であればフオ ト リ ソグラフィ一によりバタ 一二ングを行い、 非感光性もしくは感光性でも解像度が不足している 場合は、 研磨により整える。  In the present embodiment, the metal support 11 is a copper alloy plate (Kobe Steel: KFC series), and the projections 24 are formed of nickel by a plating method. The projections 24 are formed by depositing a plating resist with a thickness of 30 m on the metal support 11 and planning the projections 24 by photolithography, an exposure, current image, or laser. An opening pattern of the plating resist was formed on the ground, and electrolytic nickel plating was deposited to 25 μm. Next, as shown in FIG. 16 (b), an insulator film 12 and a first electrode pattern 13 are formed. The insulating film 12 is formed by spin coating, die coating, curtain coating, printing, or the like if the resin for the insulating film 12 is liquid. In the case of dry film or copper foil with resin, after laminating by a lamination method or the like, it is cured by drying or other treatment. At this time, the vertices of the projections 24 need to appear on the surface of the insulator film 12. If the resolution is insufficient even for non-photosensitive or photosensitive, adjust by polishing.
また、 ドライフ ィルム、 樹脂付き銅箔の場合は、 ラミネート時に突 起 2 4の頂点が飛び出す様にフィル厶のキヤ リァ側にクッションを入 れておく とよい。 ドライフィルムの場合は、 ラミネート後に研磨で整 えてもかまわない。 In the case of dry film or copper foil with resin, insert a cushion on the carrier side of the film so that the top of protrusion 24 protrudes during lamination. It is good to keep it. In the case of dry film, it may be polished after lamination.
絶縁体膜 1 2を形成した後、 第 1電極パターン 1 3をサブトラクテ ィブ法、 セミアディティブ法又はフルアディティブ法等により形成す る。 特に、 樹脂付き銅箔の樹脂を絶縁体膜 1 2とした場合は、 キヤ リ ァとして用いている銅箔をサブトラクティブ法でパターニングするこ とも可能である。  After the formation of the insulator film 12, the first electrode pattern 13 is formed by a subtractive method, a semi-additive method, a full-additive method, or the like. In particular, when the resin of the copper foil with resin is used as the insulating film 12, the copper foil used as the carrier can be patterned by a subtractive method.
また、 銅箔の厚みが 2 m以下と薄い場合は、 この銅箔を給電層と したセミアディティブ法でのパターニングも可能である。 本実施の形 態では、 樹脂付き銅箔 （住友べ一クライ ト ； A P L— 4 5 0 1 ； 銅箔 厚み、 1 8 m) を使用して絶縁体膜 1 2と、 サブトラクティブ法に より銅箔をパターニングして第 1電極パターン 1 3を形成した。  When the thickness of the copper foil is as thin as 2 m or less, patterning by the semi-additive method using this copper foil as the power supply layer is also possible. In this embodiment, a resin-coated copper foil (Sumitomo Bei-Cry; APL-4501; copper foil thickness, 18 m) is used to form an insulator film 12 and a copper film by a subtractive method. The foil was patterned to form a first electrode pattern 13.
次に、 図 1 6 ( c ) に示すように、 絶縁層 1 4と配線層 1 5を形成 する。 絶縁層 1 4を形成する方法は、 絶縁層 1 4を構成する絶縁樹脂 が液状ならば、 スピンコート法、 ダイコート法、 カーテンコート法又 は印刷法等により絶縁樹脂を積層し、 また、 絶縁樹脂がドライフィル ムであればラミネート法等により絶縁樹脂を積層した後、 乾燥等の処 理を施して前記絶縁樹脂を固める。  Next, as shown in FIG. 16 (c), an insulating layer 14 and a wiring layer 15 are formed. The method of forming the insulating layer 14 is as follows: if the insulating resin forming the insulating layer 14 is liquid, the insulating resin is laminated by a spin coating method, a die coating method, a curtain coating method, a printing method, or the like. If the film is a dry film, the insulating resin is laminated by a laminating method or the like, and then subjected to a treatment such as drying to harden the insulating resin.
そして、 前記絶縁樹脂が感光性であればフォ ト リソプロセス等によ り、 また、 前記絶縁樹脂が非感光性であればレーザ加工法等により、 前記絶縁樹脂をパターニングしてビアホールを形成し、 キュアを行つ て絶縁樹脂を硬化させて絶縁層 1 4を形成する。 次に、 配線パターン をサブトラクティブ法、 セミアディティブ法又はフルアディティブ法 等により形成し、 配線層 1 5を形成する。  If the insulating resin is photosensitive, a photolithography process or the like is used.If the insulating resin is non-photosensitive, a via hole is formed by patterning the insulating resin by a laser processing method or the like. The insulating resin is cured by curing to form an insulating layer 14. Next, a wiring pattern is formed by a subtractive method, a semi-additive method, a full-additive method, or the like, and a wiring layer 15 is formed.
次に、 図 1 6 ( d ) に示すように、 サブトラクティブ法、 セミアデ ィティブ法又はフルアディティブ法等による絶縁層 1 3の形成工程及 び配線層 1 4の形成工程を繰り返して、 配線構造膜 1 6と表層に第 2 電極パターン 1 7を形成する。 本実施の形態では、 絶縁層 1 3にァラ ミ ド不織布含浸エポキシ樹脂 （新神戸電機製 ； E A— 5 4 1 ) を使用 し、 配線層 1 4は 2 m厚みの無電解銅めつきを給電層としたセミア ディティブ法を用いた。 Next, as shown in FIG. 16 (d), the process of forming the insulating layer 13 and the process of forming the wiring layer 14 by a subtractive method, a semi-additive method, a full additive method, or the like are repeated to form a wiring structure film. 16 and a second electrode pattern 17 are formed on the surface layer. In this embodiment, the insulating layer 13 is made of epoxy resin impregnated with aramide non-woven fabric (manufactured by Shin-Kobe Electric; EA-541). For the wiring layer 14, a semi-additive method using a 2 m-thick electroless copper plating as a power supply layer was used.
次に、 図 1 6 ( e ) に示すように、 金属支持体 1 1 をエッチングに より選択除去する。 除去法としては、 エッチングするところが開口し ているエッチングレジス トを形成する。 形成方法は、 エッチングレジ ス トが液状ならばスピンコー ト法、 ダイコート法、 力一テンコート法 又は印刷法等によりエッチングレジス トを積層し、 エッチングレジス トがドライフィルムであればラミネート法等でェツチングレジス トを 積層した後、 乾燥等の処理を施してエッチングレジス トを固め、 エツ チンダレジス トが感光性であればフ ォ ト リソプロセス等により、 エツ チングレジス トが非感光性であればレ一ザ加工法等によりエッチング レジス トをパターニングする。  Next, as shown in FIG. 16 (e), the metal support 11 is selectively removed by etching. As a removal method, an etching resist having an opening at a portion to be etched is formed. If the etching resist is liquid, the etching resist is laminated by a spin coating method, a die coating method, a force coating method, a printing method, or the like. After etching, the etching resist is hardened by drying and other treatments. If the etch resist is photosensitive, a photolithography process is used.If the etch resist is non-photosensitive, the laser processing method is used. The etching resist is patterned by the above method.
その後、 このエッチングレジス トをマスクとして、 金属支持体 1 1 を絶縁体膜 1 1 と突起 2 4が露出するまでエッチングする。 また、 凹 部 2 9を形成しているため、 エッチングレジス トを用いず、 エツチン グすることも可能である。 本実施の形態では、 アンモニアを主成分と するアルカリ銅エッチング液 （メルテックス ； エープロセス） を用い てエッチングレジス トを用いずに銅合金板を選択除去した。  Thereafter, using the etching resist as a mask, the metal support 11 is etched until the insulator film 11 and the projections 24 are exposed. Further, since the concave portion 29 is formed, it is possible to perform etching without using an etching resist. In the present embodiment, the copper alloy plate was selectively removed without using an etching resist by using an alkali copper etching solution containing ammonia as a main component (Meltex; A process).
次に、 図 1 6 ( f ) に示すように、 突起 2 4をエッチング、 もしく はレーザにより選択除去する。 エッチングを行った後に開口部の形状 を整えるため、 レーザを使用してもかまわない。 突起 2 4除去後に第 1電極パターン 1 3の露出表面を正常化して搭載基板を得る。 本実施 の形態では、 突起 2 4としたニッケルを硫酸 ： 過酸化水素水 ： 純水 = 1 : 1 : 1 0の比率で混合したエッチング液を用いて除去した。  Next, as shown in FIG. 16 (f), the protrusions 24 are etched or selectively removed by laser. A laser may be used to adjust the shape of the opening after etching. After removing the projections 24, the exposed surface of the first electrode pattern 13 is normalized to obtain a mounting substrate. In the present embodiment, the nickel formed as the protrusions 24 was removed using an etching solution in which sulfuric acid: aqueous hydrogen peroxide: pure water was mixed at a ratio of 1: 1: 10.
上述の製造方法によれば、 搭載基板を効率よく製造することができ る。 また、 本実施の形態に係る製造方法によれば、 本発明の第 1の実 施の形態、第 2の実施の形態、第 3の実施の形態、第 4の実施の形態、 第 5の実施の形態のそれぞれに対応できるため、 それぞれの利点を利 用できる。 さらに、 金属支持体 1 1をエッチングする予定地を凹部 2 9としているため、 エッチングを行う量を少なくできると共に、 エツ チング精度や歩留まりの向上の効果を持っている。 According to the above-described manufacturing method, the mounting substrate can be manufactured efficiently. Further, according to the manufacturing method of the present embodiment, the first embodiment, the second embodiment, the third embodiment, the fourth embodiment, and the fifth embodiment of the present invention are described. Since each of the above forms can be handled, the respective advantages can be used. Furthermore, the place where the metal support 1 is to be etched is Since it is set to 9, the amount of etching can be reduced, and it has the effect of improving the etching accuracy and yield.
次に、 本発明に係る半導体装置搭載基板及び半導体パッケージの製 造方法の第 7の実施の形態を説明する。 図 1 7 ( a ) から （e ) は、 本発明の第 7の実施の形態に係る搭載基板の製造方法を工程順に示す 部分断面図である。 なお、 各工程間において適宜洗浄及び熱処理を行 う。 金属支持体 1 1の両表面に搭載基板を形成してから金属支持体 1 1 を水平方向で 2分割している以外の構成は、 本発明の第 1の実施の 形態の搭載基板の製造方法と同一である。 図 1 7の搭載基板の製造方 法は、 本発明の第 1の実施の形態と同一で示したが、 第 2の実施の形 態、 第 3の実施の形態、 第 4の実施の形態、 第 5の実施の形態により 搭載基板を形成してもよい。  Next, a seventh embodiment of the method for manufacturing a semiconductor device mounting substrate and a semiconductor package according to the present invention will be described. FIGS. 17 (a) to 17 (e) are partial cross-sectional views illustrating a method of manufacturing a mounting substrate according to the seventh embodiment of the present invention in the order of steps. Cleaning and heat treatment are appropriately performed between each step. Except for forming the mounting substrate on both surfaces of the metal support 11 and then dividing the metal support 11 into two parts in the horizontal direction, the method of manufacturing the mounting substrate according to the first embodiment of the present invention Is the same as The method of manufacturing the mounting board shown in FIG. 17 is the same as that of the first embodiment of the present invention, but the second embodiment, the third embodiment, the fourth embodiment, A mounting substrate may be formed according to the fifth embodiment.
先ず、 図 1 7 ( a ) に示すように、 厚さ 0 . 2乃至 3 . 0 m mに切 り しろ分の厚みを追加した金属支持体 1 1 を用意する。 この場合は、 水平方向に分割した後の金属支持体 1 1の厚みが 0 . 1乃至 1 . 5 m mとなる厚みであることが望ましい。  First, as shown in FIG. 17 (a), a metal support 11 having a thickness of 0.2 to 3.0 mm and a thickness corresponding to a margin is added. In this case, it is preferable that the thickness of the metal support 11 after being divided in the horizontal direction is 0.1 to 1.5 mm.
次に、 図 1 7 ( b ) に示すように、 金属支持体 1 1の両表面にめつ き法、 エッチング、 導電性ペース ト、 機械加工のいずれかの 1つもし くは複合した方法により突起 2 4を形成する。 突起 2 4をエッチング 除去する際に、 第 1電極パターン 1 3へのエツチングバリアのため、 突起 2 4の最上層に金、 銀、 白金、 パラジウムのいずれか一つの金属 を構成させておく ことも可能である。  Next, as shown in Fig. 17 (b), both surfaces of the metal support 11 are attached by one of the following methods: etching, conductive paste, and machining. The projections 24 are formed. When etching and removing the projections 24, any one of gold, silver, platinum, and palladium may be formed on the uppermost layer of the projections 24 to provide an etching barrier to the first electrode pattern 13. It is possible.
本実施の形態では、 金属支持体 1 1 は銅合金板 （神戸製鋼 ： K F C シリーズ） を用い、 突起 2 4はめつき法によりニッケルで形成してい る。 突起 2 4を形成する方法は、 めっきレジス トを金属支持体 1 1上 に 3 0 m厚みで積層し、 フォ ト リソグラフィ一技術である露光、 現 像、 もしくは、 レーザにより突起 2 4の予定地にめっきレジス トの開 口パターンを形成し、 電解ニッケルめっきを 2 5 〃m析出させた。 次に、 図 1 7 ( c ) に示すように、 絶縁体膜 1 2と第 1電極パター ン 1 3を形成する。 絶縁体膜 1 2の形成は、 絶縁体膜 1 2用の樹脂が 液状ならばスピンコート法、 ダイコート法、 カーテンコート法又は印 刷法等で積層する。 また、 ドライフ ィルム、 樹脂付き銅箔であればラ ミネート法等で積層した後、 乾燥等の処理を施して固める。 この際、 突起 2 4の頂点が絶縁体膜 1 2の表面上に現れている必要があるため、 液状樹脂の場合は、 感光性であればフオ ト リソグラフィ一によりパタ 一二ングを行い、 非感光性もしくは感光性でも解像度が不足している 場合は、 研磨により整える。 In the present embodiment, the metal support 11 is a copper alloy plate (Kobe Steel: KFC series), and the projections 24 are formed of nickel by a plating method. The projections 24 are formed by laminating a plating resist on the metal support 11 with a thickness of 30 m, and using a photolithography technique such as exposure, current image, or laser to plan the locations of the projections 24. An opening pattern of a plating resist was formed on the substrate, and 25 μm of electrolytic nickel plating was deposited. Next, as shown in Fig. 17 (c), the insulator film 12 and the first electrode pattern To form 13. The insulating film 12 is formed by spin coating, die coating, curtain coating, printing, or the like if the resin for the insulating film 12 is liquid. In addition, if it is a dry film or a resin-coated copper foil, it is laminated by a lamination method or the like, and then solidified by drying or the like. At this time, since the vertices of the projections 24 need to appear on the surface of the insulator film 12, in the case of a liquid resin, if the photosensitive resin is photosensitive, patterning is performed by photolithography. If the resolution is insufficient even for photosensitive or photosensitive, prepare by polishing.
また、 ドライフ ィルム、 樹脂付き銅箔の場合は、 ラミネート時に突 起 2 4の頂点が飛び出す様にフイルムのキヤ リァ側にクッションを入 れておく とよい。 ドライフィルムの場合は、 ラミネート後に研磨で整 えてもかまわない。  In the case of a dry film or a resin-coated copper foil, it is preferable to insert a cushion on the carrier side of the film so that the top of the protrusion 24 protrudes during lamination. In the case of dry film, it may be polished after lamination.
絶縁体膜 1 2を形成した後、 第 1電極パターン 1 3をサブトラクテ ィブ法、 セミアディティブ法又はフルアディティブ法等により形成す る。 特に、 樹脂付き銅箔の樹脂を絶縁体膜 1 2とした場合は、 キヤ リ ァとして用いている銅箔をサブトラクティブ法でパターニングするこ とも可能である。 また、 銅箔の厚みが 2 m以下と薄い場合は、 この 銅箔を給電層としたセミアディティプ法でのパターニングも可能であ る。  After the formation of the insulator film 12, the first electrode pattern 13 is formed by a subtractive method, a semi-additive method, a full-additive method, or the like. In particular, when the resin of the copper foil with resin is used as the insulating film 12, the copper foil used as the carrier can be patterned by a subtractive method. When the thickness of the copper foil is as thin as 2 m or less, patterning by the semi-additive method using this copper foil as the power supply layer is also possible.
本実施の形態では、 樹脂付き銅箔 （住友べ一クライ ト ； A P L— 4 5 0 1 ； 銅箔厚み、 1 8 m) を使用して絶縁体膜 1 2と、 サブトラ クティブ法により銅箔をパターニングして第 1電極パターン 1 3を形 成した。  In this embodiment, a copper foil with a resin (Sumitomo Bei-Client; APL-4501; copper foil thickness, 18 m) is used to form an insulating film 12 and a copper foil by a subtractive method. The first electrode pattern 13 was formed by patterning.
次に、 図 1 7 ( d ) に示すように、 絶縁層 1 4と配線層 1 5を形成 する。 絶縁層 1 4を形成する方法は、 絶縁層 1 4を構成する絶縁樹脂 が液状ならば、 スピンコート法、 ダイコート法、 カーテンコート法又 は印刷法等により絶縁樹脂を積層し、 また、 絶縁樹脂がドライフ ィ ル ムであればラミネ一ト法等により絶縁樹脂を積層した後、 乾燥等の処 理を施して前記絶縁樹脂を固める。 そして、 前記絶縁樹脂が感光性であればフォ ト リソプロセス等によ り、 また、 前記絶縁樹脂が非感光性であればレーザ加工法等により、 前記絶縁樹脂をパターニングしてビアホールを形成し、 キュアを行つ て絶縁樹脂を硬化させて絶縁層 1 4を形成する。 Next, as shown in FIG. 17D, an insulating layer 14 and a wiring layer 15 are formed. The method of forming the insulating layer 14 is as follows: if the insulating resin forming the insulating layer 14 is liquid, the insulating resin is laminated by a spin coating method, a die coating method, a curtain coating method, a printing method, or the like. If the film is a dry film, an insulating resin is laminated by a laminating method or the like, and then a treatment such as drying is performed to solidify the insulating resin. If the insulating resin is photosensitive, a photolithography process or the like is used.If the insulating resin is non-photosensitive, a via hole is formed by patterning the insulating resin by a laser processing method or the like. The insulating resin is cured by curing to form an insulating layer 14.
次に、 配線パターンをサブトラクティブ法、 セミアディティブ法又 はフルアディティブ法等により形成し、 配線層 1 5を形成する。 さら に、 サブトラクティプ法、 セミアディティブ法又はフルアディ ティブ 法等による絶縁層 1 3の形成工程及び配線層 1 4の形成工程を繰り返 して、 配線構造膜 1 6と表層に第 2電極パターン 1 7を形成する。 本 実施の形態では、 絶縁層 1 3にァラミ ド不織布含浸エポキシ樹脂 （新 神戸電機製 ； E A— 5 4 1 ) を使用し、 配線層 1 4は 2 m厚みの無 電解銅めつきを給電層としたセミアディティブ法を用いた。  Next, a wiring pattern is formed by a subtractive method, a semi-additive method, a full-additive method, or the like, and a wiring layer 15 is formed. Further, the process of forming the insulating layer 13 and the process of forming the wiring layer 14 by a subtractive method, a semi-additive method, a full-additive method, or the like are repeated to form the second electrode pattern 17 on the wiring structure film 16 and the surface layer. To form In this embodiment, the insulating layer 13 is made of epoxy resin impregnated with aramide non-woven fabric (manufactured by Shin Kobe Electric; EA-541), and the wiring layer 14 has a 2 m-thick electroless copper plated power supply layer. The semi-additive method was used.
次に、 図 1 7 ( e ) に示すように、 金属支持体 1 1 を水平方向の中 心位置で 2分割して、 第 2表面を形成する。 分割する方法としては、 スライサー、 ウォーターカッター等による切断をおこなう。 この工程 で形成されている状態は、 図 9 ( d ) と同一となり、 これ以降の工程 は図 9 ( e ) 以降の工程となる。  Next, as shown in FIG. 17 (e), the metal support 11 is divided into two at the center in the horizontal direction to form a second surface. As a method of dividing, cut with a slicer, water cutter or the like. The state formed in this step is the same as that in FIG. 9D, and the subsequent steps are the steps after FIG. 9E.
上述の製造方法によれば、 搭載基板を効率よく製造することができ る。 また、 本実施の形態に係る製造方法によれば、 本発明の第 1の実 施の形態、第 2の実施の形態、第 3の実施の形態、第 4の実施の形態、 第 5の実施の形態のそれぞれに対応できるため、 それぞれの利点を利 用できる。 さらに、 金属支持体 1 1の両面を利用するために、 製造数 が二倍となり生産性を向上させる効果がある。  According to the above-described manufacturing method, the mounting substrate can be manufactured efficiently. Further, according to the manufacturing method of the present embodiment, the first embodiment, the second embodiment, the third embodiment, the fourth embodiment, and the fifth embodiment of the present invention are described. Since each of the above forms can be handled, the respective advantages can be used. Furthermore, since both surfaces of the metal support 11 are used, the number of productions is doubled, which has the effect of improving productivity.
次に、 本発明に係る半導体装置搭載基板及び半導体パッケージの製 造方法の第 8の実施の形態を説明する。 図 1 8 ( a ) から （e ) は、 本発明の第 8の実施の形態に係る搭載基板の製造方法を工程順に示す 部分断面図である。 なお、 各工程間において適宜洗浄及び熱処理を行 う。 金属支持体 1 1 を二枚張り合わせて両表面に搭載基板を形成して から金属支持体 1 1 を分割している以外の構成は、 本発明の第 1の実 施の形態の搭載基板の製造方法と同一である。 図 1 8の搭載基板の製 造方法は、 本発明の第 1の実施の形態と同一で示したが、 第 2の実施 の形態、 第 3の実施の形態、 第 4の実施の形態、 第 5の実施の形態、 第 6の実施の形態により搭載基板を形成してもよい。 特に金属支持体 1 1 に凹部 2 9を設けた形状の場合は、 本発明の張り合わせによって のみ両面形成を行うことができる。 Next, an eighth embodiment of a method for manufacturing a semiconductor device mounting substrate and a semiconductor package according to the present invention will be described. FIGS. 18 (a) to 18 (e) are partial cross-sectional views illustrating a method of manufacturing a mounting board according to the eighth embodiment of the present invention in the order of steps. Cleaning and heat treatment are appropriately performed between each step. The configuration other than that two metal supports 11 are attached to each other to form a mounting substrate on both surfaces and then the metal support 11 is divided is the first embodiment of the present invention. This is the same as the method of manufacturing the mounting board according to the embodiment. The method of manufacturing the mounting board of FIG. 18 is the same as that of the first embodiment of the present invention, but is different from the second embodiment, the third embodiment, the fourth embodiment, and the fourth embodiment. The mounting substrate may be formed according to the fifth embodiment and the sixth embodiment. In particular, in the case of a shape in which the concave portion 29 is provided in the metal support 11, both sides can be formed only by bonding according to the present invention.
先ず、 図 1 8 ( a ) に示すように、 厚さ 0 . 1乃至 1 . 5 m mに金 属支持体 1 1 aと金属支持体 1 1 bを張り合わせる。 また、 凹部 2 9 が形成されている金属支持体 1 1 を用いて張り合わせることも可能で ある。 張り合わせは、 金属支持体 1 1 aと金属支持体 1 1 bの張り合 わせる面を細かな凹凸を形成してかみこませるか、 接着剤、 溶接等に より全面もしくは端部で行う。 図 1 8 ( e ) で分割することを考慮す ると、 張り合わせは端部で行う方が適している。  First, as shown in FIG. 18 (a), the metal support 11a and the metal support 11b are laminated to a thickness of 0.1 to 1.5 mm. Further, it is also possible to use the metal support 11 having the concave portion 29 formed thereon for lamination. Lamination is performed on the entire surface or at the end using an adhesive, welding, or the like, by forming fine irregularities on the surface where the metal support 11a and the metal support 11b are bonded. Considering the division shown in Fig. 18 (e), it is more appropriate to bond at the end.
次に、 図 1 8 ( b ) に示すように、 金属支持体 1 1の両表面にめつ き法、 エッチング、 導電性ペース ト、 機械加工のいずれかの 1つもし くは複合した方法により突起 2 4を形成する。 突起 2 4をエッチング 除去する際に、 第 1電極パターン 1 3へのエッチングバリァのため、 突起 2 4の最上層に金、 銀、 白金、 パラジウムのいずれか一つの金属 を構成させておく ことも可能である。 本実施の形態では、 金属支持体 1 1 は銅合金板 （神戸製鋼 ： K F Cシリーズ） を用い、 突起 2 4はめ つき法によりニッケルで形成している。 突起 2 4を形成する方法は、 めっきレジス トを金属支持体 1 1上に 3 0 m厚みで積層し、 フ ォ ト リソグラフィー技術である露光、 現像、 もしくは、 レーザにより突起 2 4の予定地にめつきレジストの開口パターンを形成し、 電解二ッケ ルめっきを 2 5 〃m析出させた。  Next, as shown in Fig. 18 (b), the metal support 11 is attached to both surfaces by one of the following methods: etching, conductive paste, and machining. The projections 24 are formed. When the protrusions 24 are removed by etching, an uppermost layer of the protrusions 24 should be made of one of gold, silver, platinum, and palladium, as an etching barrier to the first electrode pattern 13. Is also possible. In the present embodiment, the metal support 11 is a copper alloy plate (Kobe Steel: KFC series), and is formed of nickel by the projection 24 mounting method. The projections 24 can be formed by laminating a plating resist with a thickness of 30 m on the metal support 11 and applying photolithography techniques such as exposure, development, or laser to the intended location of the projections 24. An opening pattern of the plating resist was formed, and electrolytic nickel plating was deposited to a thickness of 25 μm.
次に、 図 1 8 ( c ) に示すように、 絶縁体膜 1 2と第 1電極パター ン 1 3を形成する。 絶縁体膜 1 2の形成は、 絶縁体膜 1 2用の樹脂が 液状ならばスピンコート法、 ダイコート法、 カーテンコート法又は印 刷法等で積層する。 また、 ドライフ ィ ルム、 樹脂付き銅箔であればラ ミネート法等で積層した後、 乾燥等の処理を施して固める。 この際、 突起 2 4の頂点が絶縁体膜 1 2の表面上に現れている必要があるため、 液状樹脂の場合は、 感光性であればフオ ト リソグラフィ一によりバタ 一二ングを行い、 非感光性もしくは感光性でも解像度が不足している 場合は、 研磨により整える。 Next, as shown in FIG. 18 (c), an insulator film 12 and a first electrode pattern 13 are formed. The insulating film 12 is formed by spin coating, die coating, curtain coating, printing, or the like if the resin for the insulating film 12 is liquid. Drift film or copper foil with resin After laminating by the minate method etc., it is hardened by applying processing such as drying. At this time, since the vertices of the projections 24 need to appear on the surface of the insulator film 12, in the case of a liquid resin, if photosensitive, photolithography is used to perform buttering. If the resolution is insufficient even for photosensitive or photosensitive, prepare by polishing.
また、 ドライフ ィ ルム、 樹脂付き銅箔の場合は、 ラミネート時に突 起 2 4の頂点が飛び出す様にフ ィ ルムのキヤ リ ァ側にク ッショ ンを入 れておく とよい。 ドライフィルムの場合は、 ラミネート後に研磨で整 えてもかまわない。  In the case of a dry film or a copper foil with resin, it is preferable to insert a cushion on the carrier side of the film so that the top of the protrusion 24 protrudes during lamination. In the case of dry film, it may be polished after lamination.
絶縁体膜 1 2を形成した後、 第 1電極パターン 1 3をサブトラクテ イブ法、 セミアディティブ法又はフルアディティブ法等により形成す る。 特に、 樹脂付き銅箔の樹脂を絶縁体膜 1 2とした場合は、 キヤ リ ァとして用いている銅箔をサブトラクティブ法でパターニングするこ とも可能である。  After the formation of the insulator film 12, the first electrode pattern 13 is formed by a subtractive method, a semi-additive method, a full-additive method, or the like. In particular, when the resin of the copper foil with resin is used as the insulating film 12, the copper foil used as the carrier can be patterned by a subtractive method.
また、 銅箔の厚みが 2 m以下と薄い場合は、 この銅箔を給電層と したセミアディティブ法でのパターニングも可能である。 本実施の形 態では、 樹脂付き銅箔 （住友べ一クライ ト ； A P L— 4 5 0 1 ; 銅箔 厚み、 1 8 m) を使用して絶縁体膜 1 2と、 サブトラクティブ法に より銅箔をパターニングして第 1電極パターン 1 3を形成した。  When the thickness of the copper foil is as thin as 2 m or less, patterning by the semi-additive method using this copper foil as the power supply layer is also possible. In the present embodiment, a copper foil with resin (Sumitomo Bei-Cry; APL-4501; copper foil thickness, 18 m) is used to form an insulator film 12 and a copper film by a subtractive method. The foil was patterned to form a first electrode pattern 13.
次に、 図 1 8 ( d ) に示すように、 絶縁層 1 4と配線層 1 5を形成 する。 絶縁層 1 4を形成する方法は、 絶縁層 1 4を構成する絶縁樹脂 が液状ならば、 スピンコート法、 ダイコート法、 カーテンコート法又 は印刷法等により絶縁樹脂を積層し、 また、 絶縁樹脂がドライフィル ムであればラミネ一ト法等により絶縁樹脂を積層した後、 乾燥等の処 理を施して前記絶縁樹脂を固める。  Next, as shown in FIG. 18 (d), an insulating layer 14 and a wiring layer 15 are formed. The method of forming the insulating layer 14 is as follows: if the insulating resin forming the insulating layer 14 is liquid, the insulating resin is laminated by a spin coating method, a die coating method, a curtain coating method, a printing method, or the like. If the film is a dry film, the insulating resin is laminated by a lamination method or the like, and then subjected to a treatment such as drying to harden the insulating resin.
そして、 前記絶縁樹脂が感光性であればフォ ト リソプロセス等によ り、 また、 前記絶縁樹脂が非感光性であればレーザ加工法等により、 前記絶縁樹脂をパターニングしてビアホールを形成し、 キュアを行つ て絶縁樹脂を硬化させて絶縁層 1 4を形成する。 次に、 配線パターンをサブトラクティブ法、 セミアディティブ法又 はフルアディ ティブ法等により形成し、 配線層 1 5を形成する。 さら に、 サブトラタティブ法、 セミアディティブ法又はフルアディティブ 法等による絶縁層 1 3の形成工程及び配線層 1 4の形成工程を繰り返 して、 配線構造膜 1 6と表層に第 2電極パターン 1 7を形成する。 本実施の形態では、 絶縁層 1 3にァラミ ド不織布含浸エポキシ樹脂 (新神戸電機製 ； E A— 5 4 1 ) を使用し、 配線層 1 4は 2 厚み の無電解銅めつきを給電層としたセミアディティブ法を用いた。 If the insulating resin is photosensitive, a photolithography process or the like is used.If the insulating resin is non-photosensitive, a via hole is formed by patterning the insulating resin by a laser processing method or the like. The insulating resin is cured by curing to form an insulating layer 14. Next, a wiring pattern is formed by a subtractive method, a semi-additive method, a full-additive method, or the like, and a wiring layer 15 is formed. Further, the process of forming the insulating layer 13 and the process of forming the wiring layer 14 by a subtractive method, a semi-additive method, a full-additive method, or the like are repeated to form a second electrode pattern on the wiring structure film 16 and the surface layer. Form 17 In this embodiment, an epoxy resin impregnated with nonwoven nonwoven fabric (manufactured by Shin-Kobe Electric; EA-541) is used for the insulating layer 13, and the wiring layer 14 is a 2-layer electroless copper-plated power supply layer. The semi-additive method was used.
次に、 図 1 8 ( e ) に示すように、 金属支持体 1 1を全面張り合わ せた金属支持体 1 1 は、 その中心をスライサー、 ウォーターカッター 等により切断し金属支持体 1 1 aと金属支持体 1 1 bに分割する。 端 部張り合わせた金属支持体 1 1は、 張り合わせてある端部を切断する ことで金属支持体 1 1 aと金属支持体 1 1 bに分割する。  Next, as shown in FIG. 18 (e), the metal support 11 on which the metal support 11 is bonded to the entire surface is cut at its center with a slicer, a water cutter, or the like, and the metal support 11 a and the metal support 11 a are cut. Support 1 Divide into 1b. The metal support 11 with the end bonded is divided into a metal support 11a and a metal support 11b by cutting the bonded end.
この工程で形成されている状態は、 図 9 ( d ) と同一となり、 これ 以降の工程は図 9 ( e ) 以降の工程となる。  The state formed in this step is the same as that in FIG. 9D, and the subsequent steps are the steps after FIG. 9E.
上述の製造方法によれば、 搭載基板を効率よく製造することができ る。 また、 本実施の形態に係る製造方法によれば、 本発明の第 1 の実 施の形態、第 2の実施の形態、第 3の実施の形態、第 4の実施の形態、 第 5の実施の形態、 第 6の実施の形態のそれぞれに対応できるため、 それぞれの利点を利用できる。 さらに、 金属支持体 1 1の加工を行つ た後に張り合わせることができるため、 金属支持体 1 1の加工自由度 が高く、 また、 張り合わせ両表面を使用するために製造数が二倍とな り生産性を向上させる効果がある。  According to the above-described manufacturing method, the mounting substrate can be manufactured efficiently. Further, according to the manufacturing method of the present embodiment, the first embodiment, the second embodiment, the third embodiment, the fourth embodiment, and the fifth embodiment of the present invention are provided. Since each of the embodiments and the sixth embodiment can be applied, the respective advantages can be utilized. Furthermore, since the metal support 11 can be bonded after being processed, the degree of freedom in processing the metal support 11 is high, and the production number is doubled because both surfaces are used. This has the effect of improving productivity.
次に、 本発明に係る半導体搭載基板及び半導体パッケージの製造方 法の第 9の実施の形態を説明する。 図 1 9 ( a ) から （d ) は、 本発 明の第 9の実施の形態に係る半導体パッケージの製造方法を工程順に 示す部分断面図である。 本実施の形態は、 本発明の第 5の実施の形態 (図 8 ( a ) 、 （b ) 、 ( c ) ) に係る搭載基板を製造するためのも のである。 なお、 各工程間において適宜洗浄及び熱処理を行う。 図 1 9では金属バンプ 2 7として半田ボールを用いたフリ ップチッ プによる接続を行っている。 金属バンプ 2 7としては金、 銅、 錫、 半 田などからなる金属が好適に使用される。 また、 パッ ド 2 6と第 2電 極パターン 1 7間の接続としては、 ワイヤーボンディ ング、 テープボ ンディ ングを使用できる。 Next, a ninth embodiment of a method of manufacturing a semiconductor mounting substrate and a semiconductor package according to the present invention will be described. FIGS. 19A to 19D are partial cross-sectional views illustrating a method of manufacturing a semiconductor package according to a ninth embodiment of the present invention in the order of steps. This embodiment is for manufacturing a mounting substrate according to the fifth embodiment of the present invention (FIGS. 8A, 8B, and 8C). Note that cleaning and heat treatment are appropriately performed between each step. In FIG. 19, connections are made by flip-chip using solder balls as the metal bumps 27. As the metal bump 27, a metal made of gold, copper, tin, solder, or the like is preferably used. Further, as the connection between the pad 26 and the second electrode pattern 17, wire bonding or tape bonding can be used.
先ず、 図 1 9 ( a ) に示すように、 本発明の第 1の実施の形態、 第 2の実施の形態、 第 3の実施の形態、 第 4の実施の形態、 第 5の実施 の形態、 第 6の実施の形態、 第 7の実施の形態、 第 8の実施の形態に より配線構造膜 1 6、 第 2電極パターン 1 7まで形成されている形態 (例として、 図 9 ( d ) の形態） の搭載基板を用意する。  First, as shown in FIG. 19 (a), the first embodiment, the second embodiment, the third embodiment, the fourth embodiment, and the fifth embodiment of the present invention According to the sixth embodiment, the seventh embodiment, and the eighth embodiment, the wiring structure film 16 and the second electrode pattern 17 are formed (for example, FIG. 9 (d)). Form) is prepared.
次に、 図 1 9 ( b ) に示すように、 第 2電極パターン 1 7と半導体 装置 2 5のパッ ド 2 6を金属バンプ 2 7により接続を行う。 また、 必 要であればアンダーフィル樹脂 2 8を充填してもよい。 本実施の形態 では、 半田ボールを用いて接続を行い、 アンダーフィル樹脂 2 8を充 填した。  Next, as shown in FIG. 19 (b), the second electrode pattern 17 is connected to the pad 26 of the semiconductor device 25 by a metal bump 27. If necessary, underfill resin 28 may be filled. In the present embodiment, connection is made using solder balls, and the underfill resin 28 is filled.
次に、 図 1 9 ( c ) に示すように、 金属支持体 1 1 と突起 2 4を選 択除去することで、 第 1電極パターン 1 3を露出させる。 金属支持体 1 1の除去はエッチングを用い、 突起 2 4の除去はエッチングかレー ザのいずれかもしくは複合した方法により行われる。 この際に、 搭載 した半導体装置 2 5にダメージがいかないようにレジス ト材で保護す ることが望ましい。 また、 半導体装置 2 5を搭載した半導体パッケー ジの強度が十分であれば、 図 1 9 ( d ) に示すように、 金属支持体 1 1 をすベて除去しても構わない。  Next, as shown in FIG. 19 (c), the first electrode pattern 13 is exposed by selectively removing the metal support 11 and the protrusion 24. The removal of the metal support 11 is performed by etching, and the removal of the protrusions 24 is performed by etching, laser, or a combined method. At this time, it is desirable to protect the mounted semiconductor device 25 with a resist material so as not to be damaged. If the strength of the semiconductor package on which the semiconductor device 25 is mounted is sufficient, the entire metal support 11 may be removed as shown in FIG. 19 (d).
また、 半導体装置 2 5を搭載した図 1 9 ( b ) の状態から、 図 2 0 に示すとおり、 モールド樹脂 3 0により封止する半導体パッケージと する工程をとつてもよい。  Further, a step of converting the state of FIG. 19 (b) with the semiconductor device 25 mounted thereon into a semiconductor package sealed with the mold resin 30 as shown in FIG. 20 may be taken.
先ず、 図 2 0 ( a ) に示すように、 本発明の第 1の実施の形態、 第 2の実施の形態、 第 3の実施の形態、 第 4の実施の形態、 第 5の実施 の形態、 第 6の実施の形態、 第 7の実施の形態、 第 8の実施の形態に より配線構造膜 1 6、 第 2電極パターン 1 7まで形成されている形態 (例として、 図 9 (d) の形態） の搭載基板を用意し、 半導体装置 2 5をフリ ツプチップ接続させて、アンダーフィル樹脂 28を充填する。 次に、 図 20 (b) に示すように、 モールド樹脂 30により封止を 行う。 その後、 図 20 (c) に示すように、 金属支持体 1 1 と突起 2 4を選択除去することで、 第 1電極パターン 1 3を露出させる。 金属 支持体 1 1の除去はエッチングを用い、 突起 24の除去はエッチング かレーザのいずれかもしくは複合した方法により行われる。 First, as shown in FIG. 20 (a), the first embodiment, the second embodiment, the third embodiment, the fourth embodiment, and the fifth embodiment of the present invention The sixth embodiment, the seventh embodiment, and the eighth embodiment A mounting substrate having a configuration in which the wiring structure film 16 and the second electrode pattern 17 are further formed (for example, the configuration in FIG. 9D) is prepared, and the semiconductor device 25 is flip-chip connected, and an under-mount is formed. Fill resin 28. Next, as shown in FIG. 20B, sealing is performed with a mold resin 30. After that, as shown in FIG. 20 (c), the first electrode pattern 13 is exposed by selectively removing the metal support 11 and the protrusion 24. The removal of the metal support 11 is performed by etching, and the removal of the protrusions 24 is performed by etching, laser, or a combined method.
この際に、 搭載した半導体装置 25にダメージがいかないようにレ ジス ト材で保護することが望ましい。 また、 半導体装置 25を搭載し た半導体パッケージの強度が十分であれば、 図 20 (d) に示すよう に、 金属支持体 1 1をすベて除去しても構わない。  At this time, it is desirable to protect the mounted semiconductor device 25 with a resist material so as not to be damaged. Further, if the strength of the semiconductor package on which the semiconductor device 25 is mounted is sufficient, the entire metal support 11 may be removed as shown in FIG. 20 (d).
さらに、 半導体装置 25を搭載した図 1 9 (b) の状態から、 図 2 1に示すとおり、 スぺ一サ 3 1を用いてヒートスプレッダ 32を取り 付けた半導体パッケージとする工程をとつてもよい。  Further, from the state of FIG. 19 (b) in which the semiconductor device 25 is mounted, as shown in FIG. 21, a step of forming a semiconductor package having the heat spreader 32 attached thereto using a spacer 31 may be taken. .
先ず、 図 2 1 (a) に示すように、 本発明の第 1の実施の形態、 第 2の実施の形態、 第 3の実施の形態、 第 4の実施の形態、 第 5の実施 の形態、 第 6の実施の形態、 第 7の実施の形態、 第 8の実施の形態に より配線構造膜 1 6、 第 2電極パターン 1 7まで形成されている形態 (例として、 図 9 (d) の形態） の搭載基板を用意し、 半導体装置 2 5をフリ ツプチップ接続させて、アンダーフィル樹脂 28を充填する。 次に、 図 2 1 (b) に示すように、 スぺーサ 3 1を取り付ける。 通 常、 スぺーサ 3 1は半導体装置 25上にヒートスプレッダ 32とヒー トシンクを取り付ける際の補強枠である。 材質としては、 ステンレス や銅が用いられるが、 補強に必要な強度を有している場合は、 樹脂に より形成されても構わない。  First, as shown in FIG. 21 (a), the first embodiment, the second embodiment, the third embodiment, the fourth embodiment, and the fifth embodiment of the present invention According to the sixth embodiment, the seventh embodiment, and the eighth embodiment, the wiring structure film 16 and the second electrode pattern 17 are formed (for example, FIG. 9D The mounting substrate of the above is prepared, and the semiconductor device 25 is flip-chip connected, and the underfill resin 28 is filled. Next, as shown in FIG. 21 (b), the spacer 31 is attached. Usually, the spacer 31 is a reinforcing frame for mounting the heat spreader 32 and the heat sink on the semiconductor device 25. Stainless steel or copper is used as the material, but if it has the strength required for reinforcement, it may be formed of resin.
次に、 図 2 1 ( c ) に示すように、 ヒートシンクを取り付けるため のヒートスプレッダ 32を取り付ける。 この取り付けは、 半導体装置 25とヒートスプレッダ 32の間は伝熱性の金属ペース トによる接着 剤で、 スぺ一サ 3 1 とヒートスプレッダ 3 2の間は絶縁性の接着剤で 行う。 Next, as shown in FIG. 21 (c), a heat spreader 32 for mounting a heat sink is attached. In this installation, the semiconductor device 25 and the heat spreader 32 are bonded with a heat conductive metal paste. An adhesive between the spacer 31 and the heat spreader 32 is used.
取り付けた後、 金属支持体 1 1 と突起 2 4を選択除去することで、 第 1電極パターン 1 3を露出させる。 金属支持体 1 1の除去はエツチ ングを用い、 突起 2 4の除去はエツチングかレーザのいずれかもしく は複合した方法により行われる。 この際に、 搭載したヒートスプレツ ダ 3 2、 スぺーサ 3 1、 半導体装置 2 5にダメージがいかないように レジス ト材で保護することが望ましい。 また、 半導体装置 2 5を搭載 した半導体パッケージの強度が十分であれば、 図 2 1 ( d ) に示すよ うに、 金属支持体 1 1 をすベて除去しても構わない。  After mounting, the first electrode pattern 13 is exposed by selectively removing the metal support 11 and the protrusion 24. The metal support 11 is removed by etching, and the protrusions 24 are removed by etching, laser, or a combined method. At this time, it is desirable to protect the mounted heat spreader 32, spacer 31 and semiconductor device 25 with a resist material so as not to be damaged. Further, if the strength of the semiconductor package on which the semiconductor device 25 is mounted is sufficient, the entire metal support 11 may be removed as shown in FIG. 21D.
この搭載基板は、 本発明の第 5の実施の形態に係る半導体パッケー ジと同じものであり、 上述の製造方法によれば、 この搭載基板を効率 よく製造することができる。 本発明を用いることで、 半導体装置 2 5 搭載、 アンダーフィル 2 8充填、 モールド樹脂 3 0充填、 スぺーサ 3 1、 ヒートスプレッダ 3 2それぞれの工程での搭載基板の反りやうね りなどの変形が金属支持体 1 1 により抑えられるため搭載信頼性およ ぴ組み立て歩留まりが向上する。  This mounting board is the same as the semiconductor package according to the fifth embodiment of the present invention, and according to the above-described manufacturing method, this mounting board can be manufactured efficiently. By using the present invention, deformation such as warpage or undulation of the mounting substrate in each process of mounting the semiconductor device 25, filling the underfill 28, filling the mold resin 30, filling the spacer 31, and the heat spreader 32, is eliminated. Mounting reliability and assembly yield are improved because it is suppressed by the metal support 11.
次に、 本発明に係る半導体装置搭載基板及び半導体パッケージの製 造方法の第 1 0の実施の形態を説明する。 図 2 2 ( a ) から （d ) は、 本発明の第 Γ 0の実施の形態に係る半導体パッケージの製造方法をェ 程順に示す部分断面図である。 本実施の形態は、 本発明の第 5の実施 の形態 （図 8 ( b ) 、 ( c ) 、 ( d ) ) に係る搭載基板を製造するた めのものである。なお、各工程間において適宜洗浄及び熱処理を行う。 図 2 2では金属バンプ 2 7として半田ポールを用いたフリ ップチッ プによる接続を行っている。 金属バンプ 2 7としては金、 銅、 錫、 半 田などからなる金属が好適に使用される。 また、 パッ ド 2 6と第 2電 極パターン 1 7間の接続としては、 ワイヤーボンディ ング、 テープポ ンディ ングを使用できる。  Next, a tenth embodiment of a method of manufacturing a semiconductor device mounting substrate and a semiconductor package according to the present invention will be described. FIGS. 22 (a) to 22 (d) are partial cross-sectional views sequentially showing a method of manufacturing a semiconductor package according to the tenth embodiment of the present invention. This embodiment is for manufacturing a mounting substrate according to the fifth embodiment (FIGS. 8B, 8C, and 8D) of the present invention. Note that cleaning and heat treatment are appropriately performed between each step. In FIG. 22, connection is made by flip-chip using a solder pole as the metal bump 27. As the metal bump 27, a metal made of gold, copper, tin, solder, or the like is preferably used. As the connection between the pad 26 and the second electrode pattern 17, wire bonding or tape bonding can be used.
先ず、 図 2 2 ( a ) に示すように、 本発明の第 1の実施の形態、 第 2の実施の形態、 第 3の実施の形態、 第 4の実施の形態、 第 5の実施 の形態、 第 6の実施の形態、 第 7の実施の形態、 第 8の実施の形態に より形成された搭載基板を用意する。 First, as shown in FIG. 22 (a), the first embodiment of the present invention, Formed by the second embodiment, the third embodiment, the fourth embodiment, the fifth embodiment, the sixth embodiment, the seventh embodiment, and the eighth embodiment Prepare the mounted mounting board.
次に、 図 22 (b) に示すように、 第 2電極パターン 1 7と半導体 装置 25のパッ ド 26を金属バンプ 27により接続を行う。 また、 必 要であればアンダーフィル樹脂 28を充填してもよい。 本実施の形態 では、 半田ポールを用いて接続を行い、 アンダーフィル樹脂 28を充 填した。  Next, as shown in FIG. 22B, the second electrode pattern 17 is connected to the pad 26 of the semiconductor device 25 by the metal bump 27. If necessary, underfill resin 28 may be filled. In the present embodiment, connection is made using a solder pole, and the underfill resin 28 is filled.
ここで、 図 22 (a) での搭載基板を金属支持体 1 1を除去した形 状のものとした場合は、図 22 (c)に示す半導体パ ヅケージとなる。 また、 図 22 (b) で得られた半導体パッケージの強度が十分である 場合は、 補強としてつけている金属支持体 1 1をすベて除去して、 図 22 ( c ) の形態としても構わない。  Here, when the mounting substrate in FIG. 22 (a) has a shape in which the metal support 11 is removed, the semiconductor package shown in FIG. 22 (c) is obtained. If the strength of the semiconductor package obtained in FIG. 22 (b) is sufficient, all of the metal support 11 attached as reinforcement may be removed, and the configuration shown in FIG. 22 (c) may be used. Absent.
さらに、 図 22 (d) に示すように、 モールド樹脂 30により半導 体装置 25搭載側を封止した形態や、 図 22 (e) に示すように、 ス ぺーサ 3 1を使用してヒートスプレッダ 32を取り付けた半導体パッ ケージとしてもよい。 図 22 (d) 、 (e) 共に金属支持体 1 1を残 している形状であるが、 半導体パッケージとして強度が十分であれば 金属支持体 1 1を除去しても構わない。  Further, as shown in FIG. 22 (d), the semiconductor device 25 mounting side is sealed with a mold resin 30 or, as shown in FIG. 22 (e), a heat spreader using a spacer 31 is used. It may be a semiconductor package to which 32 is attached. FIGS. 22 (d) and (e) both show the shape in which the metal support 11 remains, but the metal support 11 may be removed if the strength is sufficient for a semiconductor package.
また、 図 23に示すとおり、 金属支持体 1 1を補強枠としてのスぺ ーサ 3 1 として利用した半導体パッケージとしての工程を取ることが できる。  Further, as shown in FIG. 23, a process as a semiconductor package using the metal support 11 as a spacer 31 as a reinforcing frame can be taken.
先ず、 図 23 (a) に示すように、 本発明の第 1の実施の形態、 第 2の実施の形態、 第 3の実施の形態、 第 4の実施の形態、 第 5の実施 の形態、 第 6の実施の形態、 第 7の実施の形態、 第 8の実施の形態に より形成された搭載基板を用意する。  First, as shown in FIG. 23 (a), the first embodiment, the second embodiment, the third embodiment, the fourth embodiment, the fifth embodiment, A mounting substrate formed according to the sixth embodiment, the seventh embodiment, and the eighth embodiment is prepared.
次に、 図 23 (b) に示すように、 第 1電極パターン 1 3と半導体 装置 25のパッ ド 26を金属バンプ 27により接続を行う。 また、 必 要であればアンダーフィル樹脂 28を充填してもよい。 本実施の形態 26 Next, as shown in FIG. 23 (b), the first electrode pattern 13 and the pad 26 of the semiconductor device 25 are connected by a metal bump 27. If necessary, underfill resin 28 may be filled. This embodiment 26
54 54
では、 半田ボールを用いて接続を行い、 アンダーフィル樹脂 2 8を充 填した。 Then, connection was made using solder balls, and underfill resin 28 was filled.
次に、 図 2 3 ( c ) に示すように、 ヒー トスプレッダ 3 2を取り付 ける。 この形態とするためには、 金属支持体 1 1の厚みが搭載した半 導体装置 2 5の搭載基板上からの厚みとほぼ一致させる必要がある。 また、 ヒー トスプレッダ 3 2を取り付けないでモールド樹脂 3 0によ り封止する （図 2 3 ( d ) ) 形態もとれる。 モールと樹脂 3 0による 封止では、 金属支持体 1 1の厚みと半導体装置 2 5の搭载厚みが必ず しも一致する必要はない。  Next, as shown in FIG. 23 (c), the heat spreader 32 is attached. In order to achieve this mode, it is necessary that the thickness of the metal support 11 substantially coincides with the thickness of the mounted semiconductor device 25 from the mounting substrate. Further, the heat spreader 32 is not attached, and is sealed with the mold resin 30 (FIG. 23 (d)). In the sealing with the molding and the resin 30, the thickness of the metal support 11 and the mounting thickness of the semiconductor device 25 do not necessarily have to match.
この搭載基板は、 本発明の第 5の実施の形態に係る半導体パッケ一 ジと同じものであり、 上述の製造方法によれば、 この搭載基板を効率 よく製造することができる。 本発明を用いることで、 搭載基板の良否 選別を行った上で半導体装置 2 5の搭載ができる。 また、 金属支持体 1 1をスぺーサ 3 1 とすることで、 半導体パッケージ組み立て工数を 低減することができる。  This mounting board is the same as the semiconductor package according to the fifth embodiment of the present invention, and according to the above-described manufacturing method, this mounting board can be manufactured efficiently. By using the present invention, the semiconductor device 25 can be mounted after the quality of the mounted substrate is determined. In addition, by using the spacer 31 as the metal support 11, the number of semiconductor package assembling steps can be reduced.
次に、 本発明に係る半導体装置搭載基板及び半導体パッケージの搭 載基板の検查法について説明する。 図 2 4 ( a ) から （ c ) は、 本発 明の第 1 0の実施の形態に係る搭載基板の検査法の例を示す部分断面 図である。  Next, a method for detecting a semiconductor device mounting substrate and a semiconductor package mounting substrate according to the present invention will be described. FIGS. 24 (a) to 24 (c) are partial cross-sectional views showing an example of the mounting board inspection method according to the tenth embodiment of the present invention.
図 2 4 ( a ) は、 金属支持体 1 1 と突起 2 4を除去する前の搭載基 板の形態で行われる。 図 2 4 ( a ) では本発明の第 1の実施の形態 （図 9 ( d ) の形態） を用いているが、 第 2の実施の形態、 第 3の実施の 形態、 第 4の実施の形態、 第 5の実施の形態、 第 6の実施の形態、 第 7の実施の形態、 第 8の実施の形態により形成された搭載基板を用い てもよい。  FIG. 24 (a) is performed in the form of a mounting board before removing the metal support 11 and the protrusion 24. In FIG. 24 (a), the first embodiment of the present invention (the embodiment of FIG. 9 (d)) is used, but the second, third, and fourth embodiments of the present invention are used. The mounting substrate formed according to the embodiment, the fifth embodiment, the sixth embodiment, the seventh embodiment, and the eighth embodiment may be used.
この検査により、 搭載基板の回路のオープン検査 （導通不良） がで きる。 回路のショート検査は、 画像認識測定装置などによりパターン 検索を行って各層ごとに調べておく。 もしくは、 金属支持体 1 1 と突 起 2 4を除去した後に搭載基板の回路のショート検查を行ってもよい。 本方法を用いることで、 本発明の第 9の実施の形態で用いる搭載基板 の良否選別を行った上で半導体装置 2 5を搭載できる。 This inspection enables an open inspection (continuity failure) of the circuit on the mounting board. For short-circuit inspection of a circuit, a pattern search is performed using an image recognition measurement device or the like to check for each layer. Alternatively, after the metal support 11 and the protrusion 24 are removed, a short circuit detection of the circuit of the mounting board may be performed. By using this method, the semiconductor device 25 can be mounted after the quality of the mounting substrate used in the ninth embodiment of the present invention is determined.
図 2 4 ( b ) は、 金属支持体 1 1を選択除去し、 突起 2 4は除去し ていない状態で、 第 2電極パターン 1 7と突起 2 4を用いて搭載基板 の回路のオープン、 ショート両検査を行う。 図 2 4 ( b ) では本発明 の第 1の実施の形態 （図 9 ( e ) の形態） を用いているが、 第 2の実 施の形態、第 3の実施の形態、第 4の実施の形態、第 5の実施の形態、 第 6の実施の形態、 第 7の実施の形態、 第 8の実施の形態により形成 された搭載基板を用いてもよい。 本発明を用いることで、 第 1電極パ ターン 1 3に検査による傷を付けることなく 良否選別を行うことがで き、 本発明の第 1 0の実施の形態の図 2 3の搭載方法での接続安定性 を実現できる。  Fig. 24 (b) shows a state in which the metal support 11 is selectively removed and the protrusions 24 are not removed, and the circuit of the mounting board is opened and shorted using the second electrode patterns 17 and the protrusions 24. Perform both tests. Although FIG. 24 (b) uses the first embodiment of the present invention (the embodiment of FIG. 9 (e)), the second embodiment, the third embodiment, and the fourth embodiment The mounting substrate formed according to the embodiment, the fifth embodiment, the sixth embodiment, the seventh embodiment, and the eighth embodiment may be used. By using the present invention, it is possible to perform pass / fail sorting without damaging the first electrode pattern 13 by inspection, and the mounting method of the tenth embodiment of the present invention in FIG. Connection stability can be achieved.
図 2 4 ( c ) は、 金属支持体 1 1を検査する突起 2 4と触れない様 に開口部を形成し、 その開口部内の突起 2 4と第 2電極パターン 1 Ί により搭載基板の回路のオープン、ショ一ト両検査を行う。図 2 4 ( b ) では本発明の第 1の実施の形態 （図 9 ( d ) の形態からの開口部を形 成） を用いているが、 第 2の実施の形態、 第 3の実施の形態、 第 4の 実施の形態、 第 5の実施の形態、 第 6の実施の形態、 第 7の実施の形 態、 第 8の実施の形態により形成された搭載基板を用いてもよい。 本 方法を用いることで、 本発明の第 9の実施の形態で用いる搭載基板の 良否選別が電気的に完全に行うことができ、 金属支持体 1 1のほとん どが残っているため第 9の実施の形態で示した搭載信頼性は維持され た状態で行える。 産業上の利用可能性  In FIG. 24 (c), an opening is formed so as not to touch the protrusion 24 for inspecting the metal support 11, and the protrusion 24 in the opening and the second electrode pattern 1Ί form the circuit of the mounting board. Perform both open and short inspections. Although FIG. 24 (b) uses the first embodiment of the present invention (forming an opening from the embodiment of FIG. 9 (d)), the second embodiment and the third embodiment The mounting substrate formed according to the embodiment, the fourth embodiment, the fifth embodiment, the sixth embodiment, the seventh embodiment, and the eighth embodiment may be used. By using this method, the quality of the mounting substrate used in the ninth embodiment of the present invention can be electrically and completely selected, and almost all of the metal support 11 remains. The mounting reliability described in the embodiment can be maintained. Industrial applicability
以上説明したように本発明によれば、 半導体デバイスの端子の増加 や狭ピッチ化に対応した搭載基板の高密度化、微細配線化を実現でき、 かつ、 システムの小型化、 高密度化に対応し外部電極も狭ピッチ化し た搭載基板の実現することができる。 さらに、 本発明により実装信頼性に優れた搭載基板を提供すること ができ、 高性能かつ信頼性に優れた半導体パッケージを実現できる。 As described above, according to the present invention, it is possible to realize a high density and fine wiring of a mounting substrate corresponding to an increase in the number of terminals and a narrow pitch of a semiconductor device, and to correspond to a miniaturization and a high density of a system. In addition, it is possible to realize a mounting substrate in which external electrodes have a narrow pitch. Further, the present invention can provide a mounting substrate having excellent mounting reliability, and can realize a semiconductor package having high performance and excellent reliability.

Claims

請求の範囲 The scope of the claims
1 . 交互に積層された絶縁層と配線層からなる配線構造膜と、 電極のパターンが前記配線構造膜の片面に設けられ、 該電極パター ン側面周囲が前記絶縁層に接し、 かつ、 少なく とも前記電極パターン 下面が前記絶縁層に接することなく設けられ、 前記絶縁層面と電極パ タ一ン下面が同一平面上にある第 1電極パターンと、 1. A wiring structure film including an insulating layer and a wiring layer alternately laminated, and an electrode pattern are provided on one surface of the wiring structure film, and the periphery of the electrode pattern side surface is in contact with the insulating layer, and at least. A first electrode pattern in which the lower surface of the electrode pattern is provided without being in contact with the insulating layer, and the lower surface of the electrode pattern and the lower surface of the electrode pattern are on the same plane;
前記第 1電極パターンの反対側の面に形成された第 2電極パターン と、  A second electrode pattern formed on a surface opposite to the first electrode pattern;
前記第 1電極パターンの下部に位置する開口パターンを設けた絶縁 体膜と、  An insulating film provided with an opening pattern located below the first electrode pattern;
前記絶縁体膜下表面に設けられた金属支持体と  A metal support provided on the lower surface of the insulator film;
を有することを特徴とする半導体装置搭載基板。  A semiconductor device mounting substrate, comprising:
2 . 前記配線層の各層は、 前記絶縁曆内に設けられた第 1のビ ァを介して互いに接続され、  2. Each layer of the wiring layer is connected to each other via a first via provided in the insulating layer,
前記第 2電極パターンは、 前記配線層及び前記第 1のビアを介して 前記第 1電極パターンに接続されていることを特徴とする請求項 1 に 記載の半導体装置搭載基板。  The substrate according to claim 1, wherein the second electrode pattern is connected to the first electrode pattern via the wiring layer and the first via.
3 . 前記第 1電極パターンの間及び周囲に導体パターンが設け られ、  3. A conductor pattern is provided between and around the first electrode pattern,
該導体パターンは前記配線層と前記第 1のビアにより接続されてい ることを特徴とする請求項 1 または 2に記載の半導体装置搭載基板。  3. The semiconductor device mounting board according to claim 1, wherein the conductor pattern is connected to the wiring layer by the first via.
4 . 前記金属支持体と前記導体パタ一ンが前記絶縁体膜に形成 された第 2のビアにより接続されていることを特徴とする請求項 1か ら 3のいずれか一つに記載の半導体装置搭載基板。  4. The semiconductor according to any one of claims 1 to 3, wherein the metal support and the conductor pattern are connected by a second via formed in the insulator film. Equipment mounting board.
5 . 前記絶縁層は、膜強度が 7 O M P a以上、破断伸び率が 5 % 以上、 ガラス転移温度が 1 5 0 °C以上、 熱膨張係数が 6 0 p p mZ°C 以下の絶縁材料からなることを特徴とする請求項 1〜 4のいずれか一 つに記載の半導体装置搭載基板。 5. The insulating layer is made of an insulating material having a film strength of 7 OMPa or more, a breaking elongation of 5% or more, a glass transition temperature of 150 ° C or more, and a thermal expansion coefficient of 60 pp mZ ° C or less. The semiconductor device mounting substrate according to claim 1, wherein:
6 . 前記絶縁層は、 弾性率が 1 0 G P a以上、 熱膨張係数が 3 0 p p mZ°C以下、 ガラス転移温度が 1 5 0 °C以上の絶縁材料からな ることを特徴とする請求項 1 〜 4のいずれか一つに記載の半導体装置 搭載基板。 6. The insulating layer is made of an insulating material having an elastic modulus of 10 GPa or more, a thermal expansion coefficient of 30 ppmZ ° C or less, and a glass transition temperature of 150 ° C or more. Item 5. The semiconductor device mounting substrate according to any one of Items 1 to 4.
7 . 前記絶縁体膜は、 ソルダーレジス ト としての機能を有する ことを特徴とする請求項 1 〜 6のいずれか一つに記載の半導体装置搭 載基板。  7. The semiconductor device mounting substrate according to claim 1, wherein the insulator film has a function as a solder resist.
8 . 前記絶縁体膜が、 前記絶縁層と同一の材料からなることを 特徴とする請求項 1 〜 7のいずれか一つに記載の半導体装置搭載基板。  8. The semiconductor device mounting substrate according to claim 1, wherein the insulator film is made of the same material as the insulating layer.
9 . 前記第 1電極パターンの上面に形成された誘電体層と、 該 誘電体層の上面に前記配線構造膜と導通している導電体層とからなる コンデンサが設けられていることを特徴とする請求項 1 ~ 8のいずれ か一つに記載の半導体装置搭載基板。  9. A capacitor comprising a dielectric layer formed on the upper surface of the first electrode pattern and a conductor layer electrically connected to the wiring structure film is provided on the upper surface of the dielectric layer. The semiconductor device mounting substrate according to claim 1, wherein
1 0 . 前記金属支持体は、 ステン レス、 鉄、 ニッケル、 銅およ ぴアルミニゥムからなる群から選択された少なく とも 1種の金属又は その合金からなることを特徴とする請求項 1 〜 9のいずれか一つに記 載の半導体装置搭載基板。  10. The metal support according to claim 1, wherein the metal support is made of at least one metal selected from the group consisting of stainless steel, iron, nickel, copper and aluminum or an alloy thereof. The semiconductor device mounting board described in any one of the above.
1 1 . 前記金属支持体は、 前記絶縁体膜表面が露出するように 前記絶縁体膜の下面に設けられていることを特徴とする請求項 1 〜 1 0のいずれか一つに記載の半導体装置搭載基板。  11. The semiconductor according to any one of claims 1 to 10, wherein the metal support is provided on a lower surface of the insulator film such that a surface of the insulator film is exposed. Equipment mounting board.
1 2 . 前記金属支持体は、前記絶縁体膜の下面全体に設けられ、 かつ前記第 1電極パターンと接している突起を有していることを特徴 とする請求項 1〜 1 0のいずれか一つに記載の半導体装置搭載基板。  12. The metal support is provided on the entire lower surface of the insulator film and has a projection in contact with the first electrode pattern. A semiconductor device mounting board according to one of the above aspects.
1 3 . 前記導体パターンと前記金属支持体が、 前記突起により 接続されていることを特徴とする請求項 1 ~ 1 2のいずれか一つに記 載の半導体装置搭載基板。  13. The semiconductor device mounting board according to any one of claims 1 to 12, wherein the conductor pattern and the metal support are connected by the protrusion.
1 4 . 前記突起は、 めっき法、 エッチング、 導電性ペース ト、 機械加工のいずれかの 1つもしくは複合した方法により形成されるこ とを特徴とする請求項 1 2または 1 3に記載の半導体装置搭載基板。 ' 14. The semiconductor according to claim 12, wherein the protrusion is formed by one or a combination of plating, etching, conductive paste, and machining. Equipment mounting board. '
1 5 . 請求項 1〜 1 4のいずれか一つに記載の半導体装置搭載 基板に少なく とも 1つ以上の半導体装置が搭載されたことを特徴とす る半導体パッケージ。 15. A semiconductor package, wherein at least one semiconductor device is mounted on the semiconductor device mounting substrate according to any one of claims 1 to 14.
1 6 . 少なく とも一面に半導体装置が搭載されたことを特徴と する請求項 1 5に記載の半導体パッケージ。  16. The semiconductor package according to claim 15, wherein a semiconductor device is mounted on at least one surface.
1 7 . 前記半導体装置が、 低融点金属又は導電性樹脂のいずれ かの材料によりフリ ップチップ接続されていることを特徴とする請求 項 1 5または 1 6に記載の半導体パッケージ。  17. The semiconductor package according to claim 15 or 16, wherein the semiconductor device is flip-chip connected with either a low-melting-point metal or a conductive resin.
1 8 . 前記半導体装置が、 低融点金属、 有機樹脂又は金属混入 樹脂からなる群から選択された少なく とも 1種の材料により連結され ていることを特徴とする請求項 1 5または 1 6に記載の半導体パッケ ージ。  18. The semiconductor device according to claim 15, wherein the semiconductor devices are connected by at least one material selected from the group consisting of a low melting point metal, an organic resin, and a metal-containing resin. Semiconductor package.
1 9 . 金属支持体の表面の所望の位置に複数個の突起を形成す る工程と、  19. forming a plurality of protrusions at desired positions on the surface of the metal support;
前記金属支持体表面の前記突起形成領域を除く領域に絶縁体膜を形 成する工程と、  Forming an insulator film in a region of the metal support surface other than the protrusion formation region;
前記絶縁体膜上に第 1電極パターンを形成する工程と、  Forming a first electrode pattern on the insulator film,
該第 1電極パターンの側面周囲に接し、 かつ下面が前記第 1電極パ ターン下面と同一平面上になるように絶縁層を形成する工程と、 第 1電極パターンの片面に配線層を形成する工程と、  Forming an insulating layer in contact with the periphery of the side surface of the first electrode pattern so that the lower surface is flush with the lower surface of the first electrode pattern; and forming a wiring layer on one surface of the first electrode pattern. When,
前記第 1電極パターンの反対側の面に第 2電極パターンを形成する 工程と、  Forming a second electrode pattern on a surface opposite to the first electrode pattern;
前記金属支持体に前記絶縁体膜と前記突起が露出するように第 1の 開口部を形成する工程と、  Forming a first opening in the metal support so that the insulator film and the protrusion are exposed;
前記突起を除去して、 前記第 1電極パターンが露出するように第 2 の開口部を前記絶縁体膜に形成する工程と、  Removing the protrusion and forming a second opening in the insulator film so that the first electrode pattern is exposed;
前記絶縁体膜の開口部形状を整える工程  Step of adjusting the shape of the opening of the insulator film
を含むことを特徴とする半導体装置搭載基板の製造方法。  A method for manufacturing a semiconductor device mounting substrate, comprising:
2 0 . 金属支持体の表面の所望の位置に複数個の突起を形成す る工程と、 20. Form a plurality of protrusions at desired positions on the surface of the metal support Process,
前記金属支持体表面の前記突起形成領域を除く領域に絶縁体膜を形 成する工程と、  Forming an insulator film in a region of the metal support surface other than the protrusion formation region;
前記絶縁体膜上に第 1電極パターンを形成する工程と、  Forming a first electrode pattern on the insulator film,
前記第 1電極パターンの間及び周囲に導体パターンを形成する工程 と、  Forming a conductor pattern between and around the first electrode pattern;
該第 1電極パターンの側面周囲に接し、 かつ下面が前記第 1電極パ タ一ン下面と同一平面上になるように絶縁層を形成する工程と、 前記第 1電極パターンの片面に配線層を形成する工程と、 前記第 1電極パターンの反対側の面に第 2電極パターンを形成する 工程と、  Forming an insulating layer in contact with the periphery of the side surface of the first electrode pattern and making the lower surface flush with the lower surface of the first electrode pattern; and forming a wiring layer on one surface of the first electrode pattern. Forming; forming a second electrode pattern on a surface opposite to the first electrode pattern;
前記金属支持体に前記絶縁体膜と前記突起が露出するように第 1の 開口部を形成する工程と、  Forming a first opening in the metal support so that the insulator film and the protrusion are exposed;
前記突起を除去して、 前記第 1電極パターンが露出するように第 2 の開口部を前記絶縁体膜に形成する工程と、  Removing the protrusion and forming a second opening in the insulator film so that the first electrode pattern is exposed;
前記絶縁体膜の開口部形状を整える工程  Step of adjusting the shape of the opening of the insulator film
を含むことを特徴とする半導体装置搭載基板の製造方法。  A method for manufacturing a semiconductor device mounting substrate, comprising:
2 1 . 金属支持体の表面の所望の位置に複数個の突起を形成す る工程と、  21. forming a plurality of protrusions at desired positions on the surface of the metal support;
前記金属支持体表面の前記突起形成領域を除く領域に絶縁体膜を形 成する工程と、  Forming an insulator film in a region of the metal support surface other than the protrusion formation region;
前記絶縁体膜上に第 1電極パターンを形成する工程と、  Forming a first electrode pattern on the insulator film,
前記金属支持体の一部が露出するようにビアを形成する工程と、 前記第 1電極パターンの間及び周囲に、 かつ導体パターンが前記ビ ァにより前記金属支持体と接続できるように前記導体パターンを形成 する工程と、  Forming a via so that a part of the metal support is exposed; and forming the conductive pattern between and around the first electrode pattern and so that the conductive pattern can be connected to the metal support by the via. Forming a
該第 1電極パターンの側面周囲に接し、 かつ下面が前記第 1電極パ ターン下面と同一平面上になるように絶縁層を形成する工程と、 + 前記第 1電極パターンの片面に配線層を形成する工程と、 前記第 1電極パターンの反対側の面に第 2電極パターンを形成する 工程と、 Forming an insulating layer so as to be in contact with the side surface of the first electrode pattern and the lower surface is flush with the lower surface of the first electrode pattern; and + forming a wiring layer on one surface of the first electrode pattern. The process of Forming a second electrode pattern on a surface opposite to the first electrode pattern;
前記金属支持体に前記絶縁体膜と前記突起が露出するように第 1の 開口部を形  A first opening is formed so that the insulator film and the protrusion are exposed on the metal support.
成する工程と、 The process of
前記突起を除去して、 前記第 1電極パターンが露出するように第 2 の開口部を前記絶縁体膜に形成する工程と、  Removing the protrusion and forming a second opening in the insulator film so that the first electrode pattern is exposed;
前記絶縁体膜の開口部形状を整える工程  Step of adjusting the shape of the opening of the insulator film
を含むことを特徴とする半導体装置搭載基板の製造方法。  A method for manufacturing a semiconductor device mounting substrate, comprising:
2 2 . 前記第 1電極パターンと前記導体パターンが同一の工程 で形成されることを特徴とする請求項 2 0または 2 1に記載の半導体 装置搭載基板の製造方法。  22. The method according to claim 20, wherein the first electrode pattern and the conductor pattern are formed in the same step.
2 3 . 前記第 1電極パターンを形成する工程と、 前記第 1電極 パターン上に配線層 （ 1 5 ) を形成する工程との間に、 少なく とも 1 個の前記第 1電極パターン上に薄膜コンデンサを形成する工程を有す ることを特徴とする請求項 1 9〜 2 2のいずれか一つに記載の半導体 装置搭載基板の製造方法。  23. Between the step of forming the first electrode pattern and the step of forming a wiring layer (15) on the first electrode pattern, a thin film capacitor is formed on at least one of the first electrode patterns. The method for manufacturing a semiconductor device mounting substrate according to any one of claims 19 to 22, comprising a step of forming a substrate.
2 4 . 前記第 1電極パターンを形成する工程の前に、 前記第 1 の開口部を形成する予定の領域に凹部を形成する工程を有することを 特徴とする請求項 1 9〜 2 3のいずれか一つに記載の半導体装置搭載 基板の製造方法。  24. The method according to claim 19, further comprising, before the step of forming the first electrode pattern, a step of forming a concave portion in a region where the first opening is to be formed. The method for manufacturing a semiconductor device-mounted substrate according to any one of the above,
2 5 . 金属支持体の両表面の所望の位置に複数個の突起を形成 する工程と、  25. forming a plurality of protrusions at desired positions on both surfaces of the metal support;
前記金属支持体両表面の前記突起形成領域を除く領域に絶縁体膜を 形成する工程と、  Forming an insulator film in a region excluding the protrusion formation region on both surfaces of the metal support;
第 1電極パターンの片面に配線層を形成する工程と、  Forming a wiring layer on one side of the first electrode pattern;
該第 1電極パターンの側面周囲に接し、 かつ下面が前記第 1電極パ ターン下面と同一平面上になるように絶縁層を形成する工程と、 前記絶縁体膜上に第 1電極パターンを形成する工程と、 前記第 1電極パターンの反対側の面に第 2電極パターンを形成する 工程と、 Forming an insulating layer in contact with the periphery of the side surface of the first electrode pattern and making the lower surface flush with the lower surface of the first electrode pattern; and forming the first electrode pattern on the insulator film. Process and Forming a second electrode pattern on a surface opposite to the first electrode pattern;
前記金属支持体を水平方向で半分に分割して第 1及び第 2の金属支 持体を形成する工程と、  Dividing the metal support in half in the horizontal direction to form first and second metal supports;
前記第 1及び前記第 2の金属支持体に前記各絶縁体膜と前記各突起 が露出するように第 1の開口部を形成する工程と、  Forming a first opening in the first and second metal supports so that the insulator films and the projections are exposed;
前記突起を除去して、 前記第 1電極パターンが露出するように第 2 の開口部を前記絶縁体膜に形成する工程と、  Removing the protrusion and forming a second opening in the insulator film so that the first electrode pattern is exposed;
前記絶縁体膜の開口部形状を整える工程  Step of adjusting the shape of the opening of the insulator film
を含むことを特徴とする半導体装置搭載基板の製造方法。  A method for manufacturing a semiconductor device mounting substrate, comprising:
2 6 . 金属支持体の両表面の所望の位置に複数個の突起を形成 する工程と、  26. forming a plurality of protrusions at desired positions on both surfaces of the metal support;
前記金属支持体両表面の前記突起形成領域を除く領域に絶縁体膜を 形成する工程と、  Forming an insulator film in a region excluding the protrusion formation region on both surfaces of the metal support;
前記絶縁体膜上に第 1電極パターンを形成する工程と、  Forming a first electrode pattern on the insulator film,
前記第 1電極パターンの間及び周囲に導体パターンを形成する工程 と、  Forming a conductor pattern between and around the first electrode pattern;
該第 1電極パターンの側面周囲に接し、 かつ下面が前記第 1電極パ タ一ン下面と同一平面上になるように絶縁層を形成する工程と、 前記第 1電極パターンの片面に配線層を形成する工程と、 前記第 1電極パターンの反対側の面に第 2電極パターンを形成する 工程と、  Forming an insulating layer in contact with the periphery of the side surface of the first electrode pattern and making the lower surface flush with the lower surface of the first electrode pattern; and forming a wiring layer on one surface of the first electrode pattern. Forming; forming a second electrode pattern on a surface opposite to the first electrode pattern;
前記金属支持体を水平方向で半分に分割して第 1及び第 2の金属支 持体を形成する工程と、  Dividing the metal support in half in the horizontal direction to form first and second metal supports;
前記第 1及び前記第 2の金属支持体に前記各絶縁体膜と前記各突起 が露出するように第 1の開口部を形成する工程と、  Forming a first opening in the first and second metal supports so that the insulator films and the projections are exposed;
前記突起を除去して、 前記第 1電極パターンが露出するように第 2 の開口部を前記絶縁体膜に形成する工程と、  Removing the protrusion and forming a second opening in the insulator film so that the first electrode pattern is exposed;
前記絶縁体膜の開口部形状を整える工程 を含むことを特徴とする半導体装置搭載基板の製造方法。 Step of adjusting the shape of the opening of the insulator film A method for manufacturing a semiconductor device mounting substrate, comprising:
2 7 . 金属支持体の両表面の所望の位置に複数個の突起を形成 する工程と、  27. forming a plurality of protrusions at desired positions on both surfaces of the metal support;
前記金属支持体両表面の前記突起形成領域を除く領域に絶縁体膜を 形成する工程と、  Forming an insulator film in a region excluding the protrusion formation region on both surfaces of the metal support;
前記絶縁体膜上に第 1電極パターンを形成する工程と、  Forming a first electrode pattern on the insulator film,
前記金属支持体の一部が露出するようにビアを形成する工程と、 前記第 1電極パターンの間及び周囲に、 かつ導体パターンが前記ビ ァにより前記金属支持体と接続できるように前記導体パターンを形成 する工程と、  Forming a via so that a part of the metal support is exposed; and forming the conductive pattern between and around the first electrode pattern and so that the conductive pattern can be connected to the metal support by the via. Forming a
該第 1電極パターンの側面周囲に接し、 かつ下面が前記第 1電極パ ターン下面と同一平面上になるように絶縁層を形成する工程と、 第 1電極パターンの片面に配線層を形成する工程と、  Forming an insulating layer in contact with the periphery of the side surface of the first electrode pattern so that the lower surface is flush with the lower surface of the first electrode pattern; and forming a wiring layer on one surface of the first electrode pattern. When,
前記第 1電極パターンの反対側の面に第 2電極パターンを形成する 工程と、  Forming a second electrode pattern on a surface opposite to the first electrode pattern;
前記金属支持体を水平方向で半分に分割して第 1及び第 2の金属支 持体を形成する工程と、  Dividing the metal support in half in the horizontal direction to form first and second metal supports;
前記第 1及び前記第 2の金属支持体に前記各絶縁体膜と前記各突起 が露出するように第 1の開口部を形成する工程と、  Forming a first opening in the first and second metal supports so that the insulator films and the projections are exposed;
前記突起を除去して、 前記第 1電極パターンが露出するように第 2 の開口部を前記絶縁体膜に形成する工程と、  Removing the protrusion and forming a second opening in the insulator film so that the first electrode pattern is exposed;
前記絶縁体膜の開口部形状を整える工程  Step of adjusting the shape of the opening of the insulator film
を含むことを特徴とする半導体装置搭載基板の製造方法。  A method for manufacturing a semiconductor device mounting substrate, comprising:
2 8 . 第 1及び第 2の金属支持体を 2枚張り合わせる工程と、 前記第 1及び前記第 2の金属支持体の表面の所望の位置に複数個の 突起を形成する工程と、  28. A step of laminating two first and second metal supports, and a step of forming a plurality of projections at desired positions on the surfaces of the first and second metal supports.
前記第 1及び前記第 2の金属支持体表面の前記突起形成領域を除く 領域に絶縁体膜を形成する工程と、  Forming an insulator film in a region excluding the protrusion formation region on the first and second metal support surfaces;
前記第 1及び前記第 2の金属支持体における前記各絶縁体膜上に第 1電極パターンを形成する工程と、 On the respective insulator films of the first and second metal supports, a second 1 forming an electrode pattern,
前記第 1及び前記第 2の金属支持体における前記各第 1電極パター ンの側面周囲に接し、 かつ下面が前記第 1電極パターン下面と同一平 面上になるように絶縁層を形成する工程と、  Forming an insulating layer in contact with a side surface of each of the first electrode patterns in the first and second metal supports, and a lower surface thereof is flush with a lower surface of the first electrode pattern; ,
前記第 1及び前記第 2の金属支持体における前記各第 1電極パター ンの片面に配線層を形成する工程と、  Forming a wiring layer on one surface of each of the first electrode patterns in the first and second metal supports;
前記第 1電極パターンの反対側の面に第 2電極パターンを形成する 工程と、  Forming a second electrode pattern on a surface opposite to the first electrode pattern;
前記第 1及び前記第 2の金属支持体を水平方向で半分に分割するェ 程と、  Splitting the first and second metal supports in half in the horizontal direction;
前記第 1及び前記第 2の金属支持体に前記各絶縁体膜と前記各突起 が露出するように第 1の開口部を形成する工程と、  Forming a first opening in the first and second metal supports so that the insulator films and the projections are exposed;
前記突起を除去して、 前記第 1電極パターンが露出するように第 2 の開口部を前記絶縁体膜に形成する工程と、  Removing the protrusion and forming a second opening in the insulator film so that the first electrode pattern is exposed;
前記絶縁体膜の開口部形状を整える工程  Step of adjusting the shape of the opening of the insulator film
を含むことを特徴とする半導体装置搭載基板の製造方法。  A method for manufacturing a semiconductor device mounting substrate, comprising:
2 9 . 第 1及び第 2の金属支持体を 2枚張り合わせる工程と、 前記第 1及び前記第 2の金属支持体の表面の所望の位置に複数個の 突起を形成する工程と、  29. A step of laminating two first and second metal supports, and a step of forming a plurality of projections at desired positions on the surfaces of the first and second metal supports.
前記第 1及び前記第 2の金属支持体表面の前記突起形成領域を除く 領域に絶縁体膜を形成する工程と、  Forming an insulator film in a region excluding the protrusion formation region on the first and second metal support surfaces;
前記第 1及び前記第 2の金属支持体における前記各絶縁体膜上に第 1電極パターンを形成する工程と、  Forming a first electrode pattern on each of the insulator films in the first and second metal supports;
前記第 1及び前記第 2の金属支持体における前記各第 1電極パター ンの間及び周囲に導体パターンを形成する工程と、  Forming a conductor pattern between and around each of the first electrode patterns on the first and second metal supports;
前記第 1及び前記第 2の金属支持体における前記各第 1電極パター ンの側面周囲に接し、 かつ下面が前記第 1電極パターン下面と同一平 面上になるように絶縁層を形成する工程と、  Forming an insulating layer in contact with a side surface of each of the first electrode patterns in the first and second metal supports, and a lower surface thereof is flush with a lower surface of the first electrode pattern; ,
前記第 1及び前記第 2の金属支持体における前記各第 1電極パター ンの片面に配線層を形成する工程と、 The first electrode patterns on the first and second metal supports; Forming a wiring layer on one side of the
前記第 1電極パターンの反対側の面に第 2電極パターンを形成する 工程と、  Forming a second electrode pattern on a surface opposite to the first electrode pattern;
前記第 1及び前記第 2の金属支持体を水平方向で半分に分割するェ 程と、  Splitting the first and second metal supports in half in the horizontal direction;
前記第 1及び前記第 2の金属支持体に前記各絶縁体膜と前記各突起 が露出するように第 1の開口部を形成する工程と、  Forming a first opening in the first and second metal supports so that the insulator films and the projections are exposed;
前記突起を除去して、 前記第 1電極パターンが露出するように第 2 の開口部を前記絶縁体膜に形成する工程と、  Removing the protrusion and forming a second opening in the insulator film so that the first electrode pattern is exposed;
前記絶縁体膜の開口部形状を整える工程  Step of adjusting the shape of the opening of the insulator film
を含むことを特徴とする半導体装置搭載基板の製造方法。  A method for manufacturing a semiconductor device mounting substrate, comprising:
3 0 . 第 1及び第 2の金属支持体を 2枚張り合わせる工程と、 前記第 1及び前記第 2の金属支持体の表面の所望の位置に複数個の 突起を形成する工程と、  30. A step of laminating two first and second metal supports, and a step of forming a plurality of projections at desired positions on the surfaces of the first and second metal supports.
前記第 1及び前記第 2の金属支持体両表面の前記突起形成領域を除 く領域に絶縁体膜を形成する工程と、  Forming an insulator film in a region excluding the protrusion formation region on both surfaces of the first and second metal supports;
前記第 1及び前記第 2の金属支持体における前記各絶縁体膜上に第 1電極パターンを形成する工程と、  Forming a first electrode pattern on each of the insulator films of the first and second metal supports;
前記第 1及び前記第 2の金属支持体の一部が露出するようにビアを 形成する工程と、  Forming a via so that a part of the first and second metal supports is exposed;
前記第 1及び前記第 2の金属支持体における前記各第 1電極パター ンの間及び周囲に、 かつ導体パターンが前記ビアにより前記金属支持 体と接続できるように前記導体パターンを形成する工程と、  Forming the conductor pattern between and around each of the first electrode patterns on the first and second metal supports so that the conductor pattern can be connected to the metal support by the vias;
前記第 1及び前記第 2の金属支持体における前記各第 1電極パター ンの側面周囲に接し、 かつ下面が前記各第 1電極パターン下面と同一 平面上になるように絶縁層を形成する工程と、  Forming an insulating layer in contact with a side surface of each of the first electrode patterns in the first and second metal supports, and having a lower surface flush with a lower surface of each of the first electrode patterns. ,
前記第 1及び前記第 2の金属支持体における前記各第 1電極パター ンの片面に配線層を形成する工程と、  Forming a wiring layer on one surface of each of the first electrode patterns in the first and second metal supports;
前記各第 1電極パターンの反対側の面に第 2電極パターンを形成す る工程と、 Forming a second electrode pattern on a surface opposite to the first electrode patterns; Process,
前記第 1及び前記第 2の金属支持体を水平方向で半分に分割するェ 程と、  Splitting the first and second metal supports in half in the horizontal direction;
前記第 1及び前記第 2の金属支持体に前記絶縁体膜と前記突起が露 出するように第 1の開口部を形成する工程と、  Forming a first opening in the first and second metal supports so that the insulator film and the protrusion are exposed;
前記突起を除去して、 前記第 1電極パターンが露出するように第 2 の開口部を前記絶縁体膜に形成する工程と、  Removing the protrusion and forming a second opening in the insulator film so that the first electrode pattern is exposed;
前記絶縁体膜の開口部形状を整える工程  Step of adjusting the shape of the opening of the insulator film
を含むことを特徴とする半導体装置搭載基板の製造方法。  A method for manufacturing a semiconductor device mounting substrate, comprising:
3 1 . 前記第 1及び前記第 2の金属支持体を張り合わせる工程 の前に、 前記第 1の開口部を形成する予定の領域に凹部を形成するェ 程を有することを特徴とする請求項 2 8 - 3 0のいずれか一つに記載 の半導体装置搭載基板の製造方法。  31. A step of forming a concave portion in a region where the first opening is to be formed before the step of bonding the first and second metal supports. 30. The method for manufacturing a semiconductor device mounting board according to any one of 28-30.
3 2 . 前記第 1電極パターンを形成する工程と、 前記第 1電極 パターン上に配線層を形成する工程との間に、 少なく とも 1個の前記 第 1電極パターン上に薄膜コンデンサを形成する工程を有することを 特徴とする請求項 2 5〜 3 1のいずれか一つに記載の半導体装置搭載 基板の製造方法。  32. A step of forming a thin-film capacitor on at least one of the first electrode patterns, between the step of forming the first electrode pattern and the step of forming a wiring layer on the first electrode pattern 31. The method of manufacturing a semiconductor device-mounted substrate according to claim 25, wherein the method comprises:
3 3 . 前記第 1電極パターンが前記第 2電極パターンの所望の 位置で接続するように半田ボール又は接続ピンを形成する工程を有す ることを特徴とする請求項 1 9〜 3 2のいずれか一つに記載の半導体 装置搭載基板の製造方法。  33. The method according to claim 19, further comprising the step of forming a solder ball or a connection pin so that the first electrode pattern is connected at a desired position of the second electrode pattern. The manufacturing method of a semiconductor device mounting board according to any one of the above.
3 4 . 前記金属支持体は、 ステンレス、 鉄、 ニッケル、 銅およ ぴアルミニゥムからなる群から選択された少なく とも 1種の金属又は その合金からなることを特徴とする請求項 1 9〜 3 3のいずれか一つ に記載の半導体装置搭載基板の製造方法。  34. The method according to claim 19, wherein the metal support is made of at least one metal selected from the group consisting of stainless steel, iron, nickel, copper and aluminum, or an alloy thereof. The method for manufacturing a semiconductor device mounting substrate according to any one of the above.
3 5 . 前記突起が、 めっき法、 エッチング、 導電性ペース ト、 機械加工のいずれかの 1つもしくは複合した方法により形成されるこ とを特徴とする請求項 1 9から 3 4のいずれかに記載の半導体装置搭 載基板の製造方法。 35. The method according to any one of claims 19 to 34, wherein the protrusion is formed by any one of plating method, etching, conductive paste, and machining, or a combined method. Semiconductor device described A method for manufacturing a mounting substrate.
3 6 . 請求項 1 9 ~ 3 5のいずれか 1項に記載の方法により製 造された半導体装置搭載基板の少なく とも 1面に、 半導体装置を接続 することを特徴とする半導体パッケージの製造方法。  36. A method of manufacturing a semiconductor package, comprising: connecting a semiconductor device to at least one surface of a semiconductor device mounting substrate manufactured by the method according to any one of claims 19 to 35. .
3 7 . 前記半導体装置が、 低融点金属又は導電性樹脂のいずれ かの材料にフリ ップチップ接続されていることを特徴とする請求項 3 37. The semiconductor device according to claim 3, wherein the semiconductor device is flip-chip connected to one of a low melting point metal and a conductive resin.
6に記載の半導体パッケージの製造方法。 7. The method for manufacturing a semiconductor package according to 6.
3 8 . 請求項 1 9〜 3 5のいずれか一つに記載の方法により製 造された半導体搭載基板の前記金属支持体上に第 2電極パターンを形 成し、 前記金属支持体を選択除去した後、 突起を除去せずに接触端子 として用いて導通検査を行うことを特徴とする半導体装置搭載基板の 検査方法。  38. A second electrode pattern is formed on the metal support of the semiconductor mounting substrate manufactured by the method according to any one of claims 19 to 35, and the metal support is selectively removed. A method for inspecting a semiconductor device mounting substrate, comprising: performing a continuity inspection after removing the protrusions without removing the protrusions and using the contact terminals.
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1703558A2 (en) * 2005-03-15 2006-09-20 Shinko Electric Industries Co., Ltd. Wiring board with embedded semiconductor chip, embedded reinforcing member and method of manufacturing the same
US11942424B2 (en) 2021-12-01 2024-03-26 International Business Machines Corporation Via patterning for integrated circuits

Families Citing this family (49)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102004009567B4 (en) * 2004-02-25 2007-01-04 Infineon Technologies Ag Wiring carrier for receiving chips
JP4549692B2 (en) * 2004-02-27 2010-09-22 日本特殊陶業株式会社 Wiring board manufacturing method
JP4549693B2 (en) * 2004-02-27 2010-09-22 日本特殊陶業株式会社 Wiring board manufacturing method
JP4597561B2 (en) * 2004-04-09 2010-12-15 日本特殊陶業株式会社 Wiring board and manufacturing method thereof
JP4108643B2 (en) 2004-05-12 2008-06-25 日本電気株式会社 Wiring board and semiconductor package using the same
JP4561193B2 (en) * 2004-06-14 2010-10-13 株式会社トッパンＮｅｃサーキットソリューションズ Printed wiring board and semiconductor device
JP4170266B2 (en) * 2004-07-02 2008-10-22 日本特殊陶業株式会社 Wiring board manufacturing method
JP3961537B2 (en) * 2004-07-07 2007-08-22 日本電気株式会社 Manufacturing method of semiconductor mounting wiring board and manufacturing method of semiconductor package
JP4016039B2 (en) * 2005-06-02 2007-12-05 新光電気工業株式会社 Wiring board and method for manufacturing wiring board
JP4334005B2 (en) * 2005-12-07 2009-09-16 新光電気工業株式会社 Wiring board manufacturing method and electronic component mounting structure manufacturing method
JP5259053B2 (en) * 2005-12-15 2013-08-07 パナソニック株式会社 Semiconductor device and inspection method of semiconductor device
JP2008091719A (en) * 2006-10-03 2008-04-17 Shinko Electric Ind Co Ltd Semiconductor device
DE102007034402B4 (en) 2006-12-14 2014-06-18 Advanpack Solutions Pte. Ltd. Semiconductor package and manufacturing method therefor
JP5324051B2 (en) * 2007-03-29 2013-10-23 新光電気工業株式会社 Wiring substrate manufacturing method, semiconductor device manufacturing method, and wiring substrate
US20080246152A1 (en) 2007-04-04 2008-10-09 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device with bonding pad
JP4635033B2 (en) * 2007-08-21 2011-02-16 新光電気工業株式会社 Wiring board manufacturing method and electronic component mounting structure manufacturing method
US8238114B2 (en) * 2007-09-20 2012-08-07 Ibiden Co., Ltd. Printed wiring board and method for manufacturing same
US7790503B2 (en) * 2007-12-18 2010-09-07 Stats Chippac, Ltd. Semiconductor device and method of forming integrated passive device module
US8263878B2 (en) 2008-03-25 2012-09-11 Ibiden Co., Ltd. Printed wiring board
JP5120342B2 (en) * 2009-06-18 2013-01-16 ソニー株式会社 Manufacturing method of semiconductor package
JP5462777B2 (en) * 2010-12-09 2014-04-02 日本特殊陶業株式会社 Manufacturing method of multilayer wiring board
TWI462201B (en) * 2011-03-04 2014-11-21 Adl Engineering Inc Semiconductor package structure and method for fabricating the same
JP2013033914A (en) * 2011-06-27 2013-02-14 Toshiba Corp Semiconductor device
CN102891131B (en) 2011-07-22 2017-07-14 先进封装技术私人有限公司 Semiconductor structure and its manufacture method for manufacturing semiconductor encapsulated element
TWI508241B (en) 2011-10-20 2015-11-11 先進封裝技術私人有限公司 Package carrier, pacakge carrier manufacturing method, package structure for semiconductor device and manufacturing method thereof
CN103137570B (en) * 2011-11-29 2016-02-10 先进封装技术私人有限公司 The manufacture method of board structure, semiconductor encapsulated element and board structure
TWI474444B (en) * 2011-12-28 2015-02-21 Princo Corp Package method of thin multi-layer substrate
TWI433621B (en) * 2011-12-28 2014-04-01 Princo Corp Package method of thin multi-layer substrate
TWI440412B (en) * 2011-12-28 2014-06-01 Princo Corp Package method of thin multi-layer substrate
JP2013168400A (en) * 2012-02-14 2013-08-29 Tokyo Electron Ltd Wiring board for semiconductor device inspection apparatus and manufacturing method therefor
KR20140047967A (en) * 2012-10-15 2014-04-23 삼성전기주식회사 Multi-layer type coreless substrate and method of manufacturing the same
CN104425431B (en) * 2013-09-03 2018-12-21 日月光半导体制造股份有限公司 Board structure, encapsulating structure and its manufacturing method
TWI549234B (en) * 2014-01-17 2016-09-11 矽品精密工業股份有限公司 Layer structure for contacting setting semiconductor device and manufacturing method thereof
US20150206812A1 (en) * 2014-01-23 2015-07-23 Qualcomm Incorporated Substrate and method of forming the same
KR102249660B1 (en) * 2014-08-14 2021-05-10 삼성전기주식회사 Printed circuit board and method of manufacturing the same
US10515884B2 (en) 2015-02-17 2019-12-24 Advanced Semiconductor Engineering, Inc. Substrate having a conductive structure within photo-sensitive resin
JP6485777B2 (en) * 2016-05-31 2019-03-20 大口マテリアル株式会社 Wiring member for multi-row type semiconductor device and manufacturing method thereof
JP6485776B2 (en) * 2016-05-31 2019-03-20 大口マテリアル株式会社 Wiring member for multi-row type semiconductor device and manufacturing method thereof
JP6930073B2 (en) * 2016-07-28 2021-09-01 凸版印刷株式会社 Wiring board laminate
US10002839B2 (en) * 2016-08-29 2018-06-19 Via Alliance Semiconductor Co., Ltd. Electronic structure, and electronic structure array
US9905519B1 (en) * 2016-08-29 2018-02-27 Via Alliance Semiconductor Co., Ltd. Electronic structure process
JP6735505B2 (en) * 2016-09-06 2020-08-05 パナソニックＩｐマネジメント株式会社 Printed wiring board, printed circuit board, prepreg
JP6693850B2 (en) * 2016-09-30 2020-05-13 新光電気工業株式会社 Wiring board with carrier base material and method for manufacturing wiring board with carrier base material
JP6793755B2 (en) * 2016-12-22 2020-12-02 三井金属鉱業株式会社 Manufacturing method of multi-layer wiring board
JP7007882B2 (en) 2017-12-08 2022-01-25 新光電気工業株式会社 Wiring board and its manufacturing method
TWI713424B (en) * 2018-10-15 2020-12-11 鼎展電子股份有限公司 Copper film with buried film resistor and printed circuit board having the same
TWI691041B (en) * 2019-01-29 2020-04-11 矽品精密工業股份有限公司 Electronic package and package substrate thereof and method for manufacturing same
CN111250184B (en) * 2020-02-20 2022-04-15 北京京东方传感技术有限公司 Micro-fluidic chip, working method thereof and metal ion detection device
CN115151018A (en) * 2021-03-31 2022-10-04 华为技术有限公司 Circuit board, preparation method thereof and communication equipment

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000261124A (en) * 1999-03-05 2000-09-22 Ngk Spark Plug Co Ltd Wiring board, core board including capacitor, core board main body, capacitor, manufacture of core board main body and manufacture of core board including capacitor
JP2001024090A (en) * 1999-07-08 2001-01-26 Ibiden Co Ltd Package substrate
WO2001048821A1 (en) * 1999-12-27 2001-07-05 Mitsubishi Denki Kabushiki Kaisha Integrated circuit
US20010013425A1 (en) * 1999-03-11 2001-08-16 Shinko Electric Industries Co., Ltd. Multilayered Substrate for Semiconductor Device
US20010020739A1 (en) * 2000-03-09 2001-09-13 Nec Corporation Flip chip type semiconductor device and method for manufacturing the same
JP2002026171A (en) * 2000-07-06 2002-01-25 Sumitomo Bakelite Co Ltd Method for producing multilayer wiring board and multilayer wiring board

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000261124A (en) * 1999-03-05 2000-09-22 Ngk Spark Plug Co Ltd Wiring board, core board including capacitor, core board main body, capacitor, manufacture of core board main body and manufacture of core board including capacitor
US20010013425A1 (en) * 1999-03-11 2001-08-16 Shinko Electric Industries Co., Ltd. Multilayered Substrate for Semiconductor Device
JP2001024090A (en) * 1999-07-08 2001-01-26 Ibiden Co Ltd Package substrate
WO2001048821A1 (en) * 1999-12-27 2001-07-05 Mitsubishi Denki Kabushiki Kaisha Integrated circuit
US20010020739A1 (en) * 2000-03-09 2001-09-13 Nec Corporation Flip chip type semiconductor device and method for manufacturing the same
JP2002026171A (en) * 2000-07-06 2002-01-25 Sumitomo Bakelite Co Ltd Method for producing multilayer wiring board and multilayer wiring board

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1703558A2 (en) * 2005-03-15 2006-09-20 Shinko Electric Industries Co., Ltd. Wiring board with embedded semiconductor chip, embedded reinforcing member and method of manufacturing the same
EP1703558A3 (en) * 2005-03-15 2010-01-20 Shinko Electric Industries Co., Ltd. Wiring board with embedded semiconductor chip, embedded reinforcing member and method of manufacturing the same
US7884484B2 (en) 2005-03-15 2011-02-08 Shinko Electric Industries Co., Ltd. Wiring board and method of manufacturing the same
US11942424B2 (en) 2021-12-01 2024-03-26 International Business Machines Corporation Via patterning for integrated circuits

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