CN115151018A

CN115151018A - Circuit board, preparation method thereof and communication equipment

Info

Publication number: CN115151018A
Application number: CN202110351200.1A
Authority: CN
Inventors: 杨东成; 李飒; 高峰; 郭文韬; 谢二堂
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2021-03-31
Filing date: 2021-03-31
Publication date: 2022-10-04
Also published as: WO2022206526A1

Abstract

The application provides a circuit board, a preparation method thereof and communication equipment. The first layer structure comprises a first medium layer, a first circuit layer and a second circuit layer, wherein the first medium layer is provided with a first setting surface, the first circuit layer is arranged on the first setting surface, and the second circuit layer is embedded in the first medium layer. The thickness of the first circuit layer is greater than the thickness of the second circuit layer. The second layer structure includes a second dielectric layer into which the first circuit layer is pressed. In the technical scheme, the two circuit layers with different thicknesses are arranged in the first layer structure, wherein the first circuit layer can have a heat dissipation function, and the second circuit layer can be used as a fine circuit, so that a local thick copper and fine circuit common layer is obtained in the circuit board, the through-flow and heat dissipation performance of the circuit board is improved, and the thickness of the circuit board is reduced.

Description

Circuit board, preparation method thereof and communication equipment

Technical Field

The application relates to the technical field of circuit boards, in particular to a circuit board, a manufacturing method thereof and communication equipment.

Background

With the popularization of ICT application technologies such as AR/VR, 5G and cloud computing, the chip technology is from 14nm to 5nm, the density and power of devices are rapidly increased, the dissipation power of microelectronic elements is increased more and more, the packaging size is reduced more and more, and higher requirements on board-level heat dissipation, through flow and density of digital communication, servers and energy circuit boards are provided. The board level heat dissipation path of a conventional circuit board is shown in fig. 1, and dissipates through the copper layer vias, molding material, and board material at the periphery of the chip or device.

Thermal performance greatly occupies space for layout and wiring, and the copper blocks and the thick copper layers are high-cost materials. By adopting the technical scheme of a thick copper layer or an embedded copper block, the integration density of the product is required to be reduced due to high through-flow and high heat dissipation, the layer number and the plate thickness of the circuit board are increased, the manufacturing cost of the product is increased, and the technical route meets the bottleneck.

Disclosure of Invention

The application provides a circuit board, a preparation method thereof and communication equipment, which are used for improving the safety of the circuit board when the circuit board is plugged with an opposite terminal circuit board.

In a first aspect, a circuit board is provided, which includes a plurality of stacked layer structures, including a first layer structure and a second layer structure adjacent to each other. The first layer structure comprises a first medium layer used for bearing a circuit, the first medium layer is provided with a first setting surface, the first layer structure further comprises a first circuit layer arranged on the first setting surface, and a second circuit layer embedded in the first medium layer. In the first circuit layer and the second circuit layer, the thickness of the first circuit layer is greater than that of the second circuit layer, and the circuit density of the second circuit layer is greater than that of the first circuit layer. The second layer structure comprises a second dielectric layer into which the first circuit layer is pressed. In the technical scheme, the two circuit layers with different thicknesses are arranged in the first layer structure, wherein the first circuit layer can have a heat dissipation function, and the second circuit layer can be used as a fine circuit, so that a local thick copper and fine circuit common layer is obtained in the circuit board, the through-flow and heat dissipation performance of the circuit board is improved, and the thickness of the circuit board is reduced.

In a specific embodiment, the second circuit layer is located on a side of the first dielectric layer close to the first mounting surface. The preparation of the circuit board is convenient.

In a specific embodiment, the second circuit layer is embedded in a region corresponding to the line gap of the first circuit layer. The isolation between the first circuit layer and the second circuit layer is improved.

In a specific embodiment, the first dielectric layer further has a second mounting surface facing away from the first mounting surface; the second setting surface is provided with a third circuit layer. The pair of lines is arranged on two sides of the first dielectric layer through the first circuit layer and the third circuit layer, so that the deformation of the first layer structure after being heated is balanced.

In a specific embodiment, the ratio of the copper coating rate of the first circuit layer to the copper coating rate of the third circuit layer is between 80% and 120%. The pair of lines is arranged on two sides of the first dielectric layer through the first circuit layer and the third circuit layer, so that the deformation of the first layer structure after being heated is balanced.

In a specific embodiment, the plurality of layer structures further includes a third layer structure including a third dielectric layer, and the third circuit layer is pressed into the third dielectric layer.

In a specific possible embodiment, the circuit layers in the multiple layer structure are connected by vias.

In a specific embodiment, the second dielectric layer has a third mounting surface facing away from the first mounting surface, and the second layer structure further includes a fourth circuit layer disposed on the third mounting surface.

In a specific embodiment, the number of the first layer structures is at least two, and at least one second layer structure is arranged between adjacent first layer structures.

In a second aspect, a method for manufacturing a circuit board is provided, the method comprising the steps of:

preparing a first copper layer;

preparing an isolation layer on the first copper layer, and preparing a second circuit layer on the isolation layer;

forming a first dielectric layer; the first dielectric layer wraps the second circuit layer;

etching the first copper layer and forming a first circuit layer; the second circuit layer is partially exposed on the first setting surface; the part of the second circuit layer exposed on the first setting surface is electrically isolated from the first circuit layer;

and preparing a second dielectric layer, and pressing the first circuit layer into the second dielectric layer.

In the technical scheme, the two circuit layers with different thicknesses are arranged in the first layer structure, wherein the first circuit layer can have a heat dissipation function, and the second circuit layer can be used as a fine circuit, so that a local thick copper and fine circuit common layer is obtained in the circuit board, the through-flow and heat dissipation performance of the circuit board is improved, and the thickness of the circuit board is reduced.

In a specific embodiment, the preparing a separation layer on the first copper layer and preparing a second circuit layer on the separation layer are specifically:

preparing an etching layer on the first copper layer;

etching the etching layer to form an etching pattern corresponding to the second circuit layer;

preparing an isolation layer in the etching pattern;

and filling copper metal in the etching pattern to form a second circuit layer.

preparing a second copper layer on the isolation layer;

preparing an etching layer corresponding to the second circuit layer on the second copper layer;

and etching the second copper layer according to the etching pattern to form a second circuit layer.

In a specific embodiment, the preparation method further comprises:

and arranging a third circuit layer on one surface of the first dielectric layer, which is far away from the second dielectric layer.

In a specific embodiment, the ratio of the copper-covering rate of the first circuit layer to the copper-covering rate of the third circuit layer is between 80% and 120%.

In a third aspect, a communication device is provided, which includes a circuit board and a chip disposed on the circuit board, wherein the circuit board is any one of the circuit boards described above. In the technical scheme, the two circuit layers with different thicknesses are arranged in the first layer structure, wherein the first circuit layer can have a heat dissipation function, and the second circuit layer can be used as a fine circuit, so that a local thick copper and fine circuit common layer is obtained in the circuit board, the through-flow and heat dissipation performance of the circuit board is improved, and the thickness of the circuit board is reduced.

Drawings

FIG. 1 is a schematic diagram of a prior art circuit board;

fig. 2 is a schematic structural diagram of a circuit board according to an embodiment of the present disclosure;

FIG. 3 is a schematic diagram of a first layer structure provided by an embodiment of the present application;

fig. 4 is a schematic diagram of a first layer structure, a second layer structure and a third layer structure provided in an embodiment of the present application;

fig. 5 to 15 are flow charts of manufacturing a circuit board according to an embodiment of the present application;

fig. 16 to 27 are another flow chart of manufacturing a circuit board according to an embodiment of the present application;

FIG. 28 is a diagram illustrating a circuit board according to the prior art;

fig. 29 is a schematic structural diagram of a circuit board according to an embodiment of the present application.

Detailed Description

The circuit board provided by the embodiment of the application can be applied to digital communication equipment, servers and energy equipment and is used for bearing the circuit board in the equipment, and along with popularization of ICT application technologies such as AR/VR, 5G and cloud computing, the device density and power of the chip are increased rapidly, the dissipation power of a microelectronic element is increased more and more, the packaging size is reduced more and more, and therefore the heat dissipation requirement on the circuit board is increased more and more. As shown in fig. 1, a circuit board in the prior art includes a multi-layer structure, in which a circuit layer 3 is included. When connected to the chip 2, the chip 2 is connected to the circuit layer 3 of the circuit board 1. The heat generated by the chip 2 is conducted away through the circuit layer 33 of the circuit board (the direction of heat transfer is represented by the arrows shown in fig. 1) to achieve heat dissipation from the chip 2.

In order to improve the heat dissipation efficiency of the circuit board in the prior art, a thick copper layer and an embedded copper block are often formed in an inner layer of the circuit board, and if the thick copper layer or the embedded copper block is added in a layer structure inside the circuit board shown in fig. 1, the heat transfer performance of the circuit board is improved, but the added thick copper layer or the embedded copper block greatly occupies the space for layout and wiring, and the copper block and the thick copper layer are both high-cost materials, so that the cost of the circuit board is greatly improved. Therefore, the embodiment of the application provides a circuit board for improving the heat dissipation efficiency of the circuit board and increasing the integration density of the circuit board. The circuit board structure provided by the embodiment of the present application is described in detail below with reference to the specific drawings.

Referring to fig. 2, fig. 2 shows a schematic layer structure diagram of a circuit board provided in an embodiment of the present application. The circuit board includes a plurality of layer structures arranged in a first direction, which is a thickness direction of the circuit board. The layer structure of the circuit board includes a circuit layer and a dielectric layer carrying the circuit layer, the circuit layer is represented by black bars in fig. 2, and the dielectric layer is represented by other layers filled with patterns. It should be understood that, when a plurality of layer structures are stacked, circuit layers between adjacent layer structures are isolated, circuit layers of different layers may be connected through via holes, and a specific connection manner of the via holes may be designed according to an actual function of the circuit board, and is not specifically limited in the embodiment of the present application.

In the using process of the circuit board, besides the circuit needs to be carried, the circuit board also needs to be used as a heat dissipation channel of the chip. In order to improve the heat dissipation effect of the circuit board, the first layer structure 10 is disposed on the circuit board provided in the embodiment of the present application, and the first layer structure 10 is used for bearing a main heat dissipation function of the circuit board.

With continued reference to fig. 2, the number of the first layer structures 10 may be one, two or more (three or more), and the like, and when there are at least two first layer structures 10, at least one second layer structure 20 is spaced between the adjacent first layer structures 10. As shown in fig. 2, the number of the first layer structures 10 is two, and one second layer structure 20 is spaced between two first layer structures 10.

It should be understood that the first layer structure 10 provided by the embodiment of the present application may be any layer structure in a circuit board. In fig. 2, a schematic diagram of the first layer structure 10 as a layer structure inside the circuit board is illustrated, but in the embodiment of the present application, the position of the first layer structure 10 is not specifically limited. The first layer structure 10 may be a layer structure inside the circuit board or a layer structure on the surface of the circuit board. When the first layer structure 10 is located inside the circuit board, the circuit board further comprises a second layer structure 20 and a third layer structure 30 adjacent thereto. Of course, when the first layer structure 10 is located in a surface layer structure of a circuit board, the circuit board may further comprise a second layer structure 20 or a third layer structure 30 adjacent to the first layer structure 10.

Referring to fig. 3, a schematic of the structure of the first layer structure 10 is shown in fig. 3. The first layer structure 10 comprises a first dielectric layer 11. The first dielectric layer 11 has a first mounting surface 111 and a second mounting surface 112, and the second mounting surface 112 is away from the first mounting surface 111. With reference to the structure shown in fig. 2, the first installation surface 111 is a surface facing the second layer structure 20, and when the first layer structure 10 is connected to the second layer structure 20, the first installation surface 111 is used for connecting to the second layer structure 20. The second installation surface 112 is a surface facing the third layer structure 30, and when the first layer structure 10 is connected to the third layer structure 30, the second installation surface 112 is used for connection to the third layer structure 30.

The first layer structure 10 includes a first circuit layer 12 and a second circuit layer 13 in addition to the first dielectric layer 11. The first circuit layer 12 and the second circuit layer 13 are carried by the first dielectric layer 11. Specifically, the first circuit layer 12 is disposed on the first mounting surface 111 and exposed outside the first dielectric layer 11. When the first layer structure 10 is adjacent to the second layer structure 20, the first circuit layer 12 is pressed into the second layer structure.

As an alternative, the first circuit layer 12 has a highly planar surface to provide better uniformity of the pressing of the first circuit layer 12 into the second layer structure.

The second circuit layer 13 is embedded in the first dielectric layer 11, and the second circuit layer 13 is exemplarily located on one side of the first dielectric layer 11 close to the first arrangement surface 111. Referring to the structure shown in fig. 2, the second circuit layer 13 and the first circuit layer 12 are separated by the first mounting surface 111, the first circuit layer 12 is located outside the first dielectric layer 11, and the second circuit layer 13 is located inside the first dielectric layer 11. In addition, a portion of the second circuit layer 13 is exposed on the first mounting surface 111, and a portion of the second circuit layer 13 exposed on the first mounting surface 111 is electrically isolated from the first circuit layer 12.

As an alternative, fig. 2 illustrates a case where the first circuit layer 12 and the second circuit layer 13 do not overlap at all. For convenience of description, the area corresponding to the first circuit layer 12 is named as a first area, and the area corresponding to the second circuit layer 13 is a second area. The first region and the second region do not overlap at all, and the second circuit layer 13 may be understood to be buried in a region corresponding to a line gap of the first circuit layer 12.

When the first circuit layer 12 and the second circuit layer 13 are provided, the first circuit layer 12 and the second circuit layer 13 satisfy: the thickness of the first circuit layer 12 is greater than the thickness of the second circuit layer 13. Illustratively, the thickness of the first circuit layer 12 is between 2-3oz, such as the thickness of the first circuit layer 12 is different from 2oz, 2.5oz, 3oz, etc.; the thickness of the second circuit layer 13 is 0.1 to 1oz, for example, the thickness of the second circuit layer 13 is different from 0.1oz, 0.5oz, 1oz, etc.

Because the thickness of the first circuit layer 12 is relatively large, the first circuit layer 12 cannot be etched to form a circuit pattern with a relatively high circuit density, and thus the first circuit layer 12 can only be used for preparing a circuit pattern with a relatively low circuit density, for example, the first circuit layer 12 can implement a circuit with a line width of 4 mils, for example, the line width of the circuit in the first circuit layer 12 may be different widths such as 4 mils, 4.5 mils, 5 mils, and the like. In addition, because the thickness of the first circuit layer 12 is relatively large, the first circuit layer 12 can be used as a main heat dissipation structure of the circuit board, and devices (such as chips) arranged on the circuit board can dissipate heat through the first circuit layer 12, so that a copper block does not need to be additionally embedded in the circuit board to be used as the heat dissipation structure.

The thickness of the second circuit layer 13 is small, and the second circuit layer 13 can be etched to form a circuit pattern with a high circuit density, so that the second circuit layer 13 can be prepared to form a relatively fine circuit, and exemplarily, the second circuit layer 13 can realize a high-fine circuit with a line width of more than or equal to 1 mil. For example, the line width of the second circuit layer 13 may be 1mil, 1.5mil, 2mil, or other different thicknesses.

It can be seen from the above structure that, when the first layer structure 10 is adopted, a structure with a common layer of local thick copper (the first circuit layer 12) and fine lines (the second circuit layer 13) is realized through the first circuit layer 12 and the second circuit layer 13, so that the through-current and heat dissipation performance of the circuit board can be improved, and the thickness of the circuit board can be reduced.

As an optional solution, the first layer structure 10 further includes a third circuit layer 14, and the third circuit layer 14 is disposed on the second disposition surface 112. When the first circuit layer 12 and the third circuit layer 14 are provided, the first circuit layer 12 and the third circuit layer 14 are arranged on both sides of the first dielectric layer 11 in a quasi-symmetric manner. The third circuit layer 14 also carries the heat dissipation effect of a portion of the circuit board. At the time of production, the copper-covering ratio (ratio of copper covered per unit area) of the first circuit layer 12 and the copper-covering ratio of the third circuit layer 14 may be approximately equal. When the circuit board expands due to heat, the first circuit layer 12 and the third circuit layer 14 have the same expansion coefficient, so that the first dielectric layer 11 is prevented from warping after being heated, and the stress generated is reduced.

Illustratively, the ratio of the copper coating rate of the first circuit layer 12 to the copper coating rate of the third circuit layer 14 is 80% to 120%. If the ratio of the copper-clad ratio of the first circuit layer 12 to the copper-clad ratio of the third circuit board is: 80%, 90%, 100%, 110%, 120%, etc.

In addition, the thickness of the third circuit layer 14 is approximately equal to the thickness of the first circuit layer 12, and the ratio of the thickness of the third circuit layer to the thickness of the first circuit layer is also between 80% and 120%. If the ratio of the thickness of the first circuit layer 12 to the thickness of the third circuit layer is: 80%, 90%, 100%, 110%, 120%, etc.

In the above embodiment, two thick copper layers (the first circuit layer 12 and the third circuit layer 14) are provided in the first layer structure 10, and therefore, the heat dissipation effect of the circuit board can be improved by the first circuit layer 12 and the third circuit layer 14.

Referring to fig. 4, fig. 4 shows a schematic structural view in which the first layer structure 10, the second layer structure 20, and the third layer structure 30 are stacked. When the first layer structure 10, the second layer structure 20 and the third layer structure 30 are stacked, the first dielectric layer 11 of the first layer structure 10, the second dielectric layer 21 of the second layer structure 20 and the third dielectric layer 31 of the third layer structure 30 are stacked and connected. The first circuit layer 12 is pressed into the second dielectric layer 21, and the third circuit layer 14 is pressed into the third dielectric layer 31. So that the first circuit layer 12 and the second circuit layer 13 do not occupy an extra thickness of the circuit board.

In addition, the second dielectric layer 21 has a third mounting surface (not labeled) away from the first mounting surface 111, and the second layer structure 20 further includes a fourth circuit layer 22 disposed on the third mounting surface. The third dielectric layer 31 has a fourth mounting surface (not labeled) facing away from the second mounting surface, and the third layer structure 30 further includes a fifth circuit layer 32 disposed on the fourth mounting surface. And circuit layers are respectively arranged on the second layer structure 20 and the third layer structure 30, so that the density of the circuit layers in the circuit board is improved.

In order to facilitate understanding of the circuit board provided in the embodiments of the present application, the circuit board provided in the embodiments of the present application is described below with reference to a specific manufacturing method.

The preparation method of the circuit board provided by the embodiment of the application comprises the following steps:

step 001: a first copper layer is prepared.

Referring to fig. 5, 1-2oz or more copper foil, peelable glue 200 (a releasable adhesive material), and rigid support substrate 100 are pressed together to hold the thick copper foil flat. The rigid supporting substrate 100 is coated with a peelable adhesive 200, and the copper foil is adhesively connected to the supporting substrate 100 through the peelable adhesive 200. Wherein the copper foil is used as a first copper layer 300, and the first copper layer 300 is used for preparing and forming a first circuit layer in the subsequent steps. The thickness of the first copper layer 300 needs to meet the thickness requirements of the first circuit layer.

It should be understood that the peelable glue 200 described above is not limited to a material, and only the following conditions need to be satisfied: 1) During the first lamination press, the first copper layer 300 may be bonded to the rigid support substrate 100; 2) After the first layer structure is prepared, the rigid support substrate 100 may be peeled from the first copper layer 300 before the first layer structure and the second layer structure are laminated (the first circuit layer is pressed into the second dielectric layer). Illustratively, the peelable glue 200 may be a glue made from a release material.

The rigid support substrate 100 is not limited to a material, and only the rigid support substrate 100 needs to satisfy the following condition: 1) The rigid support substrate 100 is bonded with the peelable glue 200 to fix the first copper layer 300, so that the rigid support requirement on the first copper layer 300 is met; 2) The temperature and pressure conditions of the first pressing (pressing the second circuit layer into the first medium layer) are met; 3) The first copper layer 300 can be peeled off along with the peelable glue 200 before the first layer structure and the second layer structure are laminated (the first circuit layer is pressed into the second dielectric layer). Illustratively, the material of the rigid support substrate 100 may be resin, rubber, or the like.

Step 002: preparing an isolation layer on the first copper layer, and preparing a second circuit layer on the isolation layer;

the method specifically comprises the following steps:

a) As shown in fig. 6, an etch layer 400 is prepared on the first copper layer 300. That is, a dry film or photoresist material is attached to the exposed side of the first copper layer 300 (the side of the first copper layer 300 away from the rigid support substrate 100), and the dry film or photoresist material is used as the etching layer 400.

b) The etch layer 400 is etched to form etch patterns 401 corresponding to the second circuit layer. The etching may be prepared by dry etching or wet etching, and is not specifically limited in the embodiment of the present application. It should be understood that fig. 6 shows a cross-sectional view of the circuit board, and thus only two notches are illustrated in fig. 6, but the etched pattern 401 formed in the embodiment of the present application matches the formed circuit pattern, and the second circuit layer may be formed according to the formed etched pattern 401. It is understood that the above-described etched pattern 401 can realize a high-definition line having a line width of 1mil or more. For example, the line widths of the patterns formed by etching are different widths such as 1mil, 1.5mil, 2mil, 2.5mil, and the like.

c) As shown in fig. 7, an isolation layer 500 is prepared within the etch pattern 401. Electroplating is performed in the pattern of dry film or photoresist material, first electroplating a protective layer of metal to isolate the first copper layer 300 from the second circuit layer 13 to be fabricated. The passivation metal is an isolation layer 500 that isolates the first copper layer 300 from the second circuit layer 13. The isolation layer 500 may be made of various conductive metals, such as tin, aluminum, and other common metals.

The isolation layer 500 formed by electroplating is not limited to materials and processes, and only needs to satisfy a function that it can be formed in the formed etching pattern 401, and can be conductive so that the first circuit layer is formed by electroplating, can cover the first circuit layer during the etching of the first copper layer 300, and prevents the first circuit layer from being etched. In addition, the material of the isolation layer 500 is required to be removable in a certain manner.

d) Copper metal is filled in the etching pattern 401 to form the second circuit layer 13.

With continued reference to fig. 7, the second circuit layer 13 is formed within the fill layer by way of electroplating, wherein an electroplated copper layer is formed on the isolation layer 500 to prevent the second circuit layer 13 from sticking to the first copper layer 300.

Step 003: forming a first dielectric layer; and the first dielectric layer wraps the second circuit layer.

Referring to fig. 8, after the second circuit layer 13 is formed, the etching layer (dry film or photoresist material) is stripped, and the formed second circuit layer 13 is laminated with the first copper layer 300 and located on the side of the first copper layer 300 away from the rigid support substrate.

Referring to fig. 9, a prepreg material is covered on the surface of the first copper layer 300 (the surface facing away from the rigid support substrate), and the prepreg material is a material for preparing the first dielectric layer 11, and only needs to meet the requirement that the prepreg material can be bonded with the first copper layer 300 under certain temperature and pressure conditions, and can be applied to the embodiment of the present application, for example, the prepreg material may be resin or other materials capable of preparing a structural layer of a circuit board. When the prepreg material covers the first copper layer 300, the second circuit layer 13 and the isolation layer 500 carrying the second circuit layer 13 are pressed into the prepreg material, and when the prepreg material forms the first dielectric layer 11, the second circuit layer 13 can be buried in the first dielectric layer 11.

As shown in fig. 10, as an optional scheme, the preparation method further includes forming a second copper layer 600 on the prepreg material, where the second copper layer 600 is used for forming a third circuit of the first layer structure. The thickness of the second copper layer 600 is the same or approximately the same as the thickness of the first copper layer 300.

Step 004: etching the first copper layer and forming a first circuit layer; the second circuit layer is partially exposed on the first setting surface; the part of the second circuit layer exposed on the first setting surface is electrically isolated from the first circuit layer.

Referring to fig. 11, the peelable glue 200 and the rigid support substrate 100 are peeled away from the first copper layer 300, exposing the other side copper face of the first copper layer 300.

Referring to fig. 12 and 13, an etching layer 700 (a dry film or a photoresist material) is attached on a surface of the first copper layer 300, and an etching pattern corresponding to the first circuit layer 12 is formed on the etching layer 700. The first copper layer 300 is etched to pattern the first circuit layer 12.

As an alternative, when the first layer structure includes the second copper layer 600, the etching layer 800 is also formed on the second copper layer 600, and then the third circuit layer 14 is formed according to the pattern of the etching layer 800, which is not described herein again.

Referring to fig. 14, the surface of the etch layer 700 and the etch layer 800 (dry film or photoresist material) are removed.

Referring to fig. 15, the isolation layer on the surface of the second circuit layer 13 is removed to obtain an inner layer board or a daughter board of the circuit board with the thick copper (the first circuit layer 12 and the third circuit layer 14) on the outer side of the same layer and the fine lines (the second circuit layer 13) on the inner side of the substrate.

Step 005: and laminating the first structure layer and the rest layer structures, and performing high-temperature press fit to form the multilayer circuit board.

Specifically, the method comprises preparing a second dielectric layer, and pressing the first circuit layer into the second dielectric layer. And preparing a third dielectric layer, and pressing the third circuit layer into the third dielectric layer.

The same procedure was used to prepare the remaining layer structure to form the circuit board shown in fig. 2.

The embodiment of the application also provides another preparation method of the circuit board, and the specific preparation method comprises the following steps:

step 010: a first copper layer is prepared.

Referring to fig. 16, a thick copper foil is held flat by pressing together 1-2oz or more copper foil, peelable glue 200 (a releasable adhesive material), and rigid support substrate 100. The supporting substrate 100 is coated with a peelable adhesive 200, and the copper foil is adhesively connected to the supporting substrate 100 through the peelable adhesive 200. Wherein the copper foil is used as a first copper layer 300, and the first copper layer 300 is used for preparing and forming a first circuit layer in the subsequent steps. The thickness of the first copper layer 300 needs to meet the thickness requirements of the first circuit layer.

It should be understood that the peelable glue 200 described above is not limited to a material, and only the following conditions need to be satisfied: 1) During the first lamination process, a first copper layer 300 may be bonded to the rigid support substrate 100; 2) After the first layer structure is prepared, the rigid support substrate 100 may be peeled from the first copper layer 300 before the first layer structure and the second layer structure are laminated (the first circuit layer is pressed into the second dielectric layer). Illustratively, the peelable glue 200 may be a glue made from a release material.

The rigid support substrate 100 is not limited to a material, and only the rigid support substrate 100 needs to satisfy the following condition: 1) The rigid support substrate 100 is bonded with the peelable glue 200 to fix the first copper layer 300, so that the rigid support requirement on the first copper layer 300 is met; 2) The temperature and pressure conditions of the first pressing (pressing the second circuit layer into the first medium layer) are met; 3) The first copper layer 300 can be stripped along with the peelable glue 200 before the first layer structure and the second layer structure are laminated (the first circuit layer is pressed into the second dielectric layer). Illustratively, the material of the rigid support substrate 100 may be resin, rubber, or the like.

Step 020: preparing an isolation layer on the first copper layer, and preparing a second circuit layer on the isolation layer;

referring to fig. 17, the above steps include the steps of:

a) As shown in fig. 17, an isolation layer 510 is prepared on the first copper layer 200. That is, a layer of isolation layer 510 is formed by electroplating on the exposed side of the first copper layer 200 (the side of the first copper layer 200 away from the rigid support substrate 100), and the isolation layer 510 formed by electroplating is not limited to materials and processes, and only needs to be formed in the formed etching pattern, and be conductive so that the first circuit layer is formed by electroplating, and the first circuit layer can be covered in the etching process of the first copper layer 200, so that the first circuit layer is prevented from being etched. In addition, the material of the isolation layer 510 should be removed in a certain manner. The isolation layer 510 may be made of various conductive metals, such as tin, aluminum, and other common metals.

b) As shown in fig. 18, a second copper layer 610 is formed on the isolation layer 510. Specifically, a second copper layer 610 is formed directly on the isolation layer 510, and the second copper layer 610 is used to form a second circuit layer of the first layer structure. In a specific manufacturing process, the second copper layer 610 can be directly formed on the isolation layer 510 by electroplating.

c) An etch layer 710 corresponding to the second circuit layer is prepared on the second copper layer 610.

As shown in fig. 19, an etch layer 710 (dry film or etch material) is prepared on the second copper layer 610. The etch layer 710 is used to pattern the second circuit layer, to block portions of the second copper layer 610 that do not require etching.

Referring to fig. 20, the etching layer 710 is etched to form a pattern corresponding to the second circuit layer, which is not specifically limited in this embodiment. It should be understood that fig. 16 is a cross-sectional view of the circuit board, and thus fig. 16 illustrates only two bumps formed by etching, where the bumps block the second copper layer 610, that is, the portion of the second copper layer 610 that needs to be left. It should be understood that the etch pattern formed in the embodiments of the present application matches the circuit pattern formed, and the second circuit layer may be formed according to the formed etch pattern. The etching pattern can realize a high-precision line with the line width of more than or equal to 1 mil. For example, the line widths of the patterns formed by etching are different widths such as 1mil, 1.5mil, 2mil, 2.5mil, and the like.

d) The second copper layer is etched according to the etching pattern to form a second circuit layer 13.

As shown in fig. 21, the second copper layer is etched, and since a part of the second copper layer is blocked by the etching pattern, the copper layer under the etching pattern is remained to form the second circuit layer 13.

Step 030: forming a first dielectric layer; and the first dielectric layer wraps the second circuit layer.

Referring to fig. 22, after the second circuit layer 13 is formed, the etching layer (dry film or photoresist material) is stripped, and the formed second circuit layer 13 is laminated with the first copper layer 300 and located on a side of the first copper layer 300 away from the rigid support substrate 100.

Referring to fig. 23, the isolation layer located outside the second circuit layer is etched, leaving only the portion of the isolation layer located below the second circuit layer 13. After the isolation layer is etched, the first copper layer 300 is exposed.

Referring to fig. 24, a prepreg material is covered on the surface of the first copper layer 300 (the surface facing away from the rigid support substrate), and the prepreg material is a material for preparing the first dielectric layer 11, and only needs to meet the requirement that the prepreg material can be bonded with the first copper layer 300 under certain temperature and pressure conditions, and can be applied to the embodiment of the present application, for example, the prepreg material may be resin or other materials capable of preparing a structural layer of a circuit board. When the prepreg material covers the first copper layer 300, the second circuit layer 13 and the isolation layer carrying the second circuit layer 13 are pressed into the prepreg material, and when the prepreg material forms the first dielectric layer 11, the second circuit layer 13 can be buried in the first dielectric layer 11.

As an optional scheme, the preparation method further includes forming a third copper layer 810 on the prepreg material, where the third copper layer 810 is used for forming a third circuit of the first layer structure. The thickness of the third copper layer 810 is the same or approximately the same as the thickness of the first copper layer 300.

Step 040: etching the first copper layer and forming a first circuit layer; the second circuit layer is partially exposed on the first setting surface; the part of the second circuit layer exposed on the first setting surface is electrically isolated from the first circuit layer.

Referring to fig. 25, the peelable glue and rigid support substrate are stripped from the first copper layer 300, exposing the other copper side of the first copper layer 300. Referring to fig. 26, an etching layer 910 (dry film or photoresist material) is attached to the surface of the first copper layer 300, and an etching pattern corresponding to the first circuit layer is formed on the dry film or photoresist. The first copper layer 300 is etched to form a pattern of a first circuit layer. When the first layer structure includes the third copper layer 810, the number of the etching layers 910 is two, and the third circuit layer is also formed by covering the first copper layer 300 and the third copper layer 810 respectively and forming the first circuit layer, which is not described herein again.

The surface dry film photoresist material is removed, and then the isolation layer on the surface of the second circuit layer is removed, so as to form the circuit board inner layer board or sub-board with the outer thick copper (the first circuit layer 12 and the third circuit layer 14) and the inner thin circuit (the second circuit layer 12) on the substrate as shown in fig. 27.

Step 050: and preparing a second dielectric layer, and pressing the first circuit layer into the second dielectric layer.

And laminating the first structure layer and the rest layer structures, and performing high-temperature press fit to form the multilayer circuit board.

Specifically, the method comprises the steps of preparing a second dielectric layer, and pressing the first circuit layer into the second dielectric layer. And preparing a third dielectric layer, and pressing the third circuit layer into the third dielectric layer.

The same procedure was used to prepare the remaining layer structure to form the circuit board shown in fig. 23.

It can be seen from the above method that, in the circuit board provided in the embodiment of the present application, the thick copper foil may be fixed by using a peelable adhesive (a detachable adhesive material), a circuit layer is formed on a surface layer of the thick copper foil in a pattern electroplating manner, a prepreg (for forming a first dielectric layer) is placed on a line surface, the line surface is embedded in the prepreg in a high-temperature pressing manner, the peelable adhesive is removed, a copper surface on one side of the exposed thick copper is reduced and etched to form a thick copper surface pattern, a single-layer circuit board in which the thick copper pattern and the circuit layer are simultaneously distributed on two sides of the same layer is formed, and a multi-layer circuit board having a local thick copper + fine circuit common layer is obtained by pressing a plurality of single-layer or double-layer circuit boards on the prepreg in a stacked manner. The thick copper patterns (the first circuit layer and the third circuit layer) of the first layer structure are distributed on the outer side of the first medium layer of the first layer structure, and the functions of high through current and high heat dissipation are achieved. The circuit pattern (second circuit layer) of the first layer structure is embedded in the inner side of the first dielectric layer of the circuit board, and the circuit pattern has the functions of high-speed signals and high-density interconnection. Therefore, the high-flow and high-heat-dissipation effects are realized, and the formed first layer structure does not occupy the whole area or large-area layout and wiring space and has the characteristic of high integration. In addition, because the first circuit layer and the third circuit layer are adopted for heat dissipation, the circuit board does not need to realize whole-surface thick copper or local thick copper by means of high-cost materials such as copper blocks, thick copper layers, male and female copper core plates and the like, the circuit processing capacity of the circuit board can reach the level of a chip carrier level, and therefore the carrier level circuit capacity of 20/20 microns can be achieved, and compared with the traditional circuit board, the circuit capacity of the circuit board is improved by 4 times.

In order to facilitate understanding of effects brought by the circuit board provided by the embodiment of the application, the circuit board is compared with a circuit board in the prior art. Referring to fig. 28 and 29, fig. 28 is a schematic structural diagram of a circuit board in the prior art, and fig. 29 is a schematic structural diagram of a circuit board provided in an embodiment of the present application.

Referring to fig. 28, it can be seen from fig. 28 that the circuit board in the prior art has eight layers, and the eight-layer structure is named as a first layer 101, a second layer 102, a third layer 103, a fourth layer 104, a fifth layer 105, a sixth layer 106, a seventh layer 107, and an eighth layer 108 for convenience of description. The fifth layer 105 is an embedded copper block formed for heat dissipation.

Referring to fig. 29, it can be seen from fig. 29 that the circuit board provided in the embodiment of the present application has seven layers, namely, a first layer 111, a second layer 112, a third layer 113, a fourth layer 114, a fifth layer 115, a sixth layer 116, and a seventh layer 117. Wherein the second layer 112 and the sixth layer 116 are the first layer structure shown in fig. 2 described above.

As can be seen from comparison between fig. 28 and fig. 29, in the embodiment of the present application, there is no need to separately provide an embedded copper block as a structure for improving heat dissipation of the circuit board. The thick copper layers (first circuit layer) of the second layer 112 and the sixth layer 116 are arranged to take the heat dissipation function of the circuit board. In addition, comparing fig. 28 and 29, in the embodiment of the present application, a smaller number of layers and a smaller board thickness than those of the related art can be employed, but a better wiring density can be obtained.

It should be understood that the first layer structure provided in the embodiment of the present application can be applied to other circuit board structures besides the application shown in fig. 29, for example, the first layer structure can also be used in combination with any technical solutions, such as circuit board technologies of embedded copper blocks, cavities, mixed voltage, etc., the number of layers is not limited, and a complex circuit board structure with a multi-thickness copper distribution can be formed.

The embodiment of the application further provides communication equipment which can be ICT related equipment such as AR/VR, 5G and cloud computing. The communication device comprises a circuit board and a chip arranged on the circuit board, wherein the circuit board is any one of the circuit boards. In the technical scheme, the two circuit layers with different thicknesses are arranged in the first layer structure, wherein the first circuit layer can have a heat dissipation function, and the second circuit layer can be used as a fine circuit, so that a local thick copper and fine circuit common layer is obtained in the circuit board, the through-flow and heat dissipation performance of the circuit board is improved, and the thickness of the circuit board is reduced.

It will be apparent to those skilled in the art that various changes and modifications may be made in the present application without departing from the spirit and scope of the application. Thus, if such modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is intended to include such modifications and variations as well.

Claims

1. A circuit board, comprising: a plurality of stacked layer structures; wherein the plurality of layer structures comprise adjacent first layer structures and second layer structures:

the first layer structure comprises a first medium layer, and the first medium layer is provided with a first setting surface; the first layer structure further comprises a first circuit layer arranged on the first arrangement surface and a second circuit layer embedded in the first medium layer; wherein the thickness of the first circuit layer is greater than the thickness of the second circuit layer, and the circuit density of the second circuit layer is greater than the circuit density of the first circuit layer;

the second layer structure comprises a second dielectric layer, and the first circuit layer is pressed into the second dielectric layer.

2. The circuit board of claim 1, wherein the second circuit layer is located on a side of the first dielectric layer adjacent to the first mounting surface.

3. The circuit board according to claim 1 or 2, wherein the second circuit layer is buried in a region corresponding to the line gap of the first circuit layer.

4. The circuit board according to any one of claims 1 to 3, wherein the first dielectric layer further has a second setting surface facing away from the first setting surface; the second setting surface is provided with a third circuit layer.

5. The circuit board of claim 4, wherein a ratio of a copper covering rate of the first circuit layer to a copper covering rate of the third circuit layer is 80% to 120%.

6. The circuit board of claim 4 or 5, wherein the plurality of layer structures further comprises a third layer structure comprising a third dielectric layer, the third circuit layer being pressed into the third dielectric layer.

7. The circuit board of any one of claims 1-6, wherein the second dielectric layer has a third mounting surface facing away from the first mounting surface, and the second layer structure further comprises a fourth circuit layer disposed on the third mounting surface.

8. The circuit board according to any one of claims 1 to 7, wherein the number of the first layer structures is at least two, and at least one of the second layer structures is spaced between adjacent first layer structures.

9. A method for manufacturing a circuit board, comprising the steps of:

preparing a first copper layer;

10. The method for manufacturing a circuit board according to claim 9,

preparing an isolation layer on the first copper layer, and preparing a second circuit layer on the isolation layer, specifically:

preparing an etching layer on the first copper layer;

preparing an isolation layer in the etching pattern;

and filling copper metal in the etching pattern to form a second circuit layer.

11. The method for producing a circuit board according to claim 9,

preparing a second copper layer on the isolation layer;

12. The method for producing a circuit board according to claim 10 or 11, further comprising:

13. The method of manufacturing a circuit board according to claim 12, wherein a ratio of a copper-clad ratio of the first circuit layer to a copper-clad ratio of the third circuit layer is 80% to 120%.

14. A communication apparatus comprising a circuit board and a chip disposed on the circuit board, wherein the circuit board is the circuit board according to any one of claims 1 to 8.