JP2008071905A - Multilayer wiring substrate and semiconductor device, and production method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To achieve highly reliable junction with a semiconductor chip by improving elastic modulus in a coreless multilayer wiring substrate and to integrally form a capacitor. <P>SOLUTION: A multilayer wiring substrate has a resin laminate which consists of lamination of a plurality of build-up resin layers which support a wiring pattern each and have a via plug connected to the wiring pattern. In an upper surface and a lower surface of the resin laminate, first and second ceramic layers whose elastic modulus is larger than the elastic modulus of the build-up layer are formed, respectively. At least one of the first and second ceramic layers forms a capacitor integrated with the multilayer wiring substrate on the multilayer wiring substrate. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention generally relates to a semiconductor device, and more particularly to a resin material, a multilayer wiring board using the resin material, and a semiconductor device using the multilayer wiring board.

  In today's high-performance semiconductor devices, a resin multilayer substrate is used as a package substrate carrying a semiconductor chip. On the other hand, in recent high-performance semiconductor devices, intense heat is generated in the semiconductor chip, and the semiconductor chip has a larger elastic modulus than that of the resin substrate. Therefore, the resin multilayer substrate carrying the semiconductor chip is caused by thermal stress. Warping is likely to occur. Therefore, when such a semiconductor device is mounted on a circuit board via a solder bump or the like, a large stress is applied to the bump as the semiconductor chip generates heat, and the semiconductor chip and the package substrate or the circuit board between the package substrate and the circuit board. The problem arises that the electrical and mechanical joints are broken or damaged.

  Therefore, in order to suppress such warpage of the package substrate, a resin multilayer substrate having a high elastic modulus in which a core layer reinforced with a glass cloth is disposed at the center of the resin multilayer substrate constituting the package substrate has been conventionally used. Yes.

  On the other hand, in a package substrate having such a thick core layer, the thickness of the substrate increases, the inductance of a signal path such as a via plug formed in the substrate increases, and the transmission speed of an electric signal decreases. Occurs.

Therefore, conventionally, efforts have been made to realize an ultrathin resin multilayer substrate having a thickness of 500 μm or less except for the core layer in the resin multilayer substrate.
JP 2001-168228 A JP 2000-340895 A JP 2001-127389 A

  FIG. 1 shows an example of a multilayer wiring board 11 having a conventional core.

Referring to FIG. 1, a core portion 11C in which core layers 11C ₁ and 11C ₂ having a thickness of 40 to 60 μm in which a glass cloth 11G is impregnated with a resin is laminated is provided at the center of the multilayer wiring board 11. In addition, build-up insulating films 11A and 11B having a wiring pattern 12 are formed on the core portion 11C. Also, build-up insulating films 11D and 11E having wiring patterns 12D and 12E are formed under the core portion 11C.

  Further, a through via 12C that penetrates the core portion 11C and connects the wiring layer 12A and the wiring layer 12D is formed.

  Solder resist films 13A and 13B are formed on the outermost buildup insulating films 11B and 11E, respectively. In the solder resist film 13A, an electrode pad 14A and in the solder resist film 13B, respectively. The electrode pad 14B is formed.

  The semiconductor chip 15 is mounted face down on the multilayer wiring board 11 formed in this way, and the electrode bumps 16 of the semiconductor chip 15 are bonded to the corresponding electrode pads 14A. An underfill resin layer 17 is filled between the semiconductor chip 15 and the solder resist film 13A.

  On the back side of the multilayer wiring board 11, solder bumps 18 are formed on the electrode pads 14B in order to mount a semiconductor device comprising the semiconductor chip 15 and the multilayer wiring board 11 on a circuit board.

However, in the multilayer wiring board 11 having such a core portion 11C, the total thickness of the board including the core layers 11C ₁ and 11C ₂ may exceed 500 μm. In such a case, the through via Since the length of the signal path formed by 12C from the electrode pad 14B to the corresponding electrode pad 14A still exceeds 500 μm, the signal transmitted through the long signal path is delayed by the influence of the inductance.

  On the other hand, it is conceivable to remove the core portion 11C as shown in FIG. 2 and reduce the thickness of the multilayer wiring board. However, in a so-called coreless resin board that does not include such a core, the elastic modulus is, for example, the core. The value of 20 GPa when the portion 11C is provided is reduced to about 10 GPa or less, so that the warp or deformation of the substrate described above becomes a serious problem. However, in FIG. 2, the same reference numerals are given to the parts described above, and the description thereof is omitted.

  When the multilayer wiring board carrying the semiconductor chip is warped in this way, a large stress is applied to the joint between the multilayer wiring board and the circuit board on which the semiconductor device having the multilayer wiring board is mounted. The problem of being destroyed or damaged arises.

  In the conventional coreless substrate, in order to suppress such warpage of the substrate, a reinforcing member (stiffener) 10L is provided along the outer peripheral portion. However, even if such a reinforcing member is provided, the warping is performed. Is suppressed only in the outer peripheral portion, and warping or deformation cannot be sufficiently suppressed in most regions of the substrate.

  Further, in a semiconductor device in which a semiconductor chip is mounted on such a multilayer wiring board, a decoupling capacitor made of a ceramic capacitor is provided between a power line and a ground pattern to suppress unnecessary electromagnetic radiation. Since heat treatment at a high temperature is required, it is conventionally formed as a separate body from the multilayer wiring board and mounted on the multilayer wiring board by, for example, a flip chip method. However, in such a configuration, even if the thickness of the multilayer wiring substrate is reduced by using the folded coreless resin substrate, the effect is offset. In addition, when such an external decoupling capacitor is used, it is necessary to provide wiring for that purpose, but the problem of unnecessary radiation of electromagnetic waves from such wiring cannot be avoided.

  According to one aspect, the present invention is a multilayer wiring board provided with a resin laminate comprising a plurality of build-up resin layers each carrying a wiring pattern and further having a via plug connected to the wiring pattern. Further, first and second ceramic layers having an elastic modulus larger than the elastic modulus of the buildup layer are formed on the upper surface and the lower surface of the resin laminate, respectively. At least one of the ceramic layers forms a capacitor integrated on the multilayer wiring board on the multilayer wiring board. The multilayer wiring board is provided.

  According to another aspect, the present invention provides a method for manufacturing a multilayer wiring board comprising a resin laminate comprising a plurality of build-up resin layers each carrying a wiring pattern and having via plugs connected to the wiring pattern. The first and second ceramic layers having an elastic modulus larger than the elastic modulus of the buildup layer are formed on the upper and lower surfaces of the resin laminate, respectively. At least one of the two ceramic layers forms a capacitor integrated on the multilayer wiring board on the multilayer wiring board, and the first and second ceramic layers are formed by an aerosol deposition method. The manufacturing method of the multilayer wiring board characterized by these is provided.

  According to the present invention, in the multilayer wiring board including the coreless multilayer wiring board provided with the resin laminate including the build-up resin layer having a low elastic modulus by using the aerosol deposition technique, the surface of the resin laminate is provided. The first and second ceramic layers having a large elastic modulus are reinforced from the upper and lower sides over the entire surface. Therefore, by using such a multilayer wiring board, a semiconductor chip can be mounted with high reliability. At that time, by using at least one of the first and second ceramic layers as a capacitor, it is possible to realize a multilayer wiring board in which large-capacity ceramic capacitors are integrated and the mechanical strength is improved. . The first and second ceramic layers, like the conventional solder resist film, prevent the generation of solder bridges, the value of the amount of pick-up of solder, the prevention of contamination of the solder pot, the protection of the board during assembly, and the copper wiring pattern. It functions to prevent oxidation and corrosion, and to prevent electromigration.

  FIG. 3 is a diagram showing a configuration of the semiconductor device 40 according to the first embodiment of the present invention.

  Referring to FIG. 3, the semiconductor device 40 includes a coreless multilayer wiring board 20 and a semiconductor chip 30 flip-chip mounted on the coreless multilayer wiring board 20, and the coreless multilayer wiring board 20 is built up. It is comprised from the resin laminated body 20R which laminated | stacked the insulating films 21, 22, and 23. FIG.

  Here, the build-up insulating film 21 carries a Cu wiring pattern 20a on its lower surface and an upper Cu wiring pattern 21a, and further has a Cu via plug 21b for electrically connecting the Cu wiring pattern 21a and the Cu wiring pattern 20a. Is formed.

  The build-up insulating film 22 carries the Cu wiring pattern 21a on the lower surface and the Cu wiring pattern 22a on the upper surface, and further, a Cu via plug 22b that electrically connects the Cu wiring pattern 22a and the Cu wiring pattern 21a. Is formed.

  Further, the build-up insulating film 23 carries the Cu wiring pattern 22a on the lower surface and the Cu wiring pattern 23a on the upper surface, and further, a Cu via plug 23b that electrically connects the Cu wiring pattern 23a and the Cu wiring pattern 22a. Is formed.

  In the illustrated example, the Cu via plugs 21b, 22b, and 23b have a diameter of 40 μm, and the Cu wiring patterns 21a, 22a, and 23a form a 30 μm / 30 μm line and space pattern.

  In the semiconductor device 40 of this embodiment, the resin laminate 20R has a ceramic layer 20A having an elastic modulus of 100 to 200 GPa, for example, 150 GPa and a thickness of 10 to 50 μm on the lower surface, and a similar ceramic on the upper surface. As a result, even though the resin laminate 20R does not include a core layer, the entire surface thereof is reinforced from above and below, and the coreless multilayer wiring board 20 has at most each build-up layer. Despite having only an elastic modulus of about 2 to 20 GPa, it exhibits excellent mechanical strength, that is, an elastic modulus, as will be described later.

  The ceramic layer 20A is formed with an opening 20Ah exposing a part of the Cu wiring pattern 20a, and the Cu wiring pattern 20a exposed through the opening 20Ah forms a pad electrode. Similarly, an opening 20Bh exposing a part of the Cu wiring pattern 23a is formed in the ceramic layer 20B, and the Cu wiring pattern 23a exposed by the opening 20Bh forms a pad electrode.

  Here, as the ceramic layers 20A and 20B, a material usually used as a high elastic modulus material can be used. Examples of such a material include alumina, zirconia, aluminum nitride, cordierite, mullite, Titania, quartz, forsterite, wollastonite, anorthite, enstatite, diopsite, akermanite, gelenite, spinel, garnet, etc., and also titanates such as magnesium titanate, calcium titanate, strontium titanate, barium titanate And so on. In particular, alumina, zirconia, aluminum nitride, cordierite, mullite, etc. are preferably used from the viewpoints of insulation and strength.

  Further, like the conventional solder resist film, the ceramic layers 20A and 20B prevent the occurrence of solder bridge, the value source of the amount of solder pickup, the prevention of contamination of the solder pot, the protection of the board during assembly, and the oxidation of the copper wiring pattern. Functions such as prevention of corrosion and corrosion, and prevention of electromigration can be achieved.

  Further, in the semiconductor device of FIG. 3, the semiconductor chip 20 is flip-chip mounted on the coreless multilayer wiring board 20, and the pad electrode (not shown) on the semiconductor chip 20 is connected to the ceramic layer 20 </ b> B via the bump electrode 31. Bonded to the pad electrode 23a exposed in the opening 20Bh formed therein. Further, an underfill resin layer 32 is formed between the coreless multilayer substrate 20 and the semiconductor chip 20.

In the semiconductor device 40 of FIG. 3, on the lower surface of the resin laminate 20R, the electrode 20C is formed on the ceramic layer 20A, and a part of the wiring pattern 20a (wiring pattern 20aG) that forms a ground pattern on the buildup layer 21. ) are formed connected to the electrode 20C, together with the ceramic layers 20A and the electrode pattern 20a thereon, to form a ceramic capacitor C _3.

Similarly, in the semiconductor device 40 of FIG. 3, the electrodes 20D and 20E on the ceramic layer 20B on the resin laminate 20R form part of the wiring pattern 23a (wiring) that forms a ground pattern on the build-up layer 23. pattern 23AG) are formed respectively connected to the electrode 20D, together with the ceramic layers 20B and the electrode pattern 23a of the underlying, to form a ceramic capacitor C _2. Also, the electrodes 20E, together with the ceramic layers 20B and another electrode pattern 23a below it to form a ceramic capacitor C _1.

For example, when alumina having a relative dielectric constant of 10 is used as the ceramic layers 20A and 20B, the effective electrode area of the electrode 20C or 20D and 20E is 0.0015 μm ² , and the thickness of the ceramic layers 20A and 20B is 10 μm, the capacitor C A capacitance of about 0.13 nF can be realized as ₁ , C ₂ , and C ₃ .

  4A is a plan view of the semiconductor device 40 of FIG. 3, and FIG. 4B is a back view.

  Referring to FIG. 4A, the Cu wiring pattern 23a is covered with the ceramic layer 20B on the surface of the resin laminate 20R constituting the multilayer wiring board 20, and the surface of the ceramic layer 20B is further illustrated in FIG. It can be seen that Cu patterns corresponding to the three electrodes 20D and 20E are continuously formed.

  4B, the back surface of the resin laminate 20R constituting the multilayer wiring board 20 is covered with a ceramic layer 20A, and the ceramic layer 20A has a Cu pattern corresponding to the electrode 20C. Covered by. Also, the plan view of FIG. 4B shows a state in which the wiring pattern 20a is exposed through the opening 20Ah formed in the ceramic layer 20A and constitutes external electrodes arranged in a matrix. Yes.

  In the semiconductor device 40 of FIG. 3, the ceramic layers 20A and 20B are formed on the resin laminate 20R by an aerosol deposition method using the device shown in FIG.

  FIG. 5 shows a configuration of an aerosol deposition apparatus 60 used in the present invention.

  Referring to FIG. 5, the aerosol deposition apparatus 60 includes a processing container 61 that is evacuated by a mechanical booster pump 62 and a vacuum pump 62A. In the processing container 61, a substrate to be processed is placed on a stage 61A. W is held by the XY stage drive mechanism 61a and the Z stage drive mechanism 61b so that it can be driven in the XYZ-θ direction.

  A nozzle 61B is provided in the processing container 61 so as to face the substrate W to be processed on the stage 61A, and the nozzle 61B is supplied with an aerosol of ceramic material together with a carrier gas, and this is supplied to the substrate to be processed. The surface of W is sprayed as a jet 61c.

  The ceramic particles constituting the aerosol sprayed in this way preferably have a particle size of 0.5 μm or less, as described above. The surface of the processing substrate W is solidified by impact to form a ceramic film.

  In order to supply the aerosol to the nozzle 61B, the aerosol deposition apparatus 60 of FIG. 4 is provided with a raw material container 63 holding a ceramic powder raw material having a particle size of preferably 0.5 μm or less. A carrier gas such as inert gas or high-purity oxygen is supplied from the high-pressure gas source 64 via the mass flow controller 64A. The raw material container 63 is held on a vibration table 63A in order to promote the generation of aerosol. The raw material container 63 is maintained in a reduced pressure state prior to the film forming step by the mechanical booster pump 62 and the vacuum pump 62A, and the moisture of the ceramic powder raw material is removed.

  Next, a manufacturing process of the semiconductor device 40 of FIG. 3 performed using the aerosol deposition apparatus 60 of FIG. 5 will be described.

  Referring to FIG. 6A, first, a Cu wiring pattern 20a is formed on a substrate 70 made of Cu or a Cu alloy, and further, a first build-up insulating film 21 is formed so as to cover the Cu wiring pattern 20a. Is formed by a vacuum lamination method. For example, as the build-up insulating film 21, a resin insulating film commercially available as trade name TLF-30 from Yodogawa Paper Co., Ltd. can be used.

Further, a via hole corresponding to the plug 21b is formed in the build-up insulating film 21 by a CO ₂ laser, and the entire surface of the build-up insulating film 21 including the via hole is formed by electroless plating of Cu. A layer (not shown) is covered, and a commercially available resist film (not shown) is formed on the Cu seed layer as a trade name FOTEC RY-3229 from Hitachi Chemical Co., Ltd., for example. Further, the resist film is exposed to form an opening corresponding to the via hole, and then the via hole is filled with Cu by electrolytic plating. As a result, the Cu plug 21 b is formed in the buildup insulating film 21.

  Further, a new resist film is formed on the Cu seed layer, patterned according to a desired wiring pattern, and subjected to electrolytic plating, whereby a wiring pattern 21a is formed on the build-up insulating film 21.

  Further, after removing the Cu seed layer interposed between the wiring patterns 21a on the build-up insulating film 21 by etching, the same process is repeated, so that the base 70 is described with reference to FIG. Resin laminate 20R is formed.

  6B, the electrode pad formation region on the resin laminate 20R is covered with a screen mask M such as a metal mask, and the ceramic layer 20B is formed in the aerosol deposition apparatus 60 of FIG. As a result, as shown in FIG. 7C, a structure is obtained in which the portion constituting the pad electrode in the wiring pattern 23a is exposed through the opening 20Bh in the ceramic layer 20B.

  In the step of FIG. 7C, electrodes 20D and 20E are further connected to the Cu ground pattern 23aG on the buildup layer 23 on the ceramic layer 20B. Such electrodes 20D and 20E can also be formed by forming a Cu seed layer in the same manner as described above and performing electrolytic plating. In the step of FIG. 7C, the Cu substrate 70 is removed by wet etching.

  Next, in the step of FIG. 7D, a similar mask pattern M is formed in a predetermined electrode pad formation region on the lower surface of the buildup insulating film 21, and the ceramic layer 20A in the aerosol deposition apparatus 60 of FIG. Is formed so as to cover the lower surface of the buildup layer 21.

  Further, by removing the mask pattern M in the step of FIG. 8E, a structure in which a portion constituting the pad electrode in the wiring pattern 20a is exposed through the opening 20Ah in the ceramic layer 20A. can get.

  8F, a Cu electrode 20C is formed on the ceramic layer 20A so as to be connected to a Cu ground pattern 20aG formed on the lower surface of the buildup layer 21. Thus, the coreless multilayer wiring board 20 is formed. Is formed.

  Further, the semiconductor device 40 of FIG. 3 described above is obtained by flip-chip mounting the semiconductor chip 20 on the coreless multilayer wiring board 20 of FIG.

  6B or 7D, the ceramic film 20A or 20B is uniformly formed without using the mask pattern M, and then the ceramic films 20A and 20B are etched using a mask process. It is also possible to pattern by.

  In the steps of FIGS. 6B and 7D, the ceramic layers 20A and 20B can be made of ceramics usually used as a highly elastic material, as described above. For example, alumina, zirconia, aluminum nitride, cordierite, mullite, titania, quartz, forsterite, wollastonite, anorthite, enstatite, diopsite, akermanite, gelenite, spinel, garnet, etc., and magnesium titanate , Titanates such as calcium titanate, strontium titanate and barium titanate can be used.

  Among these, from the viewpoint of insulation and strength, it is preferable to use a powder having a particle diameter of 10 nm to 1 μm, such as alumina, zirconia, aluminum nitride, cordierite, and mullite. Furthermore, in the process of FIG. 6B or FIG. 7D, it is possible to form the ceramic layers 20A and 20B as, for example, a mixed film of alumina and zirconia by using two or more kinds of ceramics.

  In the present embodiment, in the aerosol deposition apparatus 60 of FIG. 5, commercially available alumina powder is used as a product name 160SG-4 from Showa Denko KK.

  In the semiconductor device 40 of FIG. 3, when a prepreg used for a core material impregnated with, for example, a glass cloth is used instead of the highly elastic ceramic layers 20A and 20B, the coreless multilayer wiring board 20 A sufficient increase in elastic modulus cannot be achieved. In such a case, when the electrodes 20C, 20D, and 20E in FIG. 3 are formed, a desired capacitor cannot be formed because the relative permittivity of the glass cloth impregnated layer is low.

On the other hand, in the present invention, as described above, alumina having a relative dielectric constant of 10 is used as the ceramic layers 20A and 20B, the effective electrode area of the electrode 20C or 20D and 20E is 0.0015 μm ² , and the ceramic When the thickness of the layers 20A and 20B is 10 μm, it has been confirmed that a capacitance of about 0.13 nF can be realized as the capacitors C ₁ , C ₂ and C ₃ .

  Further, when the warp of the coreless multilayer wiring board 20 formed in this way was measured without mounting the semiconductor chip 30, the warp value was about 50 μm for a substrate with a side of 4 cm. In the region where the side where the chip is mounted is 2 cm, it is about 20 μm, and it was confirmed that the semiconductor chip 3 can be mounted without using a reinforcing member.

  Further, after the semiconductor chip 30 was mounted on the coreless multilayer wiring board 20, the warpage of the coreless multilayer wiring board 20 was measured. As a result, the warpage was 100 μm or less on a substrate having a side of 4 cm. It was confirmed that no contact breakage occurred.

  Further, the semiconductor chip 30 is actually flip-chip mounted on the coreless multilayer wiring board 20 thus formed as described in FIG. 3, and the semiconductor chip 30 and the coreless multilayer wiring board 20 are After filling a general underfill resin layer 32 (CRP-4075S3 commercially available from Sumitomo Bakelite Co., Ltd.) having an elastic modulus of 10 GPa and curing it at 150 ° C. for 30 minutes, between −10 ° C. and 100 ° C. The thermal cycle test was repeated 300 times.

  As a result, in the semiconductor device 40 using the coreless multilayer wiring board 20 having the configuration in which the high-elastic ceramic layers 20A and 20B are provided on the resin laminate 20R according to the present embodiment, the gap between the semiconductor chip 30 and the coreless multilayer wiring board 20 is between. It was confirmed that no peeling or disconnection occurred.

  In the configuration of FIG. 3, the underfill resin layer 32 may be added with a filler or may not be added with a filler.

  On the other hand, in the comparative experiment in which the high elastic ceramic layers 20A and 20B were not provided in the configuration of FIG. 3, the warpage was changed from the value of 50 μm in the above embodiment to 300 μm in the substrate having a side of 4 cm. It was confirmed that it would increase. At that time, in the chip mounting region having a side of 2 cm, the warpage increases from 20 μm in the previous embodiment to about 100 μm, and the mounting of the semiconductor chip 30 is as described above with reference to FIG. It was impossible unless the reinforcing member 10L was used.

  Therefore, in the above comparative experiment, a warp was suppressed to about 100 μm by providing a reinforcing member made of stainless steel having a thickness of 1 mm on a coreless multilayer substrate without the ceramic layers 20A and 20B. After the chip was mounted and an underfill resin layer 32 similar to that of the present embodiment was formed in the same manner, the same thermal cycle test was performed.

  As a result, in the above comparative experiment, it was confirmed that a breakage occurred between the coreless multilayer substrate and the semiconductor chip after 300 thermal cycles, and it was confirmed that the warpage of the substrate in the chip mounted state reached 300 μm. It was done. Further, in this comparative experiment, peeling of the semiconductor chip and disconnection of the through via were also observed.

  Thus, according to the present invention, the coreless multilayer wiring board is effectively reinforced by forming high elastic ceramic layers on the upper and lower surfaces of the coreless multilayer wiring board having a low elastic modulus, preferably by the aerosol deposition method. Thus, the reliability of the semiconductor device using such a coreless multilayer wiring board can be greatly improved.

  Note that the present invention is not limited to a coreless multilayer wiring board, and even in a multilayer wiring board having a core member as shown in FIG. 1, particularly when the thickness is 500 μm or less and warping or deformation becomes a problem. It is also possible to apply.

  As mentioned above, although this invention was described about preferable embodiment, this invention is not limited to this specific embodiment, A various deformation | transformation and change are possible within the summary described in the claim.

(Additional remark 1) It is a multilayer wiring board provided with the resin laminated body which consists of a lamination | stacking of several buildup resin layers which carry | support each wiring pattern and also has the via plug connected to the said wiring pattern,
Furthermore, first and second ceramic layers having an elastic modulus larger than the elastic modulus of the buildup layer are respectively formed on the upper surface and the lower surface of the resin laminate,
At least one of the first and second ceramic layers forms a capacitor integrated on the multilayer wiring board on the multilayer wiring board.

  (Additional remark 2) The said multilayer wiring board is a coreless multilayer wiring board, The multilayer wiring board of Additional remark 1 characterized by the above-mentioned.

  (Additional remark 3) The said 1st and 2nd ceramic layer has an elastic modulus of 100-200 GPa, The multilayer wiring board of Additional remark 1 or 2 characterized by the above-mentioned.

  (Additional remark 4) The said 1st and 2nd ceramic layer is formed in the film thickness of 10-50 micrometers, The multilayer wiring board as described in any one among Additional remarks 1-3 characterized by the above-mentioned.

  (Supplementary Note 5) Any one of Supplementary Notes 1 to 4, wherein the first and second ceramic layers expose electrode pads formed on the top and bottom surfaces of the resin laminate, respectively. The multilayer wiring board as described.

  (Additional remark 6) The said 1st and 2nd ceramic layer is formed by the aerosol deposition method, The multilayer wiring board as described in any one of Additional remarks 1-5 characterized by the above-mentioned.

  (Additional remark 7) The said 1st and 2nd ceramic layer consists of an alumina or aluminum nitride, The multilayer wiring board as described in any one of Claims 1-6 characterized by the above-mentioned.

  (Additional remark 8) Furthermore, the ceramic layer is formed in the side wall surface of the said resin laminated body by the aerosol deposition method, The multilayer wiring board as described in any one of Additional remark 1-7 characterized by the above-mentioned.

  (Appendix 9) A semiconductor device comprising the multilayer wiring board according to any one of appendices 1 to 8 and a semiconductor chip flip-chip mounted on the multilayer wiring board.

(Additional remark 10) It is a manufacturing method of the multilayer wiring board provided with the resin laminated body which consists of lamination | stacking of several buildup resin layers which carry | support each wiring pattern and has the via plug further connected to the said wiring pattern,
First and second ceramic layers having an elastic modulus larger than the elastic modulus of the buildup layer are formed on the upper surface and the lower surface of the resin laminate, respectively.
At least one of the first and second ceramic layers forms a capacitor integrated on the multilayer wiring board on the multilayer wiring board;
The method for manufacturing a multilayer wiring board, wherein the first and second ceramic layers are formed by an aerosol deposition method.

  (Additional remark 11) The said multilayer wiring board is a coreless multilayer wiring board, The manufacturing method of the multilayer wiring board of Additional remark 10 characterized by the above-mentioned.

  (Additional remark 12) The said 1st and 2nd ceramic layer has an elasticity modulus of 100-200 GPa, The manufacturing method of the multilayer wiring board of Additional remark 10 or 11 characterized by the above-mentioned.

  (Additional remark 13) The said 1st and 2nd ceramic layer is formed in the film thickness of 10-50 micrometers, The manufacturing method of the multilayer wiring board as described in any one of Additional remarks 10-12 characterized by the above-mentioned.

  (Supplementary Note 14) Any one of Supplementary Notes 10 to 13, wherein the first and second ceramic layers expose electrode pads formed on the top and bottom surfaces of the resin laminate, respectively. The manufacturing method of the multilayer wiring board as described.

  (Additional remark 15) The said 1st and 2nd ceramic layer consists of alumina or aluminum nitride, The manufacturing method of the multilayer wiring board as described in any one of Claims 10-14 characterized by the above-mentioned.

  (Additional remark 16) Furthermore, the ceramic layer is formed in the side wall surface of the said resin laminated body by the aerosol deposition method, The manufacture of the multilayer wiring board as described in any one of Additional remarks 10-15 characterized by the above-mentioned. Method.

It is a figure which shows the structure of the semiconductor device provided with the multilayer wiring board which has a core by the related technique of this invention. It is a figure which shows the structure of the semiconductor device provided with the coreless multilayer wiring board by the related technique of this invention. It is a figure which shows the structure of the semiconductor device provided with the coreless multilayer wiring board by one Embodiment of this invention. (A), (B) is a figure which shows the top view and back view of the semiconductor device of FIG. It is a figure which shows the structure of the aerosol deposition apparatus used by this invention. (A), (B) is a figure (the 1) which shows the manufacturing process of the semiconductor device of FIG. (C), (D) is a figure (the 2) which shows the manufacturing process of the semiconductor device of FIG. (E) and (F) are views (No. 3) showing the manufacturing process of the semiconductor device of FIG.

Explanation of symbols

11 multilayer wiring board 11A, 11B, 11D, 11E buildup insulating film 11C core portion 11C _1, 11C ₂ core layer 11G glass cloth 12A, 12B, 12D, 12E wiring layer 12C through vias 13A, 13B the solder resist 15 semiconductor chip 16 bumps 17 Underfill resin layer 20 Coreless multilayer wiring board 20A, 20B, 80A, 80B High elastic ceramic layer 20Ah, 20Bh Opening 20C, 20D, 20E Capacitor electrodes 21, 22, 23 Build-up insulating films 21a, 22a, 23a Cu wiring pattern 21b , 22b, 23b Cu via plug 30 Semiconductor chip 31 Bump 32 Underfill resin layer 40, 80 Semiconductor device 60 Aerosol deposition device 61 Processing vessel 61A Stage 61B Nozzle 61a -Y stage driving mechanism 61b Z stage driving mechanism 61c jet 62 mechanical booster pump 63 material container 63A vibrating table 64 the high pressure gas source

Claims (5)

A multilayer wiring board comprising a resin laminate comprising a plurality of buildup resin layers each carrying a wiring pattern and further having via plugs connected to the wiring pattern,
Furthermore, first and second ceramic layers having an elastic modulus larger than the elastic modulus of the buildup layer are respectively formed on the upper surface and the lower surface of the resin laminate,
At least one of the first and second ceramic layers forms a capacitor integrated on the multilayer wiring board on the multilayer wiring board.   The multilayer wiring board according to claim 1, wherein the multilayer wiring board is a coreless multilayer wiring board.   The multilayer wiring board according to claim 2, wherein the first and second ceramic layers are formed by an aerosol deposition method. A semiconductor device comprising the multilayer wiring board according to claim 1 and a semiconductor chip flip-chip mounted on the multilayer wiring board. A method for producing a multilayer wiring board comprising a resin laminate comprising a plurality of build-up resin layers each carrying a wiring pattern and further having via plugs connected to the wiring pattern,
First and second ceramic layers having an elastic modulus larger than the elastic modulus of the buildup layer are formed on the upper surface and the lower surface of the resin laminate, respectively.
At least one of the first and second ceramic layers forms a capacitor integrated on the multilayer wiring board on the multilayer wiring board;
The method for manufacturing a multilayer wiring board, wherein the first and second ceramic layers are formed by an aerosol deposition method.

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