WO2009119745A1 - Wiring board, semiconductor package and method of fabricating wiring board - Google Patents
Wiring board, semiconductor package and method of fabricating wiring board Download PDFInfo
- Publication number
- WO2009119745A1 WO2009119745A1 PCT/JP2009/056133 JP2009056133W WO2009119745A1 WO 2009119745 A1 WO2009119745 A1 WO 2009119745A1 JP 2009056133 W JP2009056133 W JP 2009056133W WO 2009119745 A1 WO2009119745 A1 WO 2009119745A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- insulating layer
- wiring board
- wiring
- resin substrate
- hole
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims description 93
- 238000004519 manufacturing process Methods 0.000 title claims description 44
- 239000011347 resin Substances 0.000 claims abstract description 119
- 229920005989 resin Polymers 0.000 claims abstract description 119
- 239000000758 substrate Substances 0.000 claims abstract description 109
- 239000000919 ceramic Substances 0.000 claims abstract description 36
- 238000005245 sintering Methods 0.000 claims abstract description 20
- 238000010438 heat treatment Methods 0.000 claims abstract description 18
- 229910052574 oxide ceramic Inorganic materials 0.000 claims description 52
- 239000011224 oxide ceramic Substances 0.000 claims description 52
- 238000000034 method Methods 0.000 claims description 46
- 239000002245 particle Substances 0.000 claims description 33
- 229910000679 solder Inorganic materials 0.000 claims description 30
- 229910052751 metal Inorganic materials 0.000 claims description 29
- 239000002184 metal Substances 0.000 claims description 29
- 239000013078 crystal Substances 0.000 claims description 19
- 239000004020 conductor Substances 0.000 claims description 15
- MCMNRKCIXSYSNV-UHFFFAOYSA-N Zirconium dioxide Chemical compound O=[Zr]=O MCMNRKCIXSYSNV-UHFFFAOYSA-N 0.000 claims description 12
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 claims description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 7
- 239000000443 aerosol Substances 0.000 claims description 6
- 238000000151 deposition Methods 0.000 claims description 6
- 229910052878 cordierite Inorganic materials 0.000 claims description 5
- JSKIRARMQDRGJZ-UHFFFAOYSA-N dimagnesium dioxido-bis[(1-oxido-3-oxo-2,4,6,8,9-pentaoxa-1,3-disila-5,7-dialuminabicyclo[3.3.1]nonan-7-yl)oxy]silane Chemical compound [Mg++].[Mg++].[O-][Si]([O-])(O[Al]1O[Al]2O[Si](=O)O[Si]([O-])(O1)O2)O[Al]1O[Al]2O[Si](=O)O[Si]([O-])(O1)O2 JSKIRARMQDRGJZ-UHFFFAOYSA-N 0.000 claims description 5
- KZHJGOXRZJKJNY-UHFFFAOYSA-N dioxosilane;oxo(oxoalumanyloxy)alumane Chemical compound O=[Si]=O.O=[Si]=O.O=[Al]O[Al]=O.O=[Al]O[Al]=O.O=[Al]O[Al]=O KZHJGOXRZJKJNY-UHFFFAOYSA-N 0.000 claims description 5
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
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Images
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
- H05K3/4664—Adding a circuit layer by thick film methods, e.g. printing techniques or by other techniques for making conductive patterns by using pastes, inks or powders
- H05K3/4667—Adding a circuit layer by thick film methods, e.g. printing techniques or by other techniques for making conductive patterns by using pastes, inks or powders characterized by using an inorganic intermediate insulating layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4867—Applying pastes or inks, e.g. screen printing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49822—Multilayer substrates
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/111—Pads for surface mounting, e.g. lay-out
- H05K1/112—Pads for surface mounting, e.g. lay-out directly combined with via connections
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4602—Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/03—Use of materials for the substrate
- H05K1/0313—Organic insulating material
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/09—Use of materials for the conductive, e.g. metallic pattern
- H05K1/092—Dispersed materials, e.g. conductive pastes or inks
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09372—Pads and lands
- H05K2201/09436—Pads or lands on permanent coating which covers the other conductors
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/11—Treatments characterised by their effect, e.g. heating, cooling, roughening
- H05K2203/1131—Sintering, i.e. fusing of metal particles to achieve or improve electrical conductivity
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4688—Composite multilayer circuits, i.e. comprising insulating layers having different properties
Definitions
- the present invention is based on the priority claim of Japanese Patent Application: Japanese Patent Application No. 2008-085403 (filed on Mar. 28, 2008), the entire contents of which are incorporated herein by reference. Shall.
- the present invention relates to a wiring board and a manufacturing method thereof, and more particularly to a wiring board on which wiring is formed using a conductive paste containing conductive particles and a manufacturing method thereof.
- the present invention also relates to a semiconductor package having the wiring board.
- a circuit pattern is formed using a conductive paste containing metal fine particles. That is, after drawing a circuit pattern on the surface of the core substrate provided with via holes with a conductive paste adjusted so that silver nanoparticles having an average particle diameter of 7 nm do not aggregate, and filling the via holes with silver nanoparticles, By performing heat treatment at 250 ° C. or lower, a circuit pattern made of a silver sintered body is formed. Further, the surface of the circuit pattern is covered with a photoresist, and a via hole is formed in a part of the photoresist. Then, while drawing a circuit pattern with an electrically conductive paste and filling a silver hole with a via hole, the process of heat processing is repeated and the multilayer wiring board is obtained.
- a wiring is drawn with a paste-like silver nanoparticle dispersion on a transfer sheet surface composed of a polymer material having high heat resistance such as polyimide, By performing a heat treatment at 250 ° C. for 40 minutes, a wiring composed of a sintered body layer of silver nanoparticles is formed. Then, the formed wiring is superimposed on a ceramic substrate having an adhesive layer, heated and pressed to be pressed, and transferred onto the ceramic substrate to obtain a printed board having the wiring on the ceramic substrate.
- Patent Documents 1 and 2 are incorporated herein by reference. The following analysis is given by the present invention.
- a circuit pattern is directly formed on a core substrate, and silver nanopaste is heated and sintered when the circuit pattern is formed. Therefore, heat at the time of sintering is transferred to the core substrate, so that a material having a low heat-resistant temperature cannot be used for the core substrate.
- thermosetting resins such as epoxy and polyimide are used as the core substrate, problems such as warpage of the substrate and deterioration of mechanical characteristics occur due to long-time heating during sintering.
- a wiring board of the present invention includes a resin insulating layer, a resin substrate having an electrode provided on the surface of the resin insulating layer, and a resin substrate.
- a first insulating layer provided on the first insulating layer; a first through hole provided in the first insulating layer on the electrode; a wiring provided on the first insulating layer and in the first through hole;
- a wiring board having the following is provided.
- the wiring is in electrical contact with the electrode.
- the wiring is made of a conductor in which adjacent conductive particles are joined to each other.
- the first insulating layer is made of an oxide ceramic.
- the wiring is a sintered body obtained by sintering a conductive paste containing conductive particles and an organic compound.
- the first insulating layer is made of at least one oxide ceramic selected from the group consisting of alumina, silica, spinel, mullite, cordierite, zirconia, and zircon. .
- the wiring board further includes a solder resist layer provided on the surface of the resin substrate and having a function as a solder resist.
- the second insulating layer provided between the first insulating layer and the resin substrate, and the second penetration provided in the second insulating layer on the electrode. And a hole.
- the wiring board further includes a metal film between the resin substrate and the wiring on the first insulating layer.
- the first insulating layer is made of a translucent oxide ceramic.
- the metal film is covered with the first insulating layer or the resin insulating layer.
- the wiring board further includes a third insulating layer covering the wiring and the first insulating layer.
- the third insulating layer is made of an oxide ceramic.
- a third through hole is provided in the third insulating layer.
- Wiring is provided on the third insulating layer and in the third through hole.
- a plurality of layers made of wiring and oxide ceramics are laminated.
- the third through hole is provided in the third insulating layer.
- An external connection electrode is provided inside the third through hole. The external connection electrode and the wiring are in electrical contact.
- a conductor is provided on the external connection electrode.
- the first insulating layer is made of oxide ceramics having a polycrystalline structure including particulate crystals.
- the crystal grain size changes in the thickness direction of the first insulating layer.
- the crystal grain size in contact with the wiring provided on the first insulating layer is larger than the crystal grain size in contact with the resin substrate.
- the semiconductor package of the present invention is characterized in that at least one semiconductor device is mounted on the wiring board of the present invention.
- the wiring is electrically connected to the semiconductor device through the conductor.
- a method for manufacturing a wiring board according to the present invention includes a step of forming a first insulating layer made of an oxide ceramic on a resin substrate, and a first penetration through the first insulating layer. A step of forming a hole, a step of disposing a conductive paste on the first insulating layer and in the first through hole, and a step of heating the conductive paste.
- the step of forming the first insulating layer made of oxide ceramics on the resin substrate and the step of forming the first through hole in the first insulating layer are: In this step, the ceramic sheet provided with the first through hole is bonded to the resin substrate.
- the step of forming the first insulating layer made of oxide ceramics on the resin substrate and the step of forming the first through hole in the first insulating layer are: In this step, a part of the paste made of oxide ceramics is transferred onto the resin substrate.
- the method for manufacturing a wiring board of the present invention forms a metal film on the resin substrate before the step of forming the first insulating layer made of oxide ceramics. And a step of removing a part of the metal film.
- the step of forming the first insulating layer is an aerosol deposition method.
- the spraying speed of the raw material fine particles of the first insulating layer sprayed onto the wiring board is decreased in stages.
- the top view and sectional drawing of the wiring board which are the 1st Embodiment of this invention The enlarged view of the wiring board which is the 1st Embodiment of this invention Sectional drawing of the semiconductor package using the wiring board of the 1st Embodiment and 2nd Embodiment of this invention
- the fragmentary sectional view for demonstrating the manufacturing method of the wiring board which is the 1st Embodiment of this invention Sectional drawing and enlarged view of the wiring board which is the 2nd Embodiment of this invention
- Sectional drawing of the manufacturing method of the wiring board which is the 2nd Embodiment of this invention Sectional drawing and enlarged view of the wiring board which is the 4th Embodiment of this invention
- Sectional drawing of the manufacturing method of the wiring board which is the 4th Embodiment of this invention Sectional drawing and enlarged view of the wiring board which is the 5th Embodiment of this invention
- Sectional drawing of the manufacturing method of the wiring board which is the 5th Embodiment of this invention Sectional drawing of
- a wiring board according to the first embodiment of the present invention will be described.
- FIG. 1 is a diagram illustrating a configuration of a wiring board 60 according to the present embodiment
- FIG. 1A is a plan view of the wiring board 60 as viewed from the side where the wiring 50 is provided
- FIG. ) Is a vertical cross-sectional view along the line AA in FIG. 1A
- FIG. 1C is a cross-sectional view in the plane direction along the line BB in FIG. 1B
- FIG. 2 is an enlarged cross-sectional view of the vicinity of the electrode 20 of the wiring board 60.
- 1 includes a resin substrate 30, a first insulating layer 40, and wiring 50.
- the resin substrate 30 includes a resin insulating layer 10 and an electrode 20 provided on the surface of the resin insulating layer 10.
- the resin insulating layer 10 is, for example, one or more selected from the group consisting of epoxy resin, polyimide resin, epoxy acrylate resin, urethane acrylate resin, polyester resin, phenol resin, BCB (benzocycle) and PBO (polybenzoxole).
- the insulating resin is used.
- inner layer wiring 21 may be provided inside the insulating resin layer 10, and each inner layer wiring 21 and the electrode 20 may be electrically connected by a via (not shown).
- the side surface of the electrode 20 shown in FIG. 2 is completely embedded in the resin insulating layer 10, and the surface of the electrode 20 in contact with the wiring 50 is the surface of the resin insulating layer 10 in contact with the first insulating layer 40. It is the same surface as. However, in the wiring substrate 60 of the present embodiment, the surface of the electrode 20 in contact with the wiring 50 may not be flush with the surface of the resin insulating layer 10 in contact with the first insulating layer 40. It may be a concave surface or a convex surface with respect to the surface of the layer 10.
- the first insulating layer 40 is made of oxide ceramics, is provided on the resin substrate 30, and has a first through hole 41 on the electrode 20.
- the first insulating layer 40 is made of an oxide ceramic having a low thermal conductivity and a heat resistant temperature higher than that of the insulating resin.
- the oxide ceramics of the present invention for example, alumina (Al 2 O 3), silica (SiO 2), spinel (MgAl 2 O 4), mullite (3Al 2 O 3 ⁇ 2SiO 2 ), cordierite (2MgO ⁇ 2Al 2 O 3 .5SiO 2 ), zirconia (ZrO 2 ), zircon (ZrSiO 4 ), PLZT ((Pb, La) (Zr, Ti) O 3 ), yttria-tria (Y 2 O 3 —ThO 2 ), etc.
- the first insulating layer 40 may be made of one kind of oxide ceramics, or may be a mixture of two or more kinds of oxide ceramics.
- the wiring 50 is provided on the first insulating layer 40 and in the first through hole 41, and is in electrical contact with the electrode 20.
- the wiring 50 is a conductor in which adjacent conductive particles are joined to each other, and is a sintered body obtained by heating and sintering a conductive paste containing an organic solvent and conductive particles.
- the wiring 50 is formed by the surface of the conductive particles being melted by the heat at the time of sintering, being cooled in a state where the melted portions of the adjacent conductive particles are joined, and the melted portion solidifying.
- the organic solvent evaporates due to heat during sintering.
- conductive particles forming the wiring 50 described in the drawings of the present application are shown in an aligned state, these are schematic representations of the conductive particles.
- the conductive particles forming the wiring 50 of the present invention are not limited to the aligned particles, and the arrangement thereof may have no regularity.
- the conductive particles include gold, silver, copper, platinum, palladium, rhodium, osmium, ruthenium, iridium, iron, tin, zinc, cobalt, nickel, chromium, titanium, tantalum, tungsten, indium, and silicon.
- An alloy made of at least one kind of metal or two or more kinds of metals is used.
- the conductive particles preferably have a particle size of 1 nanometer to 100 nanometers.
- the first insulating layer 40 made of oxide ceramics having low thermal conductivity is provided on the resin substrate 30. Therefore, the wiring that is a sintered body of conductive particles is provided. Heat at the time of sintering is difficult to be transmitted to the resin substrate 30 having a low heat-resistant temperature. Therefore, it is possible to suppress the temperature rise of the resin substrate 30 during wiring sintering, and it is possible to obtain a wiring substrate with little deterioration due to the temperature rise of the resin substrate 30.
- FIG. 3 (a) and 3 (b) are diagrams showing the configuration of the semiconductor package 90 of the present embodiment, in which the semiconductor device 91 is mounted on the wiring substrate 60 of the present embodiment.
- FIG. 3A shows a semiconductor device 91 mounted on the electrode 20 provided on the surface of the resin substrate 30 that is not in contact with the first insulating layer 40.
- a conductor 93 such as solder is provided on the electrode 20 so that the semiconductor device 91 and the wiring board 60 are electrically connected.
- FIG. 3B shows the semiconductor device 91 mounted on the first insulating layer 40 of the wiring board 60.
- a conductor 93 such as solder is provided on the wiring 50, and the semiconductor device 91 and the wiring substrate 60 are electrically connected.
- the semiconductor device 91 and the wiring board 60 can be electrically connected by various methods, and can be electrically connected by, for example, flip chip, wire bonding, tape bonding, or the like.
- the semiconductor device 91 may be one or plural, and the semiconductor device 91 may be mounted on both surfaces of the wiring board 60 by combining FIG. 3A and FIG.
- the thermal expansion coefficients of the first insulating layer 40 made of oxide ceramics and the semiconductor device 91 are close to each other. Therefore, even if the first insulating layer 40 and the semiconductor device 91 are thermally expanded due to heat generated due to a change in ambient temperature, operation of the semiconductor device, or the like, the amount of thermal expansion becomes a close value. Therefore, the semiconductor package 90 can have high reliability.
- FIGS. 4A to 4E are partial cross-sectional views showing the method of manufacturing the wiring board 60 of the present embodiment in the order of steps.
- This sectional view is an enlarged view of the vicinity of the electrode 20 to which the wiring 50 is connected. Note that cleaning and heat treatment are appropriately performed between the respective steps.
- a resin substrate 30 having electrodes 20 on the surface is prepared.
- a first insulating layer 40 having a first through hole 41 is formed on the electrode 20.
- the first insulating layer 40 made of oxide ceramics is formed using an aerosol deposition method (AD method).
- a mask (not shown) is provided on the electrode 20 in advance, and after the formation of the first insulating layer 40 by the AD method is completed, the mask is removed, whereby the first penetration is formed on the electrode 20.
- the hole 41 may be formed.
- the first through-hole 41 may be formed on the electrode 20 by mechanical processing such as ultrasonic precision processing after the first insulating layer 40 is formed on the entire surface of the resin substrate 30 by the AD method.
- a conductive paste 52 is formed on the first insulating layer 40 made of oxide ceramics and in the first through hole 41 provided in the first insulating layer 40.
- a method for applying the conductive paste 52 for example, an inkjet method, a dispensing method, a screen printing method, a relief printing method, an imprinting method, or the like can be used.
- the inkjet method using a device having a head capable of applying a conductive paste, on the first insulating layer 40 and in the first through hole 41 provided in the first insulating layer 40.
- a conductive paste 52 is applied to the substrate.
- the applied conductive paste 52 may be drawn with dots, and the dots may be continuously applied to connect the dots to form a wiring.
- the conductive paste 52 on the first insulating layer 40 is heated to sinter the conductive particles.
- the surface coated with the conductive paste 52 is irradiated with electromagnetic waves and heated using its absorption characteristics.
- the electromagnetic wave wavelength is adjusted to the absorption wavelength of the conductive paste 52 and irradiated, the temperature of the conductive paste 52 rises.
- the temperature is 200 ° C. to 300 ° C., and the time is 2 hours.
- these sintering conditions are not restricted to this, It is possible to change suitably.
- a wiring substrate 60 having a wiring 50 made of a conductor in which adjacent conductive particles are bonded to each other can be obtained.
- a first insulating layer 40 made of oxide ceramics having a low thermal conductivity is provided on a resin substrate having an insulating resin having a low heat-resistant temperature.
- a conductive paste is applied on the insulating layer.
- the heat applied to the conductive paste is directly transferred to the resin substrate, so that the temperature rise of the resin substrate becomes significant, causing the resin insulating layer to warp and deteriorate physical properties. It will cause it.
- the heating of the conductive paste is suppressed in order to prevent deterioration of the physical properties of the resin substrate, the sintering becomes insufficient and there may be a problem in wiring conduction.
- the wiring is created in a separate process on the transfer sheet. After being sintered on the transfer sheet, the wiring is transferred onto the ceramic substrate.
- a very thin wiring having a wiring width of several tens of micrometers at the maximum has a low mechanical strength and is brittle. Therefore, there is a problem that there is a high possibility of disconnection due to a stress during transfer.
- a wiring board having a wiring formed by applying a conductive paste containing conductive particles directly on a substrate having an insulating resin having a low heat-resistant temperature is manufactured. Therefore, there is an effect that disconnection due to transfer does not occur.
- FIG. 5 is a diagram showing a configuration of the wiring board 60 of the present embodiment
- FIG. 5A is a schematic cross-sectional view
- FIG. It is.
- solder resist layer 11 having a function as a solder resist is provided on the surface of the resin substrate 30.
- the solder resist layer 11 is provided so that the electrode 20 is exposed, and the periphery of the electrode 20 is covered with the solder resist layer 11. Further, a step is provided at the boundary between the exposed surface of the electrode 20 and the exposed surface of the solder resist layer 11, and the exposed surface of the electrode 20 is provided at a position lower than the exposed surface of the solder resist layer 11.
- a part of the electrode 20 may be embedded in the resin insulating layer 10, or the entire electrode 20 may be embedded in the resin insulating layer 10 as in the first embodiment.
- the first insulating layer 40 and the wiring 50 are provided in the same manner as the wiring substrate according to the first embodiment.
- the wiring 50 provided on the first insulating layer 40 is in electrical contact with the electrode 20 through the first through hole 41.
- the solder resist layer 11 may be, for example, a thermosetting resin, and is preferably an epoxy resin, for example.
- the wiring board according to the present embodiment it is possible to form the wiring covered with the solder resist layer 11 on the surface of the resin substrate 30. As a result, the wiring can be multi-layered.
- the resin insulating layer 10 is covered with the solder resist layer 11, the resin insulating layer 10 can be protected when the first insulating layer 40 is formed.
- FIG. 3C is a diagram showing a configuration of the semiconductor package 90 of the present embodiment.
- the semiconductor package 90 of the present embodiment is obtained by mounting the semiconductor device 91 on the wiring board of the present embodiment.
- the mounting surface of the semiconductor device 91, the number of the semiconductor devices 91, the connection method of the semiconductor devices 91, and the like. Is the same as the semiconductor package of the first embodiment.
- a conductor 93 such as solder is provided on the electrode 20 of the resin substrate 30, and a region for mounting the semiconductor device 91 is provided there. It is also possible. That is, it is possible to form a normal mounting region and a mounting region having the wiring 50 obtained by sintering the conductive paste on one wiring board.
- 6 (a) to 6 (f) are partial cross-sectional views showing the method of manufacturing the wiring board 60 of the present embodiment in the order of steps. Note that cleaning and heat treatment are appropriately performed between the respective steps.
- a resin substrate 30 is prepared in which an electrode 20 whose surface is exposed is disposed and a solder resist layer 11 is formed so as to cover the resin insulating layer 10.
- the electrode 20 only needs to have its surface exposed, and a part of the electrode 20 may be embedded in the resin insulating layer 10 or the entire electrode 20 may be embedded in the resin insulating layer 10.
- the solder resist layer 11 is formed so that at least a part of the electrode 20 is exposed, and a step is provided at the boundary between the exposed surface (upper surface) of the electrode 20 and the exposed surface (upper surface) of the solder resist layer 11.
- the exposed surface (upper surface) of the electrode 20 is provided at a position lower than the exposed surface (upper surface) of the solder resist layer 11.
- FIGS. 6B and 6C show a process of forming the first insulating layer 40 made of oxide ceramics on the surface of the resin substrate 30.
- the surface of the solder resist layer 11 may be roughened in advance by mechanical polishing or the like in order to improve adhesion to the ceramic paste due to the anchor effect.
- the solder resist layer 11 is brought into contact with a base material 95 such as elastic rubber printed on a ceramic paste 96 having a uniform thickness.
- the ceramic paste 96 is transferred only to the portion where the solder resist layer 11 is provided. However, if the electrode 20 is sufficiently exposed, the ceramic paste may be transferred to a part of the exposed surface of the electrode 20.
- the ceramic paste for example, a ceramic paste having high heat resistance containing ceramics such as alumina, mullite, and cordierite may be used.
- the ceramic paste is left to stand at a temperature lower than the heat resistance temperature of the resin insulating layer 10 and the solder resist layer 11 to cure the first insulating layer 40. It was.
- a conductive paste 52 is applied on the first insulating layer 40 and in the first through holes 41 provided in the first insulating layer 40. The subsequent steps are the same as the steps after FIG.
- a mask for providing the first through hole 41 of the method for manufacturing the wiring substrate according to the first embodiment and a drilling step by machining are not used.
- the first through hole 41 can be formed in the first insulating layer 40.
- the state when the ceramic paste 96 is transferred to the surface of the electrode 20 can be controlled.
- Examples of the white or light oxide ceramics in the present embodiment include alumina (Al 2 O 3 ), silica (SiO 2 ), spinel (MgAl 2 O 4 ), or mullite (3Al 2 O 3 .2SiO 2). ), Cordierite (2MgO ⁇ 2Al 2 O 3 ⁇ 5SiO 2 ) and other oxide-ceramics such as alumina-silica-based double oxides may be zirconia (ZrO 2 ), zircon (ZrSiO). 4 ) and the like.
- the conductive paste 52 before sintering is irradiated with electromagnetic waves and heated.
- the heating electromagnetic wave include visible light having a wavelength longer than that of ultraviolet light, infrared light, far infrared light, microwaves, and millimeter waves.
- the electromagnetic wave irradiated when the wiring 50 is sintered is applied not only to the wiring but also to the first insulating layer 40 existing around the wiring.
- the electromagnetic wave is hardly absorbed by the white or light-colored oxide ceramics and is reflected by the oxide ceramics. That is, the electromagnetic wave heats only the conductive paste 52 and the surrounding first insulating layer 40 becomes difficult to be heated, so that the temperature rise of the resin substrate 30 existing below the first insulating layer 40 is suppressed. Is possible.
- the semiconductor package of the present embodiment is obtained by mounting a semiconductor device on the wiring substrate of the present embodiment. Regarding the mounting surface of the semiconductor device, the number of semiconductor devices, the connection method of the semiconductor devices, etc. This is the same as the semiconductor package of the embodiment.
- FIG. 7 is a diagram showing a configuration of the wiring board 60 of the present embodiment
- FIG. 7A is a schematic cross-sectional view
- FIG. 7B is an enlarged cross-sectional view of the vicinity of the electrode 20 of the wiring board 60. It is.
- a second insulating layer 70 is provided between the resin substrate 30 and the first insulating layer 40.
- a second through hole 71 is provided in the second insulating layer 70 on the electrode 20, and a wiring 50 is also provided in the second through hole 71, and the wiring 50 and the electrode 20 are in electrical contact.
- the second insulating layer 70 is for adhering the ceramic sheet forming the first insulating layer 40 to the resin substrate 30.
- an epoxy-based adhesive having heat resistance, or an alumina or zirconia-based adhesive can be used.
- the ceramic sheet is a composite material of oxide ceramics and fibers, and the oxide ceramics are already fired. This ceramic sheet is formed into a sheet shape and has high flatness.
- the first insulating layer 40 is formed using a ceramic sheet having high flatness, the flatness of the surface on which the wiring 50 is formed is increased. Can be provided. When the flatness of the surface on which the wiring 50 is formed is high, the line width of the wiring 50 formed by applying the conductive paste becomes uniform, and the conduction is stabilized. Therefore, it is possible to form a finer wiring 50.
- the semiconductor package of the present embodiment is obtained by mounting a semiconductor device on the wiring substrate of the present embodiment. Regarding the mounting surface of the semiconductor device, the number of semiconductor devices, the connection method of the semiconductor devices, etc. This is the same as the semiconductor package of the embodiment.
- a wiring board having fine wiring can be used, so that a semiconductor device having many connection electrodes can be mounted. This is because fine wiring can be formed, and even if the number of connection electrodes is large, many wirings can be routed.
- 8 (a) to 8 (f) are partial cross-sectional views showing the method of manufacturing the wiring board 60 of this embodiment in the order of steps. Note that cleaning and heat treatment are appropriately performed between the respective steps.
- a resin substrate 30 on which the electrode 20 whose surface is exposed is arranged is prepared.
- the electrode 20 only needs to have its surface exposed, and a part of the electrode 20 may be embedded in the resin insulating layer 10 or the entire electrode 20 may be embedded in the resin insulating layer 10.
- a ceramic sheet 97 provided with a first through hole 41 corresponding to the position of the electrode 20 in advance is prepared, and an epoxy-based adhesive having heat resistance or Then, an adhesive 73 based on alumina or zirconia is applied to the ceramic sheet 97. Thereafter, the ceramic sheet 97 and the resin substrate 30 are positioned.
- the ceramic sheet 97 is adhered to the resin substrate 30 via the adhesive 73, whereby a first insulating layer is formed.
- the flatness of the first insulating layer 40 can be increased. I can do it.
- the flatness of the first insulating layer 40 is high, the thickness and line width of the conductive paste applied thereon become uniform, and it is possible to form a wiring board having wiring with stable electrical conduction. Become.
- FIG. 9 is a diagram illustrating a configuration of the wiring board 60 of the present embodiment
- FIG. 9A is a schematic cross-sectional view
- FIG. 9B is an enlarged cross-sectional view of the vicinity of the electrode 20 of the wiring board 60. It is.
- a metal film 72 that reflects electromagnetic waves is provided between the resin substrate 30 and the wiring 50 on the first insulating layer 40, and the first insulating layer 40 is transparent. It is the point which is formed with the property ceramics. Other structures are the same as those in the first embodiment.
- the metal film 72 shown in FIGS. 9A and 9B is provided on the resin substrate 30 where the electrode 20 is not formed so as not to contact the wiring 50 and the electrode 20. Yes.
- the metal film 72 may not be in contact with the electrode 20 and the wiring 50, and the metal film 72 may not be in contact with the resin substrate 30. It may be provided inside the first insulating layer 40.
- the metal film 72 is provided inside the first insulating layer 40 and is at a position away from the resin substrate 30, the irradiated electromagnetic wave is reflected at a position away from the resin substrate 30 and heated by the electromagnetic wave. Therefore, the heating of the resin substrate 30 is further suppressed.
- the metal film 72 only needs to reflect an electromagnetic wave irradiated when the wiring 50 is sintered.
- at least one kind of metal among copper, silver, gold, nickel, aluminum, and palladium, or two kinds It can select from the alloy which consists of the above metal.
- the translucent ceramic include alumina (Al 2 O 3 ), PLZT ((Pb, La) (Zr, Ti) O 3 ), yttria-tria (Y 2 O 3 —ThO 2 ), spinel ( Oxide ceramics such as MgAl 2 O 4 ) can be used.
- the semiconductor package of the present embodiment is obtained by mounting a semiconductor device on the wiring substrate of the present embodiment. Regarding the mounting surface of the semiconductor device, the number of semiconductor devices, the connection method of the semiconductor devices, etc. This is the same as the semiconductor package of the embodiment.
- 10 (a) to 10 (i) are partial cross-sectional views showing a method of manufacturing the wiring board 60 of this embodiment in the order of steps. Note that cleaning and heat treatment are appropriately performed between the respective steps.
- a resin substrate 30 on which the electrode 20 with the exposed surface is arranged is prepared.
- the electrode 20 only needs to have its surface exposed, and a part of the electrode 20 may be embedded in the resin insulating layer 10 or the entire electrode 20 may be embedded in the resin insulating layer 10.
- a metal film 72 is formed on the surface of the resin substrate 30.
- the metal film 72 is formed by sputtering.
- a resist material 99 is applied and cured on the metal film 72 by screen printing or the like.
- the metal film 72 near the electrode 20 is removed by etching.
- a first insulating layer 40 made of translucent ceramics is formed.
- metal oxide particles having a low electromagnetic wave absorptivity collide with a metal film forming surface at high speed the particles are miniaturized and bonded to each other to form a translucent oxide ceramic.
- the oxide ceramics having translucency can be formed.
- a conductive paste 52 is applied on the first insulating layer 40 and in the first through holes 41 provided in the first insulating layer 40.
- the subsequent steps are the same as those shown in FIG. 10 (g).
- the metal film 72 can be formed not only on the resin substrate 30 but also inside the first insulating layer 40.
- the metal film 72 may be formed on the surface, and the first insulating layer 40 may be further formed thereon.
- an electromagnetic wave irradiated for heating passes through the first insulating layer 40, is reflected by the metal film 72, and is emitted to the outside.
- the temperature rise of the first insulating layer 40 and the resin substrate 30 due to irradiation can be further suppressed.
- the electromagnetic wave reflected by the metal film 72 can also heat the back surface of the conductive paste 52. Since the conductive paste 52 is heated from both sides by the directly irradiated electromagnetic wave and the reflected electromagnetic wave, the bonding of adjacent conductive particles is ensured. Therefore, the highly reliable wiring 50 can be formed.
- FIG. 11 is a diagram showing a configuration of the wiring board 60 of the present embodiment.
- the difference from the first embodiment is that a third insulating layer 80 that covers the first insulating layer 40 and the wiring 50 is provided.
- the third insulating layer 80 only needs to be an insulating material, and is an organic insulating material such as an epoxy resin or polyimide, or an inorganic insulating material such as an oxide ceramic, as in a general wiring board. Also good.
- By covering the wiring 50 with the third insulating layer 80 it is possible to protect the wiring 50, and it is possible to form the wiring substrate 60 with good reliability and handling properties.
- the semiconductor package of the present embodiment is obtained by mounting a semiconductor device on the wiring board of the present embodiment.
- the semiconductor device 91 cannot be mounted on the wiring 50 as shown in FIG. However, as shown in FIG. 3A, it is possible to mount the semiconductor device 91 on the electrode 20 on the surface where the first insulating layer 40 is not provided.
- the semiconductor device connection method and the like are the same as those of the semiconductor package of the first embodiment.
- the manufacturing method of the present embodiment is realized by adding a step of forming the third insulating layer 80 so as to cover the wiring 50 and the first insulating layer 40 after the wiring 50 is sintered.
- the third insulating layer 80 is formed by, for example, applying a thermosetting insulating resin such as polyimide so as to cover the wiring 50 by heat-curing, as in a general insulating layer forming method. It can be formed.
- the third insulating layer 80 made of oxide ceramics may be formed by an aerosol deposition method (AD method).
- AD method aerosol deposition method
- FIG. 12 is a diagram showing a configuration of the wiring board 60 of the present embodiment.
- the wiring 50 is not limited to a single layer, and a wiring 50 having two or more layers can be formed.
- the wiring 50 is covered with a fourth insulating layer 81, and a fourth through hole 82 is formed in the fourth insulating layer 81.
- the wiring 50 can be provided in a plurality of layers.
- the wiring 50 can be heated at a high temperature and has a low specific resistance. Can do.
- the fourth insulating layer 81 may not be an oxide ceramic but may be an insulating material.
- the uppermost layer wiring is exposed, but an insulating layer covering the uppermost layer wiring may be provided.
- the wiring 50 can be multi-layered, the wiring can be easily routed and a semiconductor device having many connection electrodes can be mounted. Therefore, high-density mounting is possible.
- the semiconductor package of the present embodiment is obtained by mounting a semiconductor device on the wiring substrate of the present embodiment. Regarding the mounting surface of the semiconductor device, the number of semiconductor devices, the connection method of the semiconductor devices, etc. This is the same as the semiconductor package of the embodiment.
- FIG. 13A and FIG. 13B are diagrams showing the configuration of the wiring board 60 of the present embodiment.
- the fifth through hole 84 is provided in the fifth insulating layer 83 covering the uppermost wiring 50 and a part of the wiring 50 is exposed.
- the exposed wiring may be subjected to surface treatment by Ni / Au plating or the like, and this may be used as the external connection electrode 92. Further, as shown in FIG. 13B, by mounting a conductor 93 such as solder on the external connection electrode 92, it can be handled in the same manner as a general mounting component.
- the semiconductor package of the present embodiment is obtained by mounting a semiconductor device on the wiring substrate of the present embodiment. Regarding the mounting surface of the semiconductor device, the number of semiconductor devices, the connection method of the semiconductor devices, etc. This is the same as the semiconductor package of the embodiment.
- a semiconductor device can be mounted by providing a conductor such as solder on the external connection electrode 92.
- the semiconductor device connection method and the like are the same as those of the semiconductor package of the first embodiment.
- FIG. 14A is a diagram showing a configuration of the wiring board 60 of the present embodiment, and is a diagram schematically showing an enlarged cross section near the electrode 20 of the wiring board 60.
- the difference from the first embodiment is that the diameter of the crystal grains 98 constituting the first insulating layer is not uniform and changes in the thickness direction of the layer.
- the diameter of the crystal particles 98 in the layer close to the resin substrate 30 forms a dense structure of about several tens of nanometers, the diameter of the crystal particles 98 gradually increases, and the crystal of the layer in contact with the wiring on the upper surface of the first insulating layer
- the diameter of the particles 98 is a rough structure of about several hundred nanometers to several micrometers. Other structures are the same as those in the first embodiment.
- FIGS. 14B and 14C are diagrams schematically showing an enlarged portion where the wiring 50 and the first insulating layer 40 are in contact with each other.
- the layer in contact with the resin substrate 30 of the first insulating layer 40 should have a relatively small crystal grain size of about several tens of nanometers in order to improve the adhesion with the resin substrate 30.
- the layer of the first insulating layer 40 in contact with the wiring 50 should have a relatively large crystal grain size of about several hundred nanometers to several micrometers.
- the wiring 50 since the wiring 50 is formed by bonding particulate conductors, the wiring 50 has a larger particle diameter of the first insulating layer 40 in contact with the wiring 50. It becomes easy to enter the unevenness of the first insulating layer 40. As a result, an effect of increasing the adhesion strength between the wiring 50 and the first insulating layer 40 is obtained.
- the semiconductor package of the present embodiment is obtained by mounting a semiconductor device on the wiring substrate of the present embodiment. Regarding the mounting surface of the semiconductor device, the number of semiconductor devices, the connection method of the semiconductor devices, etc. This is the same as the semiconductor package of the embodiment.
- the speed of the particles to be collided is high in the initial stage of the stacking, and is gradually reduced in stages to thereby reduce the crystal in the initial stage of the stacking.
- the grain size forms a dense structure of about several tens of nanometers, the crystal grain size gradually increases, and the crystal grain size in the later stage of lamination becomes a coarse structure of about several hundred nanometers to several micrometers. Thereafter, wirings are stacked as in the first embodiment.
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Abstract
In a wiring board having wirings formed on a resin substrate using a conductive paste, heat generated at the time of sintering the conductive paste is transmitted to the resin substrate, so that a low heat-resistant temperature cannot be used for the resin substrate. Further, long heating at the time of sintering causes problems, such as warping of the resin substrate and deterioration of the mechanical characteristic thereof. In addition, sintering if performed at a low temperature to prevent warping of the resin substrate and deterioration of the mechanical characteristic thereof, the conductive paste may be sintered incompletely, thus increasing the conduction resistance of the sintered wirings. A layer of ceramic oxide is provided between the wiring and the resin substrate.
Description
［関連出願の記載］
本発明は、日本国特許出願：特願２００８－０８５４０３号（２００８年３月２８日出願）の優先権主張に基づくものであり、同出願の全記載内容は引用をもって本書に組み込み記載されているものとする。
本発明は、配線基板及びその製造方法に関し、特に導電粒子を含む導電性ペーストを用いて配線が形成される配線基板及びその製造方法に関する。また、本発明は、該配線基板を有する半導体パッケージに関する。 [Description of related applications]
The present invention is based on the priority claim of Japanese Patent Application: Japanese Patent Application No. 2008-085403 (filed on Mar. 28, 2008), the entire contents of which are incorporated herein by reference. Shall.
The present invention relates to a wiring board and a manufacturing method thereof, and more particularly to a wiring board on which wiring is formed using a conductive paste containing conductive particles and a manufacturing method thereof. The present invention also relates to a semiconductor package having the wiring board.
本発明は、日本国特許出願：特願２００８－０８５４０３号（２００８年３月２８日出願）の優先権主張に基づくものであり、同出願の全記載内容は引用をもって本書に組み込み記載されているものとする。
本発明は、配線基板及びその製造方法に関し、特に導電粒子を含む導電性ペーストを用いて配線が形成される配線基板及びその製造方法に関する。また、本発明は、該配線基板を有する半導体パッケージに関する。 [Description of related applications]
The present invention is based on the priority claim of Japanese Patent Application: Japanese Patent Application No. 2008-085403 (filed on Mar. 28, 2008), the entire contents of which are incorporated herein by reference. Shall.
The present invention relates to a wiring board and a manufacturing method thereof, and more particularly to a wiring board on which wiring is formed using a conductive paste containing conductive particles and a manufacturing method thereof. The present invention also relates to a semiconductor package having the wiring board.
電子機器の小型・軽量・薄型化に伴い、配線基板の薄型化や配線の微細化の要求が高まっている。
As electronic devices become smaller, lighter and thinner, there is an increasing demand for thinner wiring boards and finer wiring.
特許文献１に記載されている多層配線板では、金属微粒子を含む導電性ペーストを用いて回路パターンを形成している。すなわち、平均粒子径７ｎｍの銀ナノ粒子が凝集しないように調整された導電性ペーストで、ビアホールを設けたコア基板の表面上に回路パターンを描画すると共に、銀ナノ粒子をビアホールに充填した後、２５０℃以下で加熱処理を行うことにより、銀の焼結体よりなる回路パターンを形成する。さらに、回路パターン表面をフォトレジストで覆い、そのフォトレジストの一部にビアホールを形成する。その後、導電性ペーストで回路パターンを描画すると共に、銀ナノ粒子をビアホールに充填した後、加熱処理という工程を繰り返して、多層配線板を得ている。
In the multilayer wiring board described in Patent Document 1, a circuit pattern is formed using a conductive paste containing metal fine particles. That is, after drawing a circuit pattern on the surface of the core substrate provided with via holes with a conductive paste adjusted so that silver nanoparticles having an average particle diameter of 7 nm do not aggregate, and filling the via holes with silver nanoparticles, By performing heat treatment at 250 ° C. or lower, a circuit pattern made of a silver sintered body is formed. Further, the surface of the circuit pattern is covered with a photoresist, and a via hole is formed in a part of the photoresist. Then, while drawing a circuit pattern with an electrically conductive paste and filling a silver hole with a via hole, the process of heat processing is repeated and the multilayer wiring board is obtained.
特許文献２に記載されている微細配線パターンの形成方法においては、ポリイミドなどの高い耐熱性を有するポリマー材料で構成された転写シート表面に、ペースト状銀ナノ粒子分散液で配線の描画を行い、２５０℃４０分の加熱処理を行うことで、銀ナノ粒子の焼結体層からなる配線を形成している。そして、形成された配線を、接着層を有するセラミック基板上に重ね合わせ、加熱加圧して押しつけることにより、セラミック基板上に転写し、セラミック基板上に配線を有するプリント基板を得ている。
In the method of forming a fine wiring pattern described in Patent Document 2, a wiring is drawn with a paste-like silver nanoparticle dispersion on a transfer sheet surface composed of a polymer material having high heat resistance such as polyimide, By performing a heat treatment at 250 ° C. for 40 minutes, a wiring composed of a sintered body layer of silver nanoparticles is formed. Then, the formed wiring is superimposed on a ceramic substrate having an adhesive layer, heated and pressed to be pressed, and transferred onto the ceramic substrate to obtain a printed board having the wiring on the ceramic substrate.
なお、上記特許文献１、２の全開示内容はその引用をもって本書に繰込み記載する。以下の分析は、本発明によって与えられたものである。
特許文献１に記載されている多層配線板は、コア基板上に直接回路パターンを形成し、回路パターンを構成するときに銀ナノペーストを加熱処理して焼結させている。そのため、焼結時の熱がコア基板に伝熱されてしまうので、コア基板に耐熱温度の低い材料を使用できない。また、コア基板として、エポキシ、ポリイミドなどの熱硬化性樹脂を使用しているが、焼結時の長時間の加熱により、基板の反りや機械的特性の劣化などの不具合が生じる。 The entire disclosures ofPatent Documents 1 and 2 are incorporated herein by reference. The following analysis is given by the present invention.
In the multilayer wiring board described inPatent Document 1, a circuit pattern is directly formed on a core substrate, and silver nanopaste is heated and sintered when the circuit pattern is formed. Therefore, heat at the time of sintering is transferred to the core substrate, so that a material having a low heat-resistant temperature cannot be used for the core substrate. Moreover, although thermosetting resins such as epoxy and polyimide are used as the core substrate, problems such as warpage of the substrate and deterioration of mechanical characteristics occur due to long-time heating during sintering.
特許文献１に記載されている多層配線板は、コア基板上に直接回路パターンを形成し、回路パターンを構成するときに銀ナノペーストを加熱処理して焼結させている。そのため、焼結時の熱がコア基板に伝熱されてしまうので、コア基板に耐熱温度の低い材料を使用できない。また、コア基板として、エポキシ、ポリイミドなどの熱硬化性樹脂を使用しているが、焼結時の長時間の加熱により、基板の反りや機械的特性の劣化などの不具合が生じる。 The entire disclosures of
In the multilayer wiring board described in
また、特許文献２によれば、高い耐熱性を有するポリマー材料上構成された転写シート上で、配線を形成させるための焼結を行うため、転写シートは機械的特性が劣化しない。
Further, according to Patent Document 2, since the sintering for forming the wiring is performed on the transfer sheet formed on the polymer material having high heat resistance, the transfer sheet does not deteriorate the mechanical characteristics.
しかしながら、転写シートに用いられている高い耐熱性を有する樹脂を基板の絶縁材料として使用すると、その樹脂自体の調達コストが高くなる。さらに、高い耐熱性を有する樹脂を使用した基板では、その製造時に、高温にて樹脂を硬化させる必要があるので、製造コストも高くなり、歩留まりも悪くなる。よって、基板の絶縁材料として、高い耐熱性を有する樹脂を使用することは、量産に向かないという課題があった。
However, if a resin having high heat resistance used for the transfer sheet is used as the insulating material for the substrate, the procurement cost of the resin itself increases. Further, in a substrate using a resin having high heat resistance, it is necessary to cure the resin at a high temperature at the time of manufacture, so that the manufacturing cost is increased and the yield is also deteriorated. Therefore, there is a problem that using a resin having high heat resistance as an insulating material for the substrate is not suitable for mass production.
また、絶縁層として高い耐熱性を有しない樹脂を用いた基板の上に特許文献２の転写シートに使用されている高い耐熱性を有する樹脂を設ける事も考えられるが転写シートに使用されている樹脂では断熱性を有しないため、焼結時の熱が転写シートを介して樹脂材料に伝熱され、樹脂材料の機械的特性が劣化し、反りなどの不具合が生じるという課題は依然解決できない。
In addition, it is possible to provide a resin having high heat resistance used in the transfer sheet of Patent Document 2 on a substrate using a resin that does not have high heat resistance as an insulating layer, but it is used in the transfer sheet. Since the resin does not have heat insulation, the problem that heat at the time of sintering is transferred to the resin material through the transfer sheet, the mechanical properties of the resin material are deteriorated, and problems such as warping still cannot be solved.
上記課題を解決するため、本発明の第１視点によれば、本発明の配線基板は樹脂絶縁層と、樹脂絶縁層の表面に設けられている電極と、を有する樹脂基板と、樹脂基板上に設けられた第１の絶縁層と、電極上の第１の絶縁層に設けられた第１の貫通孔と、第１の絶縁層上および第１の貫通孔内に設けられた配線と、を有する配線基板が提供される。配線は電極と電気的に接する。配線は隣接した導電粒子が互いに接合した導電体からなる。第１の絶縁層は酸化物セラミックスからなる。
In order to solve the above-described problem, according to a first aspect of the present invention, a wiring board of the present invention includes a resin insulating layer, a resin substrate having an electrode provided on the surface of the resin insulating layer, and a resin substrate. A first insulating layer provided on the first insulating layer; a first through hole provided in the first insulating layer on the electrode; a wiring provided on the first insulating layer and in the first through hole; A wiring board having the following is provided. The wiring is in electrical contact with the electrode. The wiring is made of a conductor in which adjacent conductive particles are joined to each other. The first insulating layer is made of an oxide ceramic.
また、上記第１視点の好ましい形態によれば、配線は導電粒子と有機化合物を含有した導電性ペーストを焼結させた焼結体である。
Further, according to a preferred form of the first aspect, the wiring is a sintered body obtained by sintering a conductive paste containing conductive particles and an organic compound.
さらに、上記第１視点の好ましい形態によれば、第１の絶縁層はアルミナ、シリカ、スピネル、ムライト、コーディエライト、ジルコニア、ジルコンからなる群から選択された少なくとも１種の酸化物セラミックスからなる。
Furthermore, according to the preferable form of the first aspect, the first insulating layer is made of at least one oxide ceramic selected from the group consisting of alumina, silica, spinel, mullite, cordierite, zirconia, and zircon. .
さらに、上記第１視点の好ましい形態によれば、配線基板は、樹脂基板表面に設けられソルダーレジストとしての機能を有するソルダーレジスト層をさらに有する。
Furthermore, according to a preferable mode of the first aspect, the wiring board further includes a solder resist layer provided on the surface of the resin substrate and having a function as a solder resist.
さらに、上記第１視点の好ましい形態によれば、第１の絶縁層と樹脂基板の間に設けられた第２の絶縁層と、電極上の第２の絶縁層に設けられた第２の貫通孔と、をさらに有する。
Furthermore, according to the preferable form of the first aspect, the second insulating layer provided between the first insulating layer and the resin substrate, and the second penetration provided in the second insulating layer on the electrode. And a hole.
さらに、上記第１視点の好ましい形態によれば、配線基板は、樹脂基板と、第１の絶縁層上の配線との間に金属膜をさらに有する。第１の絶縁層は透光性を有する酸化物セラミックスからなる。金属膜は第１の絶縁層または樹脂絶縁層に被覆されている。
Furthermore, according to a preferable mode of the first aspect, the wiring board further includes a metal film between the resin substrate and the wiring on the first insulating layer. The first insulating layer is made of a translucent oxide ceramic. The metal film is covered with the first insulating layer or the resin insulating layer.
さらに、上記第１視点の好ましい形態によれば、配線基板は、配線及び第１の絶縁層を被覆する第３の絶縁層をさらに有する。
Furthermore, according to a preferable mode of the first aspect, the wiring board further includes a third insulating layer covering the wiring and the first insulating layer.
さらに、上記第１視点の好ましい形態によれば、第３の絶縁層が酸化物セラミックスからなる。第３の絶縁層に第３の貫通孔が設けられる。第３の絶縁層上および第３の貫通孔内に配線が設けられる。配線と酸化物セラミックスからなる層が複数積層されている。
Furthermore, according to a preferred embodiment of the first aspect, the third insulating layer is made of an oxide ceramic. A third through hole is provided in the third insulating layer. Wiring is provided on the third insulating layer and in the third through hole. A plurality of layers made of wiring and oxide ceramics are laminated.
さらに、上記第１視点の好ましい形態によれば、第３の絶縁層に第３の貫通孔が設けられる。第３の貫通孔の内部に外部接続電極が設けられる。外部接続電極と配線が電気的に接している。
Furthermore, according to a preferable mode of the first aspect, the third through hole is provided in the third insulating layer. An external connection electrode is provided inside the third through hole. The external connection electrode and the wiring are in electrical contact.
さらに、上記第１視点の好ましい形態によれば、外部接続電極上に導体が設けられている。
Furthermore, according to a preferred embodiment of the first aspect, a conductor is provided on the external connection electrode.
さらに、上記第１視点の好ましい形態によれば、第１の絶縁層は、粒子状の結晶を含む多結晶構造を有する酸化物セラミックスからなる。結晶の粒径は第１の絶縁層の厚さ方向に変化する。第１の絶縁層上に設けられた配線に接する結晶の粒径は、樹脂基板に接する結晶の粒径よりも大きい。
Furthermore, according to a preferred embodiment of the first aspect, the first insulating layer is made of oxide ceramics having a polycrystalline structure including particulate crystals. The crystal grain size changes in the thickness direction of the first insulating layer. The crystal grain size in contact with the wiring provided on the first insulating layer is larger than the crystal grain size in contact with the resin substrate.
本発明の第２視点によれば、本発明の半導体パッケージは、本発明の配線基板に少なくとも１つの半導体装置が搭載されていることを特徴とする。
According to a second aspect of the present invention, the semiconductor package of the present invention is characterized in that at least one semiconductor device is mounted on the wiring board of the present invention.
また、上記第２視点の好ましい形態によれば、配線が導体を介して半導体装置と導通している。
In addition, according to the preferable mode of the second aspect, the wiring is electrically connected to the semiconductor device through the conductor.
本発明の第３視点によれば、本発明の配線基板の製造方法は、樹脂基板上に酸化物セラミックスからなる第１の絶縁層を形成する工程と、第１の絶縁層に第１の貫通孔を形成する工程と、第１の絶縁層上と第１の貫通孔内に、導電性ペーストを配置する工程と、導電性ペーストを加熱する工程と、を含む。
According to a third aspect of the present invention, a method for manufacturing a wiring board according to the present invention includes a step of forming a first insulating layer made of an oxide ceramic on a resin substrate, and a first penetration through the first insulating layer. A step of forming a hole, a step of disposing a conductive paste on the first insulating layer and in the first through hole, and a step of heating the conductive paste.
さらに、上記第３視点の好ましい形態によれば、樹脂基板上に酸化物セラミックスからなる第１の絶縁層を形成する工程と、第１の絶縁層に第１の貫通孔を形成する工程とは、第１の貫通孔が設けられているセラミックシートを樹脂基板に接着する工程である。
Furthermore, according to a preferred embodiment of the third aspect, the step of forming the first insulating layer made of oxide ceramics on the resin substrate and the step of forming the first through hole in the first insulating layer are: In this step, the ceramic sheet provided with the first through hole is bonded to the resin substrate.
さらに、上記第３視点の好ましい形態によれば、樹脂基板上に酸化物セラミックスからなる第１の絶縁層を形成する工程と、第１の絶縁層に第１の貫通孔を形成する工程とは、樹脂基板上に酸化物セラミックスからなるペーストの一部を転写する工程である。
Furthermore, according to a preferred embodiment of the third aspect, the step of forming the first insulating layer made of oxide ceramics on the resin substrate and the step of forming the first through hole in the first insulating layer are: In this step, a part of the paste made of oxide ceramics is transferred onto the resin substrate.
さらに、上記第３視点の好ましい形態によれば、本発明の配線基板の製造方法は、酸化物セラミックスからなる第１の絶縁層を形成する工程の前に、樹脂基板上に金属膜を形成する工程と、金属膜の一部を除去する工程と、をさらに含む。
Furthermore, according to the preferable form of the third aspect, the method for manufacturing a wiring board of the present invention forms a metal film on the resin substrate before the step of forming the first insulating layer made of oxide ceramics. And a step of removing a part of the metal film.
さらに、上記第３視点の好ましい形態によれば、第１の絶縁層を形成する工程はエアロゾルデポジション法である。
Furthermore, according to a preferred embodiment of the third aspect, the step of forming the first insulating layer is an aerosol deposition method.
さらに、上記第３視点の好ましい形態によれば、配線基板に噴射する第１の絶縁層の原料微粒子の噴射速度を、段階的に遅くする。
Furthermore, according to the preferable form of the third aspect, the spraying speed of the raw material fine particles of the first insulating layer sprayed onto the wiring board is decreased in stages.
以上説明したように本発明によれば、導電性ペーストを加熱し配線を形成させる時に、十分な加熱が可能となるため、電気的な導通が十分に確保できる配線を有する配線基板を提供することが可能となる。
As described above, according to the present invention, when a conductive paste is heated to form a wiring, sufficient heating is possible, and thus a wiring board having a wiring that can sufficiently secure electrical conduction is provided. Is possible.
以下、図面を参照し、本発明の実施の形態について詳細に説明する。
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
（第１の実施の形態）
(First embodiment)
本発明の第１の実施の形態である配線基板について説明する。
A wiring board according to the first embodiment of the present invention will be described.
図１は、本実施の形態の配線基板６０の構成を示す図であり、図１（ａ）は配線基板６０を配線５０が設けられている面から見た平面図であり、図１（ｂ）は図１（ａ）のＡ－Ａ線に沿った垂直方向の断面図であり、図１（ｃ）は図１（ｂ）のＢ－Ｂ線に沿った平面方向の断面図である。図２は、配線基板６０の電極２０近傍の拡大断面図である。
FIG. 1 is a diagram illustrating a configuration of a wiring board 60 according to the present embodiment, and FIG. 1A is a plan view of the wiring board 60 as viewed from the side where the wiring 50 is provided, and FIG. ) Is a vertical cross-sectional view along the line AA in FIG. 1A, and FIG. 1C is a cross-sectional view in the plane direction along the line BB in FIG. 1B. FIG. 2 is an enlarged cross-sectional view of the vicinity of the electrode 20 of the wiring board 60.
図１に示す配線基板６０は、樹脂基板３０と、第１の絶縁層４０と、配線５０と、を備える。
1 includes a resin substrate 30, a first insulating layer 40, and wiring 50.
樹脂基板３０は、樹脂絶縁層１０と、樹脂絶縁層１０の表面に設けられている電極２０と、を備える。
The resin substrate 30 includes a resin insulating layer 10 and an electrode 20 provided on the surface of the resin insulating layer 10.
樹脂絶縁層１０は、例えば、エポキシ樹脂、ポリイミド樹脂、エポキシアクリレート樹脂、ウレタンアクリレート樹脂、ポリエステル樹脂、フェノール樹脂、ＢＣＢ（ｂｅｎｚｏｃｙｃｌｏｂｕｔｅｎｅ）及びＰＢＯ（ｐｏｌｙｂｅｎｚｏｘａｚｏｌｅ）からなる群から選択された１種又は２種以上の絶縁樹脂により形成されている。
The resin insulating layer 10 is, for example, one or more selected from the group consisting of epoxy resin, polyimide resin, epoxy acrylate resin, urethane acrylate resin, polyester resin, phenol resin, BCB (benzocycle) and PBO (polybenzoxole). The insulating resin is used.
また、絶縁樹脂層１０の内部には内層配線２１が設けられていても良く、それぞれの内層配線２１や電極２０はビア（図示せず）によって、電気的に接続されていてもよい。
Further, the inner layer wiring 21 may be provided inside the insulating resin layer 10, and each inner layer wiring 21 and the electrode 20 may be electrically connected by a via (not shown).
図２に示されている電極２０は、その側面が樹脂絶縁層１０に完全に埋め込まれており、配線５０と接する電極２０の面が、第１の絶縁層４０と接する樹脂絶縁層１０の面と同一な面となっている。しかしながら、本実施の形態の配線基板６０においては、配線５０と接する電極２０の面は、第１の絶縁層４０と接する樹脂絶縁層１０の面と同一平面をなしていなくてもよく、樹脂絶縁層１０の面に対して凹んだ面になっていても、凸面になっていても良い。
The side surface of the electrode 20 shown in FIG. 2 is completely embedded in the resin insulating layer 10, and the surface of the electrode 20 in contact with the wiring 50 is the surface of the resin insulating layer 10 in contact with the first insulating layer 40. It is the same surface as. However, in the wiring substrate 60 of the present embodiment, the surface of the electrode 20 in contact with the wiring 50 may not be flush with the surface of the resin insulating layer 10 in contact with the first insulating layer 40. It may be a concave surface or a convex surface with respect to the surface of the layer 10.
第１の絶縁層４０は、酸化物セラミックスからなり、樹脂基板３０上に設けられ、電極２０上に、第１の貫通孔４１を有する。
The first insulating layer 40 is made of oxide ceramics, is provided on the resin substrate 30, and has a first through hole 41 on the electrode 20.
第１の絶縁層４０は、熱伝導率の低く、絶縁樹脂よりも耐熱温度が高い、酸化物セラミックスで形成されている。本発明の酸化物セラミックスとは、例えば、アルミナ（Ａｌ２Ｏ３）、シリカ（ＳｉＯ２）、スピネル（ＭｇＡｌ２Ｏ４）、ムライト（３Ａｌ２Ｏ３・２ＳｉＯ２）、コーディエライト（２ＭｇＯ・２Ａｌ２Ｏ３・５ＳｉＯ２）、ジルコニア（ＺｒＯ２）、ジルコン（ＺｒＳｉＯ４）、ＰＬＺＴ（（Ｐｂ，Ｌａ）（Ｚｒ，Ｔｉ）Ｏ３）、イットリア－トリア（Ｙ２Ｏ３－ＴｈＯ２）等のことであり、アルミニウム、珪素、マグネシウム、ジルコニウム、鉛、ランタン、チタン、イットリウム、トリウム、ホウ素、カルシウム、セリウムから選択された１種または２種以上の元素の金属酸化物であると好ましい。また、第１の絶縁層４０は１種類の酸化物セラミックスからなっていても良く、２種類以上の酸化物セラミックスが混合されているものであっても良い。
The first insulating layer 40 is made of an oxide ceramic having a low thermal conductivity and a heat resistant temperature higher than that of the insulating resin. The oxide ceramics of the present invention, for example, alumina (Al 2 O 3), silica (SiO 2), spinel (MgAl 2 O 4), mullite (3Al 2 O 3 · 2SiO 2 ), cordierite (2MgO · 2Al 2 O 3 .5SiO 2 ), zirconia (ZrO 2 ), zircon (ZrSiO 4 ), PLZT ((Pb, La) (Zr, Ti) O 3 ), yttria-tria (Y 2 O 3 —ThO 2 ), etc. It is preferably a metal oxide of one or more elements selected from aluminum, silicon, magnesium, zirconium, lead, lanthanum, titanium, yttrium, thorium, boron, calcium, and cerium. The first insulating layer 40 may be made of one kind of oxide ceramics, or may be a mixture of two or more kinds of oxide ceramics.
配線５０は、第１の絶縁層４０上および第１の貫通孔４１内に設けられており、電極２０と電気的に接している。
The wiring 50 is provided on the first insulating layer 40 and in the first through hole 41, and is in electrical contact with the electrode 20.
図２に示すように、配線５０は隣接した導電粒子が互いに接合した導電体であり、有機溶媒と導電粒子を含む導電性ペーストを加熱して焼結させた焼結体である。この配線５０は、焼結時の熱により導電粒子の表面が溶融し、隣接する導電粒子の溶融部分が接合した状態で冷却され、溶融部分が固まることにより形成される。また、有機溶媒は焼結時の熱により蒸発する。
As shown in FIG. 2, the wiring 50 is a conductor in which adjacent conductive particles are joined to each other, and is a sintered body obtained by heating and sintering a conductive paste containing an organic solvent and conductive particles. The wiring 50 is formed by the surface of the conductive particles being melted by the heat at the time of sintering, being cooled in a state where the melted portions of the adjacent conductive particles are joined, and the melted portion solidifying. The organic solvent evaporates due to heat during sintering.
なお、本願図面に記載されている配線５０を形成する導電粒子は、いずれも整列された状態のものが図示されているが、これらは導電粒子を模式的に表したものである。本願発明の配線５０を形成する導電粒子は整列されたものに限るものではなく、その配置に規則性が無いものであっても良い。
In addition, although all the conductive particles forming the wiring 50 described in the drawings of the present application are shown in an aligned state, these are schematic representations of the conductive particles. The conductive particles forming the wiring 50 of the present invention are not limited to the aligned particles, and the arrangement thereof may have no regularity.
この導電粒子には、例えば、金、銀、銅、白金、パラジウム、ロジウム、オスミウム、ルテニウム、イリジウム、鉄、錫、亜鉛、コバルト、ニッケル、クロム、チタン、タンタル、タングステン、インジウム、ケイ素の中の少なくとも１種類の金属、または２種類以上の金属からなる合金が用いられる。また、この導電粒子の粒径は１ナノメートルから１００ナノメートルであると好ましい。
Examples of the conductive particles include gold, silver, copper, platinum, palladium, rhodium, osmium, ruthenium, iridium, iron, tin, zinc, cobalt, nickel, chromium, titanium, tantalum, tungsten, indium, and silicon. An alloy made of at least one kind of metal or two or more kinds of metals is used. The conductive particles preferably have a particle size of 1 nanometer to 100 nanometers.
本実施の形態である配線基板によれば、熱伝導率の低い酸化物セラミックスからなる第１の絶縁層４０を樹脂基板３０の上に設けているため、導電粒子の焼結体である配線を得るための焼結時の熱が、耐熱温度の低い樹脂基板３０に伝わりにくい。よって、配線焼結時において樹脂基板３０の温度上昇を抑制することが可能となり、樹脂基板３０の温度上昇による劣化が小さい配線基板を得ることが可能となる。
According to the wiring substrate of the present embodiment, the first insulating layer 40 made of oxide ceramics having low thermal conductivity is provided on the resin substrate 30. Therefore, the wiring that is a sintered body of conductive particles is provided. Heat at the time of sintering is difficult to be transmitted to the resin substrate 30 having a low heat-resistant temperature. Therefore, it is possible to suppress the temperature rise of the resin substrate 30 during wiring sintering, and it is possible to obtain a wiring substrate with little deterioration due to the temperature rise of the resin substrate 30.
次に、本発明の第１の実施の形態の配線基板を用いた半導体パッケージについて説明する。
Next, a semiconductor package using the wiring board according to the first embodiment of the present invention will be described.
図３（ａ）および図３（ｂ）は、本実施の形態の半導体パッケージ９０の構成を示す図であり、本実施の形態の配線基板６０上に半導体装置９１を搭載させたものである。図３（ａ）は、第１の絶縁層４０とは接していない樹脂基板３０の面に設けられた電極２０に半導体装置９１を搭載したものである。電極２０上にハンダなどの導体９３を設け、半導体装置９１と配線基板６０が電気的に導通している。
3 (a) and 3 (b) are diagrams showing the configuration of the semiconductor package 90 of the present embodiment, in which the semiconductor device 91 is mounted on the wiring substrate 60 of the present embodiment. FIG. 3A shows a semiconductor device 91 mounted on the electrode 20 provided on the surface of the resin substrate 30 that is not in contact with the first insulating layer 40. A conductor 93 such as solder is provided on the electrode 20 so that the semiconductor device 91 and the wiring board 60 are electrically connected.
また、図３（ｂ）は配線基板６０の第１の絶縁層４０上に半導体装置９１を搭載したものである。配線５０上にハンダなどの導体９３を設け、半導体装置９１と配線基板６０が電気的に導通している。
FIG. 3B shows the semiconductor device 91 mounted on the first insulating layer 40 of the wiring board 60. A conductor 93 such as solder is provided on the wiring 50, and the semiconductor device 91 and the wiring substrate 60 are electrically connected.
半導体装置９１と配線基板６０は、種々の方式で電気的に導通させることが可能であり、たとえば、フリップチップ、ワイヤーボンディング、テープボンディングなどで電気的に接続させることができる。
The semiconductor device 91 and the wiring board 60 can be electrically connected by various methods, and can be electrically connected by, for example, flip chip, wire bonding, tape bonding, or the like.
半導体装置９１は１つであっても複数であっても良く、図３（ａ）と図３（ｂ）を組み合わせ配線基板６０の両面に半導体装置９１を搭載したものであっても良い。
The semiconductor device 91 may be one or plural, and the semiconductor device 91 may be mounted on both surfaces of the wiring board 60 by combining FIG. 3A and FIG.
本実施の形態である半導体パッケージ９０によれば、酸化物セラミックスからなる第１の絶縁層４０と半導体装置９１の熱膨張率が近い値を有することとなる。そのため、周囲の温度変化や半導体装置の動作などによって発生した熱によって、第１の絶縁層４０と半導体装置９１が熱膨張したとしても、その熱膨張量は近い値となる。よって、この半導体パッケージ９０は、高い信頼性を有することが出来る。
According to the semiconductor package 90 according to the present embodiment, the thermal expansion coefficients of the first insulating layer 40 made of oxide ceramics and the semiconductor device 91 are close to each other. Therefore, even if the first insulating layer 40 and the semiconductor device 91 are thermally expanded due to heat generated due to a change in ambient temperature, operation of the semiconductor device, or the like, the amount of thermal expansion becomes a close value. Therefore, the semiconductor package 90 can have high reliability.
次に、本発明の第１の実施の形態である配線基板の製造方法について説明する。
図４（ａ）から（ｅ）は、本実施の形態の配線基板６０の製造方法を工程順に示す部分断面図である。この断面図は、配線５０が接続される電極２０付近を拡大した図である。なお、各工程間において、適宜洗浄および熱処理を行う。 Next, the manufacturing method of the wiring board which is the 1st Embodiment of this invention is demonstrated.
FIGS. 4A to 4E are partial cross-sectional views showing the method of manufacturing thewiring board 60 of the present embodiment in the order of steps. This sectional view is an enlarged view of the vicinity of the electrode 20 to which the wiring 50 is connected. Note that cleaning and heat treatment are appropriately performed between the respective steps.
図４（ａ）から（ｅ）は、本実施の形態の配線基板６０の製造方法を工程順に示す部分断面図である。この断面図は、配線５０が接続される電極２０付近を拡大した図である。なお、各工程間において、適宜洗浄および熱処理を行う。 Next, the manufacturing method of the wiring board which is the 1st Embodiment of this invention is demonstrated.
FIGS. 4A to 4E are partial cross-sectional views showing the method of manufacturing the
まず、図４（ａ）に示すように、表面に電極２０を有する樹脂基板３０を用意する。
First, as shown in FIG. 4A, a resin substrate 30 having electrodes 20 on the surface is prepared.
次に、図４（ｂ）に示すように、電極２０上に第１の貫通孔４１を有する第１の絶縁層４０を形成する。たとえば、エアロゾルデポジション法（ＡＤ法）を用いて、酸化物セラミックスからなる第１の絶縁層４０を形成する。このとき、電極２０上に予めマスク（図示せず）を設けておき、ＡＤ法による第１の絶縁層４０の形成が完了した後に、マスクを除去することにより、電極２０上に第１の貫通孔４１を形成しても良い。また、ＡＤ法により、樹脂基板３０上の全面に第１の絶縁層４０を形成した後に、超音波精密加工などの機械加工により電極２０上に第１の貫通孔４１を形成しても良い。
Next, as shown in FIG. 4B, a first insulating layer 40 having a first through hole 41 is formed on the electrode 20. For example, the first insulating layer 40 made of oxide ceramics is formed using an aerosol deposition method (AD method). At this time, a mask (not shown) is provided on the electrode 20 in advance, and after the formation of the first insulating layer 40 by the AD method is completed, the mask is removed, whereby the first penetration is formed on the electrode 20. The hole 41 may be formed. Alternatively, the first through-hole 41 may be formed on the electrode 20 by mechanical processing such as ultrasonic precision processing after the first insulating layer 40 is formed on the entire surface of the resin substrate 30 by the AD method.
次に、図４（ｃ）に示すように、酸化物セラミックスからなる第１の絶縁層４０上と、第１の絶縁層４０に設けられた第１の貫通孔４１内に、導電性ペースト５２を塗布する。
導電性ペースト５２を塗布する方法としては、例えば、インクジェット法、ディスペンス法、スクリーン印刷法、凸版印刷法、インプリント法等を用いることができる。例えば、インクジェット法によれば、導電性ペーストを塗布可能なヘッドを有する装置を用いて、第１の絶縁層４０上、および、第１の絶縁層４０に設けられた第１の貫通孔４１内に導電性ペースト５２を塗布する。塗布された導電性ペースト５２は点で描画され、その点を連続して塗布することにより、点を連結させて配線を形成してもよい。 Next, as shown in FIG. 4C, aconductive paste 52 is formed on the first insulating layer 40 made of oxide ceramics and in the first through hole 41 provided in the first insulating layer 40. Apply.
As a method for applying theconductive paste 52, for example, an inkjet method, a dispensing method, a screen printing method, a relief printing method, an imprinting method, or the like can be used. For example, according to the inkjet method, using a device having a head capable of applying a conductive paste, on the first insulating layer 40 and in the first through hole 41 provided in the first insulating layer 40. A conductive paste 52 is applied to the substrate. The applied conductive paste 52 may be drawn with dots, and the dots may be continuously applied to connect the dots to form a wiring.
導電性ペースト５２を塗布する方法としては、例えば、インクジェット法、ディスペンス法、スクリーン印刷法、凸版印刷法、インプリント法等を用いることができる。例えば、インクジェット法によれば、導電性ペーストを塗布可能なヘッドを有する装置を用いて、第１の絶縁層４０上、および、第１の絶縁層４０に設けられた第１の貫通孔４１内に導電性ペースト５２を塗布する。塗布された導電性ペースト５２は点で描画され、その点を連続して塗布することにより、点を連結させて配線を形成してもよい。 Next, as shown in FIG. 4C, a
As a method for applying the
次に、図４（ｄ）に示すように、第１の絶縁層４０上の導電性ペースト５２を加熱して導電粒子を焼結する。導電性ペースト５２を塗布した面に対して、電磁波を照射し、その吸収特性を利用し加熱を行う。電磁波の波長を導電性ペースト５２の吸収波長に調整して照射すると、導電性ペースト５２の温度は上昇する。焼結条件としては、例えば、温度が２００℃から３００℃であって、時間は２時間行う。なお、これらの焼結条件は、これに限られるものではなく、適宜変更することが可能である。
Next, as shown in FIG. 4D, the conductive paste 52 on the first insulating layer 40 is heated to sinter the conductive particles. The surface coated with the conductive paste 52 is irradiated with electromagnetic waves and heated using its absorption characteristics. When the electromagnetic wave wavelength is adjusted to the absorption wavelength of the conductive paste 52 and irradiated, the temperature of the conductive paste 52 rises. As sintering conditions, for example, the temperature is 200 ° C. to 300 ° C., and the time is 2 hours. In addition, these sintering conditions are not restricted to this, It is possible to change suitably.
図４（ｅ）に示すように、加熱が完了すると、隣接した導電粒子同士が互いに接合した導電体からなる配線５０を有する配線基板６０を得ることができる。
As shown in FIG. 4E, when heating is completed, a wiring substrate 60 having a wiring 50 made of a conductor in which adjacent conductive particles are bonded to each other can be obtained.
本実施の形態である配線基板の製造方法によれば、耐熱温度の低い絶縁樹脂を有する樹脂基板上に、熱伝導率の低い酸化物セラミックスからなる第１の絶縁層４０を設け、その第１の絶縁層上に導電性ペーストを塗布する。
According to the method for manufacturing a wiring board according to the present embodiment, a first insulating layer 40 made of oxide ceramics having a low thermal conductivity is provided on a resin substrate having an insulating resin having a low heat-resistant temperature. A conductive paste is applied on the insulating layer.
その後、導電性ペーストに加えられる熱は、第１の絶縁層４０によって樹脂基板３０に伝熱されることが抑制される。よって、樹脂基板３０の温度上昇を抑えつつ、導電性ペーストを十分加熱させることが可能となるため、十分な導通が確保された配線を有する配線基板を製造することが可能となる。
Thereafter, heat applied to the conductive paste is suppressed from being transferred to the resin substrate 30 by the first insulating layer 40. Therefore, it is possible to sufficiently heat the conductive paste while suppressing the temperature rise of the resin substrate 30, and thus it is possible to manufacture a wiring substrate having wiring that ensures sufficient conduction.
第１の絶縁層が設けられていない場合、導電性ペーストに加えられた熱は、樹脂基板に直に伝熱されるため、樹脂基板の温度上昇が顕著となり、樹脂絶縁層の反りや物性劣化を生じさせてしまう。もしくは、樹脂基板の物性劣化を防止するために導電性ペーストの加熱を抑制すると、焼結が不十分となり、配線の導通に不具合が生じる恐れがある。
When the first insulating layer is not provided, the heat applied to the conductive paste is directly transferred to the resin substrate, so that the temperature rise of the resin substrate becomes significant, causing the resin insulating layer to warp and deteriorate physical properties. It will cause it. Alternatively, if the heating of the conductive paste is suppressed in order to prevent deterioration of the physical properties of the resin substrate, the sintering becomes insufficient and there may be a problem in wiring conduction.
特許文献２に記載されている配線の形成方法によれば、配線は転写シート上に別工程にて作成されている。転写シート上にて焼結された後、配線はセラミック基板上に転写される。しかしながら、配線幅が最大でも数十ミクロンメートルと大変細い配線は、機械的強度が低く、脆いために、転写する際の応力により、断線する可能性が高いという課題があった。
According to the wiring formation method described in Patent Document 2, the wiring is created in a separate process on the transfer sheet. After being sintered on the transfer sheet, the wiring is transferred onto the ceramic substrate. However, a very thin wiring having a wiring width of several tens of micrometers at the maximum has a low mechanical strength and is brittle. Therefore, there is a problem that there is a high possibility of disconnection due to a stress during transfer.
本実施の形態である配線基板の製造方法によれば、耐熱温度の低い絶縁樹脂を有する基板上に直接、導電粒子を含む導電性ペーストを塗布して形成した配線を有する配線基板を製造することが可能となるので、転写による断線が生じることはないという効果がある。
According to the method for manufacturing a wiring board according to the present embodiment, a wiring board having a wiring formed by applying a conductive paste containing conductive particles directly on a substrate having an insulating resin having a low heat-resistant temperature is manufactured. Therefore, there is an effect that disconnection due to transfer does not occur.
（第２の実施の形態）
(Second embodiment)
次に、本発明の第２の実施の形態である配線基板について説明する。
Next, a wiring board according to a second embodiment of the present invention will be described.
図５は、本実施の形態の配線基板６０の構成を示す図であり、図５（ａ）は概略断面図であり、図５（ｂ）は、配線基板６０の電極２０近傍の拡大断面図である。
FIG. 5 is a diagram showing a configuration of the wiring board 60 of the present embodiment, FIG. 5A is a schematic cross-sectional view, and FIG. It is.
第１の実施の形態との違いは、樹脂基板３０の表面に、ソルダーレジストとしての機能を有するソルダーレジスト層１１が設けられている点である。
The difference from the first embodiment is that a solder resist layer 11 having a function as a solder resist is provided on the surface of the resin substrate 30.
ソルダーレジスト層１１は、電極２０が露出するように設けられており、電極２０の周囲はソルダーレジスト層１１によって被覆されている。また、電極２０の露出面とソルダーレジスト層１１の露出面との境界には段差が設けられており、電極２０の露出面はソルダーレジスト層１１の露出面よりも低い位置に設けられている。
The solder resist layer 11 is provided so that the electrode 20 is exposed, and the periphery of the electrode 20 is covered with the solder resist layer 11. Further, a step is provided at the boundary between the exposed surface of the electrode 20 and the exposed surface of the solder resist layer 11, and the exposed surface of the electrode 20 is provided at a position lower than the exposed surface of the solder resist layer 11.
なお、電極２０は、その一部が樹脂絶縁層１０に埋まっていても良く、第１の実施の形態のように電極２０の全体が樹脂絶縁層１０に埋まっていても良い。
A part of the electrode 20 may be embedded in the resin insulating layer 10, or the entire electrode 20 may be embedded in the resin insulating layer 10 as in the first embodiment.
ソルダーレジスト層１１上には、第１の実施の形態である配線基板と同様に、第１の絶縁層４０や配線５０が設けられている。
On the solder resist layer 11, the first insulating layer 40 and the wiring 50 are provided in the same manner as the wiring substrate according to the first embodiment.
第１の絶縁層４０に上に設けられた配線５０は、第１の貫通孔４１を通って、電極２０と電気的に接している。なお、このソルダーレジスト層１１は、例えば熱硬化性樹脂であっても良く、例えばエポキシ系樹脂が好適である。
The wiring 50 provided on the first insulating layer 40 is in electrical contact with the electrode 20 through the first through hole 41. The solder resist layer 11 may be, for example, a thermosetting resin, and is preferably an epoxy resin, for example.
本実施の形態である配線基板によれば、樹脂基板３０の表面上にソルダーレジスト層１１に被覆された配線を形成することが可能となる。このことにより、配線の多層化が可能となる。
According to the wiring board according to the present embodiment, it is possible to form the wiring covered with the solder resist layer 11 on the surface of the resin substrate 30. As a result, the wiring can be multi-layered.
また、樹脂絶縁層１０がソルダーレジスト層１１によって被覆されているため、第１の絶縁層４０形成時に、樹脂絶縁層１０を保護することが可能となる。
Further, since the resin insulating layer 10 is covered with the solder resist layer 11, the resin insulating layer 10 can be protected when the first insulating layer 40 is formed.
次に、本発明の第２の実施の形態の配線基板を用いた半導体パッケージについて説明する。
Next, a semiconductor package using the wiring board according to the second embodiment of the present invention will be described.
図３（ｃ）は、本実施の形態の半導体パッケージ９０の構成を示す図である。本実施の形態の半導体パッケージ９０は、本実施の形態の配線基板上に半導体装置９１を搭載させたものであり、半導体装置９１の搭載面や半導体装置９１の数、半導体装置９１の接続方法等については第１の実施の形態の半導体パッケージと同じである。
FIG. 3C is a diagram showing a configuration of the semiconductor package 90 of the present embodiment. The semiconductor package 90 of the present embodiment is obtained by mounting the semiconductor device 91 on the wiring board of the present embodiment. The mounting surface of the semiconductor device 91, the number of the semiconductor devices 91, the connection method of the semiconductor devices 91, and the like. Is the same as the semiconductor package of the first embodiment.
本実施の形態である半導体パッケージ９０によれば、図３（ｃ）に示すように、樹脂基板３０の電極２０上にはんだ等の導体９３を設け、そこに半導体装置９１を実装する領域を設けることも可能となる。すなわち、一つの配線基板において、通常の実装領域と、導電性ペーストを焼結させた配線５０を有する実装領域を形成することが可能となる。
According to the semiconductor package 90 of the present embodiment, as shown in FIG. 3C, a conductor 93 such as solder is provided on the electrode 20 of the resin substrate 30, and a region for mounting the semiconductor device 91 is provided there. It is also possible. That is, it is possible to form a normal mounting region and a mounting region having the wiring 50 obtained by sintering the conductive paste on one wiring board.
次に、本発明の第２の実施の形態である配線基板の製造方法について説明する。
Next, a method for manufacturing a wiring board according to a second embodiment of the present invention will be described.
図６（ａ）から（ｆ）は、本実施の形態の配線基板６０の製造方法を工程順に示す部分断面図である。なお、各工程間において適宜洗浄及び熱処理を行う。
6 (a) to 6 (f) are partial cross-sectional views showing the method of manufacturing the wiring board 60 of the present embodiment in the order of steps. Note that cleaning and heat treatment are appropriately performed between the respective steps.
まず、図６（ａ）に示すように、表面が露出された電極２０が配置され、さらに樹脂絶縁層１０を覆うようにソルダーレジスト層１１が形成されている樹脂基板３０を用意する。電極２０は、その表面が露出していれば良く、その一部が樹脂絶縁層１０に埋まっていても、電極２０の全体が樹脂絶縁層１０に埋まっていても良い。
First, as shown in FIG. 6A, a resin substrate 30 is prepared in which an electrode 20 whose surface is exposed is disposed and a solder resist layer 11 is formed so as to cover the resin insulating layer 10. The electrode 20 only needs to have its surface exposed, and a part of the electrode 20 may be embedded in the resin insulating layer 10 or the entire electrode 20 may be embedded in the resin insulating layer 10.
ソルダーレジスト層１１は、電極２０の少なくとも一部が露出するように形成され、電極２０の露出面（上面）とソルダーレジスト層１１の露出面（上面）との境界には段差が設けられており、電極２０の露出面（上面）はソルダーレジスト層１１の露出面（上面）よりも低い位置に設けられている。
The solder resist layer 11 is formed so that at least a part of the electrode 20 is exposed, and a step is provided at the boundary between the exposed surface (upper surface) of the electrode 20 and the exposed surface (upper surface) of the solder resist layer 11. The exposed surface (upper surface) of the electrode 20 is provided at a position lower than the exposed surface (upper surface) of the solder resist layer 11.
次に、図６（ｂ）および（ｃ）は、樹脂基板３０表面に酸化物セラミックスからなる第１の絶縁層４０を形成する工程である。あらかじめソルダーレジスト層１１には、アンカー効果によるセラミックスペーストとの密着性を高めるため、あらかじめ機械的研磨等により表面を粗くしてもよい。
Next, FIGS. 6B and 6C show a process of forming the first insulating layer 40 made of oxide ceramics on the surface of the resin substrate 30. The surface of the solder resist layer 11 may be roughened in advance by mechanical polishing or the like in order to improve adhesion to the ceramic paste due to the anchor effect.
図６（ｂ）に示すように、弾性ゴム等のベース材９５に、セラミックスペースト９６を厚さが均一になるように印刷したものに対し、ソルダーレジスト層１１を接触させる。
As shown in FIG. 6B, the solder resist layer 11 is brought into contact with a base material 95 such as elastic rubber printed on a ceramic paste 96 having a uniform thickness.
この時、セラミックペースト９６はソルダーレジスト層１１が設けられている箇所にのみ転写される。ただし、電極２０が十分に露出していれば、電極２０の露出面の一部にセラミックペーストが転写されていても良い。
At this time, the ceramic paste 96 is transferred only to the portion where the solder resist layer 11 is provided. However, if the electrode 20 is sufficiently exposed, the ceramic paste may be transferred to a part of the exposed surface of the electrode 20.
ここでセラミックスペーストは、例えば、アルミナ、ムライト、コーディエライトなどのセラミックスを含有した耐熱性の高いセラミックスペーストを用いてもよい。
Here, as the ceramic paste, for example, a ceramic paste having high heat resistance containing ceramics such as alumina, mullite, and cordierite may be used.
次に、図６（ｃ）に示すように、セラミックスペーストを転写後、樹脂絶縁層１０およびソルダーレジスト層１１の耐熱温度以下の温度で放置し、セラミックスペーストを硬化させ、第１の絶縁層４０とした。次に、図６（ｄ）に示すように、第１の絶縁層４０上と、第１の絶縁層４０に設けられた第１の貫通孔４１中に、導電性ペースト５２を塗布する。これ以降の工程は、図４（ｄ）以降の工程と同じである。
Next, as shown in FIG. 6C, after the ceramic paste is transferred, the ceramic paste is left to stand at a temperature lower than the heat resistance temperature of the resin insulating layer 10 and the solder resist layer 11 to cure the first insulating layer 40. It was. Next, as shown in FIG. 6D, a conductive paste 52 is applied on the first insulating layer 40 and in the first through holes 41 provided in the first insulating layer 40. The subsequent steps are the same as the steps after FIG.
本実施の形態である配線基板の製造方法によれば、第１の実施の形態の配線基板の製造方法の第１の貫通孔４１を設けるためのマスクや、機械加工による穴あけ工程を用いなくとも、第１の絶縁層４０に第１の貫通孔４１を形成することが可能となる。
According to the method for manufacturing a wiring substrate according to the present embodiment, a mask for providing the first through hole 41 of the method for manufacturing the wiring substrate according to the first embodiment and a drilling step by machining are not used. Thus, the first through hole 41 can be formed in the first insulating layer 40.
なぜなら、ソルダーレジスト層１１と電極２０の境界には段差があるので、樹脂基板３０をセラミックペースト９６に接触させると、ソルダーレジスト層１１にのみ、セラミックペースト９６が転写されるからである。電極２０にはセラミックペースト９６が転写されず、その転写されなかった箇所が、第１の貫通孔４１となるためである。
This is because there is a step at the boundary between the solder resist layer 11 and the electrode 20, and when the resin substrate 30 is brought into contact with the ceramic paste 96, the ceramic paste 96 is transferred only to the solder resist layer 11. This is because the ceramic paste 96 is not transferred to the electrode 20, and the portion where the ceramic paste 96 is not transferred becomes the first through hole 41.
また、セラミックペースト９６の粘度を調整することにより、電極２０の表面にセラミックペースト９６が転写される時の状態を制御することが可能となる。
Further, by adjusting the viscosity of the ceramic paste 96, the state when the ceramic paste 96 is transferred to the surface of the electrode 20 can be controlled.
（第３の実施の形態）
(Third embodiment)
次に、本発明の第３の実施の形態である配線基板について説明する。
Next, a wiring board according to a third embodiment of the present invention will be described.
第１の絶縁層４０に用いる酸化物セラミックスとして白色または淡色の酸化物セラミックスを用いること以外は、第１の実施の形態の配線基板６０と同一である。
The same as the wiring board 60 of the first embodiment, except that white or light oxide ceramics is used as the oxide ceramics used for the first insulating layer 40.
本実施の形態における白色または淡色の酸化物セラミックスとしては、例えば、アルミナ（Ａｌ２Ｏ３）、シリカ（ＳｉＯ２）、スピネル（ＭｇＡｌ２Ｏ４）、あるいは、ムライト（３Ａｌ２Ｏ３・２ＳｉＯ２）、コーディエライト（２ＭｇＯ・２Ａｌ２Ｏ３・５ＳｉＯ２）などのアルミナ－シリカ系複酸化物等が、やや黄色あるいはやや茶色がかった酸化物セラミックスとしては、ジルコニア（ＺｒＯ２）、ジルコン（ＺｒＳｉＯ４）などのジルコニア系セラミックス等があげられる。
Examples of the white or light oxide ceramics in the present embodiment include alumina (Al 2 O 3 ), silica (SiO 2 ), spinel (MgAl 2 O 4 ), or mullite (3Al 2 O 3 .2SiO 2). ), Cordierite (2MgO · 2Al 2 O 3 · 5SiO 2 ) and other oxide-ceramics such as alumina-silica-based double oxides may be zirconia (ZrO 2 ), zircon (ZrSiO). 4 ) and the like.
これらの白色または淡色の酸化物セラミックスを第１の絶縁層４０に用いることによる、さらなる効果を説明する。焼結体である配線５０を形成する時に、焼結前の導電性ペースト５２に電磁波を照射して加熱する。この加熱電磁波として例えば、紫外光よりも波長の長い可視光、赤外線、遠赤外線、マイクロ波、ミリ波などが挙げられる。
Further effects of using these white or light oxide ceramics for the first insulating layer 40 will be described. When forming the wiring 50 which is a sintered body, the conductive paste 52 before sintering is irradiated with electromagnetic waves and heated. Examples of the heating electromagnetic wave include visible light having a wavelength longer than that of ultraviolet light, infrared light, far infrared light, microwaves, and millimeter waves.
配線５０の焼結時に照射される電磁波は、配線だけではなく、その周囲に存在する第１の絶縁層４０にも照射される。その第１の絶縁層４０が白色または淡色の酸化物セラミックスであると、電磁波は白色または淡色の酸化物セラミックスに吸収されにくく、酸化物セラミックスによって反射されることとなる。すなわち、電磁波は導電性ペースト５２のみを加熱し、その周囲の第１の絶縁層４０は加熱されにくくなるので、第１の絶縁層４０の下部に存在する樹脂基板３０の温度上昇を抑制させることが可能となる。
The electromagnetic wave irradiated when the wiring 50 is sintered is applied not only to the wiring but also to the first insulating layer 40 existing around the wiring. When the first insulating layer 40 is white or light-colored oxide ceramics, the electromagnetic wave is hardly absorbed by the white or light-colored oxide ceramics and is reflected by the oxide ceramics. That is, the electromagnetic wave heats only the conductive paste 52 and the surrounding first insulating layer 40 becomes difficult to be heated, so that the temperature rise of the resin substrate 30 existing below the first insulating layer 40 is suppressed. Is possible.
次に、本発明の第３の実施の形態の配線基板を用いた半導体パッケージについて説明する。
Next, a semiconductor package using the wiring board according to the third embodiment of the present invention will be described.
本実施の形態の半導体パッケージは、本実施の形態の配線基板上に半導体装置を搭載させたものであり、半導体装置の搭載面や半導体装置の数、半導体装置の接続方法等については第１の実施の形態の半導体パッケージと同じである。
The semiconductor package of the present embodiment is obtained by mounting a semiconductor device on the wiring substrate of the present embodiment. Regarding the mounting surface of the semiconductor device, the number of semiconductor devices, the connection method of the semiconductor devices, etc. This is the same as the semiconductor package of the embodiment.
（第４の実施の形態）
(Fourth embodiment)
次に、本発明の第４の実施の形態である配線基板について説明する。
Next, a wiring board according to a fourth embodiment of the present invention will be described.
図７は、本実施の形態の配線基板６０の構成を示す図であり、図７（ａ）は概略断面図であり、図７（ｂ）は、配線基板６０の電極２０近傍の拡大断面図である。
FIG. 7 is a diagram showing a configuration of the wiring board 60 of the present embodiment, FIG. 7A is a schematic cross-sectional view, and FIG. 7B is an enlarged cross-sectional view of the vicinity of the electrode 20 of the wiring board 60. It is.
第１の実施の形態との違いは、樹脂基板３０と第１の絶縁層４０の間に第２の絶縁層７０が設けられている点である。電極２０上の第２の絶縁層７０には第２の貫通孔７１が設けられ、第２の貫通孔７１中にも配線５０が設けられ、配線５０と電極２０が電気的に接している。
The difference from the first embodiment is that a second insulating layer 70 is provided between the resin substrate 30 and the first insulating layer 40. A second through hole 71 is provided in the second insulating layer 70 on the electrode 20, and a wiring 50 is also provided in the second through hole 71, and the wiring 50 and the electrode 20 are in electrical contact.
この第２の絶縁層７０は、第１の絶縁層４０を形成するセラミックシートを樹脂基板３０に接着するためのものである。具体的には、例えば、耐熱性を有するエポキシベースの接着剤や、アルミナやジルコニアベースの接着剤を用いることが出来る。
The second insulating layer 70 is for adhering the ceramic sheet forming the first insulating layer 40 to the resin substrate 30. Specifically, for example, an epoxy-based adhesive having heat resistance, or an alumina or zirconia-based adhesive can be used.
セラミックシートとは、酸化物セラミックスと繊維との複合材料であって、その酸化物セラミックスは既に焼成されているものである。このセラミックシートは、シート状に成形されたものであり、高い平坦度を有するものである。
The ceramic sheet is a composite material of oxide ceramics and fibers, and the oxide ceramics are already fired. This ceramic sheet is formed into a sheet shape and has high flatness.
本実施の形態である配線基板によれば、平坦度の高いセラミックシートを用いて第１の絶縁層４０が形成されているため、配線５０を形成する面の平坦度が高められている配線基板を提供することが可能となる。配線５０を形成する面の平坦度が高いと、導電性ペーストを塗布して形成される配線５０の線幅が均一となり、その導通が安定する。よって、より微細な配線５０を形成することが可能となる。
According to the wiring board according to the present embodiment, since the first insulating layer 40 is formed using a ceramic sheet having high flatness, the flatness of the surface on which the wiring 50 is formed is increased. Can be provided. When the flatness of the surface on which the wiring 50 is formed is high, the line width of the wiring 50 formed by applying the conductive paste becomes uniform, and the conduction is stabilized. Therefore, it is possible to form a finer wiring 50.
次に、本発明の第４の実施の形態の配線基板を用いた半導体パッケージについて説明する。
Next, a semiconductor package using the wiring board according to the fourth embodiment of the present invention will be described.
本実施の形態の半導体パッケージは、本実施の形態の配線基板上に半導体装置を搭載させたものであり、半導体装置の搭載面や半導体装置の数、半導体装置の接続方法等については第１の実施の形態の半導体パッケージと同じである。
The semiconductor package of the present embodiment is obtained by mounting a semiconductor device on the wiring substrate of the present embodiment. Regarding the mounting surface of the semiconductor device, the number of semiconductor devices, the connection method of the semiconductor devices, etc. This is the same as the semiconductor package of the embodiment.
本実施の形態である配線基板によれば、微細な配線を有する配線基板を用いることができるので、接続電極を多く有する半導体装置を実装することが可能となる。なぜなら、微細な配線を形成することが出来るので、接続電極の数が多くとも、多くの配線の引き回しが可能となるためである。
According to the wiring board according to the present embodiment, a wiring board having fine wiring can be used, so that a semiconductor device having many connection electrodes can be mounted. This is because fine wiring can be formed, and even if the number of connection electrodes is large, many wirings can be routed.
次に、本発明の第４の実施の形態である配線基板の製造方法について説明する。
Next, a method for manufacturing a wiring board according to a fourth embodiment of the present invention will be described.
図８（ａ）から（ｆ）は、本実施の形態の配線基板６０の製造方法を工程順に示す部分断面図である。なお、各工程間において適宜洗浄及び熱処理を行う。
8 (a) to 8 (f) are partial cross-sectional views showing the method of manufacturing the wiring board 60 of this embodiment in the order of steps. Note that cleaning and heat treatment are appropriately performed between the respective steps.
まず、図８（ａ）に示すように、表面が露出された電極２０が配置された樹脂基板３０を用意する。電極２０は、その表面が露出していれば良く、その一部が樹脂絶縁層１０に埋まっていても、電極２０の全体が樹脂絶縁層１０に埋まっていても良い。
First, as shown in FIG. 8A, a resin substrate 30 on which the electrode 20 whose surface is exposed is arranged is prepared. The electrode 20 only needs to have its surface exposed, and a part of the electrode 20 may be embedded in the resin insulating layer 10 or the entire electrode 20 may be embedded in the resin insulating layer 10.
次に、図８（ｂ）に示すように、予め電極２０の位置に対応するように第１の貫通孔４１が設けられたセラミックスシート９７を用意し、耐熱性を有するエポキシベースの接着剤や、アルミナやジルコニアベースの接着剤７３をセラミックシート９７に塗布する。その後、セラミックスシート９７と樹脂基板３０を位置決めする。
Next, as shown in FIG. 8B, a ceramic sheet 97 provided with a first through hole 41 corresponding to the position of the electrode 20 in advance is prepared, and an epoxy-based adhesive having heat resistance or Then, an adhesive 73 based on alumina or zirconia is applied to the ceramic sheet 97. Thereafter, the ceramic sheet 97 and the resin substrate 30 are positioned.
次に、図８（ｃ）に示すように、セラミックシート９７が接着剤７３を介して樹脂基板３０に接着されることにより、第１の絶縁層が形成される。
Next, as shown in FIG. 8C, the ceramic sheet 97 is adhered to the resin substrate 30 via the adhesive 73, whereby a first insulating layer is formed.
次に、図８（ｄ）に示すように、第１の絶縁層４０上と、第１の絶縁層４０に設けられた第１の貫通孔４１および第２の絶縁層７０に設けられた第２の貫通孔７１に、導電性ペースト５２を塗布する。これ以降の工程は、図４（ｄ）以降の工程と同じである。
Next, as shown in FIG. 8 (d), the first insulating layer 40, the first through-hole 41 provided in the first insulating layer 40, and the second insulating layer 70 provided in the second insulating layer 70. The conductive paste 52 is applied to the two through holes 71. The subsequent steps are the same as the steps after FIG.
本実施の形態である配線基板の製造方法によれば、平坦度の高いセラミックシート９７を用いて第１の絶縁層４０を形成するため、第１の絶縁層４０の平坦度を高くすることが出来る。第１の絶縁層４０の平坦度が高いと、その上に塗布される導電性ペーストの厚さや線幅が均一となり、電気的な導通が安定した配線を有する配線基板を形成することが可能となる。
According to the method for manufacturing a wiring board according to the present embodiment, since the first insulating layer 40 is formed using the ceramic sheet 97 having a high flatness, the flatness of the first insulating layer 40 can be increased. I can do it. When the flatness of the first insulating layer 40 is high, the thickness and line width of the conductive paste applied thereon become uniform, and it is possible to form a wiring board having wiring with stable electrical conduction. Become.
（第５の実施の形態）
(Fifth embodiment)
次に、本発明の第５の実施の形態である配線基板について説明する。
Next, a wiring board according to a fifth embodiment of the present invention will be described.
図９は、本実施の形態の配線基板６０の構成を示す図であり、図９（ａ）は概略断面図であり、図９（ｂ）は、配線基板６０の電極２０近傍の拡大断面図である。
FIG. 9 is a diagram illustrating a configuration of the wiring board 60 of the present embodiment, FIG. 9A is a schematic cross-sectional view, and FIG. 9B is an enlarged cross-sectional view of the vicinity of the electrode 20 of the wiring board 60. It is.
第１の実施の形態との違いは、樹脂基板３０と第１の絶縁層４０上の配線５０との間に電磁波を反射する金属膜７２を設け、なおかつ、第１の絶縁層４０は透光性セラミックスで形成されている点である。その他の構造は第１の実施の形態と同一である。
The difference from the first embodiment is that a metal film 72 that reflects electromagnetic waves is provided between the resin substrate 30 and the wiring 50 on the first insulating layer 40, and the first insulating layer 40 is transparent. It is the point which is formed with the property ceramics. Other structures are the same as those in the first embodiment.
図９（ａ）および図９（ｂ）において示されている金属膜７２は配線５０および電極２０に接することが無いように、樹脂基板３０上の電極２０が形成されていない箇所に設けられている。
The metal film 72 shown in FIGS. 9A and 9B is provided on the resin substrate 30 where the electrode 20 is not formed so as not to contact the wiring 50 and the electrode 20. Yes.
この金属膜７２は、電極２０および配線５０と接していなければよく、金属膜７２が樹脂基板３０と接していなくてもよい。第１の絶縁層４０の内部に設けられていてもよい。
The metal film 72 may not be in contact with the electrode 20 and the wiring 50, and the metal film 72 may not be in contact with the resin substrate 30. It may be provided inside the first insulating layer 40.
金属膜７２が第１の絶縁層４０の内部に設けられ、樹脂基板３０から離れた位置にあれば、照射される電磁波が樹脂基板３０から離れた位置で反射され、電磁波によって加熱される第１の絶縁層４０が少なくなるため、樹脂基板３０の加熱が、より抑制される。
If the metal film 72 is provided inside the first insulating layer 40 and is at a position away from the resin substrate 30, the irradiated electromagnetic wave is reflected at a position away from the resin substrate 30 and heated by the electromagnetic wave. Therefore, the heating of the resin substrate 30 is further suppressed.
金属膜７２は、配線５０の焼結時に照射される電磁波を反射するものであれば良く、例えば、銅、銀、金、ニッケル、アルミニウム、およびパラジウムの中の少なくとも１種類の金属、または２種類以上の金属からなる合金から選択することができる。また、透光性セラミックスとしては、例えば、アルミナ（Ａｌ２Ｏ３）やＰＬＺＴ（（Ｐｂ，Ｌａ）（Ｚｒ，Ｔｉ）Ｏ３）、イットリア－トリア（Ｙ２Ｏ３－ＴｈＯ２）、スピネル（ＭｇＡｌ２Ｏ４）などの酸化物セラミックスを使用することができる。
The metal film 72 only needs to reflect an electromagnetic wave irradiated when the wiring 50 is sintered. For example, at least one kind of metal among copper, silver, gold, nickel, aluminum, and palladium, or two kinds It can select from the alloy which consists of the above metal. Examples of the translucent ceramic include alumina (Al 2 O 3 ), PLZT ((Pb, La) (Zr, Ti) O 3 ), yttria-tria (Y 2 O 3 —ThO 2 ), spinel ( Oxide ceramics such as MgAl 2 O 4 ) can be used.
次に、本発明の第５の実施の形態の配線基板を用いた半導体パッケージについて説明する。
Next, a semiconductor package using the wiring board according to the fifth embodiment of the present invention will be described.
本実施の形態の半導体パッケージは、本実施の形態の配線基板上に半導体装置を搭載させたものであり、半導体装置の搭載面や半導体装置の数、半導体装置の接続方法等については第１の実施の形態の半導体パッケージと同じである。
The semiconductor package of the present embodiment is obtained by mounting a semiconductor device on the wiring substrate of the present embodiment. Regarding the mounting surface of the semiconductor device, the number of semiconductor devices, the connection method of the semiconductor devices, etc. This is the same as the semiconductor package of the embodiment.
次に、本発明の第５の実施の形態である配線基板の製造方法について説明する。
Next, a method for manufacturing a wiring board according to a fifth embodiment of the present invention will be described.
図１０（ａ）から（ｉ）は、本実施の形態の配線基板６０の製造方法を工程順に示す部分断面図である。なお、各工程間において適宜洗浄及び熱処理を行う。
10 (a) to 10 (i) are partial cross-sectional views showing a method of manufacturing the wiring board 60 of this embodiment in the order of steps. Note that cleaning and heat treatment are appropriately performed between the respective steps.
まず、図１０（ａ）に示すように、表面が露出された電極２０が配置された樹脂基板３０を用意する。電極２０は、その表面が露出していれば良く、その一部が樹脂絶縁層１０に埋まっていても、電極２０の全体が樹脂絶縁層１０に埋まっていても良い。
First, as shown in FIG. 10A, a resin substrate 30 on which the electrode 20 with the exposed surface is arranged is prepared. The electrode 20 only needs to have its surface exposed, and a part of the electrode 20 may be embedded in the resin insulating layer 10 or the entire electrode 20 may be embedded in the resin insulating layer 10.
次に、図１０（ｂ）に示すように、樹脂基板３０表面に金属膜７２を形成する。例えば、スパッタ法により、金属膜７２を形成する。
Next, as shown in FIG. 10B, a metal film 72 is formed on the surface of the resin substrate 30. For example, the metal film 72 is formed by sputtering.
次に、図１０（ｃ）に示すように、スクリーン印刷等により、レジスト材９９を金属膜７２上に塗布、硬化させる。
Next, as shown in FIG. 10C, a resist material 99 is applied and cured on the metal film 72 by screen printing or the like.
次に、図１０（ｄ）に示すように、電極２０近傍の金属膜７２をエッチングにより除去する。
Next, as shown in FIG. 10D, the metal film 72 near the electrode 20 is removed by etching.
次に、図１０（ｅ）に示すように、レジスト材を除去する。
Next, as shown in FIG. 10E, the resist material is removed.
次に、図１０（ｆ）に示すように、透光性を有するセラミックスからなる第１の絶縁層４０を形成する。電磁波吸収率の低い金属酸化物粒子を金属膜形成面に高速で衝突させると、粒子は微細化するとともに、互いに結合し、透光性を有する酸化物セラミックスとなる。
Next, as shown in FIG. 10F, a first insulating layer 40 made of translucent ceramics is formed. When metal oxide particles having a low electromagnetic wave absorptivity collide with a metal film forming surface at high speed, the particles are miniaturized and bonded to each other to form a translucent oxide ceramic.
例えば、本発明の第１の実施の形態である配線基板の製造方法において説明したエアロゾルデポジション法を用い、金属酸化物粒子の噴射速度を高速にすることにより、透光性を有する酸化物セラミックスを形成することができる。
For example, by using the aerosol deposition method described in the method for manufacturing a wiring board according to the first embodiment of the present invention, and increasing the jetting speed of metal oxide particles, the oxide ceramics having translucency Can be formed.
次に、図１０（ｇ）に示すように、第１の絶縁層４０上と、第１の絶縁層４０に設けられた第１の貫通孔４１に、導電性ペースト５２を塗布する。これ以降の工程は、図４（ｄ）以降に示す工程と同一である。
Next, as shown in FIG. 10 (g), a conductive paste 52 is applied on the first insulating layer 40 and in the first through holes 41 provided in the first insulating layer 40. The subsequent steps are the same as those shown in FIG.
なお、金属膜７２は、樹脂基板３０上だけではなく、第１の絶縁層４０の内部にも形成可能である。例えば、第１の絶縁層４０を形成した後、その表面に金属膜７２を形成し、さらにその上に、第１の絶縁層４０を形成しても良い。
Note that the metal film 72 can be formed not only on the resin substrate 30 but also inside the first insulating layer 40. For example, after forming the first insulating layer 40, the metal film 72 may be formed on the surface, and the first insulating layer 40 may be further formed thereon.
本実施の形態である配線基板の製造方法によれば、加熱のために照射される電磁波は、第１の絶縁層４０を透過し、金属膜７２で反射され外部に放出されるために、電磁波照射による第１の絶縁層４０および樹脂基板３０の温度上昇をさらに抑制することができる。
According to the method for manufacturing a wiring board according to the present embodiment, an electromagnetic wave irradiated for heating passes through the first insulating layer 40, is reflected by the metal film 72, and is emitted to the outside. The temperature rise of the first insulating layer 40 and the resin substrate 30 due to irradiation can be further suppressed.
また、金属膜７２によって反射された電磁波が導電性ペースト５２の裏面も加熱することが可能となる。導電性ペースト５２は、直接照射される電磁波と反射された電磁波によって、その両面から加熱されるため、隣接する導電粒子の接合が確実になる。よって、信頼性の高い配線５０を形成することが可能となる。
Further, the electromagnetic wave reflected by the metal film 72 can also heat the back surface of the conductive paste 52. Since the conductive paste 52 is heated from both sides by the directly irradiated electromagnetic wave and the reflected electromagnetic wave, the bonding of adjacent conductive particles is ensured. Therefore, the highly reliable wiring 50 can be formed.
（第６の実施の形態）
(Sixth embodiment)
次に、本発明の第６の実施の形態である配線基板について説明する。
Next, a wiring board according to a sixth embodiment of the present invention will be described.
図１１は、本実施の形態の配線基板６０の構成を示す図である。
FIG. 11 is a diagram showing a configuration of the wiring board 60 of the present embodiment.
第１の実施の形態との違いは、第１の絶縁層４０と配線５０を被覆する第３の絶縁層８０が設けられている点である。第３の絶縁層８０は、絶縁性を有する材料であれば良く、一般的な配線基板と同様に、エポキシ樹脂やポリイミドなどの有機絶縁材料、あるいは、酸化物セラミックスなどの無機絶縁材料であっても良い。第３の絶縁層８０によって配線５０を被覆することにより、配線５０を保護することが可能となり、信頼性やハンドリング性の良い配線基板６０を形成することが可能となる。
The difference from the first embodiment is that a third insulating layer 80 that covers the first insulating layer 40 and the wiring 50 is provided. The third insulating layer 80 only needs to be an insulating material, and is an organic insulating material such as an epoxy resin or polyimide, or an inorganic insulating material such as an oxide ceramic, as in a general wiring board. Also good. By covering the wiring 50 with the third insulating layer 80, it is possible to protect the wiring 50, and it is possible to form the wiring substrate 60 with good reliability and handling properties.
次に、本発明の第６の実施の形態の配線基板を用いた半導体パッケージについて説明する。
Next, a semiconductor package using the wiring board according to the sixth embodiment of the present invention will be described.
本実施の形態の半導体パッケージは、本実施の形態の配線基板上に半導体装置を搭載させたものである。
The semiconductor package of the present embodiment is obtained by mounting a semiconductor device on the wiring board of the present embodiment.
本実施の形態の配線５０は第３の絶縁層８０によって被覆されているため、図３（ｂ）のように配線５０に半導体デバイス９１を搭載することは出来ない。しかしながら、図３（ａ）に示されているように、第１の絶縁層４０が設けられていない面の電極２０に半導体デバイス９１を搭載することは可能である。
Since the wiring 50 of the present embodiment is covered with the third insulating layer 80, the semiconductor device 91 cannot be mounted on the wiring 50 as shown in FIG. However, as shown in FIG. 3A, it is possible to mount the semiconductor device 91 on the electrode 20 on the surface where the first insulating layer 40 is not provided.
半導体装置の接続方法等については第１の実施の形態の半導体パッケージと同じである。
The semiconductor device connection method and the like are the same as those of the semiconductor package of the first embodiment.
次に、本発明の第６の実施の形態である配線基板の製造方法について説明する。
Next, a method for manufacturing a wiring board according to a sixth embodiment of the present invention will be described.
本実施の形態の製造方法は、配線５０の焼結後に、配線５０と第１の絶縁層４０を覆うように第３の絶縁層８０を形成する工程を追加することによって、実現される。第３の絶縁層８０は、一般的な絶縁層形成方法と同様に、例えばポリイミドのように熱硬化性の絶縁性樹脂をスプレーコートにより、配線５０を覆うように塗布し、加熱硬化させることで形成可能である。
The manufacturing method of the present embodiment is realized by adding a step of forming the third insulating layer 80 so as to cover the wiring 50 and the first insulating layer 40 after the wiring 50 is sintered. The third insulating layer 80 is formed by, for example, applying a thermosetting insulating resin such as polyimide so as to cover the wiring 50 by heat-curing, as in a general insulating layer forming method. It can be formed.
また、酸化物セラミックスからなる第３の絶縁層８０をエアロゾルデポジション法（ＡＤ法）により形成しても良い。この時、ＡＤ法によって吹き付けられる酸化物セラミックスの粒子が配線に衝突する際に、衝突のエネルギーが焼結体にも付与されるために、焼結体が加熱される。その加熱により、導電粒子の表面がより多く溶融するので、冷却後の配線５０は、より緻密な構造を有し、より比抵抗の小さい配線を形成することができる。
Further, the third insulating layer 80 made of oxide ceramics may be formed by an aerosol deposition method (AD method). At this time, when the oxide ceramic particles sprayed by the AD method collide with the wiring, the energy of collision is also applied to the sintered body, so that the sintered body is heated. Since the surface of the conductive particles is melted more by the heating, the wiring 50 after cooling has a denser structure and a wiring having a smaller specific resistance can be formed.
（第７の実施の形態）
(Seventh embodiment)
次に、本発明の第７の実施の形態である配線基板について説明する。
Next, a wiring board according to a seventh embodiment of the present invention will be described.
図１２は、本実施の形態の配線基板６０の構成を示す図である。
FIG. 12 is a diagram showing a configuration of the wiring board 60 of the present embodiment.
図１２に示されるように、配線５０は１層に限定されるものではなく、２層あるいはそれ以上の層を有する配線５０を形成することができる。
As shown in FIG. 12, the wiring 50 is not limited to a single layer, and a wiring 50 having two or more layers can be formed.
配線５０は、第４の絶縁層８１によって被覆され、第４の絶縁層８１には、第４の貫通孔８２が形成されている。そして、別の配線５０を第４の絶縁層８１上と、第４の貫通孔８２中に設けることにより、複数の層に配線５０を設けることが可能となる。
複数の配線５０の下部には、酸化物セラミックスからなる層がそれぞれ積層されることにより、樹脂基板３０への熱伝導をより抑制することができる。上層の配線５０は、樹脂基板３０からの距離が大きくなり、その間には酸化物セラミックスからなる層が複数積層されているため、高温で加熱することができ、比抵抗の低い配線５０を得ることができる。 Thewiring 50 is covered with a fourth insulating layer 81, and a fourth through hole 82 is formed in the fourth insulating layer 81. By providing another wiring 50 on the fourth insulating layer 81 and in the fourth through hole 82, the wiring 50 can be provided in a plurality of layers.
By laminating layers made of oxide ceramics below the plurality ofwirings 50, heat conduction to the resin substrate 30 can be further suppressed. Since the upper wiring 50 has a large distance from the resin substrate 30 and a plurality of layers made of oxide ceramics are laminated between them, the wiring 50 can be heated at a high temperature and has a low specific resistance. Can do.
複数の配線５０の下部には、酸化物セラミックスからなる層がそれぞれ積層されることにより、樹脂基板３０への熱伝導をより抑制することができる。上層の配線５０は、樹脂基板３０からの距離が大きくなり、その間には酸化物セラミックスからなる層が複数積層されているため、高温で加熱することができ、比抵抗の低い配線５０を得ることができる。 The
By laminating layers made of oxide ceramics below the plurality of
第４の絶縁層８１は、配線５０を焼結する時の熱により劣化しても良いのであれば、酸化物セラミックスでなくともよく、絶縁性を有する材料であればよい。
If the fourth insulating layer 81 may be deteriorated by heat when the wiring 50 is sintered, the fourth insulating layer 81 may not be an oxide ceramic but may be an insulating material.
また、図１２に示されている配線基板では、最上層の配線は露出しているが、最上層の配線を被覆する絶縁層が有っても良い。
Further, in the wiring substrate shown in FIG. 12, the uppermost layer wiring is exposed, but an insulating layer covering the uppermost layer wiring may be provided.
本実施の形態である半導体パッケージによれば、配線５０を多層化できることにより、配線の引き回しが容易となり、接続電極を多く有する半導体装置を実装することが可能となる。よって、高密度実装が可能となる。
According to the semiconductor package of the present embodiment, since the wiring 50 can be multi-layered, the wiring can be easily routed and a semiconductor device having many connection electrodes can be mounted. Therefore, high-density mounting is possible.
次に、本発明の第７の実施の形態の配線基板を用いた半導体パッケージについて説明する。
Next, a semiconductor package using the wiring board according to the seventh embodiment of the present invention will be described.
本実施の形態の半導体パッケージは、本実施の形態の配線基板上に半導体装置を搭載させたものであり、半導体装置の搭載面や半導体装置の数、半導体装置の接続方法等については第１の実施の形態の半導体パッケージと同じである。
The semiconductor package of the present embodiment is obtained by mounting a semiconductor device on the wiring substrate of the present embodiment. Regarding the mounting surface of the semiconductor device, the number of semiconductor devices, the connection method of the semiconductor devices, etc. This is the same as the semiconductor package of the embodiment.
（第８の実施の形態）
(Eighth embodiment)
次に、本発明の第８の実施の形態である配線基板について説明する。
Next, a wiring board according to an eighth embodiment of the present invention will be described.
図１３（ａ）および図１３（ｂ）は、本実施の形態の配線基板６０の構成を示す図である。
FIG. 13A and FIG. 13B are diagrams showing the configuration of the wiring board 60 of the present embodiment.
本実施の形態では、最上層の配線５０を覆う第５の絶縁層８３に第５の貫通孔８４を設け、配線５０の一部を露出させる。露出された配線上にＮｉ／Ａｕめっき等による表面処理を行い、これを外部接続電極９２としても良い。また、図１３（ｂ）に示すように、外部接続電極９２上にハンダなどの導体９３を搭載することで、一般的な、実装部品と同様に取り扱うことが可能となる。
In the present embodiment, the fifth through hole 84 is provided in the fifth insulating layer 83 covering the uppermost wiring 50 and a part of the wiring 50 is exposed. The exposed wiring may be subjected to surface treatment by Ni / Au plating or the like, and this may be used as the external connection electrode 92. Further, as shown in FIG. 13B, by mounting a conductor 93 such as solder on the external connection electrode 92, it can be handled in the same manner as a general mounting component.
次に、本発明の第８の実施の形態の配線基板を用いた半導体パッケージについて説明する。
Next, a semiconductor package using the wiring board according to the eighth embodiment of the present invention will be described.
本実施の形態の半導体パッケージは、本実施の形態の配線基板上に半導体装置を搭載させたものであり、半導体装置の搭載面や半導体装置の数、半導体装置の接続方法等については第１の実施の形態の半導体パッケージと同じである。
The semiconductor package of the present embodiment is obtained by mounting a semiconductor device on the wiring substrate of the present embodiment. Regarding the mounting surface of the semiconductor device, the number of semiconductor devices, the connection method of the semiconductor devices, etc. This is the same as the semiconductor package of the embodiment.
例えば、外部接続電極９２にはんだ等の導体を設けることにより、半導体装置を搭載させることが可能である。
For example, a semiconductor device can be mounted by providing a conductor such as solder on the external connection electrode 92.
半導体装置の接続方法等については第１の実施の形態の半導体パッケージと同じである。
The semiconductor device connection method and the like are the same as those of the semiconductor package of the first embodiment.
（第９の実施の形態）
(Ninth embodiment)
次に、本発明の第９の実施の形態である配線基板について説明する。
Next, a wiring board according to a ninth embodiment of the present invention will be described.
図１４（ａ）は、本実施の形態の配線基板６０の構成を示す図であり、配線基板６０の電極２０近傍の拡大断面を模式的に表した図である。
FIG. 14A is a diagram showing a configuration of the wiring board 60 of the present embodiment, and is a diagram schematically showing an enlarged cross section near the electrode 20 of the wiring board 60.
第１の実施の形態との違いは、第１の絶縁層を構成する結晶粒子９８の径が均一でなく、層の厚さ方向に変化する点である。樹脂基板３０に近い層の結晶粒子９８の径は数十ナノメートル程度の緻密な構造を形成し、次第に結晶粒子９８の径は大きくなり、第１の絶縁層上面上の配線と接する層の結晶粒子９８の径は数百ナノメートルら数マイクロメートル程度の粗い構造としている点である。その他の構造は第１の実施の形態と同一である。
The difference from the first embodiment is that the diameter of the crystal grains 98 constituting the first insulating layer is not uniform and changes in the thickness direction of the layer. The diameter of the crystal particles 98 in the layer close to the resin substrate 30 forms a dense structure of about several tens of nanometers, the diameter of the crystal particles 98 gradually increases, and the crystal of the layer in contact with the wiring on the upper surface of the first insulating layer The diameter of the particles 98 is a rough structure of about several hundred nanometers to several micrometers. Other structures are the same as those in the first embodiment.
本実施の形態における特有の効果について、図１４（ｂ）および図１４（ｃ）を用いて説明する。図１４（ｂ）および（ｃ）は、配線５０と第１の絶縁層４０が接する部分を模式的に表し、拡大した図である。まず、第１の絶縁層４０の樹脂基板３０と接する層は、樹脂基板３０との密着性を高めるために、数十ナノメートル程度の比較的小さい結晶粒径を有した方が良い。一方、配線５０と接する第１の絶縁層４０の層は、数百ナノメートルから数ミクロンメートル程度の比較的大きな結晶粒径を有した方がよい。
The unique effect in the present embodiment will be described with reference to FIGS. 14 (b) and 14 (c). FIGS. 14B and 14C are diagrams schematically showing an enlarged portion where the wiring 50 and the first insulating layer 40 are in contact with each other. First, the layer in contact with the resin substrate 30 of the first insulating layer 40 should have a relatively small crystal grain size of about several tens of nanometers in order to improve the adhesion with the resin substrate 30. On the other hand, the layer of the first insulating layer 40 in contact with the wiring 50 should have a relatively large crystal grain size of about several hundred nanometers to several micrometers.
なぜなら、図１４（ｂ）に示すように、配線５０は粒子状の導電体が接合したものであるので、その配線５０と接する第１の絶縁層４０の粒径が大きい方が、配線５０が第１の絶縁層４０の凸凹に入り込み易くなる。その結果、配線５０と第１の絶縁層４０の密着強度が高まる効果が得られる。
This is because, as shown in FIG. 14B, since the wiring 50 is formed by bonding particulate conductors, the wiring 50 has a larger particle diameter of the first insulating layer 40 in contact with the wiring 50. It becomes easy to enter the unevenness of the first insulating layer 40. As a result, an effect of increasing the adhesion strength between the wiring 50 and the first insulating layer 40 is obtained.
一方、図１４（ｃ）に示すように、配線５０と接する第１の絶縁層４０の結晶粒径が小さいと、配線５０は、第１の絶縁層４０の凸凹に入り込みにくくなる。この場合、配線５０と第１の絶縁層４０の間には、接点が少なくなり、両者の間には比較的大きな隙間が生じるため、配線５０と第１の絶縁層４０の密着強度が弱くなる。
本実施の形態のように、配線５０と第１の絶縁層４０の密着強度が強くなることにより、焼結後、配線５０が第１の絶縁層４０から剥がれ落ちることを防止することが可能となる。次に、本発明の第９の実施の形態の配線基板を用いた半導体パッケージについて説明する。 On the other hand, as shown in FIG. 14C, when the crystal grain size of the first insulatinglayer 40 in contact with the wiring 50 is small, the wiring 50 is difficult to enter the unevenness of the first insulating layer 40. In this case, since the number of contacts is reduced between the wiring 50 and the first insulating layer 40 and a relatively large gap is generated between the two, the adhesion strength between the wiring 50 and the first insulating layer 40 is weakened. .
Since the adhesion strength between thewiring 50 and the first insulating layer 40 is increased as in the present embodiment, it is possible to prevent the wiring 50 from being peeled off from the first insulating layer 40 after sintering. Become. Next, a semiconductor package using the wiring board according to the ninth embodiment of the present invention will be described.
本実施の形態のように、配線５０と第１の絶縁層４０の密着強度が強くなることにより、焼結後、配線５０が第１の絶縁層４０から剥がれ落ちることを防止することが可能となる。次に、本発明の第９の実施の形態の配線基板を用いた半導体パッケージについて説明する。 On the other hand, as shown in FIG. 14C, when the crystal grain size of the first insulating
Since the adhesion strength between the
本実施の形態の半導体パッケージは、本実施の形態の配線基板上に半導体装置を搭載させたものであり、半導体装置の搭載面や半導体装置の数、半導体装置の接続方法等については第１の実施の形態の半導体パッケージと同じである。
The semiconductor package of the present embodiment is obtained by mounting a semiconductor device on the wiring substrate of the present embodiment. Regarding the mounting surface of the semiconductor device, the number of semiconductor devices, the connection method of the semiconductor devices, etc. This is the same as the semiconductor package of the embodiment.
次に、本発明の第９の実施の形態である配線基板の製造方法について説明する。
Next, a method for manufacturing a wiring board according to a ninth embodiment of the present invention will be described.
樹脂基板３０の表面上に、エアロゾルデポジション法を用いて第１の絶縁層４０を形成する際、衝突させる粒子の速度を、積層初期は速く、段階的に遅くすることにより、積層初期の結晶粒径は数十ナノメートル程度の緻密な構造を形成し、次第に結晶粒径は大きくなり、積層後期の結晶粒径は数百ナノメートルから数マイクロメートル程度の粗い構造となる。以降は、第１の実施の形態と同様に、配線を積層していく。
When the first insulating layer 40 is formed on the surface of the resin substrate 30 by using the aerosol deposition method, the speed of the particles to be collided is high in the initial stage of the stacking, and is gradually reduced in stages to thereby reduce the crystal in the initial stage of the stacking. The grain size forms a dense structure of about several tens of nanometers, the crystal grain size gradually increases, and the crystal grain size in the later stage of lamination becomes a coarse structure of about several hundred nanometers to several micrometers. Thereafter, wirings are stacked as in the first embodiment.
本発明の配線基板、半導体パッケージおよび配線基板の製造方法は、上記実施の形態に基づいて説明されているが、上記実施の形態に限定されることなく、本発明の範囲内において、かつ本発明の基本的技術思想に基づいて、上記実施の形態に対し種々の変形、変更及び改良を含むことができることはいうまでもない。また、本発明の請求の範囲の枠内において、種々の開示要素の多様な組み合わせ・置換ないし選択が可能である。
The wiring board, the semiconductor package, and the manufacturing method of the wiring board according to the present invention have been described based on the above embodiments, but are not limited to the above embodiments, and are within the scope of the present invention. It goes without saying that various modifications, changes, and improvements can be included in the above-described embodiment based on the basic technical idea. Further, various combinations, substitutions, or selections of various disclosed elements are possible within the scope of the claims of the present invention.
なお、上記の特許文献の各開示を、本書に引用をもって繰り込むものとする。本発明の全開示（請求の範囲を含む）の枠内において、さらにその基本的技術思想に基づいて、実施例ないし実施例の変更・調整が可能である。また、本発明の請求の範囲の枠内において種々の開示要素の多様な組み合わせないし選択が可能である。すなわち、本発明は、請求の範囲を含む全開示、技術的思想にしたがって当業者であればなし得るであろう各種変形、修正を含むことは勿論である。
It should be noted that the disclosures of the above patent documents are incorporated herein by reference. Within the scope of the entire disclosure (including claims) of the present invention, the examples and the examples can be changed and adjusted based on the basic technical concept. Various combinations and selections of various disclosed elements are possible within the scope of the claims of the present invention. That is, the present invention of course includes various variations and modifications that could be made by those skilled in the art according to the entire disclosure including the claims and the technical idea.
１０ 樹脂絶縁層
１１ ソルダーレジスト層
２０ 電極
２１ 内層配線
３０ 樹脂基板
４０ 第１の絶縁層
４１ 第１の貫通孔
５０ 配線
５２ 導電性ペースト
６０ 配線基板
７０ 第２の絶縁層
７１ 第２の貫通孔
７２ 金属膜
７３ 接着剤
８０ 第３の絶縁層
８１ 第４の絶縁層
８２ 第４の貫通孔
８３ 第５の絶縁層
８４ 第５の貫通孔
９０ 半導体パッケージ
９１ 半導体装置
９２ 外部接続電極
９３ 導体
９５ ベース材
９６ セラミックスペースト
９７ セラミックスシート
９８ 結晶粒子
９９ レジスト材 DESCRIPTION OFSYMBOLS 10 Resin insulating layer 11 Solder resist layer 20 Electrode 21 Inner layer wiring 30 Resin substrate 40 1st insulating layer 41 1st through-hole 50 Wiring 52 Conductive paste 60 Wiring board 70 2nd insulating layer 71 2nd through-hole 72 Metal film 73 Adhesive 80 Third insulating layer 81 Fourth insulating layer 82 Fourth through hole 83 Fifth insulating layer 84 Fifth through hole 90 Semiconductor package 91 Semiconductor device 92 External connection electrode 93 Conductor 95 Base material 96 Ceramic paste 97 Ceramic sheet 98 Crystal particle 99 Resist material
１１ ソルダーレジスト層
２０ 電極
２１ 内層配線
３０ 樹脂基板
４０ 第１の絶縁層
４１ 第１の貫通孔
５０ 配線
５２ 導電性ペースト
６０ 配線基板
７０ 第２の絶縁層
７１ 第２の貫通孔
７２ 金属膜
７３ 接着剤
８０ 第３の絶縁層
８１ 第４の絶縁層
８２ 第４の貫通孔
８３ 第５の絶縁層
８４ 第５の貫通孔
９０ 半導体パッケージ
９１ 半導体装置
９２ 外部接続電極
９３ 導体
９５ ベース材
９６ セラミックスペースト
９７ セラミックスシート
９８ 結晶粒子
９９ レジスト材 DESCRIPTION OF
Claims (19)
- 樹脂絶縁層と、
前記樹脂絶縁層の表面に設けられている電極と、を有する樹脂基板と、
前記樹脂基板上に設けられた第１の絶縁層と、
前記電極上の前記第１の絶縁層に設けられた第１の貫通孔と、
前記第１の絶縁層上および前記第１の貫通孔内に設けられた配線と、を有し、
前記配線は前記電極と電気的に接し、
前記配線は隣接した導電粒子が互いに接合した導電体からなり、
前記第１の絶縁層は酸化物セラミックスからなる
ことを特徴とする配線基板。 A resin insulation layer;
An electrode provided on the surface of the resin insulation layer, and a resin substrate,
A first insulating layer provided on the resin substrate;
A first through hole provided in the first insulating layer on the electrode;
Wiring provided on the first insulating layer and in the first through-hole,
The wiring is in electrical contact with the electrode;
The wiring is made of a conductor in which adjacent conductive particles are joined together,
The wiring board, wherein the first insulating layer is made of an oxide ceramic. - 前記配線は導電粒子と有機化合物を含有した導電性ペーストを焼結させた焼結体である
ことを特徴とする請求項１に記載の配線基板。 The wiring board according to claim 1, wherein the wiring is a sintered body obtained by sintering a conductive paste containing conductive particles and an organic compound. - 前記第１の絶縁層はアルミナ、シリカ、スピネル、ムライト、コーディエライト、ジルコニア、ジルコンからなる群から選択された少なくとも１種の酸化物セラミックスからなることを特徴とする請求項１または２のいずれかに記載の配線基板。 The first insulating layer is made of at least one oxide ceramic selected from the group consisting of alumina, silica, spinel, mullite, cordierite, zirconia, and zircon. A wiring board according to the above.
- 前記樹脂基板表面に設けられソルダーレジストとしての機能を有するソルダーレジスト層をさらに有することを特徴とする請求項１から３のいずれかに記載の配線基板。 The wiring board according to claim 1, further comprising a solder resist layer provided on the surface of the resin substrate and having a function as a solder resist.
- 前記第１の絶縁層と前記樹脂基板の間に設けられた第２の絶縁層と、
前記電極上の前記第２の絶縁層に設けられた第２の貫通孔と、をさらに有する
ことを特徴とする請求項１から４のいずれかに記載の配線基板。 A second insulating layer provided between the first insulating layer and the resin substrate;
5. The wiring board according to claim 1, further comprising a second through hole provided in the second insulating layer on the electrode. - 前記樹脂基板と、前記第１の絶縁層上の前記配線との間に金属膜をさらに有し、
前記第１の絶縁層は透光性を有する酸化物セラミックスからなり、
前記金属膜は前記第１の絶縁層または前記樹脂絶縁層に被覆されている
ことを特徴とする請求項１から４のいずれかに記載の配線基板。 A metal film further between the resin substrate and the wiring on the first insulating layer;
The first insulating layer is made of a translucent oxide ceramic,
The wiring board according to claim 1, wherein the metal film is covered with the first insulating layer or the resin insulating layer. - 前記配線及び前記第１の絶縁層を被覆する第３の絶縁層をさらに有する
ことを特徴とする請求項１から６のいずれかに記載の配線基板。 The wiring board according to claim 1, further comprising a third insulating layer that covers the wiring and the first insulating layer. - 前記第３の絶縁層が酸化物セラミックスからなり、
前記第３の絶縁層に第３の貫通孔が設けられ、
前記第３の絶縁層上および前記第３の貫通孔内に配線が設けられ、
前記配線と酸化物セラミックスからなる層が複数積層されている
ことを特徴とする請求項７に記載の配線基板。 The third insulating layer is made of an oxide ceramic;
A third through hole is provided in the third insulating layer;
Wiring is provided on the third insulating layer and in the third through hole;
The wiring board according to claim 7, wherein a plurality of layers made of the wiring and oxide ceramics are laminated. - 前記第３の絶縁層に第３の貫通孔が設けられ、
前記前記第３の貫通孔の内部に外部接続電極が設けられ、
前記外部接続電極と前記配線が電気的に接していることを特徴とする請求項７に記載の配線基板。 A third through hole is provided in the third insulating layer;
An external connection electrode is provided inside the third through hole,
The wiring board according to claim 7, wherein the external connection electrode and the wiring are in electrical contact. - 前記外部接続電極上に導体が設けられている
ことを特徴とする請求項９に記載の配線基板。 The wiring board according to claim 9, wherein a conductor is provided on the external connection electrode. - 前記第１の絶縁層は、粒子状の結晶を含む多結晶構造を有する酸化物セラミックスからなり、
前記結晶の粒径は前記第１の絶縁層の厚さ方向に変化し、
前記第１の絶縁層上に設けられた前記配線に接する結晶の粒径は、前記樹脂基板に接する結晶の粒径よりも大きいことを特徴とする請求項１から１０のいずれかに記載の配線基板。 The first insulating layer is made of an oxide ceramic having a polycrystalline structure including particulate crystals,
The crystal grain size changes in the thickness direction of the first insulating layer,
11. The wiring according to claim 1, wherein a crystal grain size in contact with the wiring provided on the first insulating layer is larger than a crystal grain size in contact with the resin substrate. substrate. - 請求項１から１１のいずれかに記載の配線基板に
少なくとも１つの半導体装置が搭載されていることを特徴とする半導体パッケージ。 A semiconductor package comprising at least one semiconductor device mounted on the wiring board according to claim 1. - 前記配線が導体を介して前記半導体装置と導通している
ことを特徴とする請求項１２に記載の半導体パッケージ。 The semiconductor package according to claim 12, wherein the wiring is electrically connected to the semiconductor device through a conductor. - 配線基板の製造方法であって、
樹脂基板上に酸化物セラミックスからなる第１の絶縁層を形成する工程と、
前記第１の絶縁層に第１の貫通孔を形成する工程と、
前記第１の絶縁層上と前記第１の貫通孔内に、導電性ペーストを配置する工程と、
前記導電性ペーストを加熱する工程と、
を含むことを特徴とする配線基板の製造方法。 A method for manufacturing a wiring board, comprising:
Forming a first insulating layer made of an oxide ceramic on a resin substrate;
Forming a first through hole in the first insulating layer;
Disposing a conductive paste on the first insulating layer and in the first through hole;
Heating the conductive paste;
A method for manufacturing a wiring board, comprising: - 請求項１４に記載の配線基板の製造方法であって、
樹脂基板上に酸化物セラミックスからなる第１の絶縁層を形成する前記工程と、
前記第１の絶縁層に第１の貫通孔を形成する前記工程とは、
前記第１の貫通孔が設けられているセラミックシートを前記樹脂基板に接着する工程であることを特徴とする配線基板の製造方法。 It is a manufacturing method of the wiring board according to claim 14,
Forming the first insulating layer made of an oxide ceramic on the resin substrate;
The step of forming the first through hole in the first insulating layer is:
A method of manufacturing a wiring board, comprising a step of adhering a ceramic sheet provided with the first through hole to the resin substrate. - 請求項１４に記載の配線基板の製造方法であって、
樹脂基板上に酸化物セラミックスからなる第１の絶縁層を形成する前記工程と、
前記第１の絶縁層に第１の貫通孔を形成する前記工程とは、
樹脂基板上に酸化物セラミックスからなるペーストの一部を転写する工程である
ことを特徴とする配線基板の製造方法。 It is a manufacturing method of the wiring board according to claim 14,
Forming the first insulating layer made of an oxide ceramic on the resin substrate;
The step of forming the first through hole in the first insulating layer is:
A method for manufacturing a wiring board, comprising a step of transferring a part of a paste made of an oxide ceramic onto a resin board. - 請求項１４に記載の配線基板の製造方法であって、
酸化物セラミックスからなる第１の絶縁層を形成する前記工程の前に、
前記樹脂基板上に金属膜を形成する工程と、
前記金属膜の一部を除去する工程と、
をさらに含むことを特徴とする配線基板の製造方法。 It is a manufacturing method of the wiring board according to claim 14,
Before the step of forming the first insulating layer made of oxide ceramics,
Forming a metal film on the resin substrate;
Removing a part of the metal film;
A method for manufacturing a wiring board, further comprising: - 請求項１４または１７に記載の配線基板の製造方法であって、
前記第１の絶縁層を形成する前記工程はエアロゾルデポジション法である
ことを特徴とする配線基板の製造方法。 It is a manufacturing method of the wiring board according to claim 14 or 17,
The method of manufacturing a wiring board, wherein the step of forming the first insulating layer is an aerosol deposition method. - 請求項１８に記載の配線基板の製造方法であって、
前記配線基板に噴射する前記第１の絶縁層の原料微粒子の噴射速度を、
段階的に遅くすることを特徴とする配線基板の製造方法。 It is a manufacturing method of the wiring board according to claim 18,
The spray rate of the raw material fine particles of the first insulating layer sprayed onto the wiring board is
A method of manufacturing a wiring board, characterized by slowing in steps.
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| JP2008-085403 | 2008-03-28 | ||
| JP2008085403A JP2011146408A (en) | 2008-03-28 | 2008-03-28 | Wiring board, semiconductor package, and method of manufacturing the wiring board |
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|---|---|---|---|---|
| JPH06120662A (en) * | 1992-10-05 | 1994-04-28 | Matsushita Electric Ind Co Ltd | Production of multilayer ceramic board |
| JPH1093240A (en) * | 1996-09-10 | 1998-04-10 | Yamaichi Electron Co Ltd | Multilayer wiring board and manufacturing method thereof |
| JP2001007250A (en) * | 1999-06-25 | 2001-01-12 | Ibiden Co Ltd | Package substrate |
| JP2004342831A (en) * | 2003-05-15 | 2004-12-02 | Fujitsu Ltd | Circuit board, manufacturing method therefor and electronic device |
| JP2005191242A (en) * | 2003-12-25 | 2005-07-14 | Ngk Spark Plug Co Ltd | Build-up multilayer wiring board and manufacturing method thereof |
| JP2006147932A (en) * | 2004-11-22 | 2006-06-08 | Kyocera Corp | Multilayer wiring board and its manufacturing method |
| JP2007096246A (en) * | 2005-08-30 | 2007-04-12 | Kyocera Corp | Wiring substrate and electronic device using the same |
| JP2008071905A (en) * | 2006-09-13 | 2008-03-27 | Fujitsu Ltd | Multilayer wiring substrate and semiconductor device, and production method thereof |
-
2008
- 2008-03-28 JP JP2008085403A patent/JP2011146408A/en not_active Withdrawn
-
2009
- 2009-03-26 WO PCT/JP2009/056133 patent/WO2009119745A1/en active Application Filing
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06120662A (en) * | 1992-10-05 | 1994-04-28 | Matsushita Electric Ind Co Ltd | Production of multilayer ceramic board |
| JPH1093240A (en) * | 1996-09-10 | 1998-04-10 | Yamaichi Electron Co Ltd | Multilayer wiring board and manufacturing method thereof |
| JP2001007250A (en) * | 1999-06-25 | 2001-01-12 | Ibiden Co Ltd | Package substrate |
| JP2004342831A (en) * | 2003-05-15 | 2004-12-02 | Fujitsu Ltd | Circuit board, manufacturing method therefor and electronic device |
| JP2005191242A (en) * | 2003-12-25 | 2005-07-14 | Ngk Spark Plug Co Ltd | Build-up multilayer wiring board and manufacturing method thereof |
| JP2006147932A (en) * | 2004-11-22 | 2006-06-08 | Kyocera Corp | Multilayer wiring board and its manufacturing method |
| JP2007096246A (en) * | 2005-08-30 | 2007-04-12 | Kyocera Corp | Wiring substrate and electronic device using the same |
| JP2008071905A (en) * | 2006-09-13 | 2008-03-27 | Fujitsu Ltd | Multilayer wiring substrate and semiconductor device, and production method thereof |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2022243180A1 (en) * | 2021-05-18 | 2022-11-24 | Osram Opto Semiconductors Gmbh | Carrier structure, method for producing a carrier structure and device and printhead for carrying out such a method |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2011146408A (en) | 2011-07-28 |
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