WO2009119745A1 - Carte de câblage, boîtier de semi-conducteur et procédé de fabrication de carte de câblage - Google Patents

Carte de câblage, boîtier de semi-conducteur et procédé de fabrication de carte de câblage Download PDF

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Publication number
WO2009119745A1
WO2009119745A1 PCT/JP2009/056133 JP2009056133W WO2009119745A1 WO 2009119745 A1 WO2009119745 A1 WO 2009119745A1 JP 2009056133 W JP2009056133 W JP 2009056133W WO 2009119745 A1 WO2009119745 A1 WO 2009119745A1
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WO
WIPO (PCT)
Prior art keywords
insulating layer
wiring board
wiring
resin substrate
hole
Prior art date
Application number
PCT/JP2009/056133
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English (en)
Japanese (ja)
Inventor
勝巳 阿部
Original Assignee
日本電気株式会社
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Filing date
Publication date
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Publication of WO2009119745A1 publication Critical patent/WO2009119745A1/fr

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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/4664—Adding a circuit layer by thick film methods, e.g. printing techniques or by other techniques for making conductive patterns by using pastes, inks or powders
    • H05K3/4667—Adding a circuit layer by thick film methods, e.g. printing techniques or by other techniques for making conductive patterns by using pastes, inks or powders characterized by using an inorganic intermediate insulating layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4867—Applying pastes or inks, e.g. screen printing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822—Multilayer substrates
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/111—Pads for surface mounting, e.g. lay-out
    • H05K1/112—Pads for surface mounting, e.g. lay-out directly combined with via connections
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4602—Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H05K1/0313—Organic insulating material
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/09—Use of materials for the conductive, e.g. metallic pattern
    • H05K1/092—Dispersed materials, e.g. conductive pastes or inks
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09372—Pads and lands
    • H05K2201/09436—Pads or lands on permanent coating which covers the other conductors
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/11—Treatments characterised by their effect, e.g. heating, cooling, roughening
    • H05K2203/1131—Sintering, i.e. fusing of metal particles to achieve or improve electrical conductivity
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4688—Composite multilayer circuits, i.e. comprising insulating layers having different properties

Definitions

  • the present invention is based on the priority claim of Japanese Patent Application: Japanese Patent Application No. 2008-085403 (filed on Mar. 28, 2008), the entire contents of which are incorporated herein by reference. Shall.
  • the present invention relates to a wiring board and a manufacturing method thereof, and more particularly to a wiring board on which wiring is formed using a conductive paste containing conductive particles and a manufacturing method thereof.
  • the present invention also relates to a semiconductor package having the wiring board.
  • a circuit pattern is formed using a conductive paste containing metal fine particles. That is, after drawing a circuit pattern on the surface of the core substrate provided with via holes with a conductive paste adjusted so that silver nanoparticles having an average particle diameter of 7 nm do not aggregate, and filling the via holes with silver nanoparticles, By performing heat treatment at 250 ° C. or lower, a circuit pattern made of a silver sintered body is formed. Further, the surface of the circuit pattern is covered with a photoresist, and a via hole is formed in a part of the photoresist. Then, while drawing a circuit pattern with an electrically conductive paste and filling a silver hole with a via hole, the process of heat processing is repeated and the multilayer wiring board is obtained.
  • a wiring is drawn with a paste-like silver nanoparticle dispersion on a transfer sheet surface composed of a polymer material having high heat resistance such as polyimide, By performing a heat treatment at 250 ° C. for 40 minutes, a wiring composed of a sintered body layer of silver nanoparticles is formed. Then, the formed wiring is superimposed on a ceramic substrate having an adhesive layer, heated and pressed to be pressed, and transferred onto the ceramic substrate to obtain a printed board having the wiring on the ceramic substrate.
  • Patent Documents 1 and 2 are incorporated herein by reference. The following analysis is given by the present invention.
  • a circuit pattern is directly formed on a core substrate, and silver nanopaste is heated and sintered when the circuit pattern is formed. Therefore, heat at the time of sintering is transferred to the core substrate, so that a material having a low heat-resistant temperature cannot be used for the core substrate.
  • thermosetting resins such as epoxy and polyimide are used as the core substrate, problems such as warpage of the substrate and deterioration of mechanical characteristics occur due to long-time heating during sintering.
  • a wiring board of the present invention includes a resin insulating layer, a resin substrate having an electrode provided on the surface of the resin insulating layer, and a resin substrate.
  • a first insulating layer provided on the first insulating layer; a first through hole provided in the first insulating layer on the electrode; a wiring provided on the first insulating layer and in the first through hole;
  • a wiring board having the following is provided.
  • the wiring is in electrical contact with the electrode.
  • the wiring is made of a conductor in which adjacent conductive particles are joined to each other.
  • the first insulating layer is made of an oxide ceramic.
  • the wiring is a sintered body obtained by sintering a conductive paste containing conductive particles and an organic compound.
  • the first insulating layer is made of at least one oxide ceramic selected from the group consisting of alumina, silica, spinel, mullite, cordierite, zirconia, and zircon. .
  • the wiring board further includes a solder resist layer provided on the surface of the resin substrate and having a function as a solder resist.
  • the second insulating layer provided between the first insulating layer and the resin substrate, and the second penetration provided in the second insulating layer on the electrode. And a hole.
  • the wiring board further includes a metal film between the resin substrate and the wiring on the first insulating layer.
  • the first insulating layer is made of a translucent oxide ceramic.
  • the metal film is covered with the first insulating layer or the resin insulating layer.
  • the wiring board further includes a third insulating layer covering the wiring and the first insulating layer.
  • the third insulating layer is made of an oxide ceramic.
  • a third through hole is provided in the third insulating layer.
  • Wiring is provided on the third insulating layer and in the third through hole.
  • a plurality of layers made of wiring and oxide ceramics are laminated.
  • the third through hole is provided in the third insulating layer.
  • An external connection electrode is provided inside the third through hole. The external connection electrode and the wiring are in electrical contact.
  • a conductor is provided on the external connection electrode.
  • the first insulating layer is made of oxide ceramics having a polycrystalline structure including particulate crystals.
  • the crystal grain size changes in the thickness direction of the first insulating layer.
  • the crystal grain size in contact with the wiring provided on the first insulating layer is larger than the crystal grain size in contact with the resin substrate.
  • the semiconductor package of the present invention is characterized in that at least one semiconductor device is mounted on the wiring board of the present invention.
  • the wiring is electrically connected to the semiconductor device through the conductor.
  • a method for manufacturing a wiring board according to the present invention includes a step of forming a first insulating layer made of an oxide ceramic on a resin substrate, and a first penetration through the first insulating layer. A step of forming a hole, a step of disposing a conductive paste on the first insulating layer and in the first through hole, and a step of heating the conductive paste.
  • the step of forming the first insulating layer made of oxide ceramics on the resin substrate and the step of forming the first through hole in the first insulating layer are: In this step, the ceramic sheet provided with the first through hole is bonded to the resin substrate.
  • the step of forming the first insulating layer made of oxide ceramics on the resin substrate and the step of forming the first through hole in the first insulating layer are: In this step, a part of the paste made of oxide ceramics is transferred onto the resin substrate.
  • the method for manufacturing a wiring board of the present invention forms a metal film on the resin substrate before the step of forming the first insulating layer made of oxide ceramics. And a step of removing a part of the metal film.
  • the step of forming the first insulating layer is an aerosol deposition method.
  • the spraying speed of the raw material fine particles of the first insulating layer sprayed onto the wiring board is decreased in stages.
  • the top view and sectional drawing of the wiring board which are the 1st Embodiment of this invention The enlarged view of the wiring board which is the 1st Embodiment of this invention Sectional drawing of the semiconductor package using the wiring board of the 1st Embodiment and 2nd Embodiment of this invention
  • the fragmentary sectional view for demonstrating the manufacturing method of the wiring board which is the 1st Embodiment of this invention Sectional drawing and enlarged view of the wiring board which is the 2nd Embodiment of this invention
  • Sectional drawing of the manufacturing method of the wiring board which is the 2nd Embodiment of this invention Sectional drawing and enlarged view of the wiring board which is the 4th Embodiment of this invention
  • Sectional drawing of the manufacturing method of the wiring board which is the 4th Embodiment of this invention Sectional drawing and enlarged view of the wiring board which is the 5th Embodiment of this invention
  • Sectional drawing of the manufacturing method of the wiring board which is the 5th Embodiment of this invention Sectional drawing of
  • a wiring board according to the first embodiment of the present invention will be described.
  • FIG. 1 is a diagram illustrating a configuration of a wiring board 60 according to the present embodiment
  • FIG. 1A is a plan view of the wiring board 60 as viewed from the side where the wiring 50 is provided
  • FIG. ) Is a vertical cross-sectional view along the line AA in FIG. 1A
  • FIG. 1C is a cross-sectional view in the plane direction along the line BB in FIG. 1B
  • FIG. 2 is an enlarged cross-sectional view of the vicinity of the electrode 20 of the wiring board 60.
  • 1 includes a resin substrate 30, a first insulating layer 40, and wiring 50.
  • the resin substrate 30 includes a resin insulating layer 10 and an electrode 20 provided on the surface of the resin insulating layer 10.
  • the resin insulating layer 10 is, for example, one or more selected from the group consisting of epoxy resin, polyimide resin, epoxy acrylate resin, urethane acrylate resin, polyester resin, phenol resin, BCB (benzocycle) and PBO (polybenzoxole).
  • the insulating resin is used.
  • inner layer wiring 21 may be provided inside the insulating resin layer 10, and each inner layer wiring 21 and the electrode 20 may be electrically connected by a via (not shown).
  • the side surface of the electrode 20 shown in FIG. 2 is completely embedded in the resin insulating layer 10, and the surface of the electrode 20 in contact with the wiring 50 is the surface of the resin insulating layer 10 in contact with the first insulating layer 40. It is the same surface as. However, in the wiring substrate 60 of the present embodiment, the surface of the electrode 20 in contact with the wiring 50 may not be flush with the surface of the resin insulating layer 10 in contact with the first insulating layer 40. It may be a concave surface or a convex surface with respect to the surface of the layer 10.
  • the first insulating layer 40 is made of oxide ceramics, is provided on the resin substrate 30, and has a first through hole 41 on the electrode 20.
  • the first insulating layer 40 is made of an oxide ceramic having a low thermal conductivity and a heat resistant temperature higher than that of the insulating resin.
  • the oxide ceramics of the present invention for example, alumina (Al 2 O 3), silica (SiO 2), spinel (MgAl 2 O 4), mullite (3Al 2 O 3 ⁇ 2SiO 2 ), cordierite (2MgO ⁇ 2Al 2 O 3 .5SiO 2 ), zirconia (ZrO 2 ), zircon (ZrSiO 4 ), PLZT ((Pb, La) (Zr, Ti) O 3 ), yttria-tria (Y 2 O 3 —ThO 2 ), etc.
  • the first insulating layer 40 may be made of one kind of oxide ceramics, or may be a mixture of two or more kinds of oxide ceramics.
  • the wiring 50 is provided on the first insulating layer 40 and in the first through hole 41, and is in electrical contact with the electrode 20.
  • the wiring 50 is a conductor in which adjacent conductive particles are joined to each other, and is a sintered body obtained by heating and sintering a conductive paste containing an organic solvent and conductive particles.
  • the wiring 50 is formed by the surface of the conductive particles being melted by the heat at the time of sintering, being cooled in a state where the melted portions of the adjacent conductive particles are joined, and the melted portion solidifying.
  • the organic solvent evaporates due to heat during sintering.
  • conductive particles forming the wiring 50 described in the drawings of the present application are shown in an aligned state, these are schematic representations of the conductive particles.
  • the conductive particles forming the wiring 50 of the present invention are not limited to the aligned particles, and the arrangement thereof may have no regularity.
  • the conductive particles include gold, silver, copper, platinum, palladium, rhodium, osmium, ruthenium, iridium, iron, tin, zinc, cobalt, nickel, chromium, titanium, tantalum, tungsten, indium, and silicon.
  • An alloy made of at least one kind of metal or two or more kinds of metals is used.
  • the conductive particles preferably have a particle size of 1 nanometer to 100 nanometers.
  • the first insulating layer 40 made of oxide ceramics having low thermal conductivity is provided on the resin substrate 30. Therefore, the wiring that is a sintered body of conductive particles is provided. Heat at the time of sintering is difficult to be transmitted to the resin substrate 30 having a low heat-resistant temperature. Therefore, it is possible to suppress the temperature rise of the resin substrate 30 during wiring sintering, and it is possible to obtain a wiring substrate with little deterioration due to the temperature rise of the resin substrate 30.
  • FIG. 3 (a) and 3 (b) are diagrams showing the configuration of the semiconductor package 90 of the present embodiment, in which the semiconductor device 91 is mounted on the wiring substrate 60 of the present embodiment.
  • FIG. 3A shows a semiconductor device 91 mounted on the electrode 20 provided on the surface of the resin substrate 30 that is not in contact with the first insulating layer 40.
  • a conductor 93 such as solder is provided on the electrode 20 so that the semiconductor device 91 and the wiring board 60 are electrically connected.
  • FIG. 3B shows the semiconductor device 91 mounted on the first insulating layer 40 of the wiring board 60.
  • a conductor 93 such as solder is provided on the wiring 50, and the semiconductor device 91 and the wiring substrate 60 are electrically connected.
  • the semiconductor device 91 and the wiring board 60 can be electrically connected by various methods, and can be electrically connected by, for example, flip chip, wire bonding, tape bonding, or the like.
  • the semiconductor device 91 may be one or plural, and the semiconductor device 91 may be mounted on both surfaces of the wiring board 60 by combining FIG. 3A and FIG.
  • the thermal expansion coefficients of the first insulating layer 40 made of oxide ceramics and the semiconductor device 91 are close to each other. Therefore, even if the first insulating layer 40 and the semiconductor device 91 are thermally expanded due to heat generated due to a change in ambient temperature, operation of the semiconductor device, or the like, the amount of thermal expansion becomes a close value. Therefore, the semiconductor package 90 can have high reliability.
  • FIGS. 4A to 4E are partial cross-sectional views showing the method of manufacturing the wiring board 60 of the present embodiment in the order of steps.
  • This sectional view is an enlarged view of the vicinity of the electrode 20 to which the wiring 50 is connected. Note that cleaning and heat treatment are appropriately performed between the respective steps.
  • a resin substrate 30 having electrodes 20 on the surface is prepared.
  • a first insulating layer 40 having a first through hole 41 is formed on the electrode 20.
  • the first insulating layer 40 made of oxide ceramics is formed using an aerosol deposition method (AD method).
  • a mask (not shown) is provided on the electrode 20 in advance, and after the formation of the first insulating layer 40 by the AD method is completed, the mask is removed, whereby the first penetration is formed on the electrode 20.
  • the hole 41 may be formed.
  • the first through-hole 41 may be formed on the electrode 20 by mechanical processing such as ultrasonic precision processing after the first insulating layer 40 is formed on the entire surface of the resin substrate 30 by the AD method.
  • a conductive paste 52 is formed on the first insulating layer 40 made of oxide ceramics and in the first through hole 41 provided in the first insulating layer 40.
  • a method for applying the conductive paste 52 for example, an inkjet method, a dispensing method, a screen printing method, a relief printing method, an imprinting method, or the like can be used.
  • the inkjet method using a device having a head capable of applying a conductive paste, on the first insulating layer 40 and in the first through hole 41 provided in the first insulating layer 40.
  • a conductive paste 52 is applied to the substrate.
  • the applied conductive paste 52 may be drawn with dots, and the dots may be continuously applied to connect the dots to form a wiring.
  • the conductive paste 52 on the first insulating layer 40 is heated to sinter the conductive particles.
  • the surface coated with the conductive paste 52 is irradiated with electromagnetic waves and heated using its absorption characteristics.
  • the electromagnetic wave wavelength is adjusted to the absorption wavelength of the conductive paste 52 and irradiated, the temperature of the conductive paste 52 rises.
  • the temperature is 200 ° C. to 300 ° C., and the time is 2 hours.
  • these sintering conditions are not restricted to this, It is possible to change suitably.
  • a wiring substrate 60 having a wiring 50 made of a conductor in which adjacent conductive particles are bonded to each other can be obtained.
  • a first insulating layer 40 made of oxide ceramics having a low thermal conductivity is provided on a resin substrate having an insulating resin having a low heat-resistant temperature.
  • a conductive paste is applied on the insulating layer.
  • the heat applied to the conductive paste is directly transferred to the resin substrate, so that the temperature rise of the resin substrate becomes significant, causing the resin insulating layer to warp and deteriorate physical properties. It will cause it.
  • the heating of the conductive paste is suppressed in order to prevent deterioration of the physical properties of the resin substrate, the sintering becomes insufficient and there may be a problem in wiring conduction.
  • the wiring is created in a separate process on the transfer sheet. After being sintered on the transfer sheet, the wiring is transferred onto the ceramic substrate.
  • a very thin wiring having a wiring width of several tens of micrometers at the maximum has a low mechanical strength and is brittle. Therefore, there is a problem that there is a high possibility of disconnection due to a stress during transfer.
  • a wiring board having a wiring formed by applying a conductive paste containing conductive particles directly on a substrate having an insulating resin having a low heat-resistant temperature is manufactured. Therefore, there is an effect that disconnection due to transfer does not occur.
  • FIG. 5 is a diagram showing a configuration of the wiring board 60 of the present embodiment
  • FIG. 5A is a schematic cross-sectional view
  • FIG. It is.
  • solder resist layer 11 having a function as a solder resist is provided on the surface of the resin substrate 30.
  • the solder resist layer 11 is provided so that the electrode 20 is exposed, and the periphery of the electrode 20 is covered with the solder resist layer 11. Further, a step is provided at the boundary between the exposed surface of the electrode 20 and the exposed surface of the solder resist layer 11, and the exposed surface of the electrode 20 is provided at a position lower than the exposed surface of the solder resist layer 11.
  • a part of the electrode 20 may be embedded in the resin insulating layer 10, or the entire electrode 20 may be embedded in the resin insulating layer 10 as in the first embodiment.
  • the first insulating layer 40 and the wiring 50 are provided in the same manner as the wiring substrate according to the first embodiment.
  • the wiring 50 provided on the first insulating layer 40 is in electrical contact with the electrode 20 through the first through hole 41.
  • the solder resist layer 11 may be, for example, a thermosetting resin, and is preferably an epoxy resin, for example.
  • the wiring board according to the present embodiment it is possible to form the wiring covered with the solder resist layer 11 on the surface of the resin substrate 30. As a result, the wiring can be multi-layered.
  • the resin insulating layer 10 is covered with the solder resist layer 11, the resin insulating layer 10 can be protected when the first insulating layer 40 is formed.
  • FIG. 3C is a diagram showing a configuration of the semiconductor package 90 of the present embodiment.
  • the semiconductor package 90 of the present embodiment is obtained by mounting the semiconductor device 91 on the wiring board of the present embodiment.
  • the mounting surface of the semiconductor device 91, the number of the semiconductor devices 91, the connection method of the semiconductor devices 91, and the like. Is the same as the semiconductor package of the first embodiment.
  • a conductor 93 such as solder is provided on the electrode 20 of the resin substrate 30, and a region for mounting the semiconductor device 91 is provided there. It is also possible. That is, it is possible to form a normal mounting region and a mounting region having the wiring 50 obtained by sintering the conductive paste on one wiring board.
  • 6 (a) to 6 (f) are partial cross-sectional views showing the method of manufacturing the wiring board 60 of the present embodiment in the order of steps. Note that cleaning and heat treatment are appropriately performed between the respective steps.
  • a resin substrate 30 is prepared in which an electrode 20 whose surface is exposed is disposed and a solder resist layer 11 is formed so as to cover the resin insulating layer 10.
  • the electrode 20 only needs to have its surface exposed, and a part of the electrode 20 may be embedded in the resin insulating layer 10 or the entire electrode 20 may be embedded in the resin insulating layer 10.
  • the solder resist layer 11 is formed so that at least a part of the electrode 20 is exposed, and a step is provided at the boundary between the exposed surface (upper surface) of the electrode 20 and the exposed surface (upper surface) of the solder resist layer 11.
  • the exposed surface (upper surface) of the electrode 20 is provided at a position lower than the exposed surface (upper surface) of the solder resist layer 11.
  • FIGS. 6B and 6C show a process of forming the first insulating layer 40 made of oxide ceramics on the surface of the resin substrate 30.
  • the surface of the solder resist layer 11 may be roughened in advance by mechanical polishing or the like in order to improve adhesion to the ceramic paste due to the anchor effect.
  • the solder resist layer 11 is brought into contact with a base material 95 such as elastic rubber printed on a ceramic paste 96 having a uniform thickness.
  • the ceramic paste 96 is transferred only to the portion where the solder resist layer 11 is provided. However, if the electrode 20 is sufficiently exposed, the ceramic paste may be transferred to a part of the exposed surface of the electrode 20.
  • the ceramic paste for example, a ceramic paste having high heat resistance containing ceramics such as alumina, mullite, and cordierite may be used.
  • the ceramic paste is left to stand at a temperature lower than the heat resistance temperature of the resin insulating layer 10 and the solder resist layer 11 to cure the first insulating layer 40. It was.
  • a conductive paste 52 is applied on the first insulating layer 40 and in the first through holes 41 provided in the first insulating layer 40. The subsequent steps are the same as the steps after FIG.
  • a mask for providing the first through hole 41 of the method for manufacturing the wiring substrate according to the first embodiment and a drilling step by machining are not used.
  • the first through hole 41 can be formed in the first insulating layer 40.
  • the state when the ceramic paste 96 is transferred to the surface of the electrode 20 can be controlled.
  • Examples of the white or light oxide ceramics in the present embodiment include alumina (Al 2 O 3 ), silica (SiO 2 ), spinel (MgAl 2 O 4 ), or mullite (3Al 2 O 3 .2SiO 2). ), Cordierite (2MgO ⁇ 2Al 2 O 3 ⁇ 5SiO 2 ) and other oxide-ceramics such as alumina-silica-based double oxides may be zirconia (ZrO 2 ), zircon (ZrSiO). 4 ) and the like.
  • the conductive paste 52 before sintering is irradiated with electromagnetic waves and heated.
  • the heating electromagnetic wave include visible light having a wavelength longer than that of ultraviolet light, infrared light, far infrared light, microwaves, and millimeter waves.
  • the electromagnetic wave irradiated when the wiring 50 is sintered is applied not only to the wiring but also to the first insulating layer 40 existing around the wiring.
  • the electromagnetic wave is hardly absorbed by the white or light-colored oxide ceramics and is reflected by the oxide ceramics. That is, the electromagnetic wave heats only the conductive paste 52 and the surrounding first insulating layer 40 becomes difficult to be heated, so that the temperature rise of the resin substrate 30 existing below the first insulating layer 40 is suppressed. Is possible.
  • the semiconductor package of the present embodiment is obtained by mounting a semiconductor device on the wiring substrate of the present embodiment. Regarding the mounting surface of the semiconductor device, the number of semiconductor devices, the connection method of the semiconductor devices, etc. This is the same as the semiconductor package of the embodiment.
  • FIG. 7 is a diagram showing a configuration of the wiring board 60 of the present embodiment
  • FIG. 7A is a schematic cross-sectional view
  • FIG. 7B is an enlarged cross-sectional view of the vicinity of the electrode 20 of the wiring board 60. It is.
  • a second insulating layer 70 is provided between the resin substrate 30 and the first insulating layer 40.
  • a second through hole 71 is provided in the second insulating layer 70 on the electrode 20, and a wiring 50 is also provided in the second through hole 71, and the wiring 50 and the electrode 20 are in electrical contact.
  • the second insulating layer 70 is for adhering the ceramic sheet forming the first insulating layer 40 to the resin substrate 30.
  • an epoxy-based adhesive having heat resistance, or an alumina or zirconia-based adhesive can be used.
  • the ceramic sheet is a composite material of oxide ceramics and fibers, and the oxide ceramics are already fired. This ceramic sheet is formed into a sheet shape and has high flatness.
  • the first insulating layer 40 is formed using a ceramic sheet having high flatness, the flatness of the surface on which the wiring 50 is formed is increased. Can be provided. When the flatness of the surface on which the wiring 50 is formed is high, the line width of the wiring 50 formed by applying the conductive paste becomes uniform, and the conduction is stabilized. Therefore, it is possible to form a finer wiring 50.
  • the semiconductor package of the present embodiment is obtained by mounting a semiconductor device on the wiring substrate of the present embodiment. Regarding the mounting surface of the semiconductor device, the number of semiconductor devices, the connection method of the semiconductor devices, etc. This is the same as the semiconductor package of the embodiment.
  • a wiring board having fine wiring can be used, so that a semiconductor device having many connection electrodes can be mounted. This is because fine wiring can be formed, and even if the number of connection electrodes is large, many wirings can be routed.
  • 8 (a) to 8 (f) are partial cross-sectional views showing the method of manufacturing the wiring board 60 of this embodiment in the order of steps. Note that cleaning and heat treatment are appropriately performed between the respective steps.
  • a resin substrate 30 on which the electrode 20 whose surface is exposed is arranged is prepared.
  • the electrode 20 only needs to have its surface exposed, and a part of the electrode 20 may be embedded in the resin insulating layer 10 or the entire electrode 20 may be embedded in the resin insulating layer 10.
  • a ceramic sheet 97 provided with a first through hole 41 corresponding to the position of the electrode 20 in advance is prepared, and an epoxy-based adhesive having heat resistance or Then, an adhesive 73 based on alumina or zirconia is applied to the ceramic sheet 97. Thereafter, the ceramic sheet 97 and the resin substrate 30 are positioned.
  • the ceramic sheet 97 is adhered to the resin substrate 30 via the adhesive 73, whereby a first insulating layer is formed.
  • the flatness of the first insulating layer 40 can be increased. I can do it.
  • the flatness of the first insulating layer 40 is high, the thickness and line width of the conductive paste applied thereon become uniform, and it is possible to form a wiring board having wiring with stable electrical conduction. Become.
  • FIG. 9 is a diagram illustrating a configuration of the wiring board 60 of the present embodiment
  • FIG. 9A is a schematic cross-sectional view
  • FIG. 9B is an enlarged cross-sectional view of the vicinity of the electrode 20 of the wiring board 60. It is.
  • a metal film 72 that reflects electromagnetic waves is provided between the resin substrate 30 and the wiring 50 on the first insulating layer 40, and the first insulating layer 40 is transparent. It is the point which is formed with the property ceramics. Other structures are the same as those in the first embodiment.
  • the metal film 72 shown in FIGS. 9A and 9B is provided on the resin substrate 30 where the electrode 20 is not formed so as not to contact the wiring 50 and the electrode 20. Yes.
  • the metal film 72 may not be in contact with the electrode 20 and the wiring 50, and the metal film 72 may not be in contact with the resin substrate 30. It may be provided inside the first insulating layer 40.
  • the metal film 72 is provided inside the first insulating layer 40 and is at a position away from the resin substrate 30, the irradiated electromagnetic wave is reflected at a position away from the resin substrate 30 and heated by the electromagnetic wave. Therefore, the heating of the resin substrate 30 is further suppressed.
  • the metal film 72 only needs to reflect an electromagnetic wave irradiated when the wiring 50 is sintered.
  • at least one kind of metal among copper, silver, gold, nickel, aluminum, and palladium, or two kinds It can select from the alloy which consists of the above metal.
  • the translucent ceramic include alumina (Al 2 O 3 ), PLZT ((Pb, La) (Zr, Ti) O 3 ), yttria-tria (Y 2 O 3 —ThO 2 ), spinel ( Oxide ceramics such as MgAl 2 O 4 ) can be used.
  • the semiconductor package of the present embodiment is obtained by mounting a semiconductor device on the wiring substrate of the present embodiment. Regarding the mounting surface of the semiconductor device, the number of semiconductor devices, the connection method of the semiconductor devices, etc. This is the same as the semiconductor package of the embodiment.
  • 10 (a) to 10 (i) are partial cross-sectional views showing a method of manufacturing the wiring board 60 of this embodiment in the order of steps. Note that cleaning and heat treatment are appropriately performed between the respective steps.
  • a resin substrate 30 on which the electrode 20 with the exposed surface is arranged is prepared.
  • the electrode 20 only needs to have its surface exposed, and a part of the electrode 20 may be embedded in the resin insulating layer 10 or the entire electrode 20 may be embedded in the resin insulating layer 10.
  • a metal film 72 is formed on the surface of the resin substrate 30.
  • the metal film 72 is formed by sputtering.
  • a resist material 99 is applied and cured on the metal film 72 by screen printing or the like.
  • the metal film 72 near the electrode 20 is removed by etching.
  • a first insulating layer 40 made of translucent ceramics is formed.
  • metal oxide particles having a low electromagnetic wave absorptivity collide with a metal film forming surface at high speed the particles are miniaturized and bonded to each other to form a translucent oxide ceramic.
  • the oxide ceramics having translucency can be formed.
  • a conductive paste 52 is applied on the first insulating layer 40 and in the first through holes 41 provided in the first insulating layer 40.
  • the subsequent steps are the same as those shown in FIG. 10 (g).
  • the metal film 72 can be formed not only on the resin substrate 30 but also inside the first insulating layer 40.
  • the metal film 72 may be formed on the surface, and the first insulating layer 40 may be further formed thereon.
  • an electromagnetic wave irradiated for heating passes through the first insulating layer 40, is reflected by the metal film 72, and is emitted to the outside.
  • the temperature rise of the first insulating layer 40 and the resin substrate 30 due to irradiation can be further suppressed.
  • the electromagnetic wave reflected by the metal film 72 can also heat the back surface of the conductive paste 52. Since the conductive paste 52 is heated from both sides by the directly irradiated electromagnetic wave and the reflected electromagnetic wave, the bonding of adjacent conductive particles is ensured. Therefore, the highly reliable wiring 50 can be formed.
  • FIG. 11 is a diagram showing a configuration of the wiring board 60 of the present embodiment.
  • the difference from the first embodiment is that a third insulating layer 80 that covers the first insulating layer 40 and the wiring 50 is provided.
  • the third insulating layer 80 only needs to be an insulating material, and is an organic insulating material such as an epoxy resin or polyimide, or an inorganic insulating material such as an oxide ceramic, as in a general wiring board. Also good.
  • By covering the wiring 50 with the third insulating layer 80 it is possible to protect the wiring 50, and it is possible to form the wiring substrate 60 with good reliability and handling properties.
  • the semiconductor package of the present embodiment is obtained by mounting a semiconductor device on the wiring board of the present embodiment.
  • the semiconductor device 91 cannot be mounted on the wiring 50 as shown in FIG. However, as shown in FIG. 3A, it is possible to mount the semiconductor device 91 on the electrode 20 on the surface where the first insulating layer 40 is not provided.
  • the semiconductor device connection method and the like are the same as those of the semiconductor package of the first embodiment.
  • the manufacturing method of the present embodiment is realized by adding a step of forming the third insulating layer 80 so as to cover the wiring 50 and the first insulating layer 40 after the wiring 50 is sintered.
  • the third insulating layer 80 is formed by, for example, applying a thermosetting insulating resin such as polyimide so as to cover the wiring 50 by heat-curing, as in a general insulating layer forming method. It can be formed.
  • the third insulating layer 80 made of oxide ceramics may be formed by an aerosol deposition method (AD method).
  • AD method aerosol deposition method
  • FIG. 12 is a diagram showing a configuration of the wiring board 60 of the present embodiment.
  • the wiring 50 is not limited to a single layer, and a wiring 50 having two or more layers can be formed.
  • the wiring 50 is covered with a fourth insulating layer 81, and a fourth through hole 82 is formed in the fourth insulating layer 81.
  • the wiring 50 can be provided in a plurality of layers.
  • the wiring 50 can be heated at a high temperature and has a low specific resistance. Can do.
  • the fourth insulating layer 81 may not be an oxide ceramic but may be an insulating material.
  • the uppermost layer wiring is exposed, but an insulating layer covering the uppermost layer wiring may be provided.
  • the wiring 50 can be multi-layered, the wiring can be easily routed and a semiconductor device having many connection electrodes can be mounted. Therefore, high-density mounting is possible.
  • the semiconductor package of the present embodiment is obtained by mounting a semiconductor device on the wiring substrate of the present embodiment. Regarding the mounting surface of the semiconductor device, the number of semiconductor devices, the connection method of the semiconductor devices, etc. This is the same as the semiconductor package of the embodiment.
  • FIG. 13A and FIG. 13B are diagrams showing the configuration of the wiring board 60 of the present embodiment.
  • the fifth through hole 84 is provided in the fifth insulating layer 83 covering the uppermost wiring 50 and a part of the wiring 50 is exposed.
  • the exposed wiring may be subjected to surface treatment by Ni / Au plating or the like, and this may be used as the external connection electrode 92. Further, as shown in FIG. 13B, by mounting a conductor 93 such as solder on the external connection electrode 92, it can be handled in the same manner as a general mounting component.
  • the semiconductor package of the present embodiment is obtained by mounting a semiconductor device on the wiring substrate of the present embodiment. Regarding the mounting surface of the semiconductor device, the number of semiconductor devices, the connection method of the semiconductor devices, etc. This is the same as the semiconductor package of the embodiment.
  • a semiconductor device can be mounted by providing a conductor such as solder on the external connection electrode 92.
  • the semiconductor device connection method and the like are the same as those of the semiconductor package of the first embodiment.
  • FIG. 14A is a diagram showing a configuration of the wiring board 60 of the present embodiment, and is a diagram schematically showing an enlarged cross section near the electrode 20 of the wiring board 60.
  • the difference from the first embodiment is that the diameter of the crystal grains 98 constituting the first insulating layer is not uniform and changes in the thickness direction of the layer.
  • the diameter of the crystal particles 98 in the layer close to the resin substrate 30 forms a dense structure of about several tens of nanometers, the diameter of the crystal particles 98 gradually increases, and the crystal of the layer in contact with the wiring on the upper surface of the first insulating layer
  • the diameter of the particles 98 is a rough structure of about several hundred nanometers to several micrometers. Other structures are the same as those in the first embodiment.
  • FIGS. 14B and 14C are diagrams schematically showing an enlarged portion where the wiring 50 and the first insulating layer 40 are in contact with each other.
  • the layer in contact with the resin substrate 30 of the first insulating layer 40 should have a relatively small crystal grain size of about several tens of nanometers in order to improve the adhesion with the resin substrate 30.
  • the layer of the first insulating layer 40 in contact with the wiring 50 should have a relatively large crystal grain size of about several hundred nanometers to several micrometers.
  • the wiring 50 since the wiring 50 is formed by bonding particulate conductors, the wiring 50 has a larger particle diameter of the first insulating layer 40 in contact with the wiring 50. It becomes easy to enter the unevenness of the first insulating layer 40. As a result, an effect of increasing the adhesion strength between the wiring 50 and the first insulating layer 40 is obtained.
  • the semiconductor package of the present embodiment is obtained by mounting a semiconductor device on the wiring substrate of the present embodiment. Regarding the mounting surface of the semiconductor device, the number of semiconductor devices, the connection method of the semiconductor devices, etc. This is the same as the semiconductor package of the embodiment.
  • the speed of the particles to be collided is high in the initial stage of the stacking, and is gradually reduced in stages to thereby reduce the crystal in the initial stage of the stacking.
  • the grain size forms a dense structure of about several tens of nanometers, the crystal grain size gradually increases, and the crystal grain size in the later stage of lamination becomes a coarse structure of about several hundred nanometers to several micrometers. Thereafter, wirings are stacked as in the first embodiment.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Ceramic Engineering (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

Dans une carte de câblage présentant des câblages formés sur un substrat en résine à l'aide d'une pâte conductrice, de la chaleur générée au moment de fritter la pâte conductrice est transmise au substrat en résine, de telle sorte qu'une température de résistance à la chaleur basse ne peut pas être utilisée pour le substrat en résine. En outre, un long chauffage au moment du frittage pose des problèmes, tels qu'un gauchissement du substrat en résine et une détérioration de ses caractéristiques mécaniques. De plus, si le frittage est effectué à une température basse pour éviter un gauchissement du substrat en résine et une détérioration de ses caractéristiques mécaniques, la pâte conductrice peut être frittée de manière incomplète, ce qui augmente la résistance de conduction des câblages frittés. Selon l'invention, une couche d'oxyde céramique est installée entre le câblage et le substrat en résine.
PCT/JP2009/056133 2008-03-28 2009-03-26 Carte de câblage, boîtier de semi-conducteur et procédé de fabrication de carte de câblage WO2009119745A1 (fr)

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JP2008085403A JP2011146408A (ja) 2008-03-28 2008-03-28 配線基板、半導体パッケージおよび配線基板の製造方法
JP2008-085403 2008-03-28

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WO2022243180A1 (fr) * 2021-05-18 2022-11-24 Osram Opto Semiconductors Gmbh Structure de support, procédé de fabrication d'une structure de support et dispositif et tête d'impression pour la mise en œuvre d'un tel procédé

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JP6079501B2 (ja) * 2013-08-12 2017-02-15 アイシン・エィ・ダブリュ株式会社 電子部品モジュール
CN104185360B (zh) * 2014-08-18 2017-05-24 深圳市华星光电技术有限公司 一种印刷电路板及其设计方法
KR101619455B1 (ko) * 2014-11-18 2016-05-11 주식회사 프로텍 적층형 반도체 패키지의 제조방법
JP6462408B2 (ja) * 2015-02-25 2019-01-30 京セラ株式会社 センサ基板および検出装置
JP7004921B2 (ja) 2019-04-26 2022-01-21 日亜化学工業株式会社 発光モジュールの製造方法及び発光モジュール

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JPH1093240A (ja) * 1996-09-10 1998-04-10 Yamaichi Electron Co Ltd 多層配線板および多層配線板の製造方法
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