KR101046255B1 - Method for patterning with copper foil on pcb - Google Patents

Method for patterning with copper foil on pcb Download PDF

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Publication number
KR101046255B1
KR101046255B1 KR1020100029663A KR20100029663A KR101046255B1 KR 101046255 B1 KR101046255 B1 KR 101046255B1 KR 1020100029663 A KR1020100029663 A KR 1020100029663A KR 20100029663 A KR20100029663 A KR 20100029663A KR 101046255 B1 KR101046255 B1 KR 101046255B1
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South Korea
Prior art keywords
copper foil
carrier paper
resin layer
laser beam
conductive circuit
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KR1020100029663A
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Korean (ko)
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이창덕
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앰코 테크놀로지 코리아 주식회사
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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/007—Manufacture or processing of a substrate for a printed circuit board supported by a temporary or sacrificial carrier
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B32—LAYERED PRODUCTS
    • B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B15/00—Layered products comprising a layer of metal
    • B32B15/20—Layered products comprising a layer of metal comprising aluminium or copper
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0058—Laminating printed circuit boards onto other substrates, e.g. metallic substrates
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/15—Position of the PCB during processing
    • H05K2203/1536—Temporarily stacked PCBs

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing Of Printed Circuit Boards (AREA)

Abstract

PURPOSE: A method for forming the pattern of a printed circuit substrate for a semiconductor package is provided to easily form a conductive circuit pattern by irradiating laser beam after sticking the carrier paper with a copper foil on the base resin of the substrate. CONSTITUTION: A carrier paper(100) is formed with the lamination of a copper foil(102) on one side. The carrier paper is attached to a base resin layer(104) for a printed circuit board. The surface of the copper foil is attached to the surface of the resin layer. A laser beam(106) is shot on the surface of the carrier paper according to the route in which a conductive circuit pattern is formed. A conductive circuit pattern(108) is formed on the surface of the resin layer.

Description

반도체 패키지 제조용 인쇄회로기판의 패턴 형성 방법{Method for patterning with copper foil on PCB}Pattern Forming Method of Printed Circuit Board for Manufacturing Semiconductor Package {Method for patterning with copper foil on PCB}

본 발명은 인쇄회로기판 제조 방법에 관한 것으로서, 더욱 상세하게는 카본 페이퍼의 카본입자가 종이에 새겨지는 원리와 같이, 동박이 입혀진 캐리어 페이퍼에 레이저를 조사하여 기판의 베이스 수지면에 도전성 회로패턴을 용이하게 형성시킬 수 있도록 한 반도체 패키지 제조용 인쇄회로기판의 패턴 형성 방법에 관한 것이다.
The present invention relates to a method for manufacturing a printed circuit board, and more particularly, to conduct a conductive circuit pattern on a base resin surface of a substrate by irradiating a laser on a copper foil coated carrier paper, as in the principle that carbon particles of carbon paper are engraved on paper. The present invention relates to a pattern forming method of a printed circuit board for manufacturing a semiconductor package.

통상적으로, PCB(Printed Circuit Board: 이하, 인쇄회로기판으로 칭함)는 반도체 패키지를 제조하기 위한 기판, 또는 반도체 패키지가 전자기기에 실장되기 위한 마더보드 등 각종 전자제품 및 부품 등에 필수적으로 사용되고 있다.In general, a printed circuit board (PCB) is essentially used in various electronic products and components such as a substrate for manufacturing a semiconductor package or a motherboard for mounting the semiconductor package on an electronic device.

반도체 패키지 제조용 인쇄회로기판의 일례를 첨부한 도 3 내지 도 5를 참조로 살펴보면 다음과 같다. Referring to Figures 3 to 5 attached to an example of a printed circuit board for manufacturing a semiconductor package as follows.

상기 인쇄회로기판(10)은 전자 기판용 BT(Bismaleimide-Triazine) 수지로 이루어진 수지층(12)을 중심으로 그 상면 중앙부에는 반도체 칩이 실장될 수 있는 칩탑재부가 형성되고, 상기 칩탑재부의 주변에는 방사상으로 전도성 회로패턴(16)이 소정의 회로배선 형태로 형성된다.The printed circuit board 10 has a chip mounting portion on which a semiconductor chip can be mounted and is formed in a central portion of the upper surface of the printed circuit board 10 with a resin layer 12 made of a Bismaleimide-Triazine (BT) resin for an electronic substrate. In the radially conductive circuit pattern 16 is formed in a predetermined circuit wiring form.

또한, 상기 수지층(12)의 상부에서 하부를 향하여 전도성 비아홀(18)이 형성되는 동시에 비아홀(18)의 하단부는 입출력단자인 솔더볼이 융착되는 볼랜드(20)로 형성되고, 상기 수지층(12)의 상하면에는 전도성 회로패턴(16)의 일부 및 볼랜드(20)를 제외하고는 절연재인 솔더마스크(22)로 코팅된다.In addition, the conductive via hole 18 is formed from the upper portion of the resin layer 12 toward the lower portion, and the lower end portion of the via hole 18 is formed of a ball land 20 to which solder balls, which are input / output terminals, are fused, and the resin layer 12 is formed. The upper and lower surfaces of the) are coated with a solder mask 22 that is an insulating material except for a part of the conductive circuit pattern 16 and the borland 20.

물론, 상기한 인쇄회로기판은 수지층(12) 위에 솔더마스크(22) 및 전도성 회로패턴(16)을 겹겹이 쌓아서 다층 구조로 제작될 수 있다.Of course, the printed circuit board may be manufactured in a multilayer structure by stacking the solder mask 22 and the conductive circuit pattern 16 on the resin layer 12.

이러한 구조를 갖는 인쇄회로기판의 수지층에 에칭, 세미 에디티브 등의 방법을 이용하여 전도성 회로패턴들을 형성하게 되는 바, 전자기기의 발전 동향이 점차 경박단소화되어 가는 추세에 따라 인쇄회로기판에 형성되는 각 전도성 회로패턴들이 점점 파인피치(fine pitch)화되어 가고 있다.Conductive circuit patterns are formed on a resin layer of a printed circuit board having such a structure by etching, semi-additive, etc. As the development trend of electronic devices is gradually thin and short, the printed circuit board is Each conductive circuit pattern to be formed is increasingly fine pitch.

종래 기술에 따르면, 인쇄회로기판의 수지층에 전도성 회로패턴 형성을 위해 에칭 및 도금 방법의 리소그래피(Lithography) 방식을 사용함에 따라, 에칭 레지스트 또는 도금 레지스트 등의 노광-현상-박리 공정을 거치게 되어 그에 따른 복잡한 공정과 제조비용을 높이는 등 많은 문제점이 있었다.According to the related art, as a lithography method of an etching and a plating method is used to form a conductive circuit pattern on a resin layer of a printed circuit board, an exposure-developing-peeling process such as an etching resist or a plating resist is performed. There are many problems, such as increasing the complexity of the process and manufacturing costs.

즉, 종래의 리소그래피 방법을 응용한 전도성 회로패턴 형성 방법은 한 층에 대한 회로를 형성하기 위해 노광 전처리→ 드라이 필름 도포→ 노광→ 현상→ 에칭 방식으로 진행됨에 따라, 화학적 에칭을 비롯한 공정수가 많이 들고, 치공구 관리 및 설비 등이 많이 소요되어 제조 비용이 매우 높으며, 드라이 필름 현상에 사용되는 알칼리 용액, 에칭 공정시의 염화동 용액 등 비환경 친화적인 폐기물이 발생되며, 또한 미세화 되어가는 반도체 회로에 대응하는데 한계가 되는 문제점이 있었다.That is, the conductive circuit pattern forming method applying the conventional lithography method proceeds with the exposure pretreatment → dry film application → exposure → development → etching method to form a circuit for one layer. The production cost is very high due to the large number of tools, tools and management, and non-environmental waste such as alkaline solution used for dry film development and copper chloride solution during etching process, and also to cope with the miniaturization of semiconductor circuits. There was a limiting problem.

이에, 위와 같은 종래의 전도성 회로패턴을 형성하는 방법에서의 문제점을 해소시키고, 미세 피치를 구현하며, 환경 문제를 해결할 수 있는 방법이 요구되고 있다.
Therefore, there is a need for a method of solving the problems in the conventional method of forming a conductive circuit pattern as described above, implementing a fine pitch, and solving environmental problems.

본 발명은 상기와 같은 종래의 문제점을 감안하여 안출한 것으로서, 카본 페이퍼의 카본입자가 종이에 새겨지는 원리와 같이, 일면에 동박이 부착된 캐리어 페이퍼를 수지층상에 접착시킨 다음, 레이저 빔을 캐리어 페이퍼에 조사시킴으로써, 레이저로 조사된 부위에 해당하는 동박의 일부만이 캐리어 페이퍼로부터 박리되면서 수지층의 표면에 전도성 회로패턴으로 형성될 수 있도록 한 반도체 패키지 제조용 인쇄회로기판의 패턴 형성 방법을 제공하는데 그 목적이 있다.
The present invention has been made in view of the above-described conventional problems, and the carrier paper having copper foil adhered to one surface is adhered to the resin layer on the basis of the principle that the carbon particles of the carbon paper are engraved on the paper, and then the laser beam is carried on the carrier. By irradiating the paper, only a part of the copper foil corresponding to the laser irradiated portion is peeled from the carrier paper while providing a pattern forming method of a printed circuit board for manufacturing a semiconductor package, so that a conductive circuit pattern can be formed on the surface of the resin layer. There is a purpose.

상기한 목적을 달성하기 위한 본 발명은 일면에 동박이 라미네이팅된 캐리어 페이퍼를 구비하는 단계와; 상기 캐리어 페이퍼를 인쇄회로기판용 베이스 수지층의 표면에 부착하되, 동박의 표면이 수지층의 표면에 부착되게 하는 단계와; 상기 캐리어 페이퍼의 표면에 전도성 회로패턴이 형성될 경로를 따라 레이저 빔을 조사하는 단계와; 레이저 빔이 조사된 동박의 일부가 캐리어 페이퍼로부터 박리되면서 수지층의 표면에 전도성 회로패턴들로 형성되는 단계; 를 포함하는 것을 특징으로 하는 반도체 패키지 제조용 인쇄회로기판의 패턴 형성 방법을 제공한다.The present invention for achieving the above object comprises the steps of providing a copper foil laminated carrier paper on one surface; Attaching the carrier paper to the surface of the base resin layer for a printed circuit board, wherein the surface of the copper foil is attached to the surface of the resin layer; Irradiating a laser beam along a path in which a conductive circuit pattern is to be formed on a surface of the carrier paper; A portion of the copper foil to which the laser beam is irradiated is peeled off from the carrier paper and formed of conductive circuit patterns on the surface of the resin layer; It provides a pattern forming method of a printed circuit board for manufacturing a semiconductor package comprising a.

바람직한 일 구현예로서, 레이저 빔이 조사되지 않은 동박은 캐리어 페이퍼와 함께 떼내어져 제거되는 단계와, 상기 전도성 회로패턴간의 절연을 위하여 수지층상에 솔더 레지스트를 코팅하는 단계가 더 진행되는 것을 특징으로 한다.In a preferred embodiment, the copper foil to which the laser beam has not been irradiated is removed and removed together with the carrier paper, and the step of coating the solder resist on the resin layer for insulation between the conductive circuit patterns is further performed. .

바람직한 다른 구현예로서, 상기 솔더 레지스트의 상면에 동박이 라미네이팅된 캐리어 페이퍼를 다시 부착시킨 후, 이 캐리어 페이퍼에 레이저 빔을 조사하는 단계를 반복하여, 솔더 레지스트를 사이에 두고 2층 이상의 전도성 회로패턴이 형성되도록 한 것을 특징으로 한다.
In another preferred embodiment, after re-attaching the copper foil laminated carrier paper on the upper surface of the solder resist, the step of irradiating a laser beam on the carrier paper is repeated, and the conductive circuit pattern of two or more layers with the solder resist interposed therebetween. It is characterized in that it is formed.

상기한 과제 해결 수단을 통하여, 본 발명은 다음과 같은 효과를 제공한다.Through the above problem solving means, the present invention provides the following effects.

본 발명에 따르면, 동박이 입혀진 캐리어 페이퍼를 기판의 베이스 수지면에 밀착시킨 다음, 레이저를 조사함으로써, 레이저로 조사된 부위에 해당하는 동박의 일부만이 캐리어 페이퍼로부터 박리되면서 수지층의 표면에 전도성 회로패턴으로 용이하게 형성될 수 있다.According to the present invention, the copper foil coated carrier paper is brought into close contact with the base resin surface of the substrate, and then irradiated with a laser, so that only a part of the copper foil corresponding to the laser irradiated portion is peeled off from the carrier paper and the conductive circuit pattern is formed on the surface of the resin layer. It can be formed easily.

이렇게, 레이저 빔을 동박이 입혀진 캐리어 페이퍼에 조사하여 전도성 회로패턴을 형성함에 따라, 작업 공정 및 시스템의 구성이 간단하여 인쇄회로기판의 제조 비용을 절감하면서 생산성을 향상시킬 수 있다.
Thus, as the conductive beam pattern is formed by irradiating the laser beam on the copper foil coated carrier paper, the work process and the configuration of the system can be simplified to improve productivity while reducing the manufacturing cost of the printed circuit board.

도 1 및 도 2는 본 발명에 따른 인쇄회로기판의 패턴 형성 방법을 설명하는 개략도,
도 3 및 도 4는 일반적인 인쇄회로기판의 구조를 설명하는 도면이고, 도 5는 도 3의 A-A선 단면도이다.1 and 2 is a schematic diagram illustrating a pattern forming method of a printed circuit board according to the present invention;
3 and 4 are views illustrating a structure of a general printed circuit board, and FIG. 5 is a cross-sectional view taken along the line AA of FIG. 3.

이하, 본 발명의 바람직한 실시예를 첨부도면을 참조로 상세하게 설명하기로 한다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

첨부한 도 1 및 도 2는 본 발명에 따른 인쇄회로기판의 패턴 형성 방법을 설명하는 개략도이다.1 and 2 are schematic views illustrating a method for forming a pattern of a printed circuit board according to the present invention.

본 발명은 카본 페이퍼의 카본입자가 종이에 새겨지는 원리와 같이, 일면에 동박이 부착된 캐리어 페이퍼를 인쇄회로기판의 베이스 수지층상에 접착시킨 다음, 레이저 빔을 캐리어 페이퍼에 조사시킴으로써, 레이저로 조사된 부위에 해당하는 동박의 일부만이 녹으면서 수지층의 표면에 전도성 회로패턴으로 형성될 수 있도록 한 점에 주안점이 있다.According to the present invention, carbon particles of carbon paper are engraved on paper, and a carrier paper having copper foil adhered to one surface is adhered on a base resin layer of a printed circuit board, and then irradiated with a laser by irradiating a laser beam onto the carrier paper. The main point is that only a part of the copper foil corresponding to the part is melted and can be formed as a conductive circuit pattern on the surface of the resin layer.

이를 위해, 일면에 동박(102)이 라미네이팅된 캐리어 페이퍼(100)를 구비한다.To this end, the copper foil 102 is provided with a carrier paper 100 laminated on one surface.

상기 동박(102)은 초미세 두께를 갖는 동박 포일(Ultra-thin Cu foil)이고, 상기 캐리어 페이퍼(100)는 레이저 빔의 투과가 가능한 재질로서, 이 캐리어 페이퍼(100)의 일면에 동박(102) 포일이 라미네이팅된다.The copper foil 102 is an ultra-thin Cu foil having an ultra-fine thickness, and the carrier paper 100 is a material capable of transmitting a laser beam. The copper foil 102 is formed on one surface of the carrier paper 100. ) The foil is laminated.

다음으로, 상기 캐리어 페이퍼(100)를 인쇄회로기판용 베이스 수지층(104)의 표면에 부착하되, 동박(102)의 표면이 수지층(104)의 표면에 부착되도록 한다.Next, the carrier paper 100 is attached to the surface of the base resin layer 104 for a printed circuit board, so that the surface of the copper foil 102 is attached to the surface of the resin layer 104.

즉, 상기 동박(102)의 표면에 접착수단(미도시됨)을 도포하여, 수지층(104)의 표면에 부착되도록 한다.That is, by applying an adhesive means (not shown) to the surface of the copper foil 102, it is to be attached to the surface of the resin layer 104.

이어서, 레이저 빔 조사수단(미도시됨)에서 캐리어 페이퍼(100)의 표면에 레이저 빔(106)을 조사하게 되는데, 이때의 레이저 빔 조사 경로는 인쇄회로기판의 베이스 수지층(104)상에 전도성 회로패턴(108)이 형성되는 회로 경로를 따라 조사된다.Subsequently, the laser beam irradiation means (not shown) irradiates the laser beam 106 to the surface of the carrier paper 100, wherein the laser beam irradiation path is conductive on the base resin layer 104 of the printed circuit board. The circuit pattern 108 is irradiated along the circuit path in which it is formed.

따라서, 상기 캐리어 페이퍼(100)의 표면에 전도성 회로패턴(108)이 형성될 경로를 따라 레이저 빔(106)을 조사함으로써, 레이저 빔(106)이 조사된 동박(102)의 일부가 캐리어 페이퍼(100)로부터 박리되면서 수지층(104)의 표면에 전도성 회로패턴(108)으로 형성된다.Accordingly, by irradiating the laser beam 106 along the path where the conductive circuit pattern 108 is to be formed on the surface of the carrier paper 100, a part of the copper foil 102 to which the laser beam 106 is irradiated is formed of carrier paper ( Peeled from the 100 is formed as a conductive circuit pattern 108 on the surface of the resin layer 104.

보다 상세하게는, 상기 레이저 빔(106)이 캐리어 페이퍼(100)에 조사되면, 레이저 빔(106)이 캐리어 페이퍼(100)를 그대로 투과하여 그 아래쪽의 동박(102)에 조사되고, 레이저 빔(106)의 조사를 받은 동박(102)의 일부가 박리되면서 수지층(104)의 표면에 융착되어 전도성 회로패턴(108)으로 형성되고, 반면 레이저 빔(106)을 조사받지 않은 동박(102)의 나머지 부분은 캐리어 페이퍼(100)에 계속 라미네이팅된 상태를 유지하게 된다.More specifically, when the laser beam 106 is irradiated to the carrier paper 100, the laser beam 106 is transmitted through the carrier paper 100 as it is and irradiated to the copper foil 102 below it, and the laser beam ( A portion of the copper foil 102 that has been irradiated by 106 is peeled off and fused to the surface of the resin layer 104 to form a conductive circuit pattern 108, while the copper foil 102 that has not been irradiated with the laser beam 106 is formed. The remaining portion will remain laminated to the carrier paper 100.

이에, 레이저 빔(106)이 조사되지 않은 동박(102)의 나머지 부분은 캐리어 페이퍼(100)를 떼어낼 때 함께 떼내어져 수지층(104)의 표면으로부터 제거됨으로써, 레이저 빔(106)의 조사를 받아 수지층(104)상에 융착된 동박(102)의 일부만이 전도성 회로패턴(108)으로 남게 된다.Accordingly, the remaining portion of the copper foil 102 to which the laser beam 106 has not been irradiated is removed together when the carrier paper 100 is detached and removed from the surface of the resin layer 104, thereby irradiating the laser beam 106. Only a part of the copper foil 102 fused on the resin layer 104 remains as the conductive circuit pattern 108.

이어서, 상기 전도성 회로패턴(108)간의 절연을 위하여 수지층(104)상에 절연재의 일종인 솔더 레지스트(110)를 코팅함으로써, 단층의 전도성 회로패턴(108)을 갖는 인쇄회로기판이 완성된다.Subsequently, by coating a solder resist 110, which is a kind of insulating material, on the resin layer 104 to insulate the conductive circuit patterns 108, a printed circuit board having a single conductive circuit pattern 108 is completed.

한편, 상기 전도성 회로패턴(108)을 2층 이상으로 형성시키기 위해서, 새로운 캐리어 페이퍼(100) 즉, 동박(102)이 라미네이팅된 캐리어 페이퍼(100)를 다시 솔더 레지스트(110)의 상면에 부착시키게 된다.Meanwhile, in order to form the conductive circuit pattern 108 in two or more layers, the new carrier paper 100, that is, the copper foil 102, is laminated on the upper surface of the solder resist 110. do.

연이어, 새롭게 부착된 캐리어 페이퍼(100)에 레이저 빔(106)을 재차 조사함으로써, 레이저 빔(106)을 조사받은 동박(102)의 일부가 박리되면서 솔더 레지스트(110)의 표면에 융착되어 2층의 전도성 회로패턴(108)으로 형성된다.Subsequently, by irradiating the laser beam 106 on the newly attached carrier paper 100 again, a part of the copper foil 102 irradiated with the laser beam 106 is peeled off and fused to the surface of the solder resist 110 to form two layers. Is formed of a conductive circuit pattern 108.

이때, 상기 솔더 레지스트(110)를 통해 단층의 전도성 회로패턴(108)의 일부가 노출된 상태이므로, 이 노출된 단층의 전도성 회로패턴(108)에 2층의 전도성 회로패턴(108)이 도전 가능하게 접촉되는 상태가 된다.In this case, since a part of the conductive circuit pattern 108 of the single layer is exposed through the solder resist 110, the conductive circuit pattern 108 of the two layers may be conductive to the exposed conductive circuit pattern 108 of the single layer. Is in contact with each other.

이렇게, 동박(102)이 일면에 라미네이팅된 새로운 캐리어 페이퍼(100)를 계속 적층 부착하여 상기한 레이저 빔 조사 공정을 반복함으로써, 솔더 레지스트(110)를 사이에 두고 2층 이상의 전도성 회로패턴(108)을 용이하게 형성시킬 수 있다.In this way, the copper foil 102 is repeatedly laminated with new carrier paper 100 laminated on one surface, and the laser beam irradiation process is repeated, thereby conducting the conductive circuit pattern 108 of two or more layers with the solder resist 110 interposed therebetween. Can be easily formed.

이와 같이, 본 발명에 따르면, 레이저 빔을 동박이 입혀진 캐리어 페이퍼에 조사하여 반도체 패키지 제조용 인쇄회로기판의 전도성 회로패턴을 형성함에 따라, 기존의 공정에 비하여 회로선 폭을 미세화 할 수 있을 뿐 아니라 작업 공정을 단순화시킬 수 있어고, 제조 비용 또한 절감할 수 있다.
As described above, according to the present invention, as a conductive circuit pattern of a printed circuit board for manufacturing a semiconductor package is formed by irradiating a laser beam on a carrier sheet coated with copper foil, it is possible not only to reduce the width of the circuit line as compared with the existing process and to work. The process can be simplified and manufacturing costs can be reduced.

100 : 캐리어 페이퍼
102 : 동박
104 : 수지층
106 : 레이저 빔
108 : 전도성 회로패턴
110 : 솔더 레지스트100: carrier paper
102: copper foil
104: resin layer
106: laser beam
108: conductive circuit pattern
110: solder resist

Claims (3)

일면에 동박(102)이 라미네이팅된 캐리어 페이퍼(100)를 구비하는 단계와;
상기 캐리어 페이퍼(100)를 인쇄회로기판용 베이스 수지층(104)의 표면에 부착하되, 동박(102)의 표면이 수지층(104)의 표면에 부착되게 하는 단계와;
상기 캐리어 페이퍼(100)의 표면에 전도성 회로패턴이 형성될 경로를 따라 레이저 빔(106)을 조사하는 단계와;
레이저 빔(106)이 조사된 동박(102)의 일부가 캐리어 페이퍼(100)로부터 박리되면서 수지층(104)의 표면에 전도성 회로패턴(108)들로 형성되는 단계;
를 포함하는 것을 특징으로 하는 반도체 패키지 제조용 인쇄회로기판 제조 방법.
Comprising the step of having a copper foil (102) carrier paper (100) laminated on one surface;
Attaching the carrier paper (100) to the surface of the base resin layer (104) for a printed circuit board, wherein the surface of the copper foil (102) is attached to the surface of the resin layer (104);
Irradiating a laser beam (106) along a path in which a conductive circuit pattern will be formed on a surface of the carrier paper (100);
A portion of the copper foil 102 irradiated with the laser beam 106 is peeled from the carrier paper 100 and formed of conductive circuit patterns 108 on the surface of the resin layer 104;
Printed circuit board manufacturing method for manufacturing a semiconductor package comprising a.
청구항 1에 있어서,
레이저 빔(106)이 조사되지 않은 부분의 동박은 캐리어 페이퍼(100)와 함께 떼내어져 제거되는 단계와;
상기 전도성 회로패턴(108)간의 절연을 위하여 수지층(104)상에 솔더 레지스트(110)를 코팅하는 단계;
가 더 진행되는 것을 특징으로 하는 반도체 패키지 제조용 인쇄회로기판 제조 방법.
The method according to claim 1,
Copper foil of the portion to which the laser beam 106 is not irradiated is removed together with the carrier paper 100;
Coating a solder resist (110) on the resin layer (104) for insulation between the conductive circuit patterns (108);
Printed circuit board manufacturing method for manufacturing a semiconductor package, characterized in that further proceeds.
청구항 2에 있어서,
상기 솔더 레지스트(110)의 상면에 동박(102)이 라미네이팅된 캐리어 페이퍼(100)를 다시 부착시킨 후, 이 캐리어 페이퍼(100)에 레이저 빔(106)을 조사하는 단계를 반복하여, 솔더 레지스트(110)를 사이에 두고 2층 이상의 전도성 회로패턴(108)이 형성되도록 한 것을 특징으로 하는 반도체 패키지 제조용 인쇄회로기판 제조 방법.The method according to claim 2,
After re-attaching the carrier paper 100 having the copper foil 102 laminated on the upper surface of the solder resist 110, the step of irradiating the laser beam 106 to the carrier paper 100 is repeated, and the solder resist ( Printed circuit board manufacturing method for manufacturing a semiconductor package, characterized in that two or more conductive circuit patterns (108) formed to be formed between the 110.
KR1020100029663A 2010-04-01 2010-04-01 Method for patterning with copper foil on pcb KR101046255B1 (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114080115A (en) * 2020-08-21 2022-02-22 丰田自动车株式会社 Method for manufacturing wiring substrate
US11700686B2 (en) 2020-07-06 2023-07-11 Toyota Jidosha Kabushiki Kaisha Method for manufacturing wiring board
EP3284325B1 (en) * 2015-04-13 2023-10-04 Jan Franck Device and method for producing printed circuit boards for electrical and/or electronic circuits

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20090022737A (en) * 2007-08-31 2009-03-04 삼성전기주식회사 Fabricating method of multi layer printed circuit board

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20090022737A (en) * 2007-08-31 2009-03-04 삼성전기주식회사 Fabricating method of multi layer printed circuit board

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP3284325B1 (en) * 2015-04-13 2023-10-04 Jan Franck Device and method for producing printed circuit boards for electrical and/or electronic circuits
US11700686B2 (en) 2020-07-06 2023-07-11 Toyota Jidosha Kabushiki Kaisha Method for manufacturing wiring board
CN114080115A (en) * 2020-08-21 2022-02-22 丰田自动车株式会社 Method for manufacturing wiring substrate
US11903141B2 (en) 2020-08-21 2024-02-13 Toyota Jidosha Kabushiki Kaisha Method for manufacturing wiring board
JP7456330B2 (en) 2020-08-21 2024-03-27 トヨタ自動車株式会社 Manufacturing method of wiring board

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