TWI531291B - Package board and method for manufactuing same - Google Patents

Description

Carrying plate and manufacturing method thereof

The present invention relates to the field of circuit board manufacturing technology, and in particular, to a carrier board and a manufacturing method thereof.

A printed circuit board using a flip chip ball grid array (FCBGA) typically requires a plurality of conductive bump structures arranged in an array for carrying solder balls. The conductive bumps need to penetrate the solder resist layer and are electrically connected to the corresponding conductive lines. In the prior art, a corresponding solder resist opening is formed on the conductive line, and then a plating barrier layer is formed on the solder resist layer, and a plating barrier corresponding to the solder resist opening is formed in the plating barrier layer. Since both the solder resist opening and the plating barrier opening need to be formed by development and need to communicate with each other, a corresponding plating barrier opening is required to be aligned with the solder resist opening during the fabrication process. Thereafter, conductive bumps are formed by electroless plating and then electroplating in the openings of the solder resist layer. Finally, the plating barrier is removed to obtain conductive bumps protruding from the solder resist layer. In the above manufacturing method, it is necessary to make the solder resist layer opening relatively large in order to perform alignment when developing the plating barrier opening. Moreover, since the formed conductive bumps and the solder resist layer are in contact with each other and the contact area is small, the conductive bumps are easily separated from each other in the solder resist layer, and the obtained circuit board has poor reliability. Moreover, such a manufacturing method determines that the distributed density of the conductive bump structures is small, which is disadvantageous for the dense distribution of the plurality of conductive bump structures.

In view of the above, it is necessary to provide a carrier board with a densely distributed conductive bump structure.

A manufacturing method of a carrier board, comprising the steps of: providing a first copper foil, a first release film, a film, a second release film and a second copper foil, wherein the film has a central area, and the first release film and The shape and size of the second release film correspond to the shape and size of the central region; and sequentially pressing the first copper foil, the first release film, the film, the second release film and the second copper foil into one whole The two sides of the central portion of the film are in contact with the first release film and the second release film to obtain a multi-layer substrate, and the multi-layer substrate includes a product area and a waste area surrounding the product area, and the product area is in the An orthographic projection of a copper foil surface is located within the orthographic projection of the central region on the surface of the first copper foil; forming a first photoresist layer and a first dielectric layer on the surface of the first copper foil, forming a surface of the second copper foil a second photoresist layer and a third dielectric layer; a first opening is formed in the first dielectric layer and the first photoresist layer, and a second opening is formed in the third dielectric layer and the second photoresist layer a hole; a first conductive bump is formed in the first opening, and a second conductive is formed in the second opening a first extension portion is formed in the first opening and a first conductive circuit layer is formed on the surface of the first dielectric layer, a second extension portion is formed in the second opening, and a third surface is formed on the surface of the third dielectric layer a conductive circuit layer, the first conductive circuit layer is electrically connected to the first conductive bump through the first extension portion, and the third conductive circuit layer is electrically connected to the second conductive bump through the second extension portion; The boundary line of the area is cut, and the first copper foil in the product area is naturally separated from the first release film, and the second copper foil in the product area is naturally separated from the second release film, thereby obtaining the first separated from each other. a carrier substrate and a second carrier substrate; and removing the first copper foil and the first photoresist layer from the first carrier substrate to obtain a first carrier plate, and removing the second copper foil and the second photoresist layer from the second carrier substrate , the second carrier board is obtained.

A carrier board is manufactured by the method for manufacturing the carrier board, comprising: a first dielectric layer, a plurality of conductive bumps, and a first conductive circuit layer, wherein the first dielectric layer has a relative a surface and a second surface, one end of the conductive bump protrudes from the first surface, and the first conductive circuit layer is formed on a side of the second surface of the first dielectric layer, the first The conductive circuit layer includes an extension extending into the first dielectric layer, and the metal bumps are electrically connected to the first conductive wiring layer through the extension.

The manufacturing method of the carrier board provided by the technical solution is formed by one laser ablation when forming a blind hole for forming a metal bump. In this way, it is possible to avoid the formation of an opening in the solder resist layer by using two developments in the prior art, and then forming an opening in the plating barrier layer. The opening in the plating barrier layer needs to be aligned with the opening in the solder resist layer, and needs to be set. The openings in the larger solder mask are not conducive to the formation of densely arranged conductive bumps.

10a‧‧‧First carrier board

10b‧‧‧Second carrier board

11‧‧‧First copper foil

12‧‧‧Second copper foil

13‧‧‧First release film

14‧‧‧Separate release film

15‧‧‧ Film

31‧‧‧First photoresist layer

32‧‧‧Second photoresist layer

41‧‧‧First dielectric layer

42‧‧‧ Third dielectric layer

311‧‧‧ first opening

321‧‧‧Second opening

312‧‧‧First conductive bump

322‧‧‧Second conductive bump

51‧‧‧First conductive circuit layer

511‧‧‧First electroless copper plating

512‧‧‧First plating blocking graphic

513‧‧‧First electroplated copper layer

515‧‧‧First Extension

52‧‧‧ Third conductive circuit layer

521‧‧‧Second electroless copper plating

522‧‧‧Second plating blocking graphic

523‧‧‧Second electroplated copper layer

525‧‧‧Second extension

61‧‧‧Second dielectric layer

611‧‧‧First blind hole

612‧‧‧First conductive blind hole

62‧‧‧fourth dielectric layer

621‧‧‧second blind hole

622‧‧‧Second conductive blind hole

71‧‧‧Second conductive circuit layer

72‧‧‧fourth conductive layer

81‧‧‧First solder mask

811‧‧‧ first opening

82‧‧‧Second solder mask

821‧‧‧ second opening

91‧‧‧First protective layer

92‧‧‧Second protective layer

100a‧‧‧First carrier substrate

100b‧‧‧second carrier substrate

411‧‧‧ first surface

412‧‧‧ second surface

103‧‧‧Product area

104‧‧‧ scrap area

105‧‧‧ incision

110‧‧‧Multilayer substrate

151‧‧‧Central District

152‧‧‧Edge area

90‧‧‧Surface treatment layer

1 is a schematic cross-sectional view of a first copper foil, a first release film, a film, a second release film, and a second copper foil according to an embodiment of the present application.

2 is a schematic cross-sectional view showing a multilayer substrate obtained by pressing a first copper foil, a first release film, a film, a second release film, and a second copper foil according to an embodiment of the present invention.

3 is a schematic cross-sectional view showing the first photoresist layer on the surface of the first copper foil of FIG. 2 and the second photoresist layer formed on the surface of the second copper foil.

4 is a schematic cross-sectional view showing the first photoresist layer on the surface of the first photoresist layer of FIG. 3 and the third dielectric layer on the surface of the second photoresist layer.

FIG. 5 is a first aperture, a second photoresist formed in the first photoresist layer and the first dielectric layer of FIG. A schematic cross-sectional view of the layer and the third dielectric layer after forming the second opening.

6 is a schematic cross-sectional view showing the first conductive bump formed in the first opening of FIG. 5 and the second conductive bump formed in the second opening.

7 to FIG. 10 are schematic cross-sectional views showing the surface of the first dielectric layer of FIG. 6 forming a first conductive wiring layer, and the surface of the third dielectric layer is formed with a third conductive wiring layer.

FIG. 11 is a cross-sectional view showing a second dielectric layer and a second conductive wiring layer formed on one side of the first conductive wiring layer of FIG. 10, and a fourth dielectric layer and a third conductive wiring layer are formed on one side of the second conductive wiring layer.

12 is a cross-sectional view showing the first solder resist layer and the first protective layer on the side of the second conductive wiring layer of FIG. 11, and the second solder resist layer and the second protective layer are formed on the side of the fourth conductive wiring layer.

13 and FIG. 14 are schematic cross-sectional views showing the first carrier substrate and the second carrier substrate obtained by cutting.

15 is a first carrier substrate of FIG. 14 with the first copper foil removed, the first photoresist layer and the first protective layer to obtain a first carrier, and the second carrier substrate to remove the second copper foil, the second photoresist layer, and the second substrate The second protective layer obtains a schematic cross-sectional view of the second carrier.

FIG. 16 is a cross-sectional view showing the surface of the conductive bumps of the first carrier board and the second carrier board of FIG. 15 after forming a protective layer.

The manufacturing method of the carrier board provided by the technical solution includes the following steps:

In the first step, referring to FIG. 1, a first copper foil 11, a second copper foil 12, a first release film 13, a second release film 14, and a film 15 are provided.

The first copper foil 11 and the second copper foil 12 are each a copper foil having a thickness of 5 μm to 20 μm. Preferably, the thickness of the first copper foil 11 and the second copper foil 12 are both 10 micrometers to 15 micrometers. The first release film 13 and the second release film 14 may be a PE release film or a PET release film or the like. Film 15 is a FR4 epoxy glass cloth semi-cured film. The first release film 13 and the second release film 14 may also be metal sheets.

The shapes and sizes of the first copper foil 11, the second copper foil 12, and the film 15 are the same. The shapes of the first release film 13 and the second release film 14 are the same as those of the first copper foil 11, and the sizes of the first release film 13 and the second release film 14 are smaller than the size of the first copper foil 11. Specifically, the cross-sectional areas of the first release film 13 and the second release film 14 are smaller than the cross-sectional area of the first copper foil 11. Film 15 includes a central region 151 and an edge region 152 that surrounds central region 151. The shape of the central portion 151 is the same as that of the first release film 13 and the second release film 14, and is equal in size.

Film 15 is a FR4 epoxy glass cloth semi-cured film.

In the second step, referring to FIG. 2, the first copper foil 11, the first release film 13, the film 15, the second release film 14, and the second copper foil 12 are laminated and laminated one at a time to obtain a multilayer substrate. 110.

When the first copper foil 11, the first release film 13, the film 15, the second release film 14, and the second copper foil 12 are stacked, the first copper foil 11, the first release film 13, the film 15, The centers of the second release film 14 and the second copper foil 12 are aligned with each other. Since the sizes of the first release film 13 and the second release film 14 are smaller than those of the first copper foil 11, the second copper foil 12, and the film 15, the first release film 13 and the second release film 14 are respectively associated with the film 15. The central area 151 corresponds. When the pressing is performed, both sides of the edge region 152 of the film 15 are bonded to the first copper foil 11 and the second copper foil 12, respectively, and the two sides of the central portion 151 of the film 15 are respectively associated with the first release film 13 and the first The two release films 14 are in contact with each other, and the central portion 151 of the film 15 is not in contact with the first The copper foil 11 and the second copper foil 12 are in contact with each other.

The multilayer substrate 110 has a product area 103 and a waste area 104 surrounding the product area 103. The cross-sectional area of the product region 103 is smaller than the cross-sectional area of the first release film 13. The orthographic projection of the product region 103 on the surface of the first copper foil 11 is located within the orthographic projection of the first release film 13 on the surface of the first copper foil 11.

It can be understood that when used to simultaneously fabricate a plurality of package substrates, the product region 103 may include a plurality of product units separated from each other, each product unit corresponding to a corresponding one of the package substrates.

In the third step, referring to FIG. 3, a first photoresist layer 31 is formed on the surface of the first copper foil 11, and a second photoresist layer 32 is formed on the surface of the second copper foil 12.

The first photoresist layer 31 and the second photoresist layer 32 may be formed by laminating a dry film and then exposing and developing.

In this embodiment, the first photoresist layer 31 and the second photoresist layer 32 may be replaced by other peelable layers.

In the fourth step, referring to FIG. 4, the first dielectric layer 41 is pressed on the surface of the first photoresist layer 31, and the third dielectric layer 42 is pressed on the surface of the second photoresist layer 32.

The first dielectric layer 41 and the third dielectric layer 42 may be formed by simultaneously pressing a prepreg film.

In the fifth step, referring to FIG. 5, a plurality of first openings 311 are formed in the first photoresist layer 31 and the first dielectric layer 41 in the second photoresist layer 32 and the third dielectric layer 42. A plurality of second openings 321 are formed.

In this step, the first opening 311 and the second opening may be formed by laser ablation. Hole 321. A portion of the first copper foil 11 is exposed from the bottom of the first opening 311, and a portion of the second copper foil 12 is exposed from the bottom of the second opening 321 .

In the sixth step, referring to FIG. 6 , a first conductive bump 312 is formed in the first opening 311 , and a second conductive bump 322 is formed in the second opening 321 .

In this step, the first conductive bumps 312 and the second conductive bumps 322 may be formed by electroplating. The material of the first conductive bump 312 and the second conductive bump 322 may be copper, aluminum or silver, etc., preferably copper. The thickness of the first conductive bump 312 is smaller than the sum of the thicknesses of the first photoresist layer 31 and the first dielectric layer 41, and is greater than the thickness of the first photoresist layer 31. The height of the second conductive bumps 322 is smaller than the sum of the thicknesses of the second photoresist layer 32 and the third dielectric layer 42 and greater than the thickness of the second photoresist layer 32.

In the seventh step, referring to FIG. 7 to FIG. 10, a first conductive circuit layer 51 is formed on the surface of the first dielectric layer 41 and the surface of the first conductive bump 312, and the surface of the third dielectric layer 42 and the second conductive bump A third conductive wiring layer 52 is formed on the surface of 322.

The first step is to form a first electroless copper plating layer 511 on the surface of the first dielectric layer 41 and the surface of the first conductive bump 312, and the surface of the third dielectric layer 42 and the second conductive bump 322. A second electroless copper plating layer 521 is formed on the surface.

Then, a first plating barrier pattern 512 is formed on the surface of the first electroless copper plating layer 511, and a second plating blocking pattern 522 is formed on the surface of the second electroless copper plating layer 521. The first plating blocking pattern 512 and the second plating blocking pattern 522 may be formed by pressing a dry film, then exposing and developing, to remove a portion corresponding to the pre-formed conductive wiring layer.

Next, a first electroplated copper layer 513 is formed on the surface of the first electroless copper plating layer 511 exposed from the first plating blocking pattern 512 by electroplating, in the second plating blocking diagram. A second electroplated copper layer 523 is formed on the surface of the second electroless copper plating layer 521 exposed by the shape 522.

Finally, the first plating blocking pattern 512 and the second plating blocking pattern 522 are removed, and the first electroless copper plating layer 511 originally covered by the first plating blocking pattern 512 is removed by etching, and the first layer covered by the second plating blocking pattern 522 is removed. Two electroless copper plating layer 521.

Thus, the first conductive wiring layer 51 is composed of a first electroless copper plating layer 511 and a first electroplated copper layer 513, and the third conductive wiring layer 52 is composed of a second electroless copper plating layer 521 and a second electroplated copper layer 523. The first conductive wiring layer 51 and the plurality of first conductive bumps 312 are electrically connected to each other. The third conductive circuit layer 52 and the plurality of second conductive bumps 322 are electrically connected to each other. In this embodiment, the first conductive circuit layer 51 includes a first extension 515 extending into the first opening 311. The first conductive bumps 312 are electrically connected to the first extensions 515 of the first conductive wiring layer 51. The third conductive circuit layer 52 includes a second extension 525 that extends into the second opening 321 . The second conductive bumps 322 and the second extensions 525 of the third conductive circuit layer 52 are electrically connected to each other.

In the eighth step, referring to FIG. 11, the second dielectric layer 61 is pressed on the side of the first conductive wiring layer 51, and the second conductive wiring layer 71 is formed. The fourth dielectric layer 62 is laminated on the third conductive wiring layer 52 side, and a fourth conductive wiring layer 72 is formed.

This step can be specifically produced by first pressing the second dielectric layer 61 on the side of the first conductive wiring layer 51 and pressing the fourth dielectric layer 62 on the third conductive wiring layer 52 side.

Then, a first blind via 611 is formed in the second dielectric layer 61 by laser ablation, and a second blind via 621 is formed in the fourth dielectric layer 62.

Finally, the second conductive wiring layer 71 and the fourth conductive wiring layer 72 are formed in the same manner as the above-described formation of the first conductive wiring layer 51 and the third conductive wiring layer 52, and the first The blind via 611 is formed to form a first conductive via 612, and the second blind via 621 is formed to form a second conductive via 622. The first conductive circuit layer 51 and the second conductive circuit layer 71 are electrically connected to each other through the first conductive via 612, and the third conductive circuit layer 52 and the fourth conductive circuit layer 72 are electrically connected to each other through the second conductive via 622.

In the tenth step, referring to FIG. 12, a first solder resist layer 81 is formed on the side of the second conductive circuit layer 71. The first solder resist layer 81 has a plurality of first openings 811 therein, and a portion of the second conductive trace layer 71 is from the first An opening 811 is exposed. A second solder resist layer 82 is formed on one side of the fourth conductive wiring layer 72, and the second solder resist layer 82 has a plurality of second openings 821 from which a portion of the fourth conductive wiring layer 72 is exposed.

After this step, a first protective layer 91 is formed on the surface of the first solder resist layer 81, and a second protective layer 92 is formed on the surface of the second solder resist layer 82.

In the eleventh step, please refer to FIG. 13 and FIG. 14 together, and cut along the boundary line between the product area 103 and the scrap area 104 to form an annular slit 105, thereby obtaining the first carrier substrate 100a and the second carrier substrate separated from each other. 100b.

In the product area 103, the first release film 13 and the second release film 14 are in contact with the film 15, and the first copper foil 11 and the second copper foil 12 are not bonded to the film 15, when along the product area 103. When cutting with the boundary line of the scrap area 104, the first copper foil 11 is separated from the first release film 13, and the second release film 14 and the second copper foil 12 are separated from each other, thereby obtaining two first carriers separated from each other. The substrate 100a and the second carrier substrate 100b.

In the ninth step, referring to FIG. 14 and FIG. 15, the first copper foil 11 of the first carrier substrate 100a is removed, so that the first conductive bump 312 is exposed, and the first photoresist layer 31 and the first protective layer 91 are removed. The first carrier plate 10a. Removing the second copper foil 12 of the second carrier substrate 100b, so that the second conductive bumps 322 are exposed, and removing the second photoresist layer 32 and the second The protective layer 92 obtains the second carrier 10b.

In this step, the first copper foil 11 and the second copper foil 12 are removed by etching.

Referring to FIG. 16 , the manufacturing method of the carrier board may further include forming a surface treatment layer 90 on the exposed surface of the first conductive bump 312 and the second conductive bump 322, and exposing the surface from the first opening 811. The surface of the second conductive wiring layer 71 and the surface of the fourth conductive wiring layer 72 exposed from the second opening 821 also form a surface treatment layer 90, which may be an organic solder resist layer (OSP).

The technical solution further provides a carrier board 10a including a first conductive bump 312, a first dielectric layer 41, a first conductive wiring layer 51, a second dielectric layer 61, and a second conductive wiring layer 71.

The first dielectric layer 41 has opposing first and second surfaces 411, 412. One end of the first conductive bump 312 protrudes from the first surface 411, and the first conductive circuit layer 51 is formed on a side of the second surface 412 of the first dielectric layer 41, the first The other end of the conductive bump 312 is embedded in the first dielectric layer 41 and electrically connected to the first conductive wiring layer 51. The second dielectric layer 61 is pressed on the side of the first conductive circuit layer 51, and the second conductive circuit layer 71 is formed on the side of the second dielectric layer 61 away from the first conductive circuit layer 51. A first conductive via 612 is formed in the second dielectric layer 61. The first conductive trace layer 51 and the second conductive trace layer 71 are electrically connected to each other through the first conductive via 612. The first conductive wiring layer 51 includes a first extension 515 that extends into the first opening 311. The first conductive bumps 312 are electrically connected to the first extensions 515 of the first conductive wiring layer 51.

A first solder resist layer 81 is further formed on one side of the second conductive wiring layer 71, and an opening is formed in the solder resist layer, and a part of the second conductive wiring layer 71 is exposed from the opening.

The first conductive bump 312 protrudes from the surface of the first surface 411, and the surface of the second conductive wiring layer 71 exposed from the opening of the solder resist layer is formed with the surface treatment layer 90.

In the manufacturing process of the carrier board provided by the technical solution, the release films 13 and 14 having a cross-sectional area smaller than that of the first copper foil 11 and the second copper foil 12 are disposed on both sides of the film 15, so that conductive is formed in the fabrication. After the line, the film can be easily separated from the first carrier substrate and the second carrier substrate. Therefore, the manufacturing method of the carrier board provided by the technical solution can avoid the use of a special copper foil structure which is relatively expensive, thereby reducing the manufacturing cost of the carrier board.

The manufacturing method of the carrier board provided by the technical solution is formed by one laser ablation when forming a blind hole for forming the conductive bump. In this way, it is possible to avoid the formation of an opening in the solder resist layer by using two developments in the prior art, and then forming an opening in the plating barrier layer. The opening in the plating barrier layer needs to be aligned with the opening in the solder resist layer, and needs to be set. The openings in the larger solder mask are not conducive to the formation of densely arranged conductive bumps.

In summary, the present invention complies with the requirements of the invention patent and submits a patent application according to law. However, the above description is only the preferred embodiment of the present invention, and equivalent modifications or variations made by those skilled in the art will be covered by the following claims.

10a‧‧‧First carrier board

10b‧‧‧Second carrier board

41‧‧‧First dielectric layer

42‧‧‧ Third dielectric layer

312‧‧‧First conductive bump

322‧‧‧Second conductive bump

51‧‧‧First conductive circuit layer

515‧‧‧First Extension

52‧‧‧ Third conductive circuit layer

525‧‧‧Second extension

61‧‧‧Second dielectric layer

71‧‧‧Second conductive circuit layer

72‧‧‧fourth conductive layer

81‧‧‧First solder mask

811‧‧‧ first opening

82‧‧‧Second solder mask

90‧‧‧Surface treatment layer

Claims (13)

A manufacturing method of a carrier board, comprising the steps of: providing a first copper foil, a first release film, a film, a second release film and a second copper foil, wherein the film has a central area, and the first release film and The shape and size of the second release film correspond to the shape and size of the central region; and sequentially pressing the first copper foil, the first release film, the film, the second release film and the second copper foil into one whole The two sides of the central portion of the film are in contact with the first release film and the second release film to obtain a multi-layer substrate, and the multi-layer substrate includes a product area and a waste area surrounding the product area, and the product area is in the An orthographic projection of a copper foil surface is located within the orthographic projection of the central region on the surface of the first copper foil; forming a first photoresist layer and a first dielectric layer on the surface of the first copper foil, forming a surface of the second copper foil a second photoresist layer and a third dielectric layer; a first opening is formed in the first dielectric layer and the first photoresist layer, and a second opening is formed in the third dielectric layer and the second photoresist layer a hole; a first conductive bump is formed in the first opening, and a second conductive is formed in the second opening a first extension portion is formed in the first opening and a first conductive circuit layer is formed on the surface of the first dielectric layer, a second extension portion is formed in the second opening, and a third surface is formed on the surface of the third dielectric layer a conductive circuit layer, the first conductive circuit layer is electrically connected to the first conductive bump through the first extension portion, and the third conductive circuit layer is electrically connected to the second conductive bump through the second extension portion; The boundary line of the area is cut, and the first copper foil in the product area is naturally separated from the first release film, and the second copper foil in the product area is naturally separated from the second release film, thereby obtaining the first separated from each other. a carrier substrate and a second carrier substrate; The first copper foil and the first photoresist layer are removed from the first carrier substrate to obtain a first carrier, and the second copper foil and the second photoresist layer are removed from the second carrier substrate to obtain a second carrier. The method of fabricating a carrier board according to claim 1, wherein after forming the first conductive wiring layer and the third conductive wiring layer, before performing cutting, further comprising forming a second dielectric on a side of the first conductive wiring layer And forming a second conductive circuit layer on the surface of the second dielectric layer, forming a fourth dielectric layer on one side of the third conductive circuit layer, and forming a fourth conductive circuit layer on the surface of the fourth dielectric layer. The method for fabricating a carrier board according to claim 2, further comprising forming a first conductive blind via in the second dielectric layer, the first conductive trace layer and the second conductive trace layer passing through the first conductive via hole The second conductive via hole is formed in the fourth dielectric layer, and the third conductive circuit layer and the fourth conductive circuit layer are electrically connected to each other through the second conductive blind via. The method of fabricating a carrier board according to claim 2, wherein the first copper foil is removed from the first carrier substrate by etching, and the second copper foil is removed from the second carrier substrate by etching. The method of manufacturing the carrier board according to claim 4, further comprising: forming a first protective layer on one side of the second conductive circuit layer and a second protective layer on a side of the fourth conductive circuit layer before performing the cutting, The second conductive wiring layer and the fourth conductive wiring layer are protected when the first copper foil and the second copper foil are etched. The method of manufacturing the carrier board according to claim 2, further comprising forming a first solder resist layer on the surface of the second conductive circuit layer, the first solder resist layer having a plurality of first openings, and a portion of the second conductive lines a layer is exposed from the first opening, a second solder resist layer is formed on a surface of the fourth conductive circuit layer, the second solder resist layer has a plurality of second openings, and a portion of the fourth conductive circuit layer is exposed from the second opening . The method of fabricating a carrier board according to claim 1, further comprising forming a first protective layer on a surface of the first conductive bump and forming a second protective layer on a surface of the second conductive bump. The method for fabricating a carrier board according to claim 1, wherein the first opening is formed in the first dielectric layer and the first photoresist layer by laser ablation, and the laser is ablated. A second opening is formed in the third dielectric layer and the second photoresist layer, and the first conductive bump and the second conductive bump are formed by electroplating. The method of fabricating a carrier board according to claim 1, wherein the thickness of the first conductive bump is smaller than a sum of thicknesses of the first photoresist layer and the first dielectric layer, and is greater than a thickness of the first photoresist layer The thickness of the second conductive bump is smaller than the sum of the thicknesses of the second photoresist layer and the third dielectric layer, and is greater than the thickness of the second photoresist layer. A carrier board, which is manufactured by the method for manufacturing a carrier board according to any one of claims 1 to 9, comprising a first dielectric layer, a plurality of conductive bumps, and a first conductive circuit layer, a dielectric layer has opposite first and second surfaces, one end of the conductive bump protrudes from the first surface, and each of the conductive bumps protrudes from the first surface at a uniform height The first conductive circuit layer is formed on a side of the second surface of the first dielectric layer, and the first conductive circuit layer includes an extension extending into the first dielectric layer, and the conductive bump passes The extension portion and the first conductive circuit layer are electrically connected to each other. The carrier board of claim 10, further comprising a second dielectric layer and a second conductive circuit layer, wherein the second dielectric layer is laminated on one side of the first conductive circuit layer, and the second conductive line The layer is formed on a side of the second dielectric layer away from the first conductive circuit layer, wherein the second dielectric layer is formed with a conductive blind hole, and the first conductive circuit layer and the second conductive circuit layer pass through the conductive blind hole Electrical connection. The carrier board according to claim 11, wherein a solder resist layer is formed on one side of the second conductive wiring layer, and an opening is formed in the solder resist layer, and a part of the second conductive wiring layer is exposed from the opening. The carrier board of claim 10, wherein the surface of the conductive bump is formed with a protective layer.