JP2016096196A - Electronic component built-in printed wiring board - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an electronic component built-in printed wiring board capable of enhancing connection reliability while reducing the manufacturing cost.SOLUTION: An electronic component built-in printed wiring board 1 includes a core laminate 20 having a first principal surface 20a and a second principal surface 20b on the opposite side, a wiring structure 10 arranged in the core laminate 20, a first build-up layer 30 provided on the first principal surface 20a so as to sandwich the core laminate 20, and a second build-up layer 40 provided on the second principal surface 20b. The core laminate 20 has a conductor layer 201 arranged on the first principal surface 20a, and a plurality of via conductors 210 for electrical connection with the conductor layer 201. The conductor layer 201 is embedded in the core laminate 20, and the upper surface thereof is flush with the first principal surface 20a and the upper surface of the connection pad 104 of the wiring structure 10. The via conductor 210 for connection with one conductor layer 201, and the via conductor 303 for connection with the other conductor layer expand the diameter in different directions.SELECTED DRAWING: Figure 1

Description

  The present invention relates to an electronic component built-in printed wiring board having no core substrate.

  Conventionally, as a technique in such a field, for example, there are those described in the following patent documents. In Patent Document 1, a printed wiring board including an electronic component built in an insulating layer, a conductor layer formed on the insulating layer, and an external terminal buried in the insulating layer and electrically connected to the outside Is disclosed. Patent Document 2 includes a plurality of conductor layers formed on an insulating layer, an electronic component disposed between the conductor layers, and a via conductor that electrically connects the conductor layer and the electronic component. A printed wiring board is disclosed.

JP 2012-238805 A JP 2012-191204 A

  Since none of the above-mentioned printed wiring boards has a core substrate, they are produced by a coreless construction method. That is, a method of using a support plate, sequentially laminating an insulating layer and a conductor layer on one side of the support plate, and then removing the support plate. For this reason, since the number of manufacturing steps is increased as compared with a printed wiring board having a core substrate that is manufactured by simultaneously laminating an insulating layer and a conductor layer on both sides of the core substrate, there is a problem that the manufacturing cost is increased. Further, in the above-described printed wiring board, the insulating layer and the conductor layer are laminated only in one direction, and thus thermal stress is likely to occur due to the difference in the thermal expansion coefficient of the material. As a result, the printed wiring board is likely to warp due to thermal stress, which may affect the connection reliability of the printed wiring board.

  The present invention has been made in view of the above points, and an object of the present invention is to provide a printed wiring board with a built-in electronic component capable of reducing the manufacturing cost and improving the connection reliability.

  An electronic component built-in printed wiring board of the present invention that solves the above-described problems is provided with a first main surface and a second main surface opposite to the first main surface, and the first conductor provided on the first main surface side. A core laminate including a layer, a second conductor layer provided on the second main surface side, and a plurality of first via conductors that electrically connect the first conductor layer and the second conductor layer; An electronic component provided inside the core laminate and having a plurality of connection terminals; provided on the first main surface and the first conductor layer of the core laminate; a first insulating layer; and the first insulation A first conductor layer formed on the first insulating layer; and a plurality of second via conductors that are formed inside the first insulating layer and electrically connect the first conductor layer and the third conductor layer. Provided on the buildup layer, the second main surface of the core laminate, and the second conductor layer A plurality of second insulating layers; a fourth conductor layer formed on the second insulating layer; and a plurality of conductors formed inside the second insulating layer and electrically connecting the second conductor layer and the fourth conductor layer. And a second buildup layer having a third via conductor, wherein the first conductor layer is embedded in the core laminate, and an upper surface of the printed circuit board is embedded in the core laminate. The first main surface and the upper surface of the connection terminal of the electronic component are located in the same plane, and the first via conductor connected to one of the first conductor layers and the other of the first conductor layers are connected. The diameter is expanded in a direction different from that of the second via conductor.

  According to the present invention, since the first via conductor connected to one of the first conductor layers of the core laminate and the second via conductor connected to the other of the first conductor layers are expanded in different directions, the coreless After producing the core laminate by the construction method, it is possible to produce a printed wiring board with built-in electronic components by simultaneously forming the first buildup layer and the second buildup layer on both sides of the core laminate as a core substrate. become. If it does in this way, compared with the case where only a coreless construction method is used, the number of manufacturing processes can be reduced and manufacturing cost can be reduced.

  Also, since the first and second buildup layers can be formed symmetrically on both sides of the core laminate, the thermal stress caused by the difference in thermal expansion coefficient between the first and second buildup layers can be alleviated. And the occurrence of warpage due to thermal stress can be prevented. As a result, the connection reliability of the electronic component built-in printed wiring board can be improved. Furthermore, since the upper surface of the first conductor layer is located on the same plane as the first main surface of the core laminate and the upper surface of the connection terminal of the electronic component, the first main surface of the core laminate becomes flat, Fine wiring can be easily formed on one main surface.

It is a fragmentary sectional view which shows the electronic component built-in printed wiring board which concerns on 1st Embodiment. It is an expanded sectional view which shows the wiring structure of FIG. It is process drawing explaining preparation of a wiring structure. It is process drawing explaining preparation of a wiring structure. It is process drawing explaining preparation of a wiring structure. It is process drawing explaining preparation of a wiring structure. It is process drawing explaining preparation of a wiring structure. It is process drawing explaining preparation of a wiring structure. It is process drawing explaining preparation of a wiring structure. It is process drawing explaining preparation of a wiring structure. It is process drawing explaining preparation of a core laminated body. It is process drawing explaining preparation of a core laminated body. It is process drawing explaining preparation of a core laminated body. It is process drawing explaining preparation of a core laminated body. It is process drawing explaining preparation of a core laminated body. It is process drawing explaining preparation of a core laminated body. It is process drawing explaining preparation of a core laminated body. It is process drawing explaining preparation of a core laminated body. It is process drawing explaining preparation of a core laminated body. It is process drawing explaining preparation of a core laminated body. It is process drawing explaining preparation of a core laminated body. It is process drawing explaining preparation of a core laminated body. It is process drawing explaining preparation of a core laminated body. It is process drawing explaining preparation of a core laminated body. It is process drawing explaining preparation of a core laminated body. It is process drawing explaining preparation of a printed wiring board with a built-in electronic component. It is process drawing explaining preparation of a printed wiring board with a built-in electronic component. It is process drawing explaining preparation of a printed wiring board with a built-in electronic component. It is a fragmentary sectional view which shows the electronic component built-in printed wiring board concerning 2nd Embodiment. It is a fragmentary sectional view which shows the electronic component built-in printed wiring board concerning 3rd Embodiment. It is a fragmentary sectional view which shows the electronic component built-in printed wiring board concerning 4th Embodiment. It is a fragmentary sectional view showing an electronic component built-in printed wiring board concerning a 5th embodiment. It is a fragmentary sectional view showing an electronic component built-in printed wiring board concerning a 6th embodiment. It is a fragmentary sectional view showing an electronic component built-in printed wiring board concerning a 7th embodiment.

  DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of an electronic component built-in printed wiring board according to the present invention will be described below with reference to the drawings. In the description of the drawings, the same elements are denoted by the same reference numerals, and redundant description is omitted.

<First Embodiment>
As shown in FIG. 1, an electronic component built-in printed wiring board 1 according to the present embodiment includes, for example, a mother board (via a connection pad or the like mounted on one surface with IC chips 2 and 3 mounted on the other surface). This is a wiring board to be mounted on (not shown). The electronic component built-in printed wiring board 1 includes a core laminated body 20 arranged at a central position, a first buildup layer 30 arranged on the upper side so as to sandwich the core laminated body 20, and a second build arranged on the lower side. An up layer 40 is provided.

  The core laminate 20 is a coreless substrate having no so-called core substrate, and is configured by alternately laminating a plurality of insulating layers and conductor layers. The core laminate 20 is formed in a plate shape and is located on the side close to the IC chips 2 and 3, and on the side opposite to the first main surface 20 a (that is, away from the IC chips 2 and 3). 2nd main surface 20b located in the side). In addition, the conductor layer in this embodiment is a wiring layer which comprises an electric circuit, and may include a pad, a wiring pattern, etc. depending on the arrangement position, and may include only a pad.

  A conductor layer 201 including a plurality of connection pads 200 is provided on the first main surface 20a side. The conductor layer 201 corresponds to a “first conductor layer” recited in the claims, and is configured by, for example, an electrolytic plating layer. The conductor layer 201 is embedded in the insulating layer 202, and the upper surface 201a thereof is located on the same plane as the first main surface 20a. The insulating layer 202 is the uppermost insulating layer among the plurality of insulating layers, and is formed of an interlayer resin insulating material. As the interlayer resin insulating material, for example, a prepreg containing glass cloth is used.

  A conductor layer 203 is formed on the lower surface of the insulating layer 202. The conductor layer 203 is composed of, for example, an electroless plating layer and an electrolytic plating layer. A plurality of via conductors 210 that electrically connect the conductor layer 201 and the conductor layer 203 are formed inside the insulating layer 202.

  Under the insulating layer 202 and the conductor layer 203, an insulating layer 204, a conductor layer 205, an insulating layer 206, a conductor layer 207, an insulating layer 208, and a conductor layer 209 are further stacked in this order. The insulating layers 204, 206, and 208 are formed of a prepreg containing glass cloth in the same manner as the insulating layer 202. The insulating layers 202, 204, 206, and 208 correspond to the “third insulating layer” recited in the claims. Of these insulating layers 202, 204, 206, and 208, the insulating layer 202 located on the first major surface 20a side is formed to be the thickest. On the other hand, the conductor layers 205, 207, and 209 are composed of an electroless plating layer and an electrolytic plating layer, like the conductor layer 203.

  As shown in FIG. 1, in the core laminated body 20, the insulating layer 208 is the lowermost insulating layer, and the bottom surface thereof constitutes the second main surface 20 b of the core laminated body 20. The conductor layer 209 is provided on the second main surface 20b side, and corresponds to a “second conductor layer” recited in the claims. A plurality of via conductors 211 are formed inside the insulating layer 204, a plurality of via conductors 212 are formed inside the insulating layer 206, and a plurality of via conductors 213 are formed inside the insulating layer 208. The conductor layer 203 and the conductor layer 205 are electrically connected by a via conductor 211, the conductor layer 205 and the conductor layer 207 are electrically connected by a via conductor 212, and the conductor layer 207 and the conductor layer 209 are electrically connected by a via conductor 213. Electrically connected. As a result, the conductor layer 201 provided on the first main surface 20a side becomes the conductor layer provided on the second main surface 20b side via the via conductors 210, 211, 212, 213 and the conductor layers 203, 205, 207. 209 is electrically connected. The via conductors 210, 211, 212, and 213 correspond to “first via conductors” recited in the claims.

  The via conductors 210, 211, 212, and 213 each have a truncated cone shape and are expanded in diameter in the same direction. Specifically, all of these via conductors 210, 211, 212, and 213 are formed so that the diameter increases along the direction from the first main surface 20 a to the second main surface 20 b. As shown in FIG. 1, some of these via conductors 210, 211, 212, and 213 are stacked in a straight line along the stacking direction of the insulating layer and the conductor layer to form a stack via, Are stacked at different positions along the stacking direction to form offset vias.

  A wiring structure 10 is provided inside the core laminate 20. The wiring structure 10 corresponds to an “electronic component” recited in the claims, and is embedded in the insulating layer 202 of the core laminate 20. The wiring structure 10 is formed in a flat plate shape, an insulating layer 100 disposed at the bottom thereof, a conductor layer 101 formed on the insulating layer 100, and an insulating layer 102 covering the conductor layer 101 from above the conductor layer 101. The conductive layer 103 is formed on the insulating layer 102. The conductor layer 103 is a conductor layer including a plurality of connection pads (connection terminals) 104. In the present embodiment, the conductor layers 101 and 103 are conductor layers that transmit only signals. That is, the wiring of the conductor layers 101 and 103 is composed of only signal lines.

  In the present embodiment, the conductor layers 101 and 103 of the wiring structure 10 are not connected to all the conductor layers 201, 203, 205, 207, and 209 of the core laminate 20. That is, in the electronic component built-in printed wiring board 1, the wiring structure 10 is electrically insulated from the core laminate 20.

  The insulating layers 100 and 102 correspond to the “fourth insulating layer” recited in the claims, and are insulating layers made of, for example, a photosensitive resin. By using the photosensitive resin layer in this manner, small-diameter via holes and high-density wiring patterns can be easily formed in the insulating layers 100 and 102 of the wiring structure 10. On the other hand, the conductor layers 101 and 103 are composed of a seed layer and a copper plating layer. As shown in FIG. 2, the connection pad 104 is embedded in the adhesive layer 106, and the upper surface 104 a thereof is located on the same plane as the first main surface 20 a of the core laminate 20. Further, the upper surface 106a of the adhesive layer 106 is also located on the same plane as the first main surface 20a.

  A plurality of via conductors 105 are formed inside the insulating layer 102. The via conductor 105 corresponds to a “fourth via conductor” recited in the claims, is formed in a truncated cone shape, and is a direction from the second main surface 20 b of the core laminated body 20 toward the first main surface 20 a. The diameter has been expanded. For this reason, the diameter increasing direction of the via conductor 105 is different from the diameter increasing direction of the via conductors 210, 211, 212, and 213 of the core laminate 20. The connection pad 104 is electrically connected to the conductor layer 101 via the via conductor 105.

  In the present embodiment, the wiring structure 10 has higher density wiring than the conductor layer of the core laminate 20. The widths of the wiring layers in the conductor layers 101 and 103 are smaller than the widths of the wiring layers in the conductor layers 201, 203, 205, 207, and 209, for example, in the range of 1 to 5 μm. That is, the L / S (line space) of the wiring in the conductor layers 101 and 103 is smaller than the L / S of the wiring in the conductor layers 201, 203, 205, 207, and 209. Preferably, the L / S of the wiring in the conductor layers 101 and 103 is 1 μm / 1 μm to 5 μm / 5 μm. Here, L (line) means the width of the wiring, and S (space) means the gap between the wirings.

  The first buildup layer 30 is formed on the first main surface 20 a of the core laminate 20, the conductor layer 201, and the wiring structure 10. The first buildup layer 30 is formed by laminating an insulating layer and a conductor layer one by one. Specifically, the first buildup layer 30 includes an insulating layer 302, a conductor layer 301 formed on the insulating layer 302, and a plurality of via conductors 303 formed inside the insulating layer 302. The insulating layer 302, the conductor layer 301, and the via conductor 303 correspond to “first insulating layer”, “third conductor layer”, and “second via conductor” described in the claims, respectively.

The insulating layer 302 is formed on the first major surface 20 a so as to cover the conductor layer 201 of the core laminate 20 and the wiring structure 10. The insulating layer 302 is formed of a resin insulating material containing an inorganic filler such as 30 to 80% by mass of SiO ₂ . The conductor layer 301 includes a plurality of mounting pads 300 for mounting the IC chips 2 and 3, and is composed of, for example, an electroless plating layer and an electrolytic plating layer. The IC chips 2 and 3 are electrically connected to the mounting pads 300 of the first buildup layer 30 through, for example, solder bumps S.

  The via conductor 303 electrically connects the conductor layer 301 and the conductor layer 103 of the wiring structure 10 or the conductor layer 201 of the core laminate 20. As shown in FIG. 1, the via conductor 303 is formed in a truncated cone shape and has a diameter increased in a direction from the second main surface 20 b of the core laminated body 20 toward the first main surface 20 a. Therefore, the diameter increasing direction of the via conductor 303 is opposite to the diameter increasing direction of the via conductors 210, 211, 212, 213 of the core laminate 20. Thus, the via conductor 210 connected to one of the conductor layers 201 and the via conductor 303 connected to the other of the conductor layers 201 are expanded in different directions.

  The second buildup layer 40 is formed so as to cover the second main surface 20b and the conductor layer 209 from below the second main surface 20b and the conductor layer 209 of the core laminate 20. The second buildup layer 40 is configured by laminating an insulating layer and a conductor layer one by one. Specifically, the second buildup layer 40 includes an insulating layer 402, a conductor layer 401 formed on the lower surface of the insulating layer 402, and a plurality of via conductors 403 formed inside the insulating layer 402. The insulating layer 402, the conductor layer 401, and the via conductor 403 correspond to “second insulating layer”, “fourth conductor layer”, and “third via conductor” recited in the claims, respectively.

The insulating layer 402 is formed of a resin insulating material containing an inorganic filler such as 30 to 80% by mass of SiO ₂ , similarly to the insulating layer 302 of the first buildup layer 30. The conductor layer 401 includes a plurality of mounting pads 400 for connecting to terminals, electrodes, and the like provided on the mother board, and is composed of, for example, an electroless plating layer and an electrolytic plating layer. The via conductor 403 is formed in a truncated cone shape and has a diameter increased in a direction from the first main surface 20a to the second main surface 20b of the core laminate 20. Therefore, the diameter increasing direction of the via conductor 403 of the second buildup layer 40 is different from the diameter increasing direction of the via conductor 303 of the first buildup layer 30 and is the opposite direction. The via conductor 403 electrically connects the conductor layer 401 and the conductor layer 209 of the core laminate 20.

  In the electronic component built-in printed wiring board 1 having the above configuration, the via conductor 210 of the core laminate 20 connected to one of the conductor layers 201 of the core laminate 20 and the first buildup layer connected to the other of the conductor layers 201. 30 via conductors 303 are expanded in different directions. Therefore, after the core laminate 20 is manufactured by the coreless method, the first buildup layer 30 and the second build are formed on both sides of the core laminate 20 as a core substrate. By forming the up layer 40 at the same time, the electronic component built-in printed wiring board 1 can be manufactured. If it does in this way, compared with the case where only a coreless construction method is used, the number of manufacturing processes can be reduced and manufacturing cost can be reduced.

  Further, since the first buildup layer 30 and the second buildup layer 40 can be formed symmetrically on both sides of the core laminate 20, thermal expansion of the first buildup layer 30 and the second buildup layer 40 is possible. Thermal stress caused by the difference in coefficient can be relaxed, and warpage caused by thermal stress can be prevented. As a result, the connection reliability of the electronic component built-in printed wiring board 1 can be improved. Furthermore, since the upper surface 201a of the conductor layer 201 of the core laminate 20 is located in the same plane as the first main surface 20a of the core laminate 20 and the upper surface 104a of the connection pad 104 of the wiring structure 10, the core laminate The first main surface 20a of the body 20 becomes flat, and fine wiring can be easily formed on the first main surface 20a.

  Hereinafter, the manufacturing method of the electronic component built-in printed wiring board 1 will be described. The manufacturing method of the electronic component built-in printed wiring board 1 according to the present embodiment includes a step of manufacturing the wiring structure 10 and a step of manufacturing the core stacked body 20 by embedding the wiring structure 10 in the core stacked body 20. And forming the first buildup layer 30 and the second buildup layer 40 on both sides of the core laminate 20. First, a manufacturing step of the wiring structure 10 will be described with reference to FIGS. 3A to 3H.

<Step of Fabricating Wiring Structure 10>
First, the support plate 110 is prepared. The support plate 110 is, for example, a flat glass plate having a low coefficient of thermal expansion. However, the support plate 110 is not limited to this, and may be Si, a metal plate, or the like. Subsequently, a release layer 111 is formed on the support plate 110 (see FIG. 3A). Examples of the release agent used for the release layer 111 include Wafer Bond manufactured by Brewer Science. Subsequently, an insulating layer 100 made of a resin is formed on the release layer 111. The insulating layer 100 is formed by applying and heating an insulating material made of a photosensitive polyimide resin, for example. Subsequently, the peeling layer 111 and the insulating layer 100 are bonded by heat treatment.

  Next, the conductor layer 101 is formed on the insulating layer 100 by using a semi-additive process (SAP). Specifically, first, a seed layer 101a is formed on the insulating layer 100 (see FIG. 3B). The seed layer 101a is formed by, for example, a sputtering method, and as the material of the seed layer 101a, for example, titanium, titanium nitride, chromium, copper, or the like is used. Subsequently, a predetermined resist pattern 112 is formed on the seed layer 101a. Specifically, a predetermined resist pattern 112 is formed by applying a photosensitive resist layer on the seed layer 101a and then performing an exposure process and a development process (see FIG. 3C).

  Next, a copper plating layer 101b is formed on the seed layer 101a where the resist pattern 112 is not formed. Here, the copper plating layer 101b may be an electroless plating layer, an electrolytic plating layer, or a layer formed by laminating an electroless plating layer and an electrolytic plating layer. Subsequently, the predetermined resist pattern 112 formed on the seed layer 101a is peeled off. Next, the portion of the seed layer 101a exposed to the outside by peeling off the resist pattern 112 is etched. The seed layer 101a and the copper plating layer 101b left on the insulating layer 100 constitute the conductor layer 101 (see FIG. 3D).

  Subsequently, an insulating layer 102 is formed on the conductor layer 101 and the insulating layer 100 so as to cover them (see FIG. 3E). The insulating layer 102 is formed by applying an insulating material made of a photosensitive polyimide resin and heating the same as the insulating layer 100. Subsequently, the insulating layer 102 is exposed using a mask having an opening at a predetermined position, and further developed to form a via hole 113 at the predetermined position (see FIG. 3F).

  Next, the via conductor 105 and the conductor layer 103 are formed. Specifically, first, a seed layer is formed on the insulating layer 102 and on the inner wall surface and bottom surface of the via hole 113 by a sputtering method. Subsequently, a predetermined resist pattern is formed on the seed layer by the above-described method, and then a copper plating layer is formed on the seed layer on which the resist pattern is not formed, and the resist pattern is peeled off. Further, the portion of the seed layer that is exposed to the outside by peeling off the resist pattern is etched, thereby forming the conductor layer 103 including the seed layer and the copper plating layer on the insulating layer 102. The conductor layer 103 includes a plurality of connection pads 104 for mounting the IC chips 2 and 3.

  Further, by forming a copper plating layer, the via hole 113 is filled with copper, and the filled copper constitutes the via conductor 105 (see FIG. 3G). Next, for example, from the side where the conductor layer 103 is formed, the wiring structure 10 is cut into individual pieces by cutting along a predetermined cutting line (see FIG. 3H). Thus, the production of the wiring structure 10 is completed.

<Step of Fabricating Core Laminate 20 by Embedding Wiring Structure 10 in Core Laminate 20>
Hereinafter, a step of fabricating the core laminate 20 by embedding the wiring structure 10 in the core laminate 20 will be described with reference to FIGS. 4A to 4O.

  First, a support plate 214 provided with a carrier copper foil 215 is prepared. As the support plate 214, an epoxy resin substrate (a prepreg with a core material) having a glass cloth as a core material can be used. Next, the conductor layer 201 including the plurality of connection pads 200 is formed on the support plate 214. Specifically, first, the copper foil 216 is formed on the support plate 214 (see FIG. 4A). Subsequently, a photosensitive dry film is laminated on the surface of the copper foil 216. And after making the mask film in which each predetermined pattern was formed in close contact with the photosensitive dry film, exposure processing is performed to the photosensitive dry film with ultraviolet rays. Subsequently, development processing using an alkaline aqueous solution is performed on the photosensitive dry film. As a result, a predetermined resist pattern 217 is formed (see FIG. 4B).

  Next, electrolytic plating is performed on the upper surface of the copper foil 216 to form a plating film. Then, the resist pattern 217 is removed using a solution containing monoethanolamine. Thereby, the conductor layer 201 is formed on the upper surface of the copper foil 216 (see FIG. 4C). The conductor layer 201 includes a plurality of connection pads 200. Subsequently, the adhesive layer 106 is formed by applying an adhesive to a predetermined position on the upper surface of the copper foil 216 formed on the support plate 214. As the adhesive, for example, an epoxy resin, acrylic resin, silicone resin, or the like is used. The adhesive layer 106 is formed so as to have approximately the same size as the wiring structure 10.

  Next, the wiring structure 10 is fixed on the support plate 214 so that the connection pads 104 of the wiring structure 10 face downward. Specifically, the wiring structure 10 is placed on the upper surface of the adhesive layer 106 with the connection pads 104 facing downward, and fixed to the copper foil 216 formed on the support plate 214 via the adhesive layer 106. (See FIGS. 4D and 4E). As a result, the via conductor 105 of the wiring structure 10 is in a state of increasing in diameter toward the support plate 214. Further, when the connection pads 104 are in close contact with the adhesive layer 106, the adhesive is filled between the adjacent connection pads 104 without any gap.

  Next, the support plate 110 integrated with the wiring structure 10 is peeled off. Peeling of the support plate 110 is performed, for example, by heating the wiring structure 10 and the support plate 110 to soften the peeling layer 111 and separating the wiring structure 10 and the support plate 110. Then, after peeling off the support plate 110, the release agent remaining on the wiring structure 10 is removed cleanly (see FIG. 4F).

Next, an insulating layer 202 is formed on the copper foil 216 so as to cover the conductor layer 201 and the wiring structure 10 (see FIG. 4G). As a material of the insulating layer 202, for example, a prepreg containing glass cloth is used. Subsequently, the insulating layer 202 is irradiated with CO ₂ laser light to form a plurality of via holes 218 (see FIG. 4H). After the via hole 218 is formed, a desmear process for removing smear remaining in the via hole 218 is performed. The via hole 218 is processed so that the diameter decreases toward the support plate 214. Therefore, the via conductor formed in the via hole 218 is reduced in diameter toward the support plate 214.

  Next, the support plate 214 on which the insulating layer 202 is formed is immersed in a catalyst containing Pd or the like as a main component, and the catalyst is attached to the surface of the insulating layer 202. Subsequently, the support plate 214 is immersed in an electroless copper plating solution. As a result, the electroless plating film 203a is formed on the surface of the insulating layer 202 and the inner wall surface and bottom surface of the via hole 218 (see FIG. 4I). Copper, nickel, or the like can be used as a material for the electroless plating film.

  Next, a photosensitive dry film is laminated on the surface of the electroless plating film 203a. Subsequently, after a mask film in which a predetermined pattern is formed is adhered to the photosensitive dry film, the photosensitive dry film is exposed to ultraviolet light. Subsequently, development processing using an alkaline aqueous solution is performed on the photosensitive dry film. As a result, a predetermined resist pattern 219 is formed (see FIG. 4J).

  Next, the electroless plating layer 203b is formed thereon using the electroless plating layer 203a as a seed layer (see FIG. 4K). Subsequently, after removing the resist pattern 219, the electroless plating film 203a covered with the resist pattern 219 is removed by etching. As a result, the electroless plating layer 203 a and the electrolytic plating layer 203 b left on the insulating layer 202 constitute the conductor layer 203. The via hole 218 is filled with an electrolytic plating material, and the filled electrolytic plating material forms a via conductor 210 (see FIG. 4L).

  Next, the insulating layer 204, the conductor layer 205, the via conductor 211, the insulating layer 206, the conductor layer 207, the via conductor 212, the insulating layer 208, the conductor layer 209, and the via conductor 213 are sequentially formed by repeating the above-described method. To do. As a result, the core laminate 20 is formed on the support plate 214 (see FIG. 4M).

  Next, after peeling off the support plate 214 and the carrier copper foil 215 from the core laminate 20, the core laminate 20 is turned upside down (see FIG. 4N). Subsequently, the copper foil 216 is removed by etching. Thereby, the connection pad 200 which is a part of the conductor layer 201 is exposed to the outside. Subsequently, an etching process is performed so that the upper surface 201a of the conductor layer 201 and the upper surface of the insulating layer 202 (that is, the first main surface 20a of the core laminate 20) are arranged on the same plane.

Next, the adhesive layer 106 is removed so that the upper surface 104a of the connection pad 104 is exposed to the outside by CO ₂ laser light irradiation. As a result, the connection pad 104 which is a part of the conductor layer 103 is exposed to the outside. Subsequently, an etching process is performed so that the upper surface 201a of the conductor layer 201 and the upper surface 104a of the connection pad 104 are positioned on the same plane. Further, the adhesive layer 106 is removed so that the upper surface 106a of the adhesive layer 106 and the upper surface 104a of the connection pad 104 are positioned on the same plane. This completes the production of the core laminate 20 (see FIG. 4O).

<Step of forming first buildup layer 30 and second buildup layer 40 on both sides of core laminate 20>
Hereinafter, the step of simultaneously forming the first buildup layer 30 and the second buildup layer 40 on both sides of the core laminate 20 will be described with reference to FIGS. 5A to 5C. Specifically, first, an insulating layer 302 covering the first main surface 20a, the conductor layer 201, and the wiring structure 10 from above is provided on the upper surface (that is, the first main surface 20a) of the core stacked body 20, and the core stacked body 20 An insulating layer 402 that covers the second main surface 20b and the conductor layer 209 is simultaneously formed on the bottom surface (that is, the second main surface 20b) from below (see FIG. 5A). As a material for the insulating layers 302 and 402, for example, a prepreg containing glass cloth is used.

Subsequently, the insulating layer 302 and the insulating layer 402 are irradiated with CO ₂ laser light to form a plurality of via holes 304 and 404 (see FIG. 5B). The via hole 304 formed in the insulating layer 302 is formed in a truncated cone shape, and its diameter gradually increases along the direction from the second main surface 20b of the core stacked body 20 toward the first main surface 20a. Therefore, the via conductor formed in the via hole 304 is expanded in the direction from the second main surface 20b of the core laminated body 20 toward the first main surface 20a. On the other hand, the via hole 404 formed in the insulating layer 402 is formed in a truncated cone shape, and its diameter gradually increases along the direction from the first main surface 20a to the second main surface 20b of the core laminate 20. Yes. Therefore, the via conductor formed in the via hole 404 is enlarged in the direction from the first main surface 20a to the second main surface 20b of the core laminate 20.

  Subsequently, the via conductor 303 and the conductor layer 301 of the first buildup layer 30 and the via conductor 403 and the conductor layer 401 of the second buildup layer 40 are simultaneously formed by the method shown in FIGS. 4I to 4K. Thus, the production of the electronic component built-in printed wiring board 1 is completed (see FIG. 5C).

Second Embodiment
Hereinafter, a second embodiment of the present invention will be described with reference to FIG. The electronic component built-in printed wiring board 4 according to this embodiment is different from the above-described first embodiment in that the conductor layers 101 and 103 of the wiring structure 10 are electrically connected to the conductor layer 203 of the core laminate 20. However, other structures are the same as those in the first embodiment.

  Specifically, a via conductor 220 is further provided between the conductor layer 203 of the core laminate 20 and the conductor layer 101 of the wiring structure 10 to electrically connect these conductor layers. . The via conductor 220 is formed inside the insulating layer 202 of the core laminate 20 and the insulating layer 100 of the wiring structure 10. The via conductor 220 has a frustoconical shape like the via conductor 210 formed in the insulating layer 202, and has a diameter increased in a direction from the first main surface 20 a to the second main surface 20 b of the core stacked body 20.

  By providing the via conductor 220, the conductor layer 103 of the wiring structure 10 is electrically connected to the conductor layer 401 positioned on the lowermost side of the electronic component built-in printed wiring board 4. That is, the conductor layer 103 of the wiring structure 10 includes the via conductor 105 and the conductor layer 101 of the wiring structure 10, the via conductors 220, 211, 212, 213 and the conductor layers 203, 205, 207, 209 of the core stacked body 20, Further, it is electrically connected to the lowermost conductor layer 401 through the via conductor 403 of the second buildup layer 40. Therefore, the wiring formed in this way can be used as a power supply or ground wiring. In addition, the electronic component built-in printed wiring board 4 according to the present embodiment can obtain the same effects as those of the first embodiment in that it has the same structure as that of the first embodiment.

<Third Embodiment>
Hereinafter, a third embodiment of the present invention will be described with reference to FIG. The electronic component built-in printed wiring board 5 according to this embodiment is different from the above-described first embodiment in that a part of the conductor layer 305 of the first buildup layer 31 is connected. This is the same as the embodiment.

  Specifically, the conductor layer 305 is disposed on the uppermost side of the electronic component built-in printed wiring board 5 and includes a plurality of mounting pads 306 for mounting the IC chips 2 and 3. The conductor layer 305 corresponds to a “third conductor layer” recited in the claims. Of the mounting pads 306, the mounting pads 306 a that are electrically connected to the conductor layer 103 of the wiring structure 10 via the via conductors 303 and the conductor layers 201 of the core laminate 20 are electrically connected via the via conductors 303. The mounting pads 306b to be connected are connected by wirings 307 arranged therebetween. The wiring 307 is formed on the upper surface of the insulating layer 302. The electronic component built-in printed wiring board 5 configured as described above can obtain the same effects as those of the first embodiment, and the mounting pad 306a and the mounting pad 306b are connected by the wiring 307. The wiring formed in 10 can be used not only for signal transmission but also as power supply or ground wiring, for example, and the degree of freedom in wiring design of the electronic component built-in printed wiring board 5 can be improved.

<Fourth embodiment>
The fourth embodiment of the present invention will be described below with reference to FIG. The electronic component built-in printed wiring board 6 according to this embodiment is different from the above-described first embodiment in that the wiring structure 11 is joined to the core laminated body 20 by solder joint, but other structures and the like are the first embodiment. It is the same as the form.

  Specifically, unlike the wiring structure 10 of the first embodiment, the wiring structure 11 does not have the adhesive layer 106 but includes the insulating layers 102 and 108. The insulating layer 108 is an insulating layer made of a photosensitive resin similarly to the insulating layer 102, and is filled between the connection pads 104. The upper surface 108 a of the insulating layer 108 is located in the same plane as the upper surface 104 a of the connection pad 104. The insulating layer 108 corresponds to the “fourth conductor layer” recited in the claims. Further, the lower surface 101a of the conductor layer 101 is exposed to the outside at the lower surface 102a of the insulating layer 102 that constitutes the bottom surface of the wiring structure 11. The lower surface 101a of the conductor layer 101 is located in the same plane as the lower surface 102a of the insulating layer 102.

  A part of the conductor layer 101 exposed to the outside constitutes a plurality of connection pads 107 for connection to the conductor layer 221 of the core laminate 20. On the other hand, a plurality of connection pads 222 for connecting to the connection pads 107 of the wiring structure 11 are formed on the insulating layer 204 of the core laminate 20. The connection pad 222 is a part of the conductor layer 221 and is bonded to the connection pad 107 of the wiring structure 11 via the solder 109. As a result, the connection pads 222 of the core laminate 20 and the connection pads 107 of the wiring structure 11 are electrically connected.

  In addition, among the plurality of connection pads 107 that are electrically connected to the connection pads 222 of the core multilayer body 20, some of them are via conductors 211, 212, 213 and conductor layers 205, 207, 209, Furthermore, the second buildup layer 40 is electrically connected to the conductor layer 401 located on the lowermost side of the electronic component built-in printed wiring board 6 through the via conductor 403. Therefore, the wiring formed in this way can be used as a power supply or ground wiring. In addition, the electronic component built-in printed wiring board 6 according to the present embodiment can obtain the same effects as those of the first embodiment in that it has the same structure as that of the first embodiment.

<Fifth Embodiment>
Hereinafter, a fifth embodiment of the present invention will be described with reference to FIG. In the electronic component built-in printed wiring board 7 according to this embodiment, the wiring structure 11 is joined to the core laminated body 20 by solder joint, and a part of the conductor layer 305 of the first buildup layer 31 is connected. Although different from the above-described first embodiment in other respects, other structures and the like are the same as those of the first embodiment.

  Specifically, first, the wiring structure 11 has the same structure as the wiring structure 11 according to the fourth embodiment described above. That is, the insulating layer 108 is filled between the connection pads 104 instead of the adhesive layer 106, and the upper surface 104 a of the connection pad 104 is located in the same plane as the upper surface 108 a of the insulating layer 108. A plurality of connection pads 222 for connecting to the connection pads 107 of the wiring structure 11 are formed on the insulating layer 204 of the core laminate 20. The connection pads 222 are connected to the connection pads 107 of the wiring structure 11 via the solder 109. Electrically connected. Further, some of the connection pads 107 of the wiring structure 11 include the via conductors 211, 212, 213 and the conductor layers 205, 207, and 209 of the core laminate 20, and the via conductor 403 of the second buildup layer 40. And electrically connected to the conductor layer 401 located on the lowermost side of the printed wiring board 7 with built-in electronic components. Therefore, the wiring formed in this way can be used as a power supply or ground wiring.

  The first buildup layer 31 according to this embodiment has the same structure as the first buildup layer 31 according to the third embodiment described above. That is, the conductor layer 305 located on the uppermost side of the electronic component built-in printed wiring board 7 includes a plurality of mounting pads 306 for mounting the IC chips 2 and 3. Of the mounting pads 306, the mounting pads 306 a that are electrically connected to the conductor layer 103 of the wiring structure 10 via the via conductors 303 and the conductor layers 201 of the core laminate 20 are electrically connected via the via conductors 303. The mounting pads 306b to be connected are connected by wirings 307 arranged therebetween. The electronic component built-in printed wiring board 7 configured as described above can obtain the same operation and effect as those of the first embodiment, and the mounting pad 306a and the mounting pad 306b are connected by the wiring 307. The wiring formed in 11 can be used not only for signal transmission but also as power supply or ground wiring, for example, and the degree of freedom in wiring design of the electronic component built-in printed wiring board 7 can be improved.

<Sixth Embodiment>
The sixth embodiment of the present invention will be described below with reference to FIG. The electronic component built-in printed wiring board 8 according to this embodiment is different from the first embodiment described above in that the heat dissipation member 114 is provided, but the other structures and the like are the same as those of the first embodiment.

  Specifically, a heat dissipation member 114 is provided on the lower surface of the insulating layer 100 of the wiring structure 12. The heat radiating member 114 is, for example, a metal plating layer formed by copper plating, and the thickness is preferably 10 to 80 μm. In addition to the copper plating layer described above, the heat radiating member 114 may be formed of another metal plating layer, a metal plate, or a nanocarbon material.

  The electronic component built-in printed wiring board 8 according to the present embodiment can obtain the same effects as those of the first embodiment described above, and the wiring structure 12 is provided with the heat radiating member 114, so that the IC is provided via the heat radiating member 114. Heat generated during the operation of the chips 2 and 3 can be efficiently released to the surroundings. Therefore, the influence of thermal stress can be reduced, and the effect of further improving the connection reliability of the electronic component built-in printed wiring board 8 can be achieved.

<Seventh embodiment>
Hereinafter, a seventh embodiment of the present invention will be described with reference to FIG. The printed wiring board 9 with built-in electronic components according to this embodiment is the first embodiment described above in that the core laminate is composed of one insulating layer, and the first and second buildup layers are each composed of two insulating layers. Although different from the form, other structures and the like are the same as those of the first embodiment.

  Specifically, the electronic component built-in printed wiring board 9 includes the core laminate 21, the first buildup layer 32 formed on the first main surface 21 a of the core laminate 21, and the first of the core laminate 21. And a second buildup layer 41 formed below the two major surfaces 21b. The core laminate 21 has one insulating layer 223 formed of a prepreg containing glass cloth. The insulating layer 223 corresponds to a “third insulating layer” recited in the claims. A conductor layer 201 including a plurality of connection pads 200 is provided on the first main surface 21 a side of the core laminate 21. A conductor layer 224 is formed below the second main surface 21 b of the core laminate 21. The conductor layer 224 corresponds to a “second conductor layer” recited in the claims, and is constituted by, for example, an electroless plating layer and an electrolytic plating layer.

  The conductor layer 201 and the conductor layer 224 are electrically connected by a via conductor 225 formed inside the insulating layer 223. The via conductor 225 corresponds to a “first via conductor” recited in the claims, and a plurality of via conductors 225 are formed in the insulating layer 223. The via conductor 225 has a truncated cone shape and has a diameter increased in a direction from the first main surface 21a toward the second main surface 21b. In addition, the wiring structure 10 is provided inside the core laminate 21.

The first buildup layer 32 is formed by alternately laminating two insulating layers 308 and 310 and two conductor layers 309 and 311 on the first main surface 21 a of the core laminate 21. . Insulating layer 308 is formed by a resin insulating material containing for example 30 to 80% by weight of an inorganic filler such as SiO _2. The conductor layers 309 and 311 are constituted by, for example, an electroless plating layer and an electrolytic plating layer. The conductor layer 311 is disposed on the uppermost side of the electronic component built-in printed wiring board 9 and has a plurality of mounting pads 312 for mounting the IC chips 2 and 3. The insulating layers 308 and 310 and the conductor layers 309 and 311 correspond to “first insulating layer” and “third conductor layer” recited in the claims, respectively.

  In addition, a plurality of via conductors 313 that electrically connect the conductor layer 309 and the conductor layer 201 of the core laminate 21 or the conductor layer 103 of the wiring structure 10 are formed inside the insulating layer 308. A plurality of via conductors 314 that electrically connect the conductor layer 309 and the conductor layer 311 are formed inside the insulating layer 310. The via conductors 313 and 314 correspond to “second via conductors” recited in the claims. These via conductors 313 and 314 are each formed in a truncated cone shape, and the diameter is increased in a direction from the second main surface 21b of the core laminated body 21 toward the first main surface 21a. Therefore, the diameter expansion direction of the via conductors 313 and 314 is opposite to the diameter expansion direction of the via conductor 225 of the core laminate 21. As a result, in the conductor layer 201 of the core laminate 21, the via conductor 225 connected to one of the conductor layers 201 and the via conductor 313 connected to the other of the conductor layers 201 are expanded in different directions.

The second buildup layer 41 is formed by alternately laminating two insulating layers 406 and 408 and two conductor layers 405 and 407 under the second main surface 21b of the core laminate 21. . The insulating layers 406 and 408 are made of a resin insulating material containing an inorganic filler such as 30 to 80% by mass of SiO ₂ . The conductor layers 405 and 407 are constituted by, for example, an electroless plating layer and an electrolytic plating layer. The conductor layer 407 is disposed on the lowermost side of the electronic component built-in printed wiring board 9 and has a plurality of mounting pads 409 for connecting to terminals, electrodes, and the like provided on the motherboard. The insulating layers 406 and 408 and the conductor layers 405 and 407 correspond to “second insulating layer” and “fourth conductor layer” recited in the claims, respectively.

  A plurality of via conductors 410 that electrically connect the conductor layer 405 and the conductor layer 224 of the core laminate 21 are formed inside the insulating layer 406. A plurality of via conductors 411 that electrically connect the conductor layer 405 and the conductor layer 407 are formed inside the insulating layer 408. The via conductors 410 and 411 correspond to a “third via conductor” recited in the claims. These via conductors 410 and 411 are each formed in a truncated cone shape, and have a diameter increased in a direction from the first main surface 21 a to the second main surface 21 b of the core laminated body 21. Accordingly, the diameter increasing direction of the via conductors 410 and 411 of the second buildup layer 41 is different from the diameter increasing direction of the via conductors 313 and 314 of the first buildup layer 32 and is in the opposite direction. The electronic component built-in printed wiring board 9 according to the present embodiment can obtain the same effects as those of the first embodiment described above.

  Although the embodiments of the present invention have been described in detail above, the present invention is not limited to the above-described embodiments, and various designs can be made without departing from the spirit of the present invention described in the claims. It can be changed. For example, in the above-described embodiment, the example of the wiring structure is described as the electronic component. However, the electronic component is not limited to the wiring structure, for example, an active semiconductor element, an interposer having a passive component or a wiring layer, or a rewiring layer. A semiconductor element having WLP (Wafer Level Package) may be used. Moreover, the number of layers of the core laminate, the first buildup layer, the insulating layer and the conductor layer of the second buildup layer is not limited to the above-described embodiment, and the number of layers can be changed as necessary. For example, the core laminate, the first buildup layer, and the second buildup layer may each be formed of one insulating layer. In this case, it is easy to reduce the thickness of the printed wiring board with built-in electronic components.

  Further, the conductor layers of the first buildup layer and the second buildup layer may have the same thickness or different thicknesses as necessary. For example, in order to suppress warping of the printed wiring board with built-in electronic components and refine the wiring, the thickness of the conductor layer of the first buildup layer is made thinner than that of the second buildup layer. Furthermore, the insulating layer of the core laminate, the insulating layer of the first buildup layer, and the insulating layer of the second buildup layer may all be formed of the same material. For example, all of these insulating layers may be formed of a resin insulating material containing an inorganic filler. Furthermore, a solder resist layer may be formed on the front and back surfaces of the electronic component built-in printed wiring board according to the present invention, if necessary.

1, 4, 5, 6, 7, 8, 9 Printed wiring board with built-in electronic components 2, 3 IC chip 10, 11, 12 Wiring structure (electronic component)
20, 21 Core laminates 20a, 21a First major surfaces 20b, 21b Second major surfaces 30, 31, 32 First buildup layers 40, 41 Second buildup layers 100, 102, 108 Insulating layer (fourth insulating layer) )
104 Connection pad (connection terminal)
104a Upper surface 105 Via conductor (fourth via conductor)
106 Adhesive layer 114 Heat dissipation member 200 Connection pad 201 Conductor layer (first conductor layer)
201a Upper surface 202, 204, 206, 208, 223 Insulating layer (third insulating layer)
209,224 Conductor layer (second conductor layer)
210, 211, 212, 213, 225 Via conductor (first via conductor)
301, 305, 309, 311 Conductor layer (third conductor layer)
302, 308, 310 insulating layer (first insulating layer),
303, 313, 314 Via conductor (second via conductor)
401, 405, 407 Conductor layer (fourth conductor layer)
402, 406, 408 Insulating layer (second insulating layer)
403, 410, 411 Via conductor (third via conductor)

Claims (12)

A first main surface and a second main surface opposite to the first main surface are provided, a first conductor layer provided on the first main surface side, and a second conductor layer provided on the second main surface side A core laminate having a plurality of first via conductors that electrically connect the first conductor layer and the second conductor layer;
An electronic component provided inside the core laminate and having a plurality of connection terminals;
Provided on the first main surface and the first conductor layer of the core laminate, and within the first insulating layer, a first conductor layer, a third conductor layer formed on the first insulating layer, and the first insulating layer. A first buildup layer formed and having a plurality of second via conductors electrically connecting the first conductor layer and the third conductor layer;
Provided on the second main surface and the second conductor layer of the core laminate, and a second insulating layer, a fourth conductor layer formed on the second insulating layer, and inside the second insulating layer A second buildup layer formed and having a plurality of third via conductors electrically connecting the second conductor layer and the fourth conductor layer;
An electronic component built-in printed wiring board comprising:
The first conductor layer is embedded in the core laminate, and an upper surface thereof is located on the same plane as the first main surface of the core laminate and the upper surface of the connection terminal of the electronic component,
The first via conductor connected to one of the first conductor layers and the second via conductor connected to the other of the first conductor layers are expanded in different directions. In the electronic component built-in printed wiring board according to claim 1,
The diameter of the second via conductor is increased in a direction different from that of the third via conductor. In the electronic component built-in printed wiring board according to claim 1 or 2,
The second via conductor is enlarged in a direction from the second main surface of the core laminate to the first main surface. In the electronic component built-in printed wiring board according to any one of claims 1 to 3,
The first insulating layer and the second insulating layer are formed of the same or different materials. In the electronic component built-in printed wiring board according to any one of claims 1 to 4,
The core laminate further includes a third insulating layer,
The third insulating layer is formed of the same material as the first insulating layer and the second insulating layer. In the electronic component built-in printed wiring board according to any one of claims 1 to 4,
The core laminate has a third insulating layer formed by a prepreg containing glass cloth,
The first insulating layer and the second insulating layer are formed of a resin material containing an inorganic filler. In the electronic component built-in printed wiring board according to any one of claims 1 to 6,
The thickness of the third conductor layer of the first buildup layer is different from the thickness of the fourth conductor of the second buildup layer. In the electronic component built-in printed wiring board according to claim 7,
The third conductor layer of the first buildup layer is thinner than the fourth conductor of the second buildup layer. In the electronic component built-in printed wiring board according to any one of claims 1 to 8,
The electronic component is a wiring structure having a wiring having a width narrower than a width of the first conductor layer and a width of the second conductor layer of the core structure,
The connection terminal is a connection pad of the wiring structure. In the electronic component built-in printed wiring board according to claim 9,
The wiring structure includes a fourth insulating layer and a plurality of fourth via conductors formed inside the fourth insulating layer and electrically connected to the connection pads. In the electronic component built-in printed wiring board according to claim 10,
The fourth via conductor of the wiring structure is expanded in a direction different from that of the first via conductor. In the electronic component built-in printed wiring board according to any one of claims 9 to 11,
The wiring structure is provided with a heat radiating member.

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