TWI530240B - Printed circuit board and method for manufacturing same - Google Patents

Description

Circuit board and manufacturing method thereof

The present invention relates to the field of circuit board manufacturing, and in particular, to a circuit board and a manufacturing method thereof.

In order to save the size of the package structure, it is usually necessary to package the wafer and the circuit board on the board as the package carrier. Wherein, the corresponding package area of the wafer generally needs to be provided with dense contact pads, and the contact pads of the package with the circuit board are generally larger in size and sparsely distributed. Moreover, in the packaging process, it is usually necessary to package the wafer on the package carrier, and then package the package substrate on which the wafer is packaged with other circuit boards. In the prior art, it is generally required to form two solder mask layers on the surface of the package carrier. The first solder mask is used to define the contact pads on the carrier board, and the second solder mask (Dam Ring) is formed in the first defense. The solder layer is placed around the chip package area to serve as a dam when the wafer is packaged. However, since the first solder resist layer and the second solder resist layer are respectively formed, after the package, it is easy to concentrate on the boundary between the first solder resist layer and the second solder resist layer, thereby causing the first solder resist layer and the first The two solder resist layers are separated from each other.

Therefore, it is necessary to provide a circuit board and a method thereof that can solve the above problems.

A circuit board comprising a first dielectric layer, a first conductive circuit layer, a bump pattern and a second dielectric layer, wherein the first dielectric layer and the second dielectric layer are connected to each other, the first conductive circuit layer The central package region and the peripheral package region surrounding the central package region, the bump pattern is formed on the first dielectric layer having a surface away from the second dielectric layer, the bump pattern and the first dielectric The layer is integrally formed, and the shape of the bump pattern corresponds to the intersection of the central package region and the peripheral package region.

A circuit board manufacturing method comprising the steps of: providing a carrier board, the carrier board having a first surface; forming a groove pattern from the first surface of the carrier board into the carrier board; Forming a bump pattern in the groove pattern, and simultaneously forming a first dielectric layer on the first surface of the carrier, the first dielectric layer and the bump pattern being integrally formed; in the first dielectric layer Forming a first conductive circuit layer on the surface, the first conductive circuit layer includes a central package region and a peripheral package region, and an intersection of the central package region and the peripheral package region corresponds to the bump pattern; in the first conductive line Pressing the second dielectric layer on one side of the layer; and removing the carrier.

The circuit board and the manufacturing method thereof provided by the technical solution integrate the first dielectric layer and the bump pattern by a groove pattern in the carrier board and then press-bonding manner, so that the bump pattern is integrated with the first dielectric layer forming. Compared with the prior art, it is formed by forming two solder resist layers respectively, so that after the package, the two solder resist layers are separated from each other due to stress concentration at the boundary of the two solder resist layers.

100‧‧‧ boards

110‧‧‧ Carrier Board

111‧‧‧ first surface

112‧‧‧ Groove graphics

120‧‧‧First dielectric layer

121‧‧‧ second surface

123‧‧‧First opening

124‧‧‧second opening

130‧‧‧Bump graphics

140‧‧‧First conductive circuit layer

141‧‧‧Central packaging area

1411‧‧‧First contact pad

142‧‧‧Environmental packaging area

1421‧‧‧Second contact pad

150‧‧‧Second dielectric layer

151‧‧‧ hole

152‧‧‧Electrical hole

160‧‧‧Second conductive circuit layer

161‧‧‧Connecting mat

170‧‧‧ solder mask

171‧‧‧Opening

180‧‧‧protection layer

190‧‧‧ solder bumps

1 is a schematic cross-sectional view of a carrier board provided by an embodiment of the present technical solution.

2 is a schematic cross-sectional view showing a groove pattern formed in the carrier of FIG. 1.

Figure 3 is a plan view of Figure 2.

4 is a cross-sectional view showing the surface of the carrier of FIG. 2 after the first dielectric layer is pressed.

FIG. 5 is a cross-sectional view showing the first conductive wiring layer formed on the surface of the first dielectric layer of FIG. 4. FIG.

6 is a cross-sectional view showing the first conductive layer of FIG. 5 being pressed against the second dielectric layer.

FIG. 7 is a schematic cross-sectional view showing the second conductive wiring layer formed on the surface of the second dielectric layer of FIG. 6. FIG.

Fig. 8 is a schematic cross-sectional view showing a solder resist layer formed on the surface of the second conductive wiring layer of Fig. 7.

Figure 9 is a cross-sectional view of Figure 8 with the carrier removed.

FIG. 10 is a cross-sectional view showing the first opening and the second opening formed in the first dielectric layer of FIG. 9. FIG.

11 is a schematic cross-sectional view of a circuit board fabricated by the present technical solution.

Figure 12 is a plan view of Figure 11 .

The circuit board manufacturing method provided by the technical solution includes the following steps:

In the first step, referring to FIG. 1, a carrier 110 is provided.

The carrier 110 is made of a metal material. In this embodiment, the carrier 110 is made of metal aluminum. The carrier plate 110 has a first surface 111, which is a flat surface.

In the second step, referring to FIG. 2 and FIG. 3, a groove pattern 112 is formed in the carrier 110.

The groove pattern 112 may be formed by laser ablation. Groove pattern 112 should correspond to the edge of the chip package area of the circuit board to be fabricated. In this embodiment, the groove pattern 112 has a substantially square shape. The groove pattern 112 is formed in an intermediate portion of the carrier 110.

In the third step, referring to FIG. 4, a first dielectric layer 120 is formed on the first surface 111 of the carrier 110 and a bump pattern 130 is formed in the groove pattern 112 at the same time.

The first dielectric layer 120 and the bump pattern 130 may be formed by pressing a semi-cured film. The bump pattern 130 is completely filled in the groove pattern 112, and the first dielectric layer 120 covers the entire first surface 111. The first dielectric layer 120 is integrally formed with the bump pattern 130. The material of the first dielectric layer 120 may be an insulating material commonly used in the art, such as polyimide or the like.

The first dielectric layer 120 has a second surface 121 adjacent to the first surface 111. The bump pattern 130 protrudes from the second surface 121, and the shape of the bump pattern 130 is complementary to the groove pattern 112. And corresponding to the edge of the chip package area of the circuit board to be fabricated, in the embodiment, the shape of the bump pattern 130 is substantially a square shape.

In the fourth step, referring to FIG. 5, the first conductive circuit layer 140 is formed on a side of the first dielectric layer 120 away from the carrier 110.

The first conductive wiring layer 140 may be formed by a semi-additive method. It can be understood that the first conductive circuit layer 140 can also be formed by other circuit fabrication methods commonly used in the industry.

The first conductive circuit layer 140 includes a central package region 141 and a peripheral package region 142. The central package area 141 includes a plurality of first contact pads 1411 that are densely distributed and have a small area. The peripheral package area 142 surrounds the central package area 141. The peripheral package area 142 is distributed with a sparsely distributed area. Larger Two contact pads 1421. The intersection of the central package region 141 and the peripheral package region 142 corresponds to the bump pattern 130.

In the fifth step, referring to FIG. 6, the second dielectric layer 150 is pressed on the side of the first conductive wiring layer 140.

In this step, the second dielectric layer 150 may also be formed by pressing a prepreg film. In this embodiment, the material of the second dielectric layer 150 is the same as the material of the first dielectric layer 120. The thickness of the second dielectric layer 150 may be greater than the thickness of the first dielectric layer 120.

In this embodiment, after the step, the hole 151 may be further formed in the second dielectric layer 150. The aperture 151 can be formed by laser ablation. The hole 151 penetrates the second dielectric layer 150 such that the second contact pad 1421 of the first conductive wiring layer 140 is exposed from the bottom of the hole 151.

In the sixth step, referring to FIG. 7 , a second conductive wiring layer 160 is formed on a side of the second dielectric layer 150 away from the first dielectric layer 120 .

In this step, the second conductive wiring layer 160 can also be formed in the same manner as the first conductive wiring layer 140.

In this embodiment, before or at the same time, the conductive material is formed in the hole 151 before the second conductive circuit layer 160 is formed, thereby forming the conductive hole 152, and the first conductive circuit layer 140 and the second conductive circuit layer 160 pass through the conductive hole. 152 is electrically conductive to each other.

In the seventh step, referring to FIG. 8, a solder resist layer 170 is formed on the surface of the second conductive wiring layer 160.

In this step, the solder resist layer 170 can be formed by printing a liquid solder resist ink. Said A plurality of openings 171 are formed in the solder resist layer 170, and the conductive lines in the portion of the second conductive wiring layer 160 are exposed from the openings 171 to form the electrical connection pads 161.

In the eighth step, please refer to FIG. 9 together to remove the carrier board 110.

In this embodiment, the carrier 110 is made of aluminum. In this step, the carrier 110 can be removed by chemical etching, so that the first dielectric layer 120 and the bump pattern 130 are exposed.

In a ninth step, referring to FIG. 10, a plurality of first openings 123 and a plurality of second openings 124 are formed in the first dielectric layer 120, and each of the first openings 123 corresponds to the first contact pads 1411. The first contact pads 1411 are exposed from the corresponding first openings 123. Each of the second openings 124 corresponds to a second contact pad 1421, and each of the second contact pads 1421 is exposed from the corresponding second opening 124.

The first opening 123 and the second opening 124 may be formed by laser ablation.

In the tenth step, referring to FIG. 11 and FIG. 12, a protective layer 180 is formed on the surface of the first contact pad 1411, the second contact pad 1421 and the electrical connection pad 161, and the protective layer 180 on the first contact pad 1411. The surface forms solder bumps 190, resulting in a circuit board 100.

The protective layer 180 may be an organic solder mask (OSP) or a nickel gold layer or a nickel palladium gold layer.

Referring to FIG. 11 and FIG. 12 , the technical solution further provides a circuit board 100 including a first dielectric layer 120 , a bump pattern 130 , a first conductive circuit layer 140 , a second dielectric layer 150 , and The second conductive circuit layer 160.

The first dielectric layer 120 and the second dielectric layer 150 are connected to each other. The first conductive line The via layer 140 is between the first dielectric layer 120 and the second dielectric layer 150.

The first conductive circuit layer 140 includes a central package region 141 and a peripheral package region 142. The central package area 141 includes a plurality of first contact pads 1411 that are densely distributed and have a small area. The peripheral package area 142 surrounds the central package area 141. The peripheral package area 142 is distributed with a sparsely distributed area. Larger second contact pad 1421.

The first dielectric layer 120 has a second surface 121 remote from the second dielectric layer 150. The bump pattern 130 is formed on one side of the second surface 121. The bump pattern 130 is made of the same material as the first dielectric layer 120 and is integrally formed. The bump pattern 130 corresponds to the intersection of the central package region 141 of the first conductive wiring layer 140 and the peripheral package region 142.

A plurality of first openings 123 and a plurality of second openings 124 are formed in the first dielectric layer 120. Each of the first openings 123 corresponds to the first contact pads 1411, and each of the first contact pads 1411 corresponds to The first opening 123 is exposed. Each of the second openings 124 corresponds to a second contact pad 1421, and each of the second contact pads 1421 is exposed from the corresponding second opening 124.

The second conductive circuit layer 160 is formed on a side of the second dielectric layer 150 away from the first conductive circuit layer 140. A solder resist layer 170 is formed on the surface of the second conductive wiring layer 160. A plurality of openings 171 are formed in the solder resist layer 170, and the conductive lines in the second conductive layer 160 are exposed from the openings 171 to form the electrical connection pads 161.

The circuit board 100 may further include a protective layer 180 formed on surfaces of the electrical connection pads 161, the first contact pads 1411, and the second contact pads 1421.

The surface of the protective layer 180 on the first contact pad 1411 is further formed with solder bumps 190 Used for soldering when packaging electronic components.

The circuit board and the manufacturing method thereof provided by the technical solution integrate the first dielectric layer and the bump pattern by a groove pattern in the carrier board and then press-bonding manner, so that the bump pattern is integrated with the first dielectric layer forming. Compared with the prior art, it is formed by forming two solder resist layers respectively, so that after the package, the two solder resist layers are separated from each other due to stress concentration at the boundary of the two solder resist layers.

It can be understood that the circuit board manufacturing method of the present technical solution can be applied to the fabrication of a high density interconnect circuit board (HDI).

However, the above description is only a preferred embodiment of the present invention, and it is not possible to limit the scope of the patent application of the present invention. Equivalent modifications or variations made by persons skilled in the art in light of the spirit of the invention are intended to be included within the scope of the following claims.

100‧‧‧ boards

120‧‧‧First dielectric layer

121‧‧‧ second surface

130‧‧‧Bump graphics

1411‧‧‧First contact pad

1421‧‧‧Second contact pad

150‧‧‧Second dielectric layer

160‧‧‧Second conductive circuit layer

170‧‧‧ solder mask

180‧‧‧protection layer

190‧‧‧ solder bumps

Claims (10)

A circuit board comprising a first dielectric layer, a first conductive circuit layer, a bump pattern and a second dielectric layer, wherein the first dielectric layer and the second dielectric layer are connected to each other, the first conductive circuit layer Embedded in the second dielectric layer and exposed from a contact surface of the second dielectric layer and the first dielectric layer, the first conductive circuit layer including a central package region and surrounding the center a peripheral package region of the package region, the bump pattern is formed on the first dielectric layer having a surface away from the second dielectric layer, the bump pattern being integrally formed with the first dielectric layer, the bump pattern The shape corresponds to the intersection of the central package area and the peripheral package area. The circuit board of claim 1, wherein the central package area has a plurality of first connection pads, the peripheral package area has a plurality of second connection pads, and the bump patterns are formed in the a dielectric layer having a surface away from the second dielectric layer, wherein the first dielectric layer is formed with a plurality of first openings and a plurality of second openings, each of the first openings corresponding to the first contact pads, each The second openings correspond to the second contact pads. The circuit board of claim 1, wherein the first dielectric layer, the bump pattern, and the second dielectric layer are made of the same material. The circuit board of claim 1, further comprising a second conductive circuit layer formed on a side of the second dielectric layer away from the first conductive circuit layer. The circuit board of claim 4, further comprising a conductive hole formed in the second dielectric layer, wherein the first conductive circuit layer and the second conductive circuit layer pass the conductive blind The holes are electrically conductive to each other. A circuit board manufacturing method comprising the steps of: providing a carrier board, the carrier board having a first surface; forming a groove pattern from the first surface of the carrier board into the carrier board; Forming a bump pattern in the groove pattern by pressing the insulating material, and simultaneously forming a first dielectric layer on the first surface of the carrier, the first dielectric layer and the bump pattern being integrally formed; The surface of the first dielectric layer forms a first conductive circuit layer, and the first conductive circuit layer includes a central package region and a peripheral package region, and a line intersection of the central package region and the peripheral package region and the bump pattern Correspondingly; pressing the second dielectric layer on one side of the first conductive circuit layer; and removing the carrier. The circuit board manufacturing method of claim 6, wherein the central package area has a plurality of first connection pads, and the peripheral package area has a plurality of second connection pads, wherein the carrier board is removed Thereafter, the method further includes forming a plurality of first openings and a plurality of second openings in the first dielectric layer, each of the first openings corresponding to the first contact pads, each of the second openings and the second contact pads Corresponding. The method of fabricating a circuit board according to claim 6, wherein after the second dielectric layer is pressed on the side of the first conductive circuit layer, and before the carrier is removed, the second dielectric layer is further included. A second conductive wiring layer is formed on a side away from the first dielectric layer. The method of fabricating a circuit board according to claim 8, wherein after forming the second conductive wiring layer, and before removing the carrier, further comprising forming a solder resist layer on a side of the second conductive wiring layer, An opening is formed in the solder resist layer, and part of the second conductive circuit layer is exposed from the opening to form an electrical connection pad. The method of manufacturing a circuit board according to claim 6, wherein the carrier is made of aluminum, the groove pattern is formed by laser ablation, and the carrier is removed by etching.