CN107241862B - Circuit board - Google Patents
Circuit board Download PDFInfo
- Publication number
- CN107241862B CN107241862B CN201710584291.7A CN201710584291A CN107241862B CN 107241862 B CN107241862 B CN 107241862B CN 201710584291 A CN201710584291 A CN 201710584291A CN 107241862 B CN107241862 B CN 107241862B
- Authority
- CN
- China
- Prior art keywords
- dielectric layer
- layer
- support plate
- circuit board
- conductive circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0011—Working of insulating substrates or insulating layers
- H05K3/0014—Shaping of the substrate, e.g. by moulding
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09009—Substrate related
- H05K2201/09045—Locally raised area or protrusion of insulating substrate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
A kind of circuit board, including the first dielectric layer, the first conductive circuit layer, bump pattern and the second dielectric layer, first dielectric layer and the second dielectric layer are connected with each other, first conductive circuit layer includes center packaging area and the surrounding package region around the center packaging area, the bump pattern, which is formed in the first dielectric layer, has the surface far from the second dielectric layer, the bump pattern and first dielectric layer are integrally formed, and the shape of the bump pattern is corresponding with the intersection of the center packaging area and surrounding package region.The present invention also provides a kind of production methods of circuit board.
Description
It is on 06 26th, 2013 that the application, which is application No. is the 2013102586889, applying date, invention and created name " electricity
The divisional application of the patent of the production method of road plate ".
Technical field
The present invention relates to circuit board making field more particularly to a kind of circuit boards with metal coupling.
Background technique
In the prior art, in order to save the volume of encapsulating structure.It usually requires in the circuit board top as encapsulating carrier plate
Encapsulate chip and circuit board.Wherein, the corresponding packaging area of chip usually requires to be arranged more intensive engagement pad, and and circuit
The area for the engagement pad that plate is packaged is usually larger, and is distributed more sparse.Also, during being packaged, usually
It needs then again to be packaged the package substrate for being packaged with chip and other circuit boards first by chip package in encapsulating carrier plate.
In the prior art, it usually needs make two layers of soldermask layer on the surface of encapsulating carrier plate, first layer soldermask layer is for defining support plate
On engagement pad, the second soldermask layer (Dam Ring) is formed on the first soldermask layer, and around chip package region, to encapsulate
Play the role of dykes and dams when chip.However, since the first soldermask layer and the second soldermask layer are respectively formed, after encapsulation, be easy by
The intersection of the first soldermask layer and the second soldermask layer is concentrated in stress, it is mutual so as to cause the first soldermask layer and the second soldermask layer
Separation.
Summary of the invention
Therefore, it is necessary to provide the production and its method of a kind of circuit board, it is able to solve the above problem.
A kind of circuit board, including the first dielectric layer, the first conductive circuit layer, bump pattern and the second dielectric layer, described
One dielectric layer and the second dielectric layer are connected with each other, and first conductive circuit layer includes center packaging area and the circular center
The surrounding package region of packaging area, the bump pattern are formed in the surface far from the second dielectric layer of the first dielectric layer, institute
It states bump pattern and first dielectric layer is integrally formed, the shape of the bump pattern and the center packaging area and periphery
The intersection of packaging area is corresponding.
A kind of circuit board manufacturing method, comprising steps of providing support plate, the support plate has first surface；From the support plate
First surface form groove pattern into the support plate；Convex block figure is formed in the groove pattern by pressing insulating materials
Shape, and the first dielectric layer is formed in the first surface of support plate simultaneously, first dielectric layer and the bump pattern are integrally formed；
Form the first conductive circuit layer on the surface of first dielectric layer, first conductive circuit layer include center packaging area with
Surrounding package region, the center packaging area are corresponding with the bump pattern with the intersection in surrounding package region；First
Conductive circuit layer side presses the second dielectric layer；And the removal support plate.
Compared with prior art, the circuit board and preparation method thereof that the technical program provides, by support plate inner groovy figure
Then shape is formed simultaneously the first dielectric layer and bump pattern by way of pressing, so that bump pattern and the first dielectric layer one
It is body formed.In compared with the prior art, successively formed by way of forming soldermask layer twice respectively, so as to avoid sealing
After dress, since stress concentrates on the intersection of two layers of soldermask layer, so that two layers of soldermask layer is separated from each other.
Detailed description of the invention
Fig. 1 is the diagrammatic cross-section for the support plate that the technical program embodiment provides.
Fig. 2 is that the diagrammatic cross-section after groove pattern is formed in the support plate of Fig. 1.
Fig. 3 is the top view of Fig. 2.
Fig. 4 is that the support plate surface of Fig. 2 presses the diagrammatic cross-section after the first dielectric layer.
Fig. 5 is that the first dielectric layer surface of Fig. 4 forms the diagrammatic cross-section after the first conductive circuit layer.
Fig. 6 is that the first conductive circuit layer side of Fig. 5 presses the diagrammatic cross-section after the second dielectric layer.
Fig. 7 is the diagrammatic cross-section after the second dielectric layer surface of Fig. 6 forms the second conductive circuit layer.
Fig. 8 is the diagrammatic cross-section after the second conducting wire layer surface of Fig. 7 forms soldermask layer.
Fig. 9 is the diagrammatic cross-section after Fig. 8 removal support plate.
Figure 10 is that the diagrammatic cross-section after the first opening and the second opening is formed in the first dielectric layer of Fig. 9.
Figure 11 is the diagrammatic cross-section of the circuit board of the technical program production.
Figure 12 is the top view of Figure 11.
Main element symbol description
The present invention that the following detailed description will be further explained with reference to the above drawings.
Specific embodiment
The circuit board manufacturing method that the technical program provides includes the following steps:
The first step, referring to Fig. 1, providing support plate 110.
The support plate 110 is to be made of metal material.In the present embodiment, support plate 110 is made of metallic aluminium.The load
Plate 110 has first surface 111, and the first surface 111 is plane.
Second step, please refer to figs. 2 and 3, and groove pattern 112 is formed in the support plate 110.
The groove pattern 112 can be formed by the way of laser ablation.The groove pattern 112 should be with electricity to be made
The sideline in the chip package region of road plate is corresponding, and in the present embodiment, the groove pattern 112 is generally shaped like square shape.
The groove pattern 112 is formed in the intermediate region of support plate 110.
Third step, referring to Fig. 4, the first surface 111 in the support plate 110 forms the first dielectric layer 120 and exists simultaneously
Bump pattern 130 is formed in groove pattern 112.
First dielectric layer 120 and bump pattern 130 can be formed by way of pressing semi-solid preparation film.It is described convex
Block graphics 130 is filled up completely in the groove pattern 112, and the first dielectric layer 120 covers entire first surface 111.Described
One dielectric layer 120 is integrally formed with bump pattern 130.The material of first dielectric layer 120 can be commonly used in the art exhausted
Edge material, such as polyimides.
First dielectric layer 120 has the second surface 121 adjacent with first surface 111, and the bump pattern 130 is convex
For second surface 121, the shape of the bump pattern 130 is complementary with groove pattern 112, also with the chip of circuit board to be made
The sideline of packaging area is corresponding, and in the present embodiment, the bump pattern 130 is generally shaped like square shape.
4th step, referring to Fig. 5, forming the first conductive circuit layer far from the side of support plate 110 in the first dielectric layer 120
140。
First conductive circuit layer 140 can be made of semi-additive process.It is understood that first conductor wire
Road floor 140 can also make to be formed using other circuit manufacturing methods commonly used in the trade.
First conductive circuit layer 140 includes center packaging area 141 and surrounding package region 142.The center envelope
Fill and area lesser first engagement pad 1411 more intensive including multiple distributions, the surrounding package region 142 in region 141
Around the center packaging area 141, distribution is distributed more sparse and area biggish second and connects in surrounding package region 142
Touch pad 1421.The center packaging area 141 is corresponding with bump pattern 130 with the intersection in surrounding package region 142.
5th step, referring to Fig. 6, pressing the second dielectric layer 150 in 140 side of the first conductive circuit layer.
In this step, the second dielectric layer 150 can also be formed by the way of pressing semi-solid preparation film.In the present embodiment,
The material of second dielectric layer 150 is identical as the material of the first dielectric layer 120.The thickness of second dielectric layer 150 can be greater than
The thickness of first dielectric layer 120.
In the present embodiment, after this step, the formation hole 151 in the second dielectric layer 150 can further include.It can be with
Hole 151 is formed by the way of laser ablation.Second dielectric layer 150 is run through in hole 151, so that the first conductive circuit layer 140
The second engagement pad 1421 from the bottom in hole 151 expose.
6th step, referring to Fig. 7, forming the second conductor wire far from the side of the first dielectric layer 120 in the second dielectric layer 150
Road floor 160.
This step equally can form the second conductive circuit layer using the identical method of the first conductive circuit layer 140 is formed
160。
In the present embodiment, before or while forming the second conductive circuit layer 160, conduction material also is formed in hole 151
Material, to form conductive hole 152, first conductive circuit layer 140 passes through 152 phase of conductive hole with the second conductive circuit layer 160
Transconductance is logical.
7th step, referring to Fig. 8, forming soldermask layer 170 on the surface of the second conductive circuit layer 160.
This step can form soldermask layer 170 by the way of printing liquid anti-solder ink.It is formed in the soldermask layer 170
There are multiple apertures 171, the conducting wire in the second conductive circuit layer of part 160 is exposed from aperture 171, forms electrical connection pad 161.
8th step removes support plate 110 also referring to Fig. 9.
In the present embodiment, support plate 110, which is adopted, to be formed from aluminium, this step can be removed support plate 110 by the way of chemical etching
It removes, so that the first dielectric layer 120 and bump pattern 130 are exposed.
9th step, referring to Fig. 10, forming multiple first openings 123 and multiple second in first dielectric layer 120
Opening 124, each first opening is 123 corresponding with the first engagement pad 1411, and each first engagement pad 1411 is from corresponding first
Opening 123 is exposed.Each second opening is 124 corresponding with second engagement pad 1421, and each second engagement pad 1421 is from right
The second opening 124 answered is exposed.
First opening 123 and the second opening 124 can be formed by the way of laser ablation.
Tenth step please refers to Figure 11 and Figure 12, in first engagement pad 1411, the second engagement pad 1421 and electrical connection pad
161 surface forms protective layer 180, and the surface of the protective layer 180 in the first engagement pad 1411 forms solder projection 190,
To obtain circuit board 100.
The protective layer 180 can weld film (OSP) for organic guarantor, or nickel-gold layer or NiPdAu layer.
Figure 11 and Figure 12 is please referred to, the technical program also provides a kind of circuit board 100, and the circuit board 100 includes first
Dielectric layer 120, bump pattern 130, the first conductive circuit layer 140, the second dielectric layer 150 and the second conductive circuit layer 160.
First dielectric layer 120 and the second dielectric layer 150 are connected with each other.First conductive circuit layer 140 is located at the
Between one dielectric layer 120 and the second dielectric layer 150.
First conductive circuit layer 140 includes center packaging area 141 and surrounding package region 142.The center envelope
Fill and area lesser first engagement pad 1411 more intensive including multiple distributions, the surrounding package region 142 in region 141
Around the center packaging area 141, distribution is distributed more sparse and area biggish second and connects in surrounding package region 142
Touch pad 1421.
First dielectric layer 120 has the second surface 121 far from the second dielectric layer 150.130 shape of bump pattern
121 side of second surface described in Cheng Yu.The bump pattern 130 is made with the first dielectric layer 120 of identical material, and one
It is body formed.The friendship of bump pattern 130 and first conductive circuit layer 140 center packaging area 141 and surrounding package region 142
Line is corresponding.
Multiple first openings 123 and multiple second openings 124 are formed in first dielectric layer 120, each first opens
Mouth 123 is corresponding with the first engagement pad 1411, and each first engagement pad 1411 is exposed from corresponding first opening 123.Each
Two openings 124 are corresponding with second engagement pad 1421, and each second engagement pad 1421 is revealed from corresponding second opening 124
Out.
Second conductive circuit layer 160 is formed in side of second dielectric layer 150 far from the first conductive circuit layer 140.
Second conductive circuit layer, 160 surface is formed with soldermask layer 170.Multiple apertures 171, portion are formed in the soldermask layer 170
The conducting wire divided in the second conductive circuit layer 160 is exposed from aperture 171, forms electrical connection pad 161.
The circuit board 100 can also include protective layer 180, and the protective layer 180 is formed in electrical connection pad 161, first
The surface of engagement pad 1411 and the second engagement pad 1421.
The surface of protective layer 180 in first engagement pad 1411 is also formed with solder projection 190, for encapsulating electronics
It is welded when element.
The circuit board and preparation method thereof that the technical program provides, by then passing through pressing in support plate inner groovy figure
Mode be formed simultaneously the first dielectric layer and bump pattern so that bump pattern and the first dielectric layer are integrally formed.Compared to existing
Have in technology, is successively formed by way of forming soldermask layer twice respectively, so as to avoid after encapsulation, due to stress
The intersection of two layers of soldermask layer is concentrated on, so that two layers of soldermask layer is separated from each other.
It is understood that the circuit board manufacturing method of the technical program can be applied to high-density interconnected circuit board
(HDI) production.
It is understood that for those of ordinary skill in the art, can do in accordance with the technical idea of the present invention
Various other changes and modifications out, and all these changes and deformation all should belong to the protection model of the claims in the present invention
It encloses.
Claims (9)
1. a kind of circuit board, including the first dielectric layer, the first conductive circuit layer, bump pattern and the second dielectric layer, described first
Dielectric layer and the second dielectric layer are connected with each other, and first conductive circuit layer includes center packaging area and seals around the center
The surrounding package region in region is filled, the bump pattern is formed in the surface far from the second dielectric layer of the first dielectric layer, described
Bump pattern and first dielectric layer are integrally formed, and the shape of the bump pattern is sealed with the center packaging area and outside
The intersection for filling region is corresponding；The circuit board is made with the following method:
Support plate is provided, the support plate has first surface；
Groove pattern is formed into the support plate from the first surface of the support plate；
Bump pattern is formed in the groove pattern by pressing insulating materials, and forms the in the first surface of support plate simultaneously
One dielectric layer, first dielectric layer and the bump pattern are integrally formed；
The first conductive circuit layer is formed on the surface of first dielectric layer, first conductive circuit layer includes center encapsulation region
Domain and surrounding package region, the center packaging area are corresponding with the bump pattern with the intersection in surrounding package region；
The second dielectric layer is pressed in the first conductive circuit layer side；And
Remove the support plate.
2. circuit board as described in claim 1, which is characterized in that have multiple first contacts in the center packaging area
It pads, there are multiple second engagement pads in the surrounding package region, further include being situated between described first after removing the support plate
Multiple first openings and multiple second openings, each first opening, Mei Ge corresponding with the first engagement pad are formed in electric layer
Two openings are corresponding with the second engagement pad.
3. circuit board as described in claim 1, which is characterized in that the first conductive circuit layer side press the second dielectric layer it
It afterwards, further include forming the second conductor wire far from the side of the first dielectric layer in the second dielectric layer and before removing the support plate
Road floor.
4. circuit board as claimed in claim 3, which is characterized in that after forming the second conductive circuit layer, and in removal institute
Before stating support plate, further includes forming soldermask layer in the second conductive circuit layer side, be formed with aperture, part institute in the soldermask layer
It states the second conductive circuit layer to expose from the aperture, forms electrical connection pad.
5. circuit board as described in claim 1, which is characterized in that the support plate, which is adopted, to be formed from aluminium, and the groove pattern uses
Laser ablation is formed, and the support plate is removed by the way of etching.
6. circuit board as described in claim 1, which is characterized in that have multiple first connections in the center packaging area
It pads, there are multiple second connection gaskets in the surrounding package region, the bump pattern is formed in the first dielectric layer with separate
The surface of second dielectric layer is formed with multiple first openings and multiple second openings in first dielectric layer, and each first opens
Mouth is corresponding with the first engagement pad, and each second opening is corresponding with the second engagement pad.
7. circuit board as described in claim 1, which is characterized in that first dielectric layer, bump pattern and the second dielectric layer
Material it is identical.
8. circuit board as described in claim 1, which is characterized in that it further include the second conductive circuit layer, second conductor wire
Road floor is formed in side of second dielectric layer far from the first conductive circuit layer.
9. circuit board as claimed in claim 4, which is characterized in that further include conductive hole, the conductive hole is formed in second Jie
In electric layer, first conductive circuit layer is mutually conducted with the second conductive circuit layer by the conductive hole.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710584291.7A CN107241862B (en) | 2013-06-26 | 2013-06-26 | Circuit board |
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710584291.7A CN107241862B (en) | 2013-06-26 | 2013-06-26 | Circuit board |
| CN201310258688.9A CN104254190B (en) | 2013-06-26 | 2013-06-26 | The preparation method of circuit board |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310258688.9A Division CN104254190B (en) | 2013-06-26 | 2013-06-26 | The preparation method of circuit board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN107241862A CN107241862A (en) | 2017-10-10 |
| CN107241862B true CN107241862B (en) | 2019-05-03 |
Family
ID=52188608
Family Applications (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710584291.7A Expired - Fee Related CN107241862B (en) | 2013-06-26 | 2013-06-26 | Circuit board |
| CN201310258688.9A Active CN104254190B (en) | 2013-06-26 | 2013-06-26 | The preparation method of circuit board |
Family Applications After (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310258688.9A Active CN104254190B (en) | 2013-06-26 | 2013-06-26 | The preparation method of circuit board |
Country Status (2)
| Country | Link |
|---|---|
| CN (2) | CN107241862B (en) |
| TW (1) | TWI530240B (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI624011B (en) * | 2015-06-29 | 2018-05-11 | 矽品精密工業股份有限公司 | Package structure and the manufacture thereof |
| CN106356355B (en) * | 2015-07-15 | 2020-06-26 | 恒劲科技股份有限公司 | Substrate structure and manufacturing method thereof |
| TWI679926B (en) * | 2019-01-09 | 2019-12-11 | 欣興電子股份有限公司 | Substrate structure and manufacturing method thereof |
| CN115996513A (en) * | 2021-10-19 | 2023-04-21 | 礼鼎半导体科技秦皇岛有限公司 | Packaged chip, packaging structure, circuit board and manufacturing method thereof |
| TWI845178B (en) * | 2023-03-01 | 2024-06-11 | 南亞電路板股份有限公司 | Circuit board structure and method for forming the same |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5413964A (en) * | 1991-06-24 | 1995-05-09 | Digital Equipment Corporation | Photo-definable template for semiconductor chip alignment |
| JPH1012671A (en) * | 1996-06-26 | 1998-01-16 | Ngk Spark Plug Co Ltd | Wiring board, manufacture thereof, wiring board mounted with board, and manufacture thereof |
| TW200515616A (en) * | 2003-10-21 | 2005-05-01 | Advanced Semiconductor Eng | Wafer structure for preventing contamination of bond pads during SMT process and process for the same |
| TWM450822U (en) * | 2012-10-08 | 2013-04-11 | Unimicron Technology Corp | Package substrate |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5343616B1 (en) * | 1992-02-14 | 1998-12-29 | Rock Ltd | Method of making high density self-aligning conductive networks and contact clusters |
| CN102281725B (en) * | 2010-06-10 | 2013-03-20 | 富葵精密组件(深圳)有限公司 | Manufacturing method for circuit board |
| TWI505765B (en) * | 2010-12-14 | 2015-10-21 | Unimicron Technology Corp | Wiring board and method for fabricating the same |
| TWI470759B (en) * | 2011-11-01 | 2015-01-21 | Unimicron Technology Corp | Package substrate and fabrication method thereof |
-
2013
- 2013-06-26 CN CN201710584291.7A patent/CN107241862B/en not_active Expired - Fee Related
- 2013-06-26 CN CN201310258688.9A patent/CN104254190B/en active Active
- 2013-06-28 TW TW102123339A patent/TWI530240B/en active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5413964A (en) * | 1991-06-24 | 1995-05-09 | Digital Equipment Corporation | Photo-definable template for semiconductor chip alignment |
| JPH1012671A (en) * | 1996-06-26 | 1998-01-16 | Ngk Spark Plug Co Ltd | Wiring board, manufacture thereof, wiring board mounted with board, and manufacture thereof |
| TW200515616A (en) * | 2003-10-21 | 2005-05-01 | Advanced Semiconductor Eng | Wafer structure for preventing contamination of bond pads during SMT process and process for the same |
| TWM450822U (en) * | 2012-10-08 | 2013-04-11 | Unimicron Technology Corp | Package substrate |
Also Published As
| Publication number | Publication date |
|---|---|
| CN104254190A (en) | 2014-12-31 |
| TW201507564A (en) | 2015-02-16 |
| CN104254190B (en) | 2017-12-01 |
| CN107241862A (en) | 2017-10-10 |
| TWI530240B (en) | 2016-04-11 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN105493269B (en) | Ultra micro spacing PoP centreless encapsulates | |
| CN107241862B (en) | Circuit board | |
| CN103904050B (en) | Package substrate, manufacturing method of package substrate and packaging structure | |
| US7579676B2 (en) | Leadless leadframe implemented in a leadframe-based BGA package | |
| TW201011872A (en) | Package substrate having semiconductor component embedded therein and fabrication method thereof | |
| CN102339809B (en) | QFN (quad flat non-lead) package with multiple circles of pins and manufacturing method thereof | |
| JP2012253190A (en) | Semiconductor package and assembling method of the same | |
| CN107978569A (en) | Chip-packaging structure and its manufacture method | |
| TWI497666B (en) | Surface mount technology for advanced quad flat no-lead package and stencil used therewith | |
| CN105489565A (en) | Package structure of embedded device and method for fabricating the same | |
| JP2009194079A (en) | Wiring substrate for use in semiconductor apparatus, method for fabricating the same, and semiconductor apparatus using the same | |
| CN106847705B (en) | By the method and chip-packaging structure of chip package PCB | |
| CN105762127B (en) | Package substrate, semiconductor package and fabrication method thereof | |
| CN106298729B (en) | packaging structure and manufacturing method thereof | |
| CN104254202B (en) | Circuit board with interior embedded electronic component and preparation method thereof | |
| JP2005340448A (en) | Semiconductor device, its manufacturing method, circuit board, and electronic apparatus | |
| JP3972209B2 (en) | Semiconductor device and manufacturing method thereof, circuit board, and electronic apparatus | |
| CN101944520B (en) | Semiconductor packaging structure and semiconductor packaging process | |
| CN110391143A (en) | Semiconductor package and its packaging method | |
| CN104576402B (en) | Encapsulating carrier plate and preparation method thereof | |
| CN202940226U (en) | Package substrate | |
| JP2009099816A (en) | Semiconductor device, method of manufacturing the same and mounting method of semiconductor device | |
| TWI595616B (en) | Chip package and method for forming the same | |
| CN203787410U (en) | High radiating chip embedded electromagnetic shielding packaging structure | |
| CN102931165B (en) | The manufacture method of base plate for packaging |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| TA01 | Transfer of patent application right |
Effective date of registration: 20190409 Address after: 437199 Xianning Economic Development Zone, Hubei Province Applicant after: Hubei Yihong Precision Manufacturing Co., Ltd. Address before: 524299 No. 054 Xihu Avenue, Leicheng Town, Leizhou City, Zhanjiang City, Guangdong Province Applicant before: Gao Yun |
|
| TA01 | Transfer of patent application right | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20190503 Termination date: 20190626 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |