TWI470759B - Package substrate and fabrication method thereof - Google Patents
Package substrate and fabrication method thereof Download PDFInfo
- Publication number
- TWI470759B TWI470759B TW100139864A TW100139864A TWI470759B TW I470759 B TWI470759 B TW I470759B TW 100139864 A TW100139864 A TW 100139864A TW 100139864 A TW100139864 A TW 100139864A TW I470759 B TWI470759 B TW I470759B
- Authority
- TW
- Taiwan
- Prior art keywords
- layer
- electrical contact
- contact pads
- opening
- metal
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
Description
本發明係有關一種封裝基板及其製法,尤指一種具有金屬柱之封裝基板及其製法。 The invention relates to a package substrate and a preparation method thereof, in particular to a package substrate with a metal column and a preparation method thereof.
隨著電子產品的微型化發展趨勢,印刷電路板(PCB)表面可供設置半導體封裝結構的面積越來越小,因此遂發展出一種半導體封裝結構之立體堆疊技術,其係於一半導體封裝結構上形成有金屬凸塊或金屬柱,並將另一半導體封裝結構疊置於該金屬凸塊或金屬柱上,而成為一層疊封裝件(package on package,簡稱POP),以符合小型表面接合面積與高密度元件設置之要求。 With the development trend of miniaturization of electronic products, the area of the printed circuit board (PCB) surface for mounting the semiconductor package structure is getting smaller and smaller, so a three-dimensional stacking technology of the semiconductor package structure is developed, which is attached to a semiconductor package structure. Metal bumps or metal pillars are formed thereon, and another semiconductor package structure is stacked on the metal bumps or metal pillars to form a package on package (POP) to conform to a small surface joint area. Requirements for setting with high density components.
請參閱第1A至1J圖,係為習知用於層疊封裝件之封裝基板及其製法之剖視圖。 Please refer to FIGS. 1A to 1J, which are cross-sectional views of a conventional package substrate for a package and a method of manufacturing the same.
如第1A圖所示,提供一基板本體10,其具有相對之第一表面10a與第二表面10b,該第一表面10a具有複數第一電性接觸墊111與複數第二電性接觸墊112,該基板本體10之第二表面10b具有複數第三電性接觸墊113,於該第一表面10a、第一電性接觸墊111與第二電性電性接觸墊112上形成有第一絕緣保護層12a,該第一絕緣保護層12a具有分別對應外露各該第一電性接觸墊111與第二電性接觸墊112的第一開孔121與第二開孔122,於該第二表面10b與第三電性接觸墊113上形成有第二絕緣保護層12b,該第二絕緣保護層12b具有對應外露各該第三電 性接觸墊113的第三開孔123。 As shown in FIG. 1A, a substrate body 10 is provided having an opposite first surface 10a and a second surface 10b. The first surface 10a has a plurality of first electrical contact pads 111 and a plurality of second electrical contact pads 112. The second surface 10b of the substrate body 10 has a plurality of third electrical contact pads 113. The first surface 10a, the first electrical contact pads 111 and the second electrical contact pads 112 are formed with a first insulation. The first insulating layer 12a has a first opening 121 and a second opening 122 respectively corresponding to the first electrical contact pads 111 and the second electrical contact pads 112, respectively, on the second surface A second insulating protective layer 12b is formed on the 10b and the third electrical contact pads 113, and the second insulating protective layer 12b has a corresponding corresponding exposed third electrical The third opening 123 of the contact pad 113.
如第1B圖所示,於該第一絕緣保護層12a、第一電性接觸墊111與第二電性接觸墊112上形成第一導電層13a,並於該第二絕緣保護層12b與第三電性接觸墊113上形成第二導電層13b。 As shown in FIG. 1B, a first conductive layer 13a is formed on the first insulating protective layer 12a, the first electrical contact pad 111 and the second electrical contact pad 112, and the second insulating protective layer 12b and the second insulating protective layer 12b A second conductive layer 13b is formed on the three-electrode contact pad 113.
如第1C圖所示,於該第一導電層13a上形成第一阻層14a,且該第一阻層14a具有對應分別外露各該第一開孔121與第二開孔122的第一阻層開孔141與第二阻層開孔142,並於該第二導電層13b上形成第三阻層14b。 As shown in FIG. 1C, a first resist layer 14a is formed on the first conductive layer 13a, and the first resist layer 14a has a first resistor corresponding to each of the first opening 121 and the second opening 122, respectively. The layer opening 141 and the second resist layer opening 142 form a third resist layer 14b on the second conductive layer 13b.
如第1D圖所示,於各該第一阻層開孔141與第二阻層開孔142中分別電鍍形成第一金屬凸塊151與第二金屬凸塊152。 As shown in FIG. 1D, first metal bumps 151 and second metal bumps 152 are respectively plated in each of the first resistive layer opening 141 and the second resistive layer opening 142.
如第1E圖所示,於該第一阻層14a、第一金屬凸塊151與第二金屬凸塊152上形成第二阻層17,且該第二阻層17具有外露該等第二金屬凸塊152的第三阻層開孔170。 As shown in FIG. 1E, a second resist layer 17 is formed on the first resistive layer 14a, the first metal bump 151 and the second metal bump 152, and the second resist layer 17 has the second metal exposed. The third resistive opening 170 of the bump 152.
如第1F圖所示,於各該第二金屬凸塊152上形成焊料層16。 As shown in FIG. 1F, a solder layer 16 is formed on each of the second metal bumps 152.
如第1G圖所示,移除該第二阻層17、第一阻層14a與第三阻層14b。 As shown in FIG. 1G, the second resist layer 17, the first resist layer 14a and the third resist layer 14b are removed.
如第1H圖所示,於該第一導電層13a與焊料層16上形成第四阻層19a,且該第四阻層19a具有複數對應各該第一金屬凸塊151的第四阻層開孔190,並於該第二導電層13b上形成第五阻層19b。 As shown in FIG. 1H, a fourth resist layer 19a is formed on the first conductive layer 13a and the solder layer 16, and the fourth resist layer 19a has a plurality of fourth resist layers corresponding to the first metal bumps 151. The hole 190 and the fifth resist layer 19b are formed on the second conductive layer 13b.
如第1I圖所示,於各該第一金屬凸塊151上形成金屬柱18。 As shown in FIG. 1I, metal posts 18 are formed on each of the first metal bumps 151.
如第1J圖所示,移除該第四阻層19a及其所覆蓋的第一導電層13a,並移除該第五阻層19b及其所覆蓋的第二導電層13b。 As shown in FIG. 1J, the fourth resist layer 19a and the first conductive layer 13a covered thereby are removed, and the fifth resist layer 19b and the second conductive layer 13b covered thereby are removed.
惟,上述習知之封裝基板的製法係經過三次的阻層圖案化製程與兩次的阻層移除製程,整體製程流程較為複雜、冗長且耗時,使得整體產品的成本不易降低,而最終容易導致產品失去競爭力。 However, the conventional method for manufacturing a package substrate is three times of a resist layer patterning process and two resist layer removal processes, and the overall process flow is complicated, lengthy, and time consuming, so that the cost of the overall product is not easily reduced, and ultimately it is easy. Lead to loss of competitiveness.
因此,如何提出一種封裝基板及其製法,以避免習知技術的製作流程過於繁雜而效率低落,導致產品成本過高等問題,實已成為目前亟欲解決的課題。 Therefore, how to propose a package substrate and a manufacturing method thereof to avoid the problem that the manufacturing process of the prior art is too complicated and inefficient, resulting in an excessively high product cost has become a problem to be solved at present.
鑑於上述習知技術之製程較為繁複的缺失,本發明揭露一種封裝基板,係包括:基板本體,係具有相對之第一表面與第二表面,且該第一表面具有複數第一電性接觸墊與複數第二電性接觸墊;第一絕緣保護層,係形成於該第一表面、第一電性接觸墊與第二電性電性接觸墊上,該第一絕緣保護層具有複數分別對應外露各該第一電性接觸墊與第二電性接觸墊的第一開孔與第二開孔;導電層,係形成於各該第一電性接觸墊、第二電性接觸墊及其周緣的第一絕緣保護層上;第一金屬凸塊與第二金屬凸塊,係分別對應形成於各該第一電性接觸墊與第二電性接觸墊上方的導電層上;焊料層,係形成於該第二金屬凸塊上;以及金 屬柱,係形成於該第一金屬凸塊上,且該金屬柱的寬度係不同於該第一金屬凸塊的寬度。 In view of the cumbersome process of the above-mentioned prior art, the present invention discloses a package substrate comprising: a substrate body having opposite first and second surfaces, and the first surface having a plurality of first electrical contact pads And a plurality of second electrical contact pads; the first insulating protective layer is formed on the first surface, the first electrical contact pad and the second electrical contact pad, and the first insulating protective layer has a plurality of corresponding corresponding exposed a first opening and a second opening of each of the first electrical contact pads and the second electrical contact pads; and a conductive layer formed on each of the first electrical contact pads, the second electrical contact pads, and the periphery thereof The first metal bump and the second metal bump are respectively formed on the conductive layer above the first electrical contact pad and the second electrical contact pad; the solder layer is Formed on the second metal bump; and gold The pillars are formed on the first metal bump, and the width of the metal pillar is different from the width of the first metal bump.
本發明揭露另一種封裝基板,係包括:基板本體,係具有相對之第一表面與第二表面,該第一表面具有複數第一電性接觸墊與複數第二電性接觸墊;第一絕緣保護層,係形成於該第一表面、第一電性接觸墊與第二電性電性接觸墊上,該第一絕緣保護層具有分別對應外露各該第一電性接觸墊與第二電性接觸墊的第一開孔與第二開孔;導電層,係形成於各該第一電性接觸墊、第二電性電性接觸墊及其周緣的第一絕緣保護層上;金屬凸塊,係對應形成於各該第二電性接觸墊上方的導電層上;焊料層,係形成於該金屬凸塊上;以及金屬柱,係對應形成於各該第一電性接觸墊上方的導電層上。 The present invention discloses a package substrate, comprising: a substrate body having opposite first and second surfaces, the first surface having a plurality of first electrical contact pads and a plurality of second electrical contact pads; a protective layer is formed on the first surface, the first electrical contact pad and the second electrical contact pad, the first insulating protective layer respectively corresponding to the exposed first electrical contact pads and the second electrical a first opening and a second opening of the contact pad; a conductive layer formed on each of the first electrical contact pad, the second electrical contact pad and the first insulating protective layer on the periphery thereof; the metal bump Corresponding to the conductive layer formed on each of the second electrical contact pads; a solder layer formed on the metal bump; and a metal pillar corresponding to the conductive layer formed on each of the first electrical contact pads On the floor.
本發明復揭露一種封裝基板之製法,係包括:提供一基板本體,其具有相對之第一表面與第二表面,該第一表面具有複數第一電性接觸墊與複數第二電性接觸墊,於該第一表面、第一電性接觸墊與第二電性電性接觸墊上形成有第一絕緣保護層,該第一絕緣保護層具有分別對應外露各該第一電性接觸墊與第二電性接觸墊的第一開孔與第二開孔;於該第一絕緣保護層、第一電性接觸墊與第二電性接觸墊上形成導電層;於該導電層上形成第一阻層,且該第一阻層具有對應分別外露各該第一開孔與第二開孔的第一阻層開孔與第二阻層開孔;於各該第一阻層開孔與第二阻層開孔中分別電鍍形成第一金屬凸塊與第二金屬凸塊; 於該第一金屬凸塊與第二金屬凸塊上形成焊料層;於該第一阻層與焊料層上形成第二阻層,該第二阻層具有對應該第一金屬凸塊的第三阻層開孔;移除該第一金屬凸塊上的焊料層;於各該第一金屬凸塊上形成金屬柱;以及移除該第二阻層、第一阻層及其所覆蓋的導電層。 The invention discloses a method for manufacturing a package substrate, comprising: providing a substrate body having opposite first and second surfaces, the first surface having a plurality of first electrical contact pads and a plurality of second electrical contact pads Forming, on the first surface, the first electrical contact pad and the second electrical contact pad, a first insulating protective layer, wherein the first insulating protective layer has a corresponding corresponding first exposed first electrical contact pad and a first opening and a second opening of the second electrical contact pad; forming a conductive layer on the first insulating protective layer, the first electrical contact pad and the second electrical contact pad; forming a first resistance on the conductive layer a first resist layer having a first resistive opening and a second resistive opening respectively corresponding to each of the first opening and the second opening; and the first resistive opening and the second Forming a first metal bump and a second metal bump respectively in the opening of the resist layer; Forming a solder layer on the first metal bump and the second metal bump; forming a second resist layer on the first resist layer and the solder layer, the second resist layer having a third corresponding to the first metal bump a barrier layer opening; removing a solder layer on the first metal bump; forming a metal pillar on each of the first metal bumps; and removing the second resist layer, the first resist layer, and the conductive layer covered thereby Floor.
本發明復揭露另一種封裝基板之製法,係包括:提供一基板本體,其具有相對之第一表面與第二表面,該第一表面具有複數第一電性接觸墊與複數第二電性接觸墊,於該第一表面、第一電性接觸墊與第二電性電性接觸墊上形成有第一絕緣保護層,該第一絕緣保護層具有分別對應外露各該第一電性接觸墊與第二電性接觸墊的第一開孔與第二開孔;於該第一絕緣保護層、第一電性接觸墊與第二電性接觸墊上形成導電層;於該導電層上形成第一阻層,且該第一阻層具有對應外露各該第二開孔的第一阻層開孔;於各該第一阻層開孔中的導電層上電鍍形成金屬凸塊;於該金屬凸塊上形成焊料層;移除該第一阻層;於該導電層、金屬凸塊與焊料層上形成第二阻層,該第二阻層具有對應該第一開孔的第二阻層開孔;於各該第二阻層開孔中的導電層上形成金屬柱;以及移除該第二阻層及其所覆蓋的導電層。 The invention further discloses a method for fabricating another package substrate, comprising: providing a substrate body having opposite first and second surfaces, the first surface having a plurality of first electrical contact pads and a plurality of second electrical contacts a first insulating protective layer is formed on the first surface, the first electrical contact pad and the second electrical contact pad, and the first insulating protective layer has a corresponding corresponding first electrical contact pad and a first opening and a second opening of the second electrical contact pad; forming a conductive layer on the first insulating protective layer, the first electrical contact pad and the second electrical contact pad; forming a first layer on the conductive layer a first resist layer having a first resistive opening corresponding to each of the second openings; electroplating on the conductive layer in each of the first resistive openings to form a metal bump; Forming a solder layer on the block; removing the first resist layer; forming a second resist layer on the conductive layer, the metal bump and the solder layer, the second resist layer having a second resist layer corresponding to the first opening a hole; a metal pillar is formed on the conductive layer in each of the openings of the second resist layer; And removing the second resist layer and the conductive layer covered.
由上可知,因為本發明係以較少之阻層圖案化製程與阻層移除製程來於封裝基板上形成金屬凸塊與金屬柱,所以可縮短整體製程步驟與時間,進而有利於成本的降低。 As can be seen from the above, since the present invention forms metal bumps and metal pillars on the package substrate with less resist patterning process and barrier removal process, the overall process steps and time can be shortened, thereby facilitating cost. reduce.
以下藉由特定的具體實施例說明本發明之實施方式,熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。 The other embodiments of the present invention will be readily understood by those skilled in the art from this disclosure.
須知,本說明書所附圖式所繪示之結構、比例、大小等,均僅用以配合說明書所揭示之內容,以供熟悉此技藝之人士之瞭解與閱讀,並非用以限定本發明可實施之限定條件,故不具技術上之實質意義,任何結構之修飾、比例關係之改變或大小之調整,在不影響本發明所能產生之功效及所能達成之目的下,均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時,本說明書中所引用之如「上」、「周緣」及「上方」等之用語,亦僅為便於敘述之明瞭,而非用以限定本發明可實施之範圍,其相對關係之改變或調整,在無實質變更技術內容下,當亦視為本發明可實施之範疇。 It is to be understood that the structure, the proportions, the size, and the like of the present invention are intended to be used in conjunction with the disclosure of the specification, and are not intended to limit the invention. The conditions are limited, so it is not technically meaningful. Any modification of the structure, change of the proportional relationship or adjustment of the size should remain in this book without affecting the effects and the objectives that can be achieved by the present invention. The technical content disclosed in the invention can be covered. In the meantime, the terms "upper", "peripheral" and "above" as used in the specification are merely for convenience of description, and are not intended to limit the scope of the invention, and the relative relationship may be changed or Adjustments, where there is no material change, are considered to be within the scope of the invention.
請參閱第2A至2I圖,係本發明之封裝基板及其製法的第一實施例的剖視圖,其中,第2F’至2I’圖與第2F”至2I”圖係為第2F至2I圖的不同實施態樣。 2A to 2I are cross-sectional views showing a first embodiment of a package substrate and a method of manufacturing the same according to the present invention, wherein the 2F' to 2I' and the 2F' to 2I' drawings are 2F to 2I. Different implementations.
如第2A圖所示,提供一基板本體20,其具有相對之第一表面20a與第二表面20b,該第一表面20a具有複數第一電性接觸墊211與複數第二電性接觸墊212,該基板本體20之第二表面20b具有複數第三電性接觸墊213,於該第一表面20a、第一電性接觸墊211與第二電性電性接觸墊212上形成有第一絕緣保護層22a,該第一絕緣保護 層22a具有分別對應外露各該第一電性接觸墊211與第二電性接觸墊212的第一開孔221與第二開孔222,於該第二表面20b與第三電性接觸墊213上形成有第二絕緣保護層22b,該第二絕緣保護層22b具有對應外露各該第三電性接觸墊213的第三開孔223,其中,該基板本體20可為核心板、有核心之多層板、無核心之單層板或無核心之多層板。 As shown in FIG. 2A, a substrate body 20 is provided having an opposite first surface 20a and a second surface 20b. The first surface 20a has a plurality of first electrical contact pads 211 and a plurality of second electrical contact pads 212. The second surface 20b of the substrate body 20 has a plurality of third electrical contact pads 213, and a first insulation is formed on the first surface 20a, the first electrical contact pads 211 and the second electrical electrical contact pads 212. Protective layer 22a, the first insulation protection The layer 22a has a first opening 221 and a second opening 222 respectively corresponding to the first electrical contact pads 211 and the second electrical contact pads 212, and the second surface 20b and the third electrical contact pads 213. The second insulating protective layer 22b has a third opening 223 corresponding to each of the third electrical contact pads 213. The substrate body 20 can be a core board and has a core. Multilayer boards, coreless single layer boards or coreless multi-layer boards.
如第2B圖所示,於該第一絕緣保護層22a、第一電性接觸墊211與第二電性接觸墊212上形成第一導電層23a,並於該第二絕緣保護層22b與第三電性接觸墊213上形成第二導電層23b。 As shown in FIG. 2B, a first conductive layer 23a is formed on the first insulating protective layer 22a, the first electrical contact pad 211 and the second electrical contact pad 212, and the second insulating protective layer 22b and the second insulating protective layer 22b A second conductive layer 23b is formed on the three-electrode contact pad 213.
如第2C圖所示,於該第一導電層23a上形成第一阻層24a,且該第一阻層24a具有對應分別外露各該第一開孔221與第二開孔222的第一阻層開孔241與第二阻層開孔242,並於該第二導電層23b上形成第三阻層24b。 As shown in FIG. 2C, a first resist layer 24a is formed on the first conductive layer 23a, and the first resistive layer 24a has a first resistance corresponding to each of the first opening 221 and the second opening 222, respectively. The layer opening 241 and the second resist layer opening 242 form a third resist layer 24b on the second conductive layer 23b.
如第2D圖所示,於各該第一阻層開孔241與第二阻層開孔242中分別電鍍形成第一金屬凸塊251與第二金屬凸塊252,且該第一金屬凸塊251與第二金屬凸塊252之材質可為銅。 As shown in FIG. 2D, a first metal bump 251 and a second metal bump 252 are respectively plated in each of the first resistive layer opening 241 and the second resistive layer opening 242, and the first metal bump is formed. The material of the 251 and the second metal bumps 252 may be copper.
如第2E圖所示,於該第一金屬凸塊251與第二金屬凸塊252上形成焊料層26。 As shown in FIG. 2E, a solder layer 26 is formed on the first metal bump 251 and the second metal bump 252.
如第2F圖所示,於該第一阻層24a與焊料層26上形成第二阻層27,該第二阻層27具有對應該第一金屬凸塊251的第三阻層開孔270,其中,該第三阻層開孔270之孔 徑係等於該第一阻層開孔241之孔徑。 As shown in FIG. 2F, a second resist layer 27 is formed on the first resist layer 24a and the solder layer 26, and the second resist layer 27 has a third resistive opening 270 corresponding to the first metal bump 251. Wherein the hole of the third resistive layer opening 270 The diameter is equal to the aperture of the first resistive opening 241.
如第2G圖所示,移除該第一金屬凸塊251上的焊料層26。 As shown in FIG. 2G, the solder layer 26 on the first metal bump 251 is removed.
如第2H圖所示,於各該第一金屬凸塊251上形成金屬柱28,且該金屬柱28之材質可為銅。 As shown in FIG. 2H, a metal post 28 is formed on each of the first metal bumps 251, and the material of the metal post 28 may be copper.
如第2I圖所示,移除該第二阻層27、第一阻層24a及其所覆蓋的第一導電層23a,並移除該第三阻層24b及其所覆蓋的第二導電層23b。 As shown in FIG. 2I, the second resist layer 27, the first resist layer 24a and the first conductive layer 23a covered thereon are removed, and the third resist layer 24b and the second conductive layer covered thereby are removed. 23b.
另請參閱第2F’至2I’圖與第2F”至2I”圖,其係為第2F至2I圖的不同實施態樣,其主要不同之處僅在於第2F’至2I’圖之該第三阻層開孔270之孔徑係大於該第一阻層開孔241之孔徑,而第2F”至2I”圖之該第三阻層開孔270之孔徑係小於該第一阻層開孔241之孔徑,其他部分則大致相同,本發明所屬技術領域之通常知識者應能依據第2F至2I圖而瞭解第2F’至2I’圖與第2F”至2I”圖的具體步驟,故不在此加以贅述。 Please also refer to the 2F′ to 2I′ and 2F′′ to 2I” diagrams, which are different implementations of the 2F to 2I diagrams, the main difference being only in the 2F′ to 2I′ diagrams. The aperture of the third resistive opening 270 is larger than the aperture of the first resistive opening 241, and the aperture of the third resistive opening 270 of the 2F' to 2I" is smaller than the first resistive opening 241. The apertures and other parts are substantially the same, and those skilled in the art to which the present invention pertains should be able to understand the specific steps of the 2F' to 2I' and 2F' to 2I" diagrams according to the 2F to 2I diagrams. Repeat them.
請參閱第3A至3I圖,係本發明之封裝基板及其製法的第二實施例的剖視圖。 3A to 3I are cross-sectional views showing a second embodiment of the package substrate of the present invention and a method of manufacturing the same.
如第3A圖所示,提供一基板本體20,其具有相對之第一表面20a與第二表面20b,該第一表面20a具有複數第一電性接觸墊211與複數第二電性接觸墊212,該基板本體20之第二表面20b具有複數第三電性接觸墊213,於該第一表面20a、第一電性接觸墊211與第二電性電性接 觸墊212上形成有第一絕緣保護層22a,該第一絕緣保護層22a具有分別對應外露各該第一電性接觸墊211與第二電性接觸墊212的第一開孔221與第二開孔222,於該第二表面20b與第三電性接觸墊213上形成有第二絕緣保護層22b,該第二絕緣保護層22b具有對應外露各該第三電性接觸墊213的第三開孔223,其中,該基板本體20可為核心板、有核心之多層板、無核心之單層板或無核心之多層板。 As shown in FIG. 3A, a substrate body 20 is provided having an opposite first surface 20a and a second surface 20b. The first surface 20a has a plurality of first electrical contact pads 211 and a plurality of second electrical contact pads 212. The second surface 20b of the substrate body 20 has a plurality of third electrical contact pads 213, and the first surface 20a, the first electrical contact pads 211 and the second electrical contact pads A first insulating protective layer 22a is formed on the contact pad 212, and the first insulating protective layer 22a has a first opening 221 and a second corresponding to each of the first electrical contact pad 211 and the second electrical contact pad 212 respectively. The second insulating layer 22b is formed on the second surface 20b and the third electrical contact pad 213, and the second insulating protective layer 22b has a third corresponding to the third electrical contact pads 213. The opening 223, wherein the substrate body 20 can be a core board, a cored multi-layer board, a coreless single layer board or a coreless multi-layer board.
如第3B圖所示,於該第一絕緣保護層22a、第一電性接觸墊211與第二電性接觸墊212上形成第一導電層23a,並於該第二絕緣保護層22b與第三電性接觸墊213上形成第二導電層23b。 As shown in FIG. 3B, a first conductive layer 23a is formed on the first insulating protective layer 22a, the first electrical contact pads 211 and the second electrical contact pads 212, and the second insulating protective layer 22b and the second insulating protective layer 22b A second conductive layer 23b is formed on the three-electrode contact pad 213.
如第3C圖所示,於該第一導電層23a上形成第一阻層24a,且該第一阻層24a具有對應外露各該第二開孔222的第一阻層開孔240,並於該第二導電層23b上形成第三阻層24b。 As shown in FIG. 3C, a first resistive layer 24a is formed on the first conductive layer 23a, and the first resistive layer 24a has a first resistive opening 240 corresponding to each of the second openings 222. A third resist layer 24b is formed on the second conductive layer 23b.
如第3D圖所示,於各該第一阻層開孔240中的第一導電層23a上電鍍形成金屬凸塊25,且該金屬凸塊25之材質可為銅。 As shown in FIG. 3D, metal bumps 25 are formed on the first conductive layer 23a in each of the first barrier openings 240, and the metal bumps 25 may be made of copper.
如第3E圖所示,於該金屬凸塊25上形成焊料層26。 As shown in FIG. 3E, a solder layer 26 is formed on the metal bumps 25.
如第3F圖所示,移除該第一阻層24a與第三阻層24b。 As shown in FIG. 3F, the first resist layer 24a and the third resist layer 24b are removed.
如第3G圖所示,於該第一導電層23a、金屬凸塊25與焊料層26上形成第二阻層27a,該第二阻層27a具有對應該第一開孔221的第二阻層開孔271,並於該第二導電 層23b上形成第四阻層27b。 As shown in FIG. 3G, a second resist layer 27a is formed on the first conductive layer 23a, the metal bumps 25 and the solder layer 26, and the second resist layer 27a has a second resist layer corresponding to the first opening 221 Opening 271, and in the second conductive A fourth resist layer 27b is formed on the layer 23b.
如第3H圖所示,於各該第二阻層開孔271中的第一導電層23a上形成金屬柱28,該金屬柱28之材質可為銅。 As shown in FIG. 3H, metal pillars 28 are formed on the first conductive layer 23a in each of the second resistive layer openings 271, and the metal pillars 28 may be made of copper.
如第3I圖所示,移除該第二阻層27a及其所覆蓋的第一導電層23a,並移除該第四阻層27b及其所覆蓋的第二導電層23b。 As shown in FIG. 3I, the second resist layer 27a and the first conductive layer 23a covered thereby are removed, and the fourth resist layer 27b and the second conductive layer 23b covered thereby are removed.
本發明復提供一種封裝基板,係包括:基板本體20,係具有相對之第一表面20a與第二表面20b,且該第一表面20a具有複數第一電性接觸墊211與複數第二電性接觸墊212;第一絕緣保護層22a,係形成於該第一表面20a、第一電性接觸墊211與第二電性電性接觸墊212上,該第一絕緣保護層22a具有複數分別對應外露各該第一電性接觸墊211與第二電性接觸墊212的第一開孔221與第二開孔222;第一導電層23a,係形成於各該第一電性接觸墊211、第二電性接觸墊212及其周緣的第一絕緣保護層22a上;第一金屬凸塊251與第二金屬凸塊252,係分別對應形成於各該第一電性接觸墊211與第二電性接觸墊212上方的第一導電層23a上;焊料層26,係形成於該第二金屬凸塊252上;以及金屬柱28,係形成於該第一金屬凸塊251上,且該金屬柱28的寬度係不同於該第一金屬凸塊251的寬度。 The present invention further provides a package substrate, comprising: a substrate body 20 having opposite first and second surfaces 20a and 20b, and the first surface 20a has a plurality of first electrical contact pads 211 and a plurality of second electrical properties. The first insulating protective layer 22a is formed on the first surface 20a, the first electrical contact pad 211 and the second electrical contact pad 212, and the first insulating protective layer 22a has a plurality of corresponding The first opening 221 and the second opening 222 of the first electrical contact pad 211 and the second electrical contact pad 212 are exposed; the first conductive layer 23a is formed on each of the first electrical contact pads 211, The second electrical contact pad 212 and the peripheral first insulating protective layer 22a thereof; the first metal bump 251 and the second metal bump 252 are respectively formed on the first electrical contact pads 211 and the second On the first conductive layer 23a above the electrical contact pad 212; a solder layer 26 is formed on the second metal bump 252; and a metal pillar 28 is formed on the first metal bump 251, and the metal The width of the post 28 is different from the width of the first metal bump 251.
於前述之封裝基板中,該金屬柱28的寬度係大於或小於該第一金屬凸塊251的寬度。 In the foregoing package substrate, the width of the metal pillar 28 is greater or smaller than the width of the first metal bump 251.
依前所述之封裝基板,該基板本體20之第二表面20b 具有複數第三電性接觸墊213,於該第二表面20b與第三電性接觸墊213上形成有第二絕緣保護層22b,該第二絕緣保護層22b具有對應外露各該第三電性接觸墊213的第三開孔223。 The second surface 20b of the substrate body 20 according to the package substrate as described above A plurality of third electrical contact pads 213 are formed, and a second insulating protective layer 22b is formed on the second surface 20b and the third electrical contact pads 213, and the second insulating protective layer 22b has corresponding corresponding exposed third electrical properties. The third opening 223 of the contact pad 213.
於本發明之封裝基板中,該基板本體20係為核心板、有核心之多層板、無核心之單層板或無核心之多層板,且該第一金屬凸塊251、第二金屬凸塊252與金屬柱28之材質係為銅。 In the package substrate of the present invention, the substrate body 20 is a core board, a core multi-layer board, a coreless single layer board or a coreless multi-layer board, and the first metal bump 251 and the second metal bump The material of 252 and metal post 28 is copper.
本發明又提供另一種封裝基板,係包括:基板本體20,係具有相對之第一表面20a與第二表面20b,該第一表面20a具有複數第一電性接觸墊211與複數第二電性接觸墊212;第一絕緣保護層22a,係形成於該第一表面20a、第一電性接觸墊211與第二電性電性接觸墊212上,該第一絕緣保護層22a具有分別對應外露各該第一電性接觸墊211與第二電性接觸墊212的第一開孔221與第二開孔222;第一導電層23a,係形成於各該第一電性接觸墊211、第二電性電性接觸墊212及其周緣的第一絕緣保護層22a上;金屬凸塊25,係對應形成於各該第二電性接觸墊212上方的第一導電層23a上;焊料層26,係形成於該金屬凸塊25上;以及金屬柱28,係對應形成於各該第一電性接觸墊211上方的第一導電層23a上。 The present invention further provides another package substrate, comprising: a substrate body 20 having an opposite first surface 20a and a second surface 20b, the first surface 20a having a plurality of first electrical contact pads 211 and a plurality of second electrical properties The first insulating protective layer 22a is formed on the first surface 20a, the first electrical contact pad 211 and the second electrical contact pad 212, and the first insulating protective layer 22a has a corresponding exposed surface. a first opening 221 and a second opening 222 of the first electrical contact pad 211 and the second electrical contact pad 212; the first conductive layer 23a is formed on each of the first electrical contact pads 211, a second electrical contact pad 212 and a peripheral insulating layer 22a thereon; a metal bump 25 corresponding to the first conductive layer 23a formed on each of the second electrical contact pads 212; the solder layer 26 And being formed on the metal bumps 25; and the metal pillars 28 are correspondingly formed on the first conductive layer 23a above the first electrical contact pads 211.
於前述之封裝基板中,該基板本體20係為核心板、有核心之多層板、無核心之單層板或無核心之多層板。 In the foregoing package substrate, the substrate body 20 is a core board, a core multi-layer board, a coreless single layer board or a coreless multi-layer board.
於本發明的封裝基板中,該基板本體20之第二表面 20b具有複數第三電性接觸墊213,於該第二表面20b與第三電性接觸墊213上形成有第二絕緣保護層22b,該第二絕緣保護層22b具有對應外露各該第三電性接觸墊213的第三開孔223。 In the package substrate of the present invention, the second surface of the substrate body 20 20b has a plurality of third electrical contact pads 213, and a second insulating protective layer 22b is formed on the second surface 20b and the third electrical contact pads 213, and the second insulating protective layer 22b has corresponding corresponding exposed third electrical The third opening 223 of the contact pad 213.
所述之封裝基板中,該金屬凸塊25與金屬柱28之材質係為銅。 In the package substrate, the metal bumps 25 and the metal pillars 28 are made of copper.
綜上所述,不同於習知技術,由於本發明係以較少之阻層圖案化製程與阻層移除製程來於封裝基板上形成金屬凸塊與金屬柱,因此可縮短整體製程步驟與時間,進而有利於成本的降低。 In summary, unlike the prior art, since the present invention forms metal bumps and metal pillars on the package substrate with fewer resist layer patterning processes and resist removal processes, the overall process steps can be shortened. Time, which in turn contributes to cost reduction.
上述實施例係用以例示性說明本發明之原理及其功效,而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下,對上述實施例進行修改。因此本發明之權利保護範圍,應如後述之申請專利範圍所列。 The above embodiments are intended to illustrate the principles of the invention and its effects, and are not intended to limit the invention. Any of the above-described embodiments may be modified by those skilled in the art without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention should be as set forth in the appended claims.
10,20‧‧‧基板本體 10,20‧‧‧Substrate body
10a,20a‧‧‧第一表面 10a, 20a‧‧‧ first surface
10b,20b‧‧‧第二表面 10b, 20b‧‧‧ second surface
111,211‧‧‧第一電性接觸墊 111,211‧‧‧First electrical contact pads
112,212‧‧‧第二電性接觸墊 112,212‧‧‧Second electrical contact pads
113,213‧‧‧第三電性接觸墊 113,213‧‧‧ Third electrical contact pads
12a,22a‧‧‧第一絕緣保護層 12a, 22a‧‧‧first insulating protective layer
12b,22b‧‧‧第二絕緣保護層 12b, 22b‧‧‧Second insulation protection layer
121,221‧‧‧第一開孔 121,221‧‧‧ first opening
122,222‧‧‧第二開孔 122, 222‧‧‧ second opening
123,223‧‧‧第三開孔 123, 223‧‧‧ third opening
13a,23a‧‧‧第一導電層 13a, 23a‧‧‧ first conductive layer
13b,23b‧‧‧第二導電層 13b, 23b‧‧‧ second conductive layer
14a,24a‧‧‧第一阻層 14a, 24a‧‧‧ first barrier
14b,24b‧‧‧第三阻層 14b, 24b‧‧‧ third resistive layer
141,240,241‧‧‧第一阻層開孔 141,240,241‧‧‧first barrier opening
142,242,271‧‧‧第二阻層開孔 142,242,271‧‧‧second barrier opening
151,251‧‧‧第一金屬凸塊 151,251‧‧‧First metal bumps
152,252‧‧‧第二金屬凸塊 152,252‧‧‧Second metal bumps
16,26‧‧‧焊料層 16,26‧‧‧ solder layer
17,27,27a‧‧‧第二阻層 17,27,27a‧‧‧second barrier
170,270‧‧‧第三阻層開孔 170, 270‧‧‧ third barrier opening
18,28‧‧‧金屬柱 18,28‧‧‧Metal column
19a,27b‧‧‧第四阻層 19a, 27b‧‧‧ fourth resistive layer
19b‧‧‧第五阻層 19b‧‧‧ fifth barrier layer
190‧‧‧第四阻層開孔 190‧‧‧4th barrier layer opening
25‧‧‧金屬凸塊 25‧‧‧Metal bumps
第1A至1J圖係為習知用於層疊封裝件之封裝基板及其製法之剖視圖;第2A至2I圖係本發明之封裝基板及其製法的第一實施例的剖視圖,其中,第2F’至2I’圖與第2F”至2I”圖係為第2F至2I圖的不同實施態樣;以及第3A至3I圖係本發明之封裝基板及其製法的第二實施例的剖視圖。 1A to 1J are cross-sectional views of a conventional package substrate for laminating a package and a method of manufacturing the same; and FIGS. 2A to 2I are cross-sectional views showing a first embodiment of the package substrate of the present invention and a method of manufacturing the same, wherein the 2F' 2A' and 2F" to 2I" are different embodiments of the 2F to 2I drawings; and 3A to 3I are cross-sectional views of the second embodiment of the package substrate of the present invention and a method of manufacturing the same.
20‧‧‧基板本體 20‧‧‧Substrate body
20a‧‧‧第一表面 20a‧‧‧ first surface
20b‧‧‧第二表面 20b‧‧‧second surface
211‧‧‧第一電性接觸墊 211‧‧‧First electrical contact pads
212‧‧‧第二電性接觸墊 212‧‧‧Second electrical contact pads
213‧‧‧第三電性接觸墊 213‧‧‧ Third electrical contact pad
22a‧‧‧第一絕緣保護層 22a‧‧‧First insulation protection layer
22b‧‧‧第二絕緣保護層 22b‧‧‧Second insulation protection layer
221‧‧‧第一開孔 221‧‧‧ first opening
222‧‧‧第二開孔 222‧‧‧Second opening
223‧‧‧第三開孔 223‧‧‧ third opening
23a‧‧‧第一導電層 23a‧‧‧First conductive layer
251‧‧‧第一金屬凸塊 251‧‧‧First metal bump
252‧‧‧第二金屬凸塊 252‧‧‧Second metal bumps
26‧‧‧焊料層 26‧‧‧ solder layer
28‧‧‧金屬柱 28‧‧‧Metal column
Claims (8)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW100139864A TWI470759B (en) | 2011-11-01 | 2011-11-01 | Package substrate and fabrication method thereof |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW100139864A TWI470759B (en) | 2011-11-01 | 2011-11-01 | Package substrate and fabrication method thereof |
Publications (2)
Publication Number | Publication Date |
---|---|
TW201320274A TW201320274A (en) | 2013-05-16 |
TWI470759B true TWI470759B (en) | 2015-01-21 |
Family
ID=48872627
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW100139864A TWI470759B (en) | 2011-11-01 | 2011-11-01 | Package substrate and fabrication method thereof |
Country Status (1)
Country | Link |
---|---|
TW (1) | TWI470759B (en) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN104254190B (en) * | 2013-06-26 | 2017-12-01 | 陈丽专 | The preparation method of circuit board |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1980538A (en) * | 2005-11-30 | 2007-06-13 | 全懋精密科技股份有限公司 | Method for forming circuit-board electric connection end |
CN101287331B (en) * | 2007-04-10 | 2010-12-08 | 全懋精密科技股份有限公司 | Conductive structure of electrically connected mat of circuit board |
-
2011
- 2011-11-01 TW TW100139864A patent/TWI470759B/en active
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1980538A (en) * | 2005-11-30 | 2007-06-13 | 全懋精密科技股份有限公司 | Method for forming circuit-board electric connection end |
CN101287331B (en) * | 2007-04-10 | 2010-12-08 | 全懋精密科技股份有限公司 | Conductive structure of electrically connected mat of circuit board |
Also Published As
Publication number | Publication date |
---|---|
TW201320274A (en) | 2013-05-16 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
TWI533771B (en) | Coreless package substrate and fabrication method thereof | |
US20140239490A1 (en) | Packaging substrate and fabrication method thereof | |
JP2007013092A5 (en) | ||
TWI517269B (en) | Package on package structure and manufacturing method thereof | |
US9899235B2 (en) | Fabrication method of packaging substrate | |
TWI542263B (en) | Interposer substrate and a method for fabricating the same | |
TWI545997B (en) | Interposer substrate and method of manufacture | |
JPWO2012133380A1 (en) | Circuit board and circuit board manufacturing method | |
TWI591739B (en) | Method of manufacture a package stack-up structure | |
TWI541965B (en) | Semiconductor package and method of manufacture | |
TWI433278B (en) | Non-carrier type semiconductor package and fabrication method thereof | |
US9066458B2 (en) | Fabricating method of circuit board and circuit board | |
TWI470759B (en) | Package substrate and fabrication method thereof | |
TWI548011B (en) | Package substrates and methods for fabricating the same | |
TWI512922B (en) | Package substrate and method of forming the same | |
TWI484600B (en) | Coreless package and method of fabricating the same | |
TWI416680B (en) | Package substrate and fabrication method thereof | |
TWI501366B (en) | Package substrate and fabrication method thereof | |
TWI566330B (en) | Method of fabricating an electronic package structure | |
TW200917911A (en) | Printed circuit board and fabrication method thereof | |
TWI446850B (en) | Method of forming circuit layer | |
TWM462947U (en) | Package substrate | |
TW201330729A (en) | Package structure having embedded electronic element and method of forming same | |
TW201601224A (en) | Packaging substrate and method for fabricating the same | |
TWI604542B (en) | Package substrate and the manufacture thereof |