TW201601224A - Packaging substrate and method for fabricating the same - Google Patents
Packaging substrate and method for fabricating the same Download PDFInfo
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- TW201601224A TW201601224A TW103120817A TW103120817A TW201601224A TW 201601224 A TW201601224 A TW 201601224A TW 103120817 A TW103120817 A TW 103120817A TW 103120817 A TW103120817 A TW 103120817A TW 201601224 A TW201601224 A TW 201601224A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
Description
本發明係有關一種封裝基板結構,尤指一種能簡化製程之封裝基板結構及其製法。 The invention relates to a package substrate structure, in particular to a package substrate structure and a method for manufacturing the same.
隨著電子產業的發達,現今的電子產品已趨向輕薄短小與功能多樣化的方向設計,半導體封裝技術亦隨之開發出不同的封裝型態。而針對不同之封裝結構,亦發展出各種封裝用之封裝基板,以接置半導體晶片。為了滿足半導體封裝件薄型化的封裝需求,遂而研發出一種無核心(coreless)之封裝基板之技術。 With the development of the electronics industry, today's electronic products have been designed in a light, short, and versatile manner, and semiconductor packaging technologies have also developed different packaging types. For different package structures, various package substrates for packaging have been developed to connect semiconductor wafers. In order to meet the packaging requirements for thinning semiconductor packages, a coreless package substrate technology has been developed.
第1A至1E圖係為習知無核心(coreless)之單層線路之封裝基板1之製法的剖視示意圖。 1A to 1E are schematic cross-sectional views showing a method of manufacturing a package substrate 1 of a conventional coreless single-layer wiring.
如1A圖所示,提供一承載體10,該承載體10之構造係為於一銅箔基板10a之其中一側上形成支撐部10b。具體地,該銅箔基板10a具有一絕緣層101、及設於該絕緣層101相對二表面上之銅箔層102,且於其中一銅箔層102上形成該支撐部10b之玻璃纖維環氧樹脂(fiberglass reinforced epoxy resin,如FR-4)層103,該支撐部10b復 具有依序形成於該玻璃纖維環氧樹脂層103上之第一金屬層104(如銅層)與第二金屬層105(如銅層)。 As shown in FIG. 1A, a carrier 10 is provided which is constructed to form a support portion 10b on one side of a copper foil substrate 10a. Specifically, the copper foil substrate 10a has an insulating layer 101, and a copper foil layer 102 disposed on opposite surfaces of the insulating layer 101, and a glass fiber epoxy of the supporting portion 10b is formed on one of the copper foil layers 102. a fiberglass reinforced epoxy resin (such as FR-4) layer 103, the support portion 10b There is a first metal layer 104 (such as a copper layer) and a second metal layer 105 (such as a copper layer) sequentially formed on the glass fiber epoxy resin layer 103.
如第1B圖所示,進行圖案化製程,以於該第二金屬層105上形成複數電性接觸墊11。 As shown in FIG. 1B, a patterning process is performed to form a plurality of electrical contact pads 11 on the second metal layer 105.
如第1C圖所示,形成一具有盲孔120之介電層12於該第二金屬層105與該些電性接觸墊11上。 As shown in FIG. 1C, a dielectric layer 12 having a blind via 120 is formed on the second metal layer 105 and the electrical contact pads 11.
如第1D圖所示,以電鍍方式形成一線路層13於該介電層12上,且該線路層13具有複數形成於該盲孔120中之導電盲孔130,以令該導電盲孔130電性連接該些電性接觸墊11。 As shown in FIG. 1D, a circuit layer 13 is formed on the dielectric layer 12 by electroplating, and the circuit layer 13 has a plurality of conductive vias 130 formed in the blind via 120 to make the conductive via 130. The electrical contact pads 11 are electrically connected.
如第1E圖所示,形成一絕緣保護層14於該線路層13與該介電層12上,且圖案化該絕緣保護層14以形成外露部分該線路層13之開孔140,而製成該封裝基板1於該承載體10上。之後,可形成一表面處理層15於該開孔140中之線路層13上。 As shown in FIG. 1E, an insulating protective layer 14 is formed on the wiring layer 13 and the dielectric layer 12, and the insulating protective layer 14 is patterned to form an exposed portion 140 of the wiring layer 13. The package substrate 1 is on the carrier 10. Thereafter, a surface treatment layer 15 may be formed on the wiring layer 13 in the opening 140.
於後續製程中,可將其應用至封裝製程中。 It can be applied to the packaging process in subsequent processes.
如第1F圖所示,於該絕緣保護層14上設置一晶片16,且該晶片16係以複數銲線17電性連接該線路層13。接著,進行模封(molding compound)作業,即形成封裝膠體18於該絕緣保護層14上,以包覆該晶片16及該銲線17。 As shown in FIG. 1F, a wafer 16 is disposed on the insulating protective layer 14, and the wafer 16 is electrically connected to the wiring layer 13 by a plurality of bonding wires 17. Next, a molding operation is performed to form an encapsulant 18 on the insulating protective layer 14 to coat the wafer 16 and the bonding wire 17.
如第1G圖所示,分離該第一金屬層104與第二金屬層105,以移除該銅箔基板10a、玻璃纖維環氧樹脂層103與第一金屬層104。具體地,該第一金屬層104係以物理 方式高壓結合該第二金屬層105,且該物理方式係為卡合、靜電、吸附、或黏著物等,亦即可物理性剝除該第一金屬層104。 As shown in FIG. 1G, the first metal layer 104 and the second metal layer 105 are separated to remove the copper foil substrate 10a, the glass fiber epoxy layer 103, and the first metal layer 104. Specifically, the first metal layer 104 is physically The second metal layer 105 is combined with the high voltage, and the physical mode is a bonding, static electricity, adsorption, or adhesion, etc., and the first metal layer 104 may be physically stripped.
如第1H圖所示,蝕刻移除該第二金屬層105。 The second metal layer 105 is removed by etching as shown in FIG. 1H.
惟,習知封裝基板1及其封裝之製法中,需以具有銅箔基板10a與支撐部10b之承載體10作為支撐件以增加結構支撐力與整體構造之強度,故於進行封裝製程後,需先移除該銅箔基板10a、玻璃纖維環氧樹脂層103與第一金屬層104,再移除該第二金屬層105,即兩次移除製程,導致整體製程之步驟繁多,遂而造成製程時間冗長,而使製造成本隨之提升。 However, in the conventional method of manufacturing the package substrate 1 and the package, the carrier 10 having the copper foil substrate 10a and the support portion 10b is required as a support member to increase the structural support force and the strength of the overall structure, so that after the packaging process is performed, The copper foil substrate 10a, the glass fiber epoxy resin layer 103 and the first metal layer 104 are removed, and the second metal layer 105 is removed, that is, the process is removed twice, resulting in a large number of steps in the overall process. This results in lengthy process times and increases manufacturing costs.
因此,如何克服上述習知技術之種種問題,實已成為目前業界亟待克服之難題。 Therefore, how to overcome the various problems of the above-mentioned prior art has become a difficult problem to be overcome in the industry.
鑑於上述習知技術之種種缺失,本發明係提供一種封裝基板結構,係包括:金屬層,其上具有複數電性接觸墊;絕緣保護層,係設於該金屬層上,且該絕緣保護層具有相對之第一表面與第二表面,以令該些電性接觸墊外露於該絕緣保護層之第一表面,且該絕緣保護層之第二表面上方僅設有該金屬層;介電層,係設於該絕緣保護層與該些電性接觸墊上;以及線路層,係設於該介電層上,且該線路層電性連接該些電性接觸墊。 The present invention provides a package substrate structure comprising: a metal layer having a plurality of electrical contact pads thereon; an insulating protective layer disposed on the metal layer, and the insulating protective layer The first surface and the second surface are opposite to expose the electrical contact pads to the first surface of the insulating protective layer, and the metal layer is only disposed on the second surface of the insulating protective layer; the dielectric layer And being disposed on the insulating protective layer and the electrical contact pads; and the circuit layer is disposed on the dielectric layer, and the circuit layer is electrically connected to the electrical contact pads.
本發明復提供一種封裝基板結構之製法,係包括:提供一具有複數電性接觸墊之金屬層;形成一絕緣保護層於 該金屬層上,且該絕緣保護層具有相對之第一表面與第二表面,以令該些電性接觸墊外露於該絕緣保護層之第一表面,且該絕緣保護層之第二表面上方僅設有該金屬層;形成一介電層於該絕緣保護層之第一表面與該些電性接觸墊上;以及形成線路層於該介電層上,且該線路層電性連接該些電性接觸墊。 The invention provides a method for fabricating a package substrate structure, comprising: providing a metal layer having a plurality of electrical contact pads; forming an insulating protective layer on On the metal layer, the insulating protective layer has a first surface and a second surface opposite to expose the electrical contact pads to the first surface of the insulating protective layer, and the second surface of the insulating protective layer Providing only the metal layer; forming a dielectric layer on the first surface of the insulating protective layer and the electrical contact pads; and forming a wiring layer on the dielectric layer, and the circuit layer is electrically connected to the electricity Sexual contact pads.
前述之製法中,復包括移除該金屬層,以外露該絕緣保護層與該些電性接觸墊。 In the above method, the removing includes removing the metal layer to expose the insulating protective layer and the electrical contact pads.
前述之封裝基板結構及其製法中,絕緣保護層係為防銲層。 In the above package substrate structure and method of manufacturing the same, the insulating protective layer is a solder resist layer.
前述之封裝基板結構及其製法中,該線路層具有複數位於該介電層中之導電盲孔,以令該導電盲孔電性連接該些電性接觸墊。 In the foregoing package substrate structure and the method of manufacturing the same, the circuit layer has a plurality of conductive blind holes in the dielectric layer, so that the conductive blind holes are electrically connected to the electrical contact pads.
前述之封裝基板結構及其製法中,復包括形成表面處理層於該線路層上。 In the foregoing package substrate structure and method of manufacturing the same, the method further comprises forming a surface treatment layer on the circuit layer.
由上可知,本發明之封裝基板結構及其製法,藉由先形成該絕緣保護層,再形成該介電層,以藉該絕緣保護層加強整體結構的支撐力,而使該介電層不會發生翹曲現象,故相較於習知技術,本發明之製法無需使用如習知銅箔基板之另一支撐件作為承載用。 It can be seen from the above that the package substrate structure of the present invention and the method for manufacturing the same are formed by first forming the insulating protective layer to strengthen the supporting force of the overall structure by the insulating protective layer, so that the dielectric layer is not The warpage phenomenon occurs, so that the method of the present invention does not require the use of another support member such as a conventional copper foil substrate as a carrier as compared with the prior art.
因此,本發明之製法藉由該金屬層作支撐件,故於封裝後,僅需移除該金屬層即可,而不需進行如習知移除該銅箔基板、玻璃纖維環氧樹脂層與第一金屬層之製程,故能達成減少製程步驟與縮短製程時間之目的,因而能降低 製作成本。 Therefore, the method of the present invention uses the metal layer as a support member, so that only the metal layer needs to be removed after packaging, without removing the copper foil substrate or the glass fiber epoxy resin layer as conventionally removed. With the process of the first metal layer, the purpose of reducing the process steps and shortening the process time can be achieved, thereby reducing production cost.
1,2a‧‧‧封裝基板 1,2a‧‧‧Package substrate
10‧‧‧承載體 10‧‧‧Carrier
10a‧‧‧銅箔基板 10a‧‧‧copper foil substrate
10b‧‧‧支撐部 10b‧‧‧Support
101‧‧‧絕緣層 101‧‧‧Insulation
102‧‧‧銅箔層 102‧‧‧copper layer
103‧‧‧玻璃纖維環氧樹脂層 103‧‧‧glass fiber epoxy layer
104‧‧‧第一金屬層 104‧‧‧First metal layer
105‧‧‧第二金屬層 105‧‧‧Second metal layer
11,21‧‧‧電性接觸墊 11,21‧‧‧Electrical contact pads
12,22‧‧‧介電層 12,22‧‧‧ dielectric layer
120,220‧‧‧盲孔 120,220‧‧‧blind holes
13,23‧‧‧線路層 13,23‧‧‧circuit layer
130,230‧‧‧導電盲孔 130, 230‧‧‧ conductive blind holes
14,24‧‧‧絕緣保護層 14,24‧‧‧Insulating protective layer
140‧‧‧開孔 140‧‧‧Opening
15,25‧‧‧表面處理層 15,25‧‧‧ surface treatment layer
16‧‧‧晶片 16‧‧‧ wafer
17,27‧‧‧銲線 17,27‧‧‧welding line
18‧‧‧封裝膠體 18‧‧‧Package colloid
2‧‧‧封裝基板結構 2‧‧‧Package substrate structure
20‧‧‧金屬層 20‧‧‧metal layer
24a‧‧‧第一表面 24a‧‧‧ first surface
24b‧‧‧第二表面 24b‧‧‧second surface
26‧‧‧電子元件 26‧‧‧Electronic components
28‧‧‧封裝材 28‧‧‧Package
t‧‧‧厚度 T‧‧‧thickness
第1A至1H圖係為習知單層線路之封裝基板及其封裝之製法的剖視示意圖;以及第2A至2H圖係為本發明封裝基板結構及其封裝之製法的剖視示意圖。 1A to 1H are schematic cross-sectional views showing a method of manufacturing a package substrate of a conventional single-layer wiring and a package thereof; and FIGS. 2A to 2H are schematic cross-sectional views showing a method of manufacturing the package substrate structure and the package thereof.
以下藉由特定的具體實施例說明本發明之實施方式,熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。 The other embodiments of the present invention will be readily understood by those skilled in the art from this disclosure.
須知,本說明書所附圖式所繪示之結構、比例、大小等,均僅用以配合說明書所揭示之內容,以供熟悉此技藝之人士之瞭解與閱讀,並非用以限定本發明可實施之限定條件,故不具技術上之實質意義,任何結構之修飾、比例關係之改變或大小之調整,在不影響本發明所能產生之功效及所能達成之目的下,均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時,本說明書中所引用之如“上”、“第一”、“第二”、及“一”等之用語,亦僅為便於敘述之明瞭,而非用以限定本發明可實施之範圍,其相對關係之改變或調整,在無實質變更技術內容下,當亦視為本發明可實施之範疇。 It is to be understood that the structure, the proportions, the size, and the like of the present invention are intended to be used in conjunction with the disclosure of the specification, and are not intended to limit the invention. The conditions are limited, so it is not technically meaningful. Any modification of the structure, change of the proportional relationship or adjustment of the size should remain in this book without affecting the effects and the objectives that can be achieved by the present invention. The technical content disclosed in the invention can be covered. In the meantime, the terms "upper", "first", "second", "one" and "the" are used in the description, and are not intended to limit the scope of the invention. Changes or adjustments in the relative relationship are considered to be within the scope of the invention without substantial changes.
第2A至2H圖係為本發明之封裝基板結構及其封裝之製法之剖視示意圖。 2A to 2H are schematic cross-sectional views showing the structure of the package substrate and the method of packaging the same according to the present invention.
如第2A圖所示,提供一如銅箔之金屬層20,以作為 支撐件。 As shown in FIG. 2A, a metal layer 20 such as a copper foil is provided as supporting item.
於本實施例中,該金屬層20之厚度t係大於10μm以上,藉此得到較佳的支撐強度。 In the present embodiment, the thickness t of the metal layer 20 is greater than 10 μm, thereby obtaining better support strength.
再者,該金屬層20係用以取代習知承載體10,故該金屬層20之構造更為簡易。 Moreover, the metal layer 20 is used to replace the conventional carrier 10, so the structure of the metal layer 20 is simpler.
如第2B圖所示,形成複數電性接觸墊21於該金屬層20上。 As shown in FIG. 2B, a plurality of electrical contact pads 21 are formed on the metal layer 20.
如第2C圖所示,形成一如防銲層(solder mask)、綠漆或其它材質之絕緣保護層24於該金屬層20上,且該絕緣保護層24具有相對之第一表面24a與第二表面24b。 As shown in FIG. 2C, an insulating protective layer 24 such as a solder mask, green lacquer or other material is formed on the metal layer 20, and the insulating protective layer 24 has a first surface 24a opposite to the first surface. Two surfaces 24b.
於本實施例中,該第一表面24a係與該些電性接觸墊21之表面齊平。 In this embodiment, the first surface 24a is flush with the surface of the electrical contact pads 21.
再者,藉由該絕緣保護層24之形成,可增強目前整體結構之支撐力,故不需再另外製作支撐件,因而可縮減製程時間。 Moreover, by the formation of the insulating protective layer 24, the support force of the current overall structure can be enhanced, so that no additional support member can be produced, thereby reducing the processing time.
如第2D圖所示,形成一介電層22於該絕緣保護層24之第一表面24a與該些電性接觸墊21上,且圖案化該介電層22,以形成複數個外露該些電性接觸墊21之盲孔220於該介電層22上。 As shown in FIG. 2D, a dielectric layer 22 is formed on the first surface 24a of the insulating protective layer 24 and the electrical contact pads 21, and the dielectric layer 22 is patterned to form a plurality of exposed portions. A blind via 220 of the electrical contact pad 21 is on the dielectric layer 22.
如第2E圖所示,形成一線路層23於該介電層22上,且該線路層23具有複數形成於該盲孔220中之導電盲孔230,以令該導電盲孔230電性連接該些電性接觸墊21,而製成一無核心式且僅具單層線路之封裝基板2a於該金屬層20上。之後,可形成一表面處理層25於該線路層23 上。 As shown in FIG. 2E, a circuit layer 23 is formed on the dielectric layer 22, and the circuit layer 23 has a plurality of conductive vias 230 formed in the blind vias 220 to electrically connect the conductive vias 230. The electrical contact pads 21 are formed on the metal layer 20 with a core-free package substrate 2a having only a single layer. Thereafter, a surface treatment layer 25 may be formed on the wiring layer 23 on.
於本實施例中,形成該表面處理層25之材質係為鎳、鈀、金所組群組之合金、多層金屬或有機保焊劑(Organic Solderability Preservative,OSP)所組成之群組中之其中一者,例如,電鍍鎳/金、化學鍍鎳/金、化鎳浸金(ENIG)、化鎳鈀浸金(ENEPIG)、化學鍍錫(Immersion Tin)等,但不限於上述。 In the present embodiment, the material of the surface treatment layer 25 is one of a group consisting of an alloy of nickel, palladium, gold, a multilayer metal or an organic soldering preservative (OSP). For example, electroplating nickel/gold, electroless nickel/gold, nickel immersion gold (ENIG), enamel immersion gold (ENEPIG), electroless tin plating (Immersion Tin), and the like, but not limited thereto.
本發明之製法中,藉由先形成該絕緣保護層24,再形成該介電層22,以藉該絕緣保護層24加強整體結構的支撐力,而使該介電層22不會發生翹曲現象,故本發明之製法中無需使用如習知銅箔基板之另一支撐件作為承載用。 In the manufacturing method of the present invention, the dielectric layer 22 is formed by forming the insulating protective layer 24 first, so as to strengthen the supporting force of the overall structure by the insulating protective layer 24, so that the dielectric layer 22 does not warp. Phenomenon, in the process of the present invention, it is not necessary to use another support member such as a conventional copper foil substrate for carrying.
如第2F圖所示,設置至少一電子元件26於該介電層22上(或該線路層23上),且該電子元件26電性連接該線路層23。 As shown in FIG. 2F, at least one electronic component 26 is disposed on the dielectric layer 22 (or the wiring layer 23), and the electronic component 26 is electrically connected to the wiring layer 23.
於本實施例中,該電子元件26係以複數銲線27電性連接該線路層23;於其它實施例中,該電子元件26亦可以覆晶方式或其它方式電性連接該線路層23。 In this embodiment, the electronic component 26 is electrically connected to the circuit layer 23 by a plurality of bonding wires 27; in other embodiments, the electronic component 26 can be electrically connected to the circuit layer 23 by flip chip or other means.
再者,該電子元件26係為主動元件、被動元件或其組合(如堆疊組合、並排組合等),且該主動元件係例如晶片,而該被動元件係例如電阻、電容及電感。 Moreover, the electronic component 26 is an active component, a passive component or a combination thereof (such as a stacked combination, a side-by-side combination, etc.), and the active component is, for example, a wafer, and the passive component is, for example, a resistor, a capacitor, and an inductor.
如第2G圖所示,形成封裝材28於該介電層22上,藉以包覆該線路層23、該電子元件26及該銲線27。 As shown in FIG. 2G, a package material 28 is formed on the dielectric layer 22 to cover the circuit layer 23, the electronic component 26, and the bonding wire 27.
於本實施例中,該封裝材28係以模封(molding)方式製作;於其它實施例中,亦可採用壓合(Lamination)絕 緣膜方式製作。因此,製作該封裝材28之方式可依需求選擇不同方式,並不限於上述。 In this embodiment, the package material 28 is formed by a molding method; in other embodiments, a lamination may also be used. Made by the film. Therefore, the manner of fabricating the package material 28 can be selected according to requirements, and is not limited to the above.
再者,形成該封裝材28之材質可為乾膜型(Dry Film Type)環氧樹脂(Epoxy)、流體狀環氧樹脂、或有機材質,如ABF(Ajinomoto Build-up Film)樹脂,但不限於上述。 Furthermore, the material of the package material 28 may be a dry film type epoxy resin (Epoxy), a fluid epoxy resin, or an organic material such as ABF (Ajinomoto Build-up Film) resin, but not Limited to the above.
如第2H圖所示,蝕刻或其它方式移除該金屬層20,以外露該絕緣保護層24之第二表面24b與該些電性接觸墊21,以供複數如銲球之導電元件(圖略)結合至該些電性接觸墊21上。 As shown in FIG. 2H, the metal layer 20 is etched or otherwise removed, and the second surface 24b of the insulating protective layer 24 and the electrical contact pads 21 are exposed for a plurality of conductive elements such as solder balls (Fig. Slightly) bonded to the electrical contact pads 21.
本發明之製法中,該金屬層20取代習知承載體,故僅需移除該金屬層20即可,而不需進行如習知移除該銅箔基板、玻璃纖維環氧樹脂層與第一金屬層之製程,故能達成縮短製程時間之目的,因而能降低製作成本。 In the manufacturing method of the present invention, the metal layer 20 replaces the conventional carrier, so that only the metal layer 20 needs to be removed, without removing the copper foil substrate, the glass fiber epoxy layer and the like as in the prior art. The process of a metal layer can achieve the purpose of shortening the process time, thereby reducing the manufacturing cost.
本發明亦提供一種封裝基板結構2,係包括:一金屬層20、設於該金屬層20上之一絕緣保護層24、設於該絕緣保護層24上之一介電層22、以及設於該介電層22上之一線路層23。 The present invention also provides a package substrate structure 2, comprising: a metal layer 20, an insulating protective layer 24 disposed on the metal layer 20, a dielectric layer 22 disposed on the insulating protective layer 24, and One of the circuit layers 23 on the dielectric layer 22.
所述之金屬層20之表面上具有複數電性接觸墊21。 The metal layer 20 has a plurality of electrical contact pads 21 on its surface.
所述之絕緣保護層24係具有相對之第一表面24a與第二表面24b,以令該絕緣保護層24之第二表面24b上方僅設有該金屬層20,且該些電性接觸墊21之表面齊平該絕緣保護層24之第一表面24a,而使該些電性接觸墊21外露於該絕緣保護層24之第一表面24a。 The insulating protective layer 24 has a first surface 24a and a second surface 24b opposite to each other such that the metal layer 20 is disposed on the second surface 24b of the insulating protective layer 24, and the electrical contact pads 21 are provided. The surface of the insulating protective layer 24 is flush with the first surface 24a of the insulating protective layer 24, and the electrical contact pads 21 are exposed to the first surface 24a of the insulating protective layer 24.
所述之介電層22復設於該些電性接觸墊21上。 The dielectric layer 22 is disposed on the electrical contact pads 21 .
所述之線路層23係具有複數位於該介電層22中之導電盲孔230,以令該導電盲孔230電性連接該些電性接觸墊21。 The circuit layer 23 has a plurality of conductive blind holes 230 in the dielectric layer 22 to electrically connect the conductive blind holes 230 to the electrical contact pads 21.
於一實施例中,所述之封裝基板結構2復包括形成於該線路層23上之一表面處理層25。 In one embodiment, the package substrate structure 2 includes a surface treatment layer 25 formed on the circuit layer 23.
綜上所述,本發明之封裝基板結構及其製法,藉由形成該絕緣保護層,以達到增強於後段製程時整體結構之支撐力,此外,本發明因為不需再另外製作與移除具有玻璃纖維環氧樹脂層之承載體,而可大幅縮減製程,進而縮短了時程而達成降低製造成本之目的。 In summary, the package substrate structure of the present invention and the method of manufacturing the same, by forming the insulating protective layer, can enhance the supporting force of the overall structure during the back-end process, and further, the present invention does not require additional fabrication and removal. The carrier of the glass fiber epoxy layer can greatly reduce the process, thereby shortening the time course and achieving the purpose of reducing the manufacturing cost.
由上可知,本發明之封裝基板結構及其製法,藉由該金屬層作支撐件,且先形成該絕緣保護層之製程設計,故無需使用其它支撐件,因此,於封裝製程時,僅需移除該金屬層,因而能有效縮短製程時間,以降低製作成本。 It can be seen from the above that the package substrate structure of the present invention and the manufacturing method thereof, by using the metal layer as a support member and forming the process design of the insulating protective layer, do not need to use other support members, and therefore, only need to be used in the packaging process The metal layer is removed, thereby effectively reducing the process time and reducing the manufacturing cost.
上述實施例係用以例示性說明本發明之原理及其功效,而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下,對上述實施例進行修改。因此本發明之權利保護範圍,應如後述之申請專利範圍所列。 The above embodiments are intended to illustrate the principles of the invention and its effects, and are not intended to limit the invention. Any of the above-described embodiments may be modified by those skilled in the art without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention should be as set forth in the appended claims.
2‧‧‧封裝基板結構 2‧‧‧Package substrate structure
2a‧‧‧封裝基板 2a‧‧‧Package substrate
20‧‧‧金屬層 20‧‧‧metal layer
21‧‧‧電性接觸墊 21‧‧‧Electrical contact pads
22‧‧‧介電層 22‧‧‧Dielectric layer
220‧‧‧盲孔 220‧‧‧Blind hole
23‧‧‧線路層 23‧‧‧Line layer
230‧‧‧導電盲孔 230‧‧‧conductive blind holes
24‧‧‧絕緣保護層 24‧‧‧Insulation protective layer
25‧‧‧表面處理層 25‧‧‧Surface treatment layer
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