TWI501366B - Package substrate and fabrication method thereof - Google Patents
Package substrate and fabrication method thereof Download PDFInfo
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- TWI501366B TWI501366B TW100112523A TW100112523A TWI501366B TW I501366 B TWI501366 B TW I501366B TW 100112523 A TW100112523 A TW 100112523A TW 100112523 A TW100112523 A TW 100112523A TW I501366 B TWI501366 B TW I501366B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
Description
本發明係有關一種封裝基板及其製法，尤指一種具直柱型銅凸塊之封裝基板及其製法。The invention relates to a package substrate and a preparation method thereof, in particular to a package substrate with straight-type copper bumps and a preparation method thereof.
隨著電子產品的微型化發展趨勢，印刷電路板（PCB）表面可供設置半導體封裝結構的面積越來越小，因此遂發展出一種半導體封裝結構之立體堆疊技術，其係將複數個半導體封裝結構相互堆疊一起，而成為一層疊封裝件（package on package，簡稱POP），以符合小型表面接合面積與高密度元件設置之要求。With the development trend of miniaturization of electronic products, the area of printed circuit board (PCB) surface for mounting semiconductor package structure is getting smaller and smaller, so a three-dimensional stacking technology of semiconductor package structure is developed, which is a plurality of semiconductor packages. The structures are stacked on top of each other to form a package on package (POP) to meet the requirements of small surface bonding area and high density component placement.
請參閱第1圖，係習知之層疊封裝件之剖視圖，如圖所示，習知之層疊封裝件係將兩個具有晶片111,121的封裝結構11,12相互堆疊，並直接以焊球13連接，俾使該兩個封裝結構11,12之間有所間隔而不至於互相碰觸。Referring to FIG. 1, a cross-sectional view of a conventional laminated package is shown. As shown, a conventional package package stacks two package structures 11, 12 having wafers 111, 121 on each other and directly connected by solder balls 13. The two package structures 11, 12 are spaced apart from each other without touching each other.
惟，為了確保兩個封裝結構11,12之間不會互相碰觸，習知技術一般須使用較大直徑之焊球13以加深晶片封裝區域深度D，這使得焊球13的體積較大而佔用較大封裝基板表面積，進而不利於封裝基板面積的縮小；另外，在現代電子產品逐漸微型化之趨勢下，封裝基板上的焊墊112,122之間的間距也愈來愈小，因此於迴銲連接時，體積較大的焊球13也容易溢流至四周而造成橋接現象，進而導致不良品的產生。However, in order to ensure that the two package structures 11, 12 do not touch each other, conventional techniques generally use a larger diameter solder ball 13 to deepen the depth D of the package area, which makes the solder ball 13 larger. Occupying a larger surface area of the package substrate, which is disadvantageous for the reduction of the area of the package substrate; in addition, under the trend of miniaturization of modern electronic products, the spacing between the pads 112, 122 on the package substrate is becoming smaller and smaller, so that the reflow is performed. When connected, the large-sized solder ball 13 easily overflows to the surroundings and causes bridging, which leads to defective products.
因此，如何避免習知技術中之層疊封裝件的焊球佔用過大的封裝基板面積，且容易在迴銲時造成橋接，而使得整體良率下降等問題，實已成為目前亟欲解決的課題。Therefore, how to avoid the problem that the solder ball of the laminated package in the prior art occupies an excessively large package substrate area and is easy to cause bridging during reflow, and the overall yield is lowered has become a problem to be solved at present.
鑑於上述習知技術之種種缺失，本發明之主要目的係提供一種良率較高之封裝基板及其製法。In view of the above-mentioned various deficiencies of the prior art, the main object of the present invention is to provide a package substrate having a high yield and a method of manufacturing the same.
為達上述及其他目的，本發明揭露一種封裝基板，係包括：線路板，係具有交互相疊之至少一介電層與線路層，且具有相對之第一表面及第二表面；複數第一電性接觸墊，係設於該第一表面上；複數第二電性接觸墊，係設於該第一表面上，其中，該等第一電性接觸墊係圍繞該等第二電性接觸墊，且該第一電性接觸墊之寬度係大於該第二電性接觸墊之寬度；以及直柱型銅凸塊，係設於各該第一電性接觸墊上，且該直柱型銅凸塊與該第一電性接觸墊之間係具有一導電層，其中，該直柱型銅凸塊之寬度係小於該第一電性接觸墊之寬度，且該直柱型銅凸塊係高於該第二電性接觸墊，以供該直柱型銅凸塊藉由焊料連接至其他基板，同時，該第一表面、第一電性接觸墊、第二電性接觸墊、與直柱型銅凸塊表面係外露於環境中。To achieve the above and other objects, the present invention discloses a package substrate comprising: a circuit board having at least one dielectric layer and a circuit layer alternately stacked, and having opposite first and second surfaces; An electrical contact pad is disposed on the first surface; a plurality of second electrical contact pads are disposed on the first surface, wherein the first electrical contact pads surround the second electrical contacts a pad, and the width of the first electrical contact pad is greater than a width of the second electrical contact pad; and a straight-type copper bump is disposed on each of the first electrical contact pads, and the straight-type copper The conductive layer is formed between the bump and the first electrical contact pad, wherein the width of the straight-type copper bump is smaller than the width of the first electrical contact pad, and the straight-type copper bump is Higher than the second electrical contact pad for connecting the straight-type copper bumps to other substrates by soldering, while the first surface, the first electrical contact pads, the second electrical contact pads, and the straight The surface of the cylindrical copper bump is exposed to the environment.
前述之封裝基板中，該第二表面復可具有複數第三電性接觸墊。In the foregoing package substrate, the second surface may have a plurality of third electrical contact pads.
依上述之封裝基板，該導電層22之材料係可選自由電鍍鎳/金、化學鍍鎳/金、化鎳浸金（ENIG）、化鎳鈀浸金（ENEPIG）及化學鍍錫（Immersion Tin）所組成之群組中之其中一者。According to the above package substrate, the material of the conductive layer 22 is optionally electroplated with nickel/gold, electroless nickel/gold, nickel immersion gold (ENIG), nickel-palladium immersion gold (ENEPIG) and electroless tin plating (Immersion Tin). One of the group consisting of.
本發明復提供一種封裝基板之製法，係包括：提供一線路板，係具有交互相疊之至少一介電層與線路層，且具有相對之第一表面及第二表面，該第一表面上設有複數第一電性接觸墊及複數第二電性接觸墊，其中，該等第一電性接觸墊係圍繞該等第二電性接觸墊，且該第一電性接觸墊之寬度係大於該第二電性接觸墊之寬度；於該第一表面、該第一電性接觸墊及第二電性接觸墊上形成第一阻層，且該第一阻層具有複數第一開孔，以令各該第一電性接觸墊對應外露於各該第一開孔；於各該第一開孔外露之第一電性接觸墊上形成直柱型銅凸塊；以及移除該第一阻層，俾令該直柱型銅凸塊高於該第二電性接觸墊，該直柱型銅凸塊之寬度係小於該第一電性接觸墊之寬度，該直柱型銅凸塊係用以藉由焊料連接其他基板，且該第一表面、第一電性接觸墊、第二電性接觸墊、與直柱型銅凸塊表面係外露於環境中。The invention provides a method for manufacturing a package substrate, comprising: providing a circuit board having at least one dielectric layer and a circuit layer alternately stacked, and having opposite first and second surfaces on the first surface a plurality of first electrical contact pads and a plurality of second electrical contact pads are disposed, wherein the first electrical contact pads surround the second electrical contact pads, and the width of the first electrical contact pads is The first resistive layer is formed on the first surface, the first electrical contact pad and the second electrical contact pad, and the first resistive layer has a plurality of first openings, So that each of the first electrical contact pads is exposed to each of the first openings; forming a straight-type copper bump on the first electrical contact pads exposed by the first openings; and removing the first resistance The layer-shaped copper bump is higher than the second electrical contact pad, and the width of the straight-type copper bump is smaller than the width of the first electrical contact pad, and the straight-type copper bump is Used to connect other substrates by solder, and the first surface, the first electrical contact pad, and the second electrical Contact pads, the surface of the copper-based bump Straight exposed to the environment.
依上所述之封裝基板之製法，該第二表面復可具有複數第三電性接觸墊。According to the manufacturing method of the package substrate, the second surface may have a plurality of third electrical contact pads.
前述之封裝基板之製法中，形成該直柱型銅凸塊之步驟係可包括：於形成該第一阻層前，於該線路板之第一表面、該等第一電性接觸墊及第二電性接觸墊上形成導電層；於該導電層上形成該第一阻層，且該第一阻層中形成該等第一開孔；電鍍形成該直柱型銅凸塊；以及移除該第一阻層之步驟復包括移除該第一阻層所覆蓋之導電層。In the method of manufacturing the package substrate, the step of forming the straight-type copper bump may include: before forming the first resist layer, on the first surface of the circuit board, the first electrical contact pads, and a conductive layer is formed on the second electrical contact pad; the first resistive layer is formed on the conductive layer, and the first opening is formed in the first resistive layer; the straight pillar type copper bump is formed by electroplating; and the The step of the first resist layer further includes removing the conductive layer covered by the first resist layer.
由上可知，由於本發明之封裝基板用以連接其他封裝 結構的金屬凸塊係明顯高於置晶用電性接觸墊，所以能有效提高層疊封裝件(POP)對晶片的容許厚度，並避免相互堆疊之封裝結構有非預期的碰觸，且可使用較小直徑焊球，進而能改善後續封裝結構的可靠度。As can be seen from the above, the package substrate of the present invention is used to connect other packages. The metal bumps of the structure are significantly higher than the electrical contact pads for the crystallizing, so that the allowable thickness of the stacked package (POP) to the wafer can be effectively improved, and the package structure of the stacked stacks can be prevented from being unexpectedly touched, and can be used. Smaller diameter solder balls can improve the reliability of subsequent package structures.
以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。The other embodiments of the present invention will be readily understood by those skilled in the art from this disclosure.
請參閱第2A至2F圖，係本發明之封裝基板及其製法的剖視圖。2A to 2F are cross-sectional views showing a package substrate of the present invention and a method of manufacturing the same.
如第2A圖所示，提供一線路板20，係具有交互相疊之至少一介電層(未以元件符號標示)與例如內層線路201的線路層，且具有相對之第一表面20a及第二表面20b，該第一表面20a上設有複數第一電性接觸墊211及複數第二電性接觸墊212，其中，該等第一電性接觸墊211係圍繞該等第二電性接觸墊212，且該第一電性接觸墊211之寬度係大於該第二電性接觸墊212之寬度，且該第二表面20b復具有複數第三電性接觸墊213。As shown in FIG. 2A, a circuit board 20 is provided having at least one dielectric layer (not labeled by a component symbol) and a circuit layer such as an inner layer line 201, and having a first surface 20a opposite thereto. a second surface 20b, the first surface 20a is provided with a plurality of first electrical contact pads 211 and a plurality of second electrical contact pads 212, wherein the first electrical contact pads 211 surround the second electrical contacts The pad is 212, and the width of the first electrical contact pad 211 is greater than the width of the second electrical contact pad 212, and the second surface 20b has a plurality of third electrical contact pads 213.
如第2B圖所示，於該線路板20之第一表面20a、該等第一電性接觸墊211及第二電性接觸墊212上形成導電層22。As shown in FIG. 2B, a conductive layer 22 is formed on the first surface 20a of the circuit board 20, the first electrical contact pads 211, and the second electrical contact pads 212.
如第2C圖所示，於該導電層22上形成該第一阻層23a，且該第一阻層23a中形成有複數第一開孔230，以令各該第一電性接觸墊211對應外露於各該第一開孔230，並 於該第二表面20b與第三電性接觸墊213上形成該第二阻層23b。As shown in FIG. 2C, the first resistive layer 23a is formed on the conductive layer 22, and a plurality of first openings 230 are formed in the first resistive layer 23a, so that the first electrical contact pads 211 are corresponding to each other. Exposed to each of the first openings 230, and The second resist layer 23b is formed on the second surface 20b and the third electrical contact pad 213.
如第2D圖所示，於各該第一開孔230外露之第一電性接觸墊211上形成直柱型銅凸塊24。As shown in FIG. 2D, a stud-type copper bump 24 is formed on the first electrical contact pad 211 exposed by each of the first openings 230.
如第2E圖所示，移除該第二阻層23b、該第一阻層23a及其所覆蓋之導電層22，俾令該直柱型銅凸塊24高於該第二電性接觸墊212，該直柱型銅凸塊24之寬度係小於該第一電性接觸墊211之寬度，且該第一表面20a、第一電性接觸墊211、第二電性接觸墊212、與直柱型銅凸塊24表面係顯露於外。As shown in FIG. 2E, the second resistive layer 23b, the first resistive layer 23a and the conductive layer 22 covered thereon are removed, so that the straight-type copper bumps 24 are higher than the second electrical contact pads. 212, the width of the straight-type copper bumps 24 is smaller than the width of the first electrical contact pads 211, and the first surface 20a, the first electrical contact pads 211, the second electrical contact pads 212, and the straight The surface of the columnar copper bump 24 is exposed.
本發明復提供一種封裝基板，係包括：線路板20，係具有交互相疊之至少一介電層與線路層，且具有相對之第一表面20a及第二表面20b；複數第一電性接觸墊211，係設於該第一表面20a上；複數第二電性接觸墊212，係設於該第一表面20a上，其中，該等第一電性接觸墊211係圍繞該等第二電性接觸墊212，且該第一電性接觸墊211之寬度係大於該第二電性接觸墊212之寬度；以及直柱型銅凸塊24，係設於各該第一電性接觸墊211上，且該直柱型銅凸塊24與該第一電性接觸墊211之間係具 有一導電層22，其中，該直柱型銅凸塊24之寬度係小於該第一電性接觸墊211之寬度，且該直柱型銅凸塊24係高於該第二電性接觸墊212，以供該直柱型銅凸塊24藉由焊料連接至其他基板，同時，該第一表面20a、第一電性接觸墊211、第二電性接觸墊212、與直柱型銅凸塊24表面係外露於環境中。The present invention further provides a package substrate, comprising: a circuit board 20 having at least one dielectric layer and a circuit layer alternately stacked, and having opposite first and second surfaces 20a and 20b; and a plurality of first electrical contacts a pad 211 is disposed on the first surface 20a; a plurality of second electrical contact pads 212 are disposed on the first surface 20a, wherein the first electrical contact pads 211 surround the second electrical And the width of the first electrical contact pad 211 is greater than the width of the second electrical contact pad 212; and the straight-type copper bumps 24 are disposed on the first electrical contact pads 211. Upper and between the straight-type copper bumps 24 and the first electrical contact pads 211 The width of the straight-type copper bumps 24 is smaller than the width of the first electrical contact pads 211, and the straight-type copper bumps 24 are higher than the second electrical contact pads 212. For the straight-type copper bumps 24 to be connected to other substrates by solder, the first surface 20a, the first electrical contact pads 211, the second electrical contact pads 212, and the straight-type copper bumps 24 surface systems are exposed to the environment.
所述之封裝基板中，該第二表面20b復可具有複數第三電性接觸墊213。In the package substrate, the second surface 20b may have a plurality of third electrical contact pads 213.
於上述之封裝基板中，該導電層22之材料係可選自由電鍍鎳/金、化學鍍鎳/金、化鎳浸金(ENIG)、化鎳鈀浸金(ENEPIG)及化學鍍錫(Immersion Tin)所組成之群組中之其中一者。In the above package substrate, the material of the conductive layer 22 is optionally electroplated with nickel/gold, electroless nickel/gold, nickel immersion gold (ENIG), nickel-palladium immersion gold (ENEPIG) and electroless tin plating (Immersion). One of the groups consisting of Tin).
綜上所述，相較於習知技術，由於本發明之封裝基板用以連接其他封裝結構的金屬凸塊(例如直柱型銅凸塊24)係明顯高於置晶用電性接觸墊(例如第二電性接觸墊212)，所以能有效提高層疊封裝件(package on package，簡稱POP)對晶片的容許厚度，並避免相互堆疊之封裝結構有非預期的碰觸，且可使用較小直徑焊球，而能防止迴銲時的橋接，進而能改善後續封裝結構的可靠度。In summary, compared with the prior art, the metal bumps (for example, the straight-type copper bumps 24) for connecting the other package structures of the package substrate of the present invention are significantly higher than the electrical contact pads for crystallizing ( For example, the second electrical contact pad 212) can effectively increase the allowable thickness of the package on package (POP) to the wafer, and avoid unintended contact between the package structures stacked on each other, and can be used less. The diameter of the solder ball can prevent bridging during reflow, which can improve the reliability of the subsequent package structure.
上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修改。因此本發明之權利保護範圍，應如後述之申請專 利範圍所列。The above embodiments are intended to illustrate the principles of the invention and its effects, and are not intended to limit the invention. Any of the above-described embodiments may be modified by those skilled in the art without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention should be as described later. Listed in the range of benefits.
11、12‧‧‧封裝結構11, 12‧‧‧Package structure
111、121‧‧‧晶片111, 121‧‧‧ wafer
112、122‧‧‧焊墊112, 122‧‧‧ solder pads
13、32‧‧‧焊球13, 32‧‧‧ solder balls
D‧‧‧晶片封裝區域深度D‧‧‧Depth of chip package area
20‧‧‧線路板20‧‧‧ circuit board
20a‧‧‧第一表面20a‧‧‧ first surface
20b‧‧‧第二表面20b‧‧‧second surface
201‧‧‧內層線路201‧‧‧ Inner line
211‧‧‧第一電性接觸墊211‧‧‧First electrical contact pads
212‧‧‧第二電性接觸墊212‧‧‧Second electrical contact pads
213‧‧‧第三電性接觸墊213‧‧‧ Third electrical contact pad
22‧‧‧導電層22‧‧‧ Conductive layer
23a‧‧‧第一阻層23a‧‧‧First barrier layer
230‧‧‧第一開孔230‧‧‧First opening
23b‧‧‧第二阻層23b‧‧‧second barrier layer
24‧‧‧直柱型銅凸塊24‧‧‧Straight copper bumps
26‧‧‧第一晶片26‧‧‧First chip
27‧‧‧封裝材料27‧‧‧Packaging materials
3‧‧‧封裝結構3‧‧‧Package structure
31‧‧‧第二晶片31‧‧‧second chip
第1圖係習知之層疊封裝件之剖視圖；以及第2A至2E圖係本發明之封裝基板及其製法的剖視圖。1 is a cross-sectional view of a conventional laminated package; and 2A to 2E are cross-sectional views of a package substrate of the present invention and a method of manufacturing the same.
20．．．線路板20. . . circuit board
20a．．．第一表面20a. . . First surface
20b．．．第二表面20b. . . Second surface
201．．．內層線路201. . . Inner line
211．．．第一電性接觸墊211. . . First electrical contact pad
212．．．第二電性接觸墊212. . . Second electrical contact pad
213．．．第三電性接觸墊213. . . Third electrical contact pad
22．．．導電層twenty two. . . Conductive layer
24．．．直柱型銅凸塊twenty four. . . Straight cylindrical copper bump
Claims (6)
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| TWI501366B true TWI501366B (en) | 2015-09-21 |
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| TWI555101B (en) * | 2014-05-27 | 2016-10-21 | 矽品精密工業股份有限公司 | Package structure and method of manufacture |
| CN108231729B (en) * | 2017-12-29 | 2020-07-14 | 通富微电子股份有限公司 | Packaging substrate, chip packaging body and chip stacking and packaging method |
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| TW200837910A (en) * | 2007-03-14 | 2008-09-16 | Phoenix Prec Technology Corp | Semiconductor package substrate structure and fabrication method thereof |
| TW201042741A (en) * | 2009-05-26 | 2010-12-01 | Phoenix Prec Technology Corp | Electrical connecting structure of package substrate and package structure |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| TW200837910A (en) * | 2007-03-14 | 2008-09-16 | Phoenix Prec Technology Corp | Semiconductor package substrate structure and fabrication method thereof |
| TW201042741A (en) * | 2009-05-26 | 2010-12-01 | Phoenix Prec Technology Corp | Electrical connecting structure of package substrate and package structure |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108321136A (en) * | 2017-01-18 | 2018-07-24 | 南茂科技股份有限公司 | Semiconductor packaging structure and manufacturing method thereof |
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