CN107241862A - Circuit board - Google Patents
Circuit board Download PDFInfo
- Publication number
- CN107241862A CN107241862A CN201710584291.7A CN201710584291A CN107241862A CN 107241862 A CN107241862 A CN 107241862A CN 201710584291 A CN201710584291 A CN 201710584291A CN 107241862 A CN107241862 A CN 107241862A
- Authority
- CN
- China
- Prior art keywords
- dielectric layer
- layer
- support plate
- circuit board
- conductive circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000004806 packaging method and process Methods 0.000 claims abstract description 23
- 238000003466 welding Methods 0.000 claims description 24
- 230000015572 biosynthetic process Effects 0.000 claims description 8
- 239000000463 material Substances 0.000 claims description 8
- 238000003825 pressing Methods 0.000 claims description 7
- 238000000034 method Methods 0.000 claims description 5
- 239000004020 conductor Substances 0.000 claims description 4
- 238000005538 encapsulation Methods 0.000 claims description 4
- 238000000608 laser ablation Methods 0.000 claims description 4
- 239000004411 aluminium Substances 0.000 claims description 3
- 229910052782 aluminium Inorganic materials 0.000 claims description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 3
- 239000011810 insulating material Substances 0.000 claims description 2
- 238000005530 etching Methods 0.000 claims 1
- 238000002360 preparation method Methods 0.000 abstract description 6
- 239000010410 layer Substances 0.000 description 110
- 239000011241 protective layer Substances 0.000 description 6
- 238000009826 distribution Methods 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 229910000679 solder Inorganic materials 0.000 description 3
- 230000005611 electricity Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000007787 solid Substances 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 1
- 239000000654 additive Substances 0.000 description 1
- 238000003486 chemical etching Methods 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 239000012141 concentrate Substances 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- MSNOMDLPLDYDME-UHFFFAOYSA-N gold nickel Chemical compound [Ni].[Au] MSNOMDLPLDYDME-UHFFFAOYSA-N 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 238000007639 printing Methods 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0011—Working of insulating substrates or insulating layers
- H05K3/0014—Shaping of the substrate, e.g. by moulding
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09009—Substrate related
- H05K2201/09045—Locally raised area or protrusion of insulating substrate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
A kind of circuit board, including the first dielectric layer, the first conductive circuit layer, bump pattern and the second dielectric layer, first dielectric layer and the second dielectric layer are connected with each other, first conductive circuit layer includes center packaging area and the surrounding package region around the center packaging area, the bump pattern, which is formed at the first dielectric layer, has the surface away from the second dielectric layer, the bump pattern is integrally formed with first dielectric layer, and the shape of the bump pattern is corresponding with the intersection of the center packaging area and surrounding package region.The present invention also provides a kind of preparation method of the circuit board.
Description
The application be Application No. 2013102586889, the applying date be on 06 26th, 2013, invention and created name " electricity
Road plate preparation method " patent divisional application.
Technical field
The present invention relates to circuit board making field, more particularly to a kind of circuit board with metal coupling.
Background technology
In the prior art, in order to save the volume of encapsulating structure.It is generally necessary in the circuit board top as encapsulating carrier plate
Encapsulate chip and circuit board.Wherein, the corresponding packaging area of chip usually requires to set more intensive engagement pad, and and circuit
The area for the engagement pad that plate is packaged is generally larger, and is distributed more sparse.Also, during being packaged, generally
Need, first by chip package in encapsulating carrier plate, to be then again packaged the package substrate for being packaged with chip with other circuit boards.
In the prior art, it usually needs two layers of welding resisting layer is made on the surface of encapsulating carrier plate, first layer welding resisting layer is used to define support plate
On engagement pad, the second welding resisting layer (Dam Ring) formation is on the first welding resisting layer, and around chip package region, with encapsulation
Dykes and dams effect is played during chip.However, because the first welding resisting layer and the second welding resisting layer are formed respectively, after encapsulation, easily by
In stress concentration in the first welding resisting layer and the intersection of the second welding resisting layer, so as to cause the first welding resisting layer and the second welding resisting layer mutual
Separation.
The content of the invention
Therefore, it is necessary to provide making and its method for a kind of circuit board, above mentioned problem can solve the problem that.
A kind of circuit board, including the first dielectric layer, the first conductive circuit layer, bump pattern and the second dielectric layer, described
One dielectric layer and the second dielectric layer are connected with each other, and first conductive circuit layer includes center packaging area and around the center
The surrounding package region of packaging area, the bump pattern, which is formed at the first dielectric layer, has the surface away from the second dielectric layer,
The bump pattern is integrally formed with first dielectric layer, and the shape of the bump pattern is with the center packaging area and outside
The intersection for enclosing packaging area is corresponding.
A kind of circuit board manufacturing method, including step：Support plate is provided, the support plate has first surface；From the support plate
First surface form groove pattern into the support plate；Projection figure is formed in the groove pattern by pressing insulating materials
Shape, and simultaneously in first surface the first dielectric layer of formation of support plate, first dielectric layer is integrally formed with the bump pattern；
First dielectric layer surface formed the first conductive circuit layer, first conductive circuit layer include center packaging area with
Surrounding package region, the center packaging area and the intersection in surrounding package region are corresponding with the bump pattern；First
Conductive circuit layer side presses the second dielectric layer；And remove the support plate.
Compared with prior art, circuit board that the technical program is provided and preparation method thereof, by support plate inner groovy figure
Shape, then forms the first dielectric layer and bump pattern so that bump pattern and the first dielectric layer one simultaneously by way of pressing
It is body formed.Compared in the prior art, successively formed respectively by way of forming welding resisting layer twice, so as to avoid in envelope
After dress, because stress concentration is in the intersection of two layers of welding resisting layer so that two layers of welding resisting layer is separated from each other.
Brief description of the drawings
Fig. 1 is the diagrammatic cross-section for the support plate that the technical program embodiment is provided.
Fig. 2 is the diagrammatic cross-section formed in Fig. 1 support plate after groove pattern.
Fig. 3 is Fig. 2 top view.
Fig. 4 is that Fig. 2 support plate surface presses the diagrammatic cross-section after the first dielectric layer.
Fig. 5 is the diagrammatic cross-section after Fig. 4 the first dielectric layer surface the first conductive circuit layer of formation.
Fig. 6 is that Fig. 5 the first conductive circuit layer side presses the diagrammatic cross-section after the second dielectric layer.
Fig. 7 is the diagrammatic cross-section after Fig. 6 the second dielectric layer surface the second conductive circuit layer of formation.
Fig. 8 is the diagrammatic cross-section after Fig. 7 the second conducting wire layer surface formation welding resisting layer.
Fig. 9 is that Fig. 8 removes the diagrammatic cross-section after support plate.
Figure 10 is the diagrammatic cross-section formed in Fig. 9 the first dielectric layer after the first opening and the second opening.
Figure 11 is the diagrammatic cross-section for the circuit board that the technical program makes.
Figure 12 is Figure 11 top view.
Main element symbol description
Following embodiment will further illustrate the present invention with reference to above-mentioned accompanying drawing.
Embodiment
The circuit board manufacturing method that the technical program is provided comprises the following steps：
The first step, referring to Fig. 1, providing support plate 110.
The support plate 110 is made up of use metal material.In the present embodiment, support plate 110 is made of metallic aluminium.It is described to carry
Plate 110 has first surface 111, and the first surface 111 is plane.
Second step, refers to Fig. 2 and Fig. 3, and groove pattern 112 is formed in the support plate 110.
The groove pattern 112 can be formed by the way of laser ablation.The groove pattern 112 should be with electricity to be made
The sideline in the chip package region of road plate is corresponding, in the present embodiment, and the groove pattern 112 is generally shaped like square shape.
The groove pattern 112 is formed at the intermediate region of support plate 110.
3rd step, referring to Fig. 4, first dielectric layer of the formation of first surface 111 120 in the support plate 110 simultaneously exists simultaneously
Bump pattern 130 is formed in groove pattern 112.
First dielectric layer 120 and bump pattern 130 can be formed by way of pressing semi-solid preparation film.It is described convex
Block graphics 130 is filled up completely with the groove pattern 112, and the first dielectric layer 120 covers whole first surface 111.Described
One dielectric layer 120 is integrally formed with bump pattern 130.The material of first dielectric layer 120 can be commonly used in the art exhausted
Edge material, such as polyimides.
First dielectric layer 120 has the second surface 121 adjacent with first surface 111, and the bump pattern 130 is convex
For second surface 121, the shape and groove pattern 112 of the bump pattern 130 are complementary, also with the chip of circuit board to be made
The sideline of packaging area is corresponding, in the present embodiment, and the bump pattern 130 is generally shaped like square shape.
4th step, referring to Fig. 5, forming the first conductive circuit layer in side of first dielectric layer 120 away from support plate 110
140。
First conductive circuit layer 140 can be made of semi-additive process.It is understood that first conductor wire
Road floor 140 can also make to be formed using other circuit manufacturing methods commonly used in the trade.
First conductive circuit layer 140 includes center packaging area 141 and surrounding package region 142.The center envelope
Filling includes multiple distribution less first engagement pads 1411 of more intensive and area, the surrounding package region 142 in region 141
Around the center packaging area 141, distribution is distributed more sparse and larger area second and connect in surrounding package region 142
Touch pad 1421.The center packaging area 141 and the intersection in surrounding package region 142 are corresponding with bump pattern 130.
5th step, referring to Fig. 6, pressing the second dielectric layer 150 in the side of the first conductive circuit layer 140.
In this step, it would however also be possible to employ the mode of pressing semi-solid preparation film forms the second dielectric layer 150.In the present embodiment,
The material of second dielectric layer 150 is identical with the material of the first dielectric layer 120.The thickness of second dielectric layer 150 can be more than
The thickness of first dielectric layer 120.
In the present embodiment, after this step, it can further include and form hole 151 in the second dielectric layer 150.Can be with
Hole 151 is formed by the way of laser ablation.Second dielectric layer 150 is run through in hole 151 so that the first conductive circuit layer 140
The second engagement pad 1421 expose from the bottom in hole 151.
6th step, referring to Fig. 7, forming the second conductor wire in side of second dielectric layer 150 away from the first dielectric layer 120
Road floor 160.
This step equally can form the second conductive circuit layer using the identical method of the first conductive circuit layer 140 is formed
160。
In the present embodiment, prior to or while the second conductive circuit layer 160 is formed, conduction material is also formed in hole 151
Material, so as to form conductive hole 152, first conductive circuit layer 140 passes through the phase of conductive hole 152 with the second conductive circuit layer 160
Transconductance leads to.
7th step, referring to Fig. 8, forming welding resisting layer 170 on the surface of the second conductive circuit layer 160.
This step can form welding resisting layer 170 by the way of printing liquid anti-solder ink.Formed in the welding resisting layer 170
There is the conducting wire in multiple perforates 171, the second conductive circuit layer of part 160 to expose from perforate 171, form electrical connection pad 161.
8th step, also referring to Fig. 9, removes support plate 110.
In the present embodiment, support plate 110, which is adopted, to be formed from aluminium, and this step can be removed support plate 110 by the way of chemical etching
Remove so that the first dielectric layer 120 and bump pattern 130 are exposed.
9th step, referring to Fig. 10, forming multiple first openings 123 and multiple second in first dielectric layer 120
Opening 124, each first opening is 123 corresponding with the first engagement pad 1411, and each first engagement pad 1411 is from corresponding first
Opening 123 is exposed.Each second opening is 124 corresponding with second engagement pad 1421, and each second engagement pad 1421 is from right
The second opening 124 answered is exposed.
The opening 124 of first opening 123 and second can be formed by the way of laser ablation.
Tenth step, refers to Figure 11 and Figure 12, in first engagement pad 1411, the second engagement pad 1421 and electrical connection pad
161 surface forms protective layer 180, and the surface of the protective layer 180 in the first engagement pad 1411 forms solder projection 190,
So as to obtain circuit board 100.
The protective layer 180 can be organic guarantor weldering film (OSP), or nickel-gold layer or NiPdAu layer.
Figure 11 and Figure 12 is referred to, the technical program also provides a kind of circuit board 100, and the circuit board 100 includes first
Dielectric layer 120, bump pattern 130, the first conductive circuit layer 140, the second dielectric layer 150 and the second conductive circuit layer 160.
The dielectric layer 150 of first dielectric layer 120 and second is connected with each other.First conductive circuit layer 140 is located at the
Between one dielectric layer 120 and the second dielectric layer 150.
First conductive circuit layer 140 includes center packaging area 141 and surrounding package region 142.The center envelope
Filling includes multiple distribution less first engagement pads 1411 of more intensive and area, the surrounding package region 142 in region 141
Around the center packaging area 141, distribution is distributed more sparse and larger area second and connect in surrounding package region 142
Touch pad 1421.
First dielectric layer 120 has the second surface 121 away from the second dielectric layer 150.The shape of bump pattern 130
The side of second surface 121 described in Cheng Yu.The bump pattern 130 is made with the first dielectric layer 120 of identical material, and one
It is body formed.Bump pattern 130 and the center packaging area 141 of the first conductive circuit layer 140 and the friendship in surrounding package region 142
Line is corresponding.
Multiple first openings 123 and multiple second openings 124 are formed with first dielectric layer 120, each first opens
Mouth 123 is corresponding with the first engagement pad 1411, and each first engagement pad 1411 is exposed from the corresponding first opening 123.Each
Two openings 124 are corresponding with second engagement pad 1421, and each second engagement pad 1421 is revealed from the corresponding second opening 124
Go out.
Second conductive circuit layer 160 is formed at side of second dielectric layer 150 away from the first conductive circuit layer 140.
The surface of second conductive circuit layer 160 is formed with welding resisting layer 170.Multiple perforates 171, portion are formed with the welding resisting layer 170
The conducting wire divided in the second conductive circuit layer 160 is exposed from perforate 171, forms electrical connection pad 161.
The circuit board 100 can also include protective layer 180, and the protective layer 180 is formed at electrical connection pad 161, first
The surface of the engagement pad 1421 of engagement pad 1411 and second.
The surface of protective layer 180 in first engagement pad 1411 is also formed with solder projection 190, for encapsulating electronics
Welded during element.
Circuit board that the technical program is provided and preparation method thereof, by support plate inner groovy figure, then passing through pressing
Mode form the first dielectric layer and bump pattern simultaneously so that bump pattern is integrally formed with the first dielectric layer.Compared to existing
Have in technology, successively formed respectively by way of forming welding resisting layer twice, so as to avoid after encapsulation, due to stress
Concentrate on the intersection of two layers of welding resisting layer so that two layers of welding resisting layer is separated from each other.
It is understood that the circuit board manufacturing method of the technical program can apply to high-density interconnected circuit board
(HDI) making.
It is understood that for the person of ordinary skill of the art, can be done with technique according to the invention design
Go out other various corresponding changes and deformation, and all these changes and deformation should all belong to the protection model of the claims in the present invention
Enclose.
Claims (9)
1. a kind of circuit board, including the first dielectric layer, the first conductive circuit layer, bump pattern and the second dielectric layer, described first
Dielectric layer and the second dielectric layer are connected with each other, and first conductive circuit layer includes center packaging area and around center envelope
The surrounding package region in region is filled, the bump pattern, which is formed at the first dielectric layer, has the surface away from the second dielectric layer, institute
State bump pattern to be integrally formed with first dielectric layer, the shape of the bump pattern and the center packaging area and periphery
The intersection of packaging area is corresponding；The circuit board is adopted to be made with the following method：
Support plate is provided, the support plate has first surface；
From the first surface of the support plate groove pattern is formed into the support plate；
Bump pattern is formed in the groove pattern by pressing insulating materials, and simultaneously in the first surface formation the of support plate
One dielectric layer, first dielectric layer is integrally formed with the bump pattern；
The first conductive circuit layer is formed on the surface of first dielectric layer, first conductive circuit layer includes center encapsulation region
Domain and surrounding package region, the center packaging area and the intersection in surrounding package region are corresponding with the bump pattern；
The second dielectric layer is pressed in the first conductive circuit layer side；And
Remove the support plate.
2. circuit board as claimed in claim 1, it is characterised in that there are the multiple first contacts in the center packaging area
There are multiple second engagement pads in pad, the surrounding package region, after the support plate is removed, be additionally included in described first and be situated between
Multiple first openings and multiple second openings, each first opening, Mei Ge corresponding with the first engagement pad are formed with electric layer
Two openings are corresponding with the second engagement pad.
3. circuit board as claimed in claim 1, it is characterised in that pressed in the first conductive circuit layer side the second dielectric layer it
Afterwards, and before the support plate is removed, it is additionally included in side of second dielectric layer away from the first dielectric layer and forms the second conductor wire
Road floor.
4. circuit board as claimed in claim 3, it is characterised in that after the second conductive circuit layer is formed, and removing institute
State before support plate, be additionally included in the second conductive circuit layer side formation welding resisting layer, the welding resisting layer and be formed with perforate, part institute
State the second conductive circuit layer from the perforate to expose, form electrical connection pad.
5. circuit board as claimed in claim 1, it is characterised in that the support plate, which is adopted, to be formed from aluminium, the groove pattern is used
Laser ablation is formed, and the support plate is removed by the way of etching.
6. circuit board as claimed in claim 1, it is characterised in that there are the multiple first connections in the center packaging area
Pad, with multiple second connection gaskets in the surrounding package region, the bump pattern be formed at the first dielectric layer have it is remote
Multiple first openings and multiple second openings are formed with the surface of second dielectric layer, first dielectric layer, each first opens
Mouth is corresponding with the first engagement pad, and each second opening is corresponding with the second engagement pad.
7. circuit board as claimed in claim 1, it is characterised in that first dielectric layer, bump pattern and the second dielectric layer
Material it is identical.
8. circuit board as claimed in claim 1, it is characterised in that also including the second conductive circuit layer, second conductor wire
Road floor is formed at side of second dielectric layer away from the first conductive circuit layer.
9. circuit board as claimed in claim 4, it is characterised in that also including conductive hole, the conductive hole is formed at second Jie
In electric layer, first conductive circuit layer is mutually conducted with the second conductive circuit layer by the conductive blind hole.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710584291.7A CN107241862B (en) | 2013-06-26 | 2013-06-26 | Circuit board |
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310258688.9A CN104254190B (en) | 2013-06-26 | 2013-06-26 | The preparation method of circuit board |
| CN201710584291.7A CN107241862B (en) | 2013-06-26 | 2013-06-26 | Circuit board |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310258688.9A Division CN104254190B (en) | 2013-06-26 | 2013-06-26 | The preparation method of circuit board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN107241862A true CN107241862A (en) | 2017-10-10 |
| CN107241862B CN107241862B (en) | 2019-05-03 |
Family
ID=52188608
Family Applications (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310258688.9A Active CN104254190B (en) | 2013-06-26 | 2013-06-26 | The preparation method of circuit board |
| CN201710584291.7A Expired - Fee Related CN107241862B (en) | 2013-06-26 | 2013-06-26 | Circuit board |
Family Applications Before (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310258688.9A Active CN104254190B (en) | 2013-06-26 | 2013-06-26 | The preparation method of circuit board |
Country Status (2)
| Country | Link |
|---|---|
| CN (2) | CN104254190B (en) |
| TW (1) | TWI530240B (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI624011B (en) * | 2015-06-29 | 2018-05-11 | 矽品精密工業股份有限公司 | Package structure and the manufacture thereof |
| CN106356355B (en) * | 2015-07-15 | 2020-06-26 | 恒劲科技股份有限公司 | Substrate structure and manufacturing method thereof |
| TWI679926B (en) * | 2019-01-09 | 2019-12-11 | 欣興電子股份有限公司 | Substrate structure and manufacturing method thereof |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5413964A (en) * | 1991-06-24 | 1995-05-09 | Digital Equipment Corporation | Photo-definable template for semiconductor chip alignment |
| JPH1012671A (en) * | 1996-06-26 | 1998-01-16 | Ngk Spark Plug Co Ltd | Wiring board, manufacture thereof, wiring board mounted with board, and manufacture thereof |
| TW200515616A (en) * | 2003-10-21 | 2005-05-01 | Advanced Semiconductor Eng | Wafer structure for preventing contamination of bond pads during SMT process and process for the same |
| TWM450822U (en) * | 2012-10-08 | 2013-04-11 | Unimicron Technology Corp | Package substrate |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5343616B1 (en) * | 1992-02-14 | 1998-12-29 | Rock Ltd | Method of making high density self-aligning conductive networks and contact clusters |
| CN102281725B (en) * | 2010-06-10 | 2013-03-20 | 富葵精密组件(深圳)有限公司 | Manufacturing method for circuit board |
| TWI505765B (en) * | 2010-12-14 | 2015-10-21 | Unimicron Technology Corp | Wiring board and method for fabricating the same |
| TWI470759B (en) * | 2011-11-01 | 2015-01-21 | Unimicron Technology Corp | Package substrate and fabrication method thereof |
-
2013
- 2013-06-26 CN CN201310258688.9A patent/CN104254190B/en active Active
- 2013-06-26 CN CN201710584291.7A patent/CN107241862B/en not_active Expired - Fee Related
- 2013-06-28 TW TW102123339A patent/TWI530240B/en active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5413964A (en) * | 1991-06-24 | 1995-05-09 | Digital Equipment Corporation | Photo-definable template for semiconductor chip alignment |
| JPH1012671A (en) * | 1996-06-26 | 1998-01-16 | Ngk Spark Plug Co Ltd | Wiring board, manufacture thereof, wiring board mounted with board, and manufacture thereof |
| TW200515616A (en) * | 2003-10-21 | 2005-05-01 | Advanced Semiconductor Eng | Wafer structure for preventing contamination of bond pads during SMT process and process for the same |
| TWM450822U (en) * | 2012-10-08 | 2013-04-11 | Unimicron Technology Corp | Package substrate |
Also Published As
| Publication number | Publication date |
|---|---|
| TW201507564A (en) | 2015-02-16 |
| TWI530240B (en) | 2016-04-11 |
| CN104254190B (en) | 2017-12-01 |
| CN104254190A (en) | 2014-12-31 |
| CN107241862B (en) | 2019-05-03 |
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Effective date of registration: 20190409 Address after: 437199 Xianning Economic Development Zone, Hubei Province Applicant after: Hubei Yihong Precision Manufacturing Co., Ltd. Address before: 524299 No. 054 Xihu Avenue, Leicheng Town, Leizhou City, Zhanjiang City, Guangdong Province Applicant before: Gao Yun |
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