TWM508791U - Package substrate and chip package structure - Google Patents

Abstract

A package substrate includes a sensing layer, a conductive layer and a stacked-layer structure. The conductive layer has a first surface and a second surface opposite to each other, and the sensing layer is disposed on the first surface. The stacked-layer structure has a first dielectric layer, a first conductive pad, and a first circuit pattern layer, all disposed on the second surface. The dielectric layer has a third surface and a fourth surface opposite to each other, and a first conductive via. In addition, a chip package structure including the package substrate is also provided.

Description

Package substrate and chip package structure

The present invention relates to a package substrate, and more particularly to a coreless package substrate and a chip package structure using the package substrate.

In recent years, with the development of the technology industry, electronic products such as notebook computers (NB), tablet computers, and smart phones have been widely used in daily life. The types and functions of electronic products are becoming more and more diverse. Therefore, circuit boards and related packaging structures used in electronic products also play an important role in related technologies. In order to increase the application of the circuit board, many different kinds of electronic components, such as wafers, can be disposed on the circuit board by a suitable package technology to form a chip package structure and increase its use function.

In addition, in order to meet the packaging requirements of semiconductor chip package high integration and miniaturization, for more active and passive component level lines, the substrate of the semiconductor chip package structure gradually evolves from two layers to multiple layers. (multi-layer) to enable the use of inter-layer connection techniques in a limited space (interlayer connection) to expand the effective circuit layout area on the semiconductor package substrate to meet the high circuit density integrated circuit.

As shown in FIG. 1, in the fabrication of the current package substrate, generally starting from a core layer 12, a circuit layer 15 and a dielectric layer 16 are formed on the upper and lower surfaces of the core layer 12 to complete a core substrate. Then, the build-up substrate 18 conforming to the design application requirements is completed via the line build-up technique, and the solder resist layer 17 is applied to the partially exposed circuit layer 15. However, the through holes 13a and the pads 13b of the core layer 12 are limited in effective wiring space at a limited substrate thickness due to the limitation of the aspect ratio. In other words, the multilayer substrate produced by the above manufacturing method can increase the wiring space, but cannot effectively reduce the thickness of the entire package structure, and is disadvantageous in terms of thinning and miniaturization of the chip package structure. In particular, when the above-described package substrate 10 is applied to a chip package structure, the thickness of the entire device is increased, and the assembly demand and development trend of thinning and miniaturization of the mobile electronic device cannot be met.

The novel creation provides a package substrate that reduces substrate thickness and increases effective wiring space.

The novel creation provides a chip package structure that can effectively improve the accuracy of the fingerprint identification device.

The package substrate created by the present invention comprises a sensing layer, a conductive layer and a laminated structure. The conductive layer has a first surface and a second surface opposite to each other, and the sensing layer is disposed on the first surface of the conductive layer. The stacked structure has a first dielectric layer, A first conductive pad and a first patterned circuit layer are disposed on the second surface. The first dielectric layer has a first surface and a fourth surface, and a first conductive via, wherein the first dielectric layer covers the first conductive pad and the first patterned circuit layer.

In an embodiment of the present invention, the package substrate further includes a build-up structure disposed on the fourth surface of the laminate structure, the build-up structure having an opposite fifth surface and a sixth surface. The build-up structure includes at least one second dielectric layer, at least one second conductive via, and a plurality of second conductive pads and a second patterned circuit layer. The second dielectric layer is disposed on the fifth surface, and the second conductive via is disposed in the second dielectric layer. The plurality of second conductive pads and the second patterned circuit layer are disposed on at least the fifth surface and the sixth surface, wherein the first conductive via, the first conductive pad, the second conductive via, and one of the second conductive The pads are electrically connected to each other.

In an embodiment of the present invention, the package substrate further includes a first solder resist layer disposed on the sixth surface and covering the second conductive pad and a portion of the second patterned circuit layer. The first solder mask has an opening adapted to receive a wafer, and the opening exposes a portion of the second patterned wiring layer and a sixth surface of the portion buildup structure.

In an embodiment of the present invention, the package substrate further includes a plurality of solder balls disposed on the second patterned circuit layer partially exposed in the opening, wherein the wafer passes through the solder balls and the second patterns The circuit layer is electrically connected and adapted to receive sensing information from the sensing layer.

In an embodiment of the present invention, the package substrate further includes a package An encapsulant disposed on the sixth surface to encapsulate the wafer, the first solder mask, and a sixth surface of the buildup structure partially exposed within the opening.

In an embodiment of the present invention, the package substrate further includes a carrier plate disposed on the first surface of the conductive layer, and a release film disposed between the carrier and the conductive layer, wherein the carrier is separated by The film is removed from the first surface of the conductive layer.

In an embodiment of the present invention, the sensing layer is composed of a piezoelectric film.

In an embodiment of the present invention, the first conductive via and the second conductive via have a conductive material, and are electrically connected to the first and second conductive pads respectively by a conductive material.

The chip package structure created by the present invention comprises the above package substrate, at least one wafer and a plurality of solder balls. The wafer is disposed on the package substrate, and the solder balls are disposed on the second patterned circuit layer, wherein the wafer is electrically connected to each other through the solder balls and the second patterned circuit layer.

In an embodiment of the present invention, the wafer is a fingerprint identification chip, and the fingerprint recognition chip receives a fingerprint signal from the sensing layer and performs a fingerprint identification analysis.

Based on the above, the package substrate of the present invention includes a laminated structure, and may further include a build-up structure to become a coreless substrate without a core layer structure. As such, the thickness of the package substrate can be effectively reduced, and an effective wiring space is increased. In addition, the present invention can fabricate the above-mentioned package substrate on a carrier board, and arrange a release film between the package substrate and the carrier. After the package substrate is completed, it can be borrowed The carrier is removed by the release film to achieve a flat surface and the sensing layer is disposed thereon. Therefore, in the chip package structure using the package substrate, in addition to effectively reducing the thickness of the package structure and increasing the effective wiring space, the fingerprint identification wafer is soldered to the package substrate, and the sensing layer is disposed on the flat surface. When the fingerprint sensing surface unevenness factor is effectively reduced, the accuracy of fingerprint sensing and identification is effectively improved.

The above described features and advantages of the present invention will become more apparent and understood from the following description.

10, 100‧‧‧ package substrate

12‧‧‧ nuclear layer

13a‧‧‧through hole

13b‧‧‧ pads

15‧‧‧Line layer

16‧‧‧Dielectric layer

17‧‧‧ solder mask

18‧‧‧Additional substrate

50‧‧‧ Edition

60‧‧‧ release film

110‧‧‧Sense layer

120‧‧‧ Conductive layer

125a‧‧‧First conductive pad

125b‧‧‧First patterned circuit layer

130‧‧‧Laminated structure

133‧‧‧First dielectric layer

137‧‧‧First conductive via

140‧‧‧Additional structure

143‧‧‧Second dielectric layer

145a‧‧‧Second conductive pads

145b‧‧‧Second patterned circuit layer

146‧‧‧ solder balls

147‧‧‧Second conductive via

150‧‧‧First solder mask

152‧‧‧ openings

160‧‧‧Package colloid

200‧‧‧ wafer/fingerprint wafer

S1‧‧‧ first surface

S2‧‧‧ second surface

S3‧‧‧ third surface

S4‧‧‧ fourth surface

S5‧‧‧ fifth surface

S6‧‧‧ sixth surface

FIG. 1 is a schematic view of a conventional package substrate.

2 is a cross-sectional view showing a wafer package structure according to an embodiment of the present invention.

3 is a cross-sectional view showing a wafer package structure according to another embodiment of the present invention.

4A to FIG. 4I are schematic diagrams showing the fabrication process of the chip package structure and the package substrate of FIG.

2 is a cross-sectional view showing a wafer package structure of an embodiment of the present invention. Referring to FIG. 2, in the embodiment, the package substrate 100 includes a sensing layer 110, Conductive layer 120 and laminate structure 130. The conductive layer 120 has an opposite first surface S1 and a second surface S2, and the first conductive pad 125a and the first patterned circuit layer 125b are disposed on the second surface S2, and the sensing layer 110 is disposed on the conductive layer 120. A surface S1. The laminated structure 130 has a first dielectric layer 133 disposed on the second surface S2. The first dielectric layer 133 includes a third surface S3 and a fourth surface S4 and a first conductive via 137, and the first dielectric layer 133 covers the first conductive pad 125a and the first patterned wiring layer 125b. In addition, the stacked structure 130 of the present embodiment may further include a plurality of second conductive pads 145a and second patterned conductive layers 145b on the fourth surface S4. Moreover, the first solder resist layer 150 may be coated on the second conductive pad 145a and a portion of the second patterned circuit layer 145b to insulate and protect the circuit layer exposed on the stacked structure 130. In the present embodiment, the coated first solder resist layer 150 defines an opening 152 on the fourth surface S4, and the fourth surface S4 of the partial stacked structure 130 and a portion of the second patterned wiring layer 145b. Exposure to opening 152. In the present embodiment, the second patterned wiring layer 145b exposed in the opening 152 can serve as a ball bonding pad for connecting external electronic components. In detail, a plurality of solder balls 146 may be disposed on a portion of the second surface S4 that can be used as a ball bonding pad on the second patterned wiring layer 145b to solder external electronic components such as the wafer 200 to the aforementioned portion. The second patterned circuit layer 145b. In addition, the present embodiment may further configure the encapsulant 160 on the fourth surface S4 to completely separate the first solder mask 150, the wafer 200 in the opening 152 thereof, and the gap between the wafer 200 and the fourth surface S4. Covered with ground.

3 is a cross-sectional view of a wafer package structure in accordance with another embodiment of the present invention. In this embodiment, the package substrate of FIG. 3 further includes a buildup layer. The other components are the same as those of the package substrate of FIG. 2, and the same components are denoted by the same reference numerals, and the description of the same components is omitted. In the present embodiment, the package substrate 100 includes a build-up structure 140 disposed on the fourth surface S4 of the laminate structure 130, and the build-up structure 140 has opposite fifth and sixth surfaces S5 and S6. In detail, the build-up structure 140 includes a second dielectric layer 143 and a plurality of second conductive vias 147 disposed in the second dielectric layer 143 . In addition, the build-up structure 140 further includes a plurality of second conductive pads 145a and a plurality of second patterned conductive layers 145b disposed on the fifth surface S5, the sixth surface S6 of the build-up structure 140, and the stack of the build-up structures 140. The contact surface between the layers. In this embodiment, the first conductive vias 137, the first conductive pads 125a, the second conductive vias 147, and one of the second conductive pads 145a are electrically connected to each other. Furthermore, as shown in FIG. 2, the build-up structure 140 of the present embodiment has a two-layer laminate structure, but the present invention is not limited thereto. In other embodiments not shown, the build-up structure 140 The number of layers and thickness of the laminate can be varied depending on the actual wiring requirements.

In addition, in FIG. 3, the components on the sixth surface S6 of the build-up structure 140 of the package substrate 100 and their arrangement, and their associated functional descriptions are the components on the fourth surface S4 of the laminate structure 130 of FIG. The configuration is the same. Therefore, the novel creations herein will not be repeated.

Moreover, in the foregoing embodiment, the wafer 200 can be a fingerprint recognition wafer. The fingerprint identification wafer 200 can pass through the second patterned conductive layer 145b, the second conductive pad 145a, the second conductive via 147, the first conductive via 137 of the stacked structure 130, the first conductive pad 125a, and the conductive layer. 120 is electrically connected to the sensing layer 110. Further, the sensing layer 110 can sense and receive the fingerprint signal to transmit the fingerprint signal to the fingerprint recognition chip 200. In addition, the fingerprint recognition chip 200 can receive and analyze the fingerprint signal from the sensing layer 110 to identify the fingerprint features of the contact. In this embodiment, the sensing layer 110 can be, for example but not limited to, composed of a piezoelectric film to convert the pressure signal value generated from the fingerprint contact into an electrical signal for subsequent signal transmission and analysis.

Referring to FIG. 3 again, in the present embodiment, since the stacked structure 130 and the build-up structure 140 do not have the structure of the core layer 12 of FIG. Therefore, the first conductive via 137 and the second conductive via 147 of the embodiment are not limited by the high aspect ratio between the conductive via and the conductive pad in the core layer. Therefore, the stacked structure 130 and the build-up structure 140 of the present embodiment may have a relatively thin thickness. Therefore, the thickness of the wafer package structure using the package substrate 100 can be further reduced, and the line wiring space in the substrate can be effectively increased. Furthermore, applying the foregoing wafer package structure using the package substrate 100 to the package of the fingerprint recognition wafer 200 can effectively reduce the overall thickness of the fingerprint identification device (not shown), so that the fingerprint identification device can be applied to the current trend. Light and thin in various mobile electronic devices.

On the other hand, the materials of the first and second dielectric layers 133 and 143 in the foregoing embodiments may be, for example, ABF (Ajinomoto build-up film) resin, benzocyclobutene (BCB) resin, and light. Resistive material, polybenzoxazole (PBO), methyl silicone, ethyl silicone, cyclophenyl tannin, epoxy resin or polymer resin. In addition, the material of the first solder resist layer 150 may be, for example, but not limited to, a solder resist green paint, a resin or a viscous material or the like.

4A to FIG. 4I are schematic diagrams showing the fabrication process of the chip package structure and the package substrate of FIG. The fabrication flow of the package substrate of the present embodiment will be described below with reference to FIGS. 4A to 4I. However, the above drawings are merely illustrative and are not intended to limit the package substrate 100 provided by the present invention. First, as shown in FIG. 4A, a carrier 50 is provided, and a release film 60 is disposed on the carrier 50. Next, as shown in FIG. 4B, the conductive layer 120 is further disposed on the release film 60, wherein the conductive layer 120 has opposite first and second surfaces S1 and S2. Then, referring to FIG. 4C, the first conductive pad 125a and the first patterned circuit layer 125b are formed on the second surface S2 of the conductive layer 120. Next, referring to FIG. 4D, a first dielectric layer 133 is formed on the conductive layer 120, and the first conductive pad 125a and the first patterned circuit layer 125b are covered. In addition, the first dielectric layer 133 is penetrated through, for example, a laser drill or other suitable process to form an opening and expose a portion of the first conductive pad 125a. Then, a conductive material is disposed in the opening to form the first conductive via 137 and electrically connected to the first conductive pad 125a, wherein the conductive material may be, for example, but not limited to copper or other suitable conductive material. In this embodiment, the stacked structure 130 having the first dielectric layer 133, the first conductive pads 125a, the first patterned wiring layer 125b, and the first conductive vias 137 can be completed by the above process. Moreover, as shown in FIG. 4D, the first dielectric layer 133 of the stacked structure 130 has a third surface S3 and a fourth surface S4, and a second conductive pad 145a can be formed on the fourth surface S4. Circuit layer 145b.

As described above, the material of the first dielectric layer 133 of the present embodiment is, for example, an ABF resin material or other suitable dielectric material. The material of the first patterned conductive layer 125a and the first patterned circuit layer 125b is, for example, copper or other suitable conductive material. The material is formed on the second surface S2 of the conductive layer by, for example, an electroless plating process or other suitable process. Next, referring to FIG. 4E, after the foregoing stacked structure 130 is completed, the build-up structure 140 may be formed on the stacked structure 130. In this embodiment, the build-up structure 140 may be stacked in a stack of one or more layers. Although the build-up structure 140 of the present invention is composed of a two-layer laminated structure as shown in FIG. 4E, the novel creation is not limited thereto, and the number of layers of the build-up structure 140 can be adjusted and configured according to actual wiring requirements. The first dielectric layer 133 of the stacked structure 130 is placed to increase the layout space of the chip package structure. Further, the build-up structure 140 of the present embodiment has a fifth surface S5 and a sixth surface S6, wherein the fifth surface S5 and the fourth surface S4 of the first dielectric layer 133 are in contact with each other. In this embodiment, the build-up structure includes two layers of the second dielectric layer 143 respectively disposed with at least one second conductive pad 145a and the second patterned circuit layer 145b. In addition, the build-up structure 140 further includes a plurality of second conductive vias 147 electrically connected to the second conductive pads 145a and the second patterned circuit layer 145b. Further, in the embodiment, the second conductive vias 147 and the second conductive pads 145a of the build-up structure 140 and the first conductive vias 137 and the first conductive pads 125a of the stacked structure 130 are electrically connected to each other. Sexual connection. On the other hand, the process of forming the second patterned circuit layer 145b, the second conductive pads 145a, and the second conductive vias 147 of the build-up structure 140 of the present embodiment and the first patterned circuit layer in the stacked structure 130 The first conductive pad 125a and the first conductive via 137 are the same. Therefore, the novel creations will not be repeatedly described herein.

Referring to FIG. 4E again, in the embodiment, the second conductive pad 145a and the second patterned circuit layer 145b are formed on the sixth surface S6 of the build-up structure 140. Connect A first solder resist layer 150 for insulating protection is applied on the second conductive pad 145a and a portion of the second patterned circuit layer 145b, wherein the first solder resist layer 150 may be, for example but not limited to, a green paint material. . In the present embodiment, the first solder resist layer 150 defines and forms an opening 152 on the sixth surface S6 of the build-up structure 140, and a portion of the second patterned wiring layer 145b is exposed in the opening 152 as an external electron. Ball bonding pads for components. In detail, referring to FIG. 4F, in the embodiment, a plurality of solder balls 146 may be further disposed in the opening 152 and as the second patterned circuit layer 145b of the ball bonding pad to be, for example, External electronic components such as the wafer 200 are soldered to the package substrate 100. In addition, as described above, the wafer 200 of the embodiment may be a fingerprint identification chip for receiving and analyzing the fingerprint signal.

Further, referring to FIG. 4G, after the fingerprint identification wafer 200 is soldered to the package substrate 100, the fingerprint identification wafer 200, the first solder resist layer 150, and the first solder resist layer 150 are then overmolded by the encapsulant 160. The fingerprint identifies the gap between the wafer 200 and the sixth surface S6 exposed within the opening 152. Then, as shown in FIG. 4H, after the injection molding step is completed, the carrier 50 can be removed from the package substrate 100 by the release film 60 through a simple cutting step. In the present embodiment, the configuration time required to remove the carrier 50 can be reduced by the configuration of the release film 60, and the complexity of the process can be further reduced. In addition, after the release film 60 is removed, the present embodiment may remove the residue remaining on the first surface S1 after the release film 60 is removed, for example, but not limited to plasma etching, so that the conductive layer 120 is removed. The first surface S1 becomes a highly flat surface after the carrier 50 is removed.

Finally, as shown in FIG. 4I, after the carrier 50 is removed, the conductive layer can be A sensing layer 110 for contacting and receiving a fingerprint signal is formed on the first surface S1 of 120. In this embodiment, the sensing layer 110 disposed on the first surface S1 can be patterned by the first and second conductive pads 125a, 145a, the first and second layers in the stacked structure 130 and the build-up structure 140. The circuit layers 125b and 145b and the first and second conductive vias 137 and 147 are electrically connected to the fingerprint identification chip 200 to transmit the fingerprint contact sensing signals received by the sensing layer 110 to the fingerprint recognition wafer 200. In addition, as described above, the sensing layer 110 of the present embodiment may be, for example but not limited to, composed of a piezoelectric film to convert the pressure signal generated by the fingerprint into an electrical signal. In the present embodiment, since the first surface S1 of the conductive layer 120 removes the carrier 50 by the release film 60 and removes the residual glue by etching, it can become a highly flat surface. Therefore, the sensing layer 110 is disposed on the first surface S1 to have good flatness, and the interference of the fingerprint sensing surface unevenness factor can be reduced or eliminated, so that the fingerprint sensing of the sensing layer 110 and the overall fingerprint identification device are accurately identified. Degrees have been further improved.

In summary, the package substrate provided by the novel creation has a laminated structure, and may further include a build-up structure, wherein the build-up structure may include a plurality of layers of alternately stacked laminate structures to increase the wiring space of the circuit layer. In addition, due to the coreless layer structure of the package substrate created by the novel, the conductive via and the conductive pad created by the novel are not limited to the high aspect ratio configuration of the conventional core substrate, and the package of the novel creation is made. The substrate has a relatively thin thickness and can accommodate a stack of more layers under the same thickness space, and has more wiring space. Therefore, applying the foregoing package substrate to a package such as a fingerprint recognition wafer can further reduce the thickness of the entire chip package structure and facilitate the aforementioned fingerprint recognition crystal The package structure of the chip is applied to mobile electronic devices that are currently becoming thinner and lighter. In addition, since the manufacturing method of the present invention is to form a package substrate on a carrier having a release film configuration, after the package substrate is completed, the carrier can be removed by a release film and etched. The residual glue is removed so that the surface after removal of the carrier can have good flatness. Furthermore, the sensing layer applied to the sensing fingerprint, for example, is disposed on the aforementioned flat surface, which can reduce or eliminate the interference of the fingerprint sensing surface unevenness factor, and further improve the accuracy of fingerprint sensing and identification.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the novel creation, and any person skilled in the art can make some changes without departing from the spirit and scope of the novel creation. Retouching, the scope of protection of this new creation is subject to the definition of the scope of the patent application attached.

100‧‧‧Package substrate

110‧‧‧Sense layer

120‧‧‧ Conductive layer

125a‧‧‧First conductive pad

125b‧‧‧First patterned circuit layer

130‧‧‧Laminated structure

133‧‧‧First dielectric layer

137‧‧‧First conductive via

145a‧‧‧Second conductive pads

145b‧‧‧Second patterned circuit layer

146‧‧‧ solder balls

150‧‧‧First solder mask

152‧‧‧ openings

160‧‧‧Package colloid

200‧‧‧ wafer/fingerprint wafer

S1‧‧‧ first surface

S2‧‧‧ second surface

S3‧‧‧ third surface

S4‧‧‧ fourth surface

Claims (10)

A package substrate comprising: a sensing layer; a conductive layer having an opposite first surface and a second surface, wherein the sensing layer is disposed on the first surface of the conductive layer; and a laminated structure The laminated structure has a first dielectric layer, a first conductive pad and a first patterned circuit layer, all disposed on the second surface, and the first dielectric layer has a third surface opposite to a fourth surface and a first conductive via, wherein the first dielectric layer covers the first conductive pad and the first patterned circuit layer. The package substrate of claim 1, further comprising at least one build-up structure disposed on the fourth surface of the laminate structure, the build-up structure having a fifth surface and a sixth surface opposite to each other And the layered structure includes: at least one second dielectric layer disposed on the fifth surface; at least one second conductive via disposed in the second dielectric layer; and a plurality of second conductive pads And the second patterned circuit layer is disposed on the fifth surface and the sixth surface, wherein the first conductive via, the first conductive pad, the at least one second conductive via, and one of the plurality The second conductive pads are electrically connected to each other. The package substrate of claim 2, further comprising a first solder resist layer disposed on the sixth surface and covering the second conductive pad and a portion of the second patterned circuit layer, The first solder mask has an opening adapted to receive a wafer, and the opening exposes a portion of the second patterned wiring layer and a portion of the sixth surface of the buildup structure. The package substrate of claim 3, further comprising a plurality of solder balls disposed on the second patterned circuit layer partially exposed in the opening, wherein the wafer transmits the solder balls and the plurality of solder balls The second patterned circuit layer is electrically connected and adapted to receive sensing information from the sensing layer. The package substrate of claim 3, further comprising an encapsulant disposed on the sixth surface to encapsulate the wafer, the first solder mask, and the portion of the wafer exposed to the opening a gap between the sixth surfaces. The package substrate of claim 1, further comprising a carrier disposed on the first surface of the conductive layer, and a release film disposed between the carrier and the conductive layer, wherein the package The carrier is removed from the first surface of the conductive layer by the release film. The package substrate according to claim 1, wherein the sensing layer is composed of a piezoelectric film. The package substrate of claim 2, wherein the first conductive via and the second conductive via respectively have a conductive material, and the first and second conductive vias are respectively separated by the conductive material The first and second conductive pads are electrically connected to each other. A chip package structure comprising: the package substrate according to claim 1; at least one wafer disposed on the package substrate; and a plurality of second conductive pads and a second patterned circuit layer disposed on the first And a plurality of solder balls disposed on the second patterned circuit layer, wherein the wafer is electrically connected to the second patterned circuit layer through the solder balls. The chip package structure of claim 9, wherein the wafer is a fingerprint identification chip, the fingerprint recognition chip receives a fingerprint signal from the sensing layer, and performs a fingerprint identification analysis.