CN105226031A - Substrate, its semiconductor packages and manufacturing process thereof - Google Patents

Substrate, its semiconductor packages and manufacturing process thereof Download PDF

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Publication number
CN105226031A
CN105226031A CN201410312237.3A CN201410312237A CN105226031A CN 105226031 A CN105226031 A CN 105226031A CN 201410312237 A CN201410312237 A CN 201410312237A CN 105226031 A CN105226031 A CN 105226031A
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China
Prior art keywords
circuit layer
protuberance
conductive
layer
conductive trace
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CN201410312237.3A
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Chinese (zh)
Inventor
陈天赐
王圣民
陈光雄
李育颖
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Advanced Semiconductor Engineering Inc
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Advanced Semiconductor Engineering Inc
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Priority to CN201410312237.3A priority Critical patent/CN105226031A/en
Publication of CN105226031A publication Critical patent/CN105226031A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/486—Via connections through the substrate with or without pins
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4857—Multilayer substrates
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
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    • H01L2224/4805—Shape
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    • H01L2224/48091—Arched
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
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    • H01L2224/732—Location after the connecting process
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    • H01L2224/73265—Layer and wire connectors
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822—Multilayer substrates
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
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    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15313—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a land array, e.g. LGA
    • H—ELECTRICITY
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Manufacturing Of Printed Circuit Boards (AREA)

Abstract

The invention provides a kind of substrate, its semiconductor packages and manufacturing process thereof.Described substrate comprises: lower circuit layer, has lower surface; Upper circuit layer, is placed on described lower circuit layer; Dielectric layer, between described upper circuit layer and described lower circuit layer, and defines multiple opening; And conductive connecting material, be arranged in described opening; The part of wherein said upper circuit layer extends to described opening, and is connected with described lower circuit layer by described conductive connecting material.

Description

Substrate, its semiconductor packages and manufacturing process thereof
Technical field
The present invention relates to a kind of substrate for semiconductor packages and manufacturing process thereof.
Background technology
When current making comprises the substrate of two sandwich circuits or more, several mode below normal use does electrically conducting between line layer: (1) first utilizes machine drilling mode to get out through hole, and recycling electroless copper (chemical copper) and electro-coppering form the hole that electrically conducts; (2) first utilize laser to get out blind hole, recycling electroless copper (chemical copper) and electro-coppering form the blind hole that electrically conducts; (3) first utilize laser to get out blind hole, recycling physical vapour deposition (PVD) mode deposited copper and electro-coppering form the blind hole that electrically conducts; And (4) first utilize machinery/laser mode to get out through hole, then formation conductive pole refills tin material to form electric connection part in through-holes.But no matter be utilize machinery or laser mode boring, its manufacturing cost is high and boring can produce scrap, easily affects successive process yield; In addition, if utilize chemical copper or electro-coppering processing procedure, in chemical copper groove or electroplating bath unpredictable and changeable copper facing parameter often can cause excessively plating or plating not enough, adverse influence is produced to conductance efficiency, and its processing procedure cost is also high; And utilizing conductive pole to add, filling tin material is to be formed in the technology of electric connection part, and tin material often can cause tin material to overflow because of exposing surface and form short circuit in the process contacted with upper wiring layer pressing.Therefore, new structure and manufacture craft are wished in the substrate Ji making two sandwich circuits or more at present, and the phase can overcome one or more above problem.
Summary of the invention
One embodiment of the invention relate to a kind of substrate, and it comprises: lower circuit layer, has lower surface; Upper circuit layer, is placed on described lower circuit layer; Dielectric layer, between described upper circuit layer and described lower circuit layer, and defines multiple opening; And conductive connecting material, be arranged in described opening; The part of wherein said upper circuit layer extends to described opening, and is connected with described lower circuit layer by described conductive connecting material.
Another embodiment of the present invention relates to a kind of semiconductor packages, and it comprises: substrate, and described substrate comprises: lower circuit layer, has lower surface; Upper circuit layer, is placed on described lower circuit layer; Dielectric layer, between described upper circuit layer and described lower circuit layer, and defines multiple opening; And conductive connecting material, be arranged in described opening, the part of wherein said upper circuit layer extends to described opening, and is connected with described lower circuit layer by described conductive connecting material; And chip, be electrically connected at described upper circuit layer.
Another embodiment of the present invention relates to a kind of technique manufacturing substrate, and it comprises: provide lower circuit layer, and described lower circuit layer comprises conductive trace and protuberance; Form dielectric layer to cover described conductive trace and described protuberance, wherein said dielectric layer has opening to expose described protuberance; Form conductive connecting material on the described described protuberance exposed; Settle conductive foil on described dielectric layer; And conductive foil described in patterning, to form upper circuit layer.
Accompanying drawing explanation
Fig. 1 shows the schematic diagram of an embodiment of substrate of the present invention.
Fig. 2 shows the enlarged drawing of Fig. 1 substrate regional area.
Fig. 3 shows the schematic diagram of an embodiment of semiconductor packages of the present invention.
Fig. 4 shows the schematic diagram of another embodiment of semiconductor packages of the present invention.
Fig. 5 A to 5X shows the schematic diagram of an embodiment of the manufacturing process of substrate of the present invention.
Embodiment
The specification of this case and graphic only for explaining the present invention, is not intended to limit interest field of the present invention; In addition, graphic middle the illustrated each technical characteristic of this case and element are only for making the technology personage in field of the present invention more understand the present invention, its size illustrated and corresponding relation thereof may not represent its actual relationship, the technology personage in field of the present invention, when the claims that can provide according to this case, invention description and graphic, understand the invention scope that this case claims are contained, interest field of the present invention is when being as the criterion with this case claims, and the technology personage containing field of the present invention is from the specification of this case and graphic the scope that can rationally know by inference.
Please refer to Fig. 1, the schematic diagram of an embodiment of its display substrate of the present invention.Described substrate 1 can comprise supporting layer 3, be positioned at lower protective layer 5 above supporting layer 3, be positioned at lower circuit layer 8 above lower protective layer 5 and dielectric layer 9, be positioned at upper circuit layer 11 above lower circuit layer 8 and dielectric layer 9 and up-protective layer 13.Described upper circuit layer 11 has multiple upper conductive trace 14, and described lower circuit layer 8 has multiple lower conductive trace 7, and wherein said lower circuit layer 8 has more a protuberance 15, and described protuberance 15 is given prominence to from described lower conductive trace 7; Have a conductive connecting material 17 between described protuberance 15 and described upper conductive trace, described whereby lower conductive trace 7 can be electrically connected with described upper conductive trace 14.Although described substrate 1 is illustrated as have two-tier circuit layer, in other embodiments, described substrate 1 can utilize similar arrangement to form three layers, four layers, five layers or more circuit layers.
Described supporting layer 3 can be metal level, for providing lower circuit layer 8 and upper circuit layer 11 bracing force, strengthens substrate strength in order to during follow-up upper chip package routing.
Described lower protective layer 5 is placed on the back side 7b of lower circuit layer 8.Described lower protective layer 5 can have the part that at least one opening 5c manifests the described lower circuit layer 8 of part; the part wherein appeared can be used as ball pad (ballpad); such as ball grid array end points (ballgridarrayterminal); with spherical grid array (ballgridarray) soldered ball 28 (asking for an interview Fig. 3) formed thereon, connect for exposed electrical.In certain embodiments, described lower protective layer 5 can be extra dielectric layer or welding resisting layer (solderresist or soldermask).The material of described lower protective layer 5 such as can be but is not limited to polyimides.
Described lower circuit layer 8 is positioned on described lower protective layer 5, and described lower circuit layer 8 has multiple lower conductive trace 7, and dielectric layer 9 can be utilized each other to separate.In addition described protuberance 15 itself is integrally formed with described lower conductive trace 7, therefore structural strength is higher.The side of described protuberance 15 and the side of described lower conductive trace 7 all concave, or described protuberance 15 and described lower conductive trace 7 have a concave side respectively, and described concave side is towards described upper circuit layer 11.As long as the material of described lower circuit layer 8 be applicable to as circuit person all can, such as but not limited to copper.
As long as the material of described conductive connecting material 17 can conduct electricity all can, such as but not limited to tin, copper, nickel or its combination.Described conductive connecting material can utilize dipping, plating, chemical plating, printing or alternate manner to be formed.In certain embodiments, described conductive connecting material 17 utilizes dipping or mode of printing to be formed on the protuberance 15 of described lower circuit layer 8, to be electrically connected with described upper circuit layer 11.As shown in Figure 2, when described conductive connecting material 17 is formed, its surperficial 17a is not more than or equal in fact in fact the average height h of surperficial 7a to the surperficial 17a of described conductive connecting material 17 of described track section 7 on average higher than the average height H of the surperficial 9a of (being less than or equal to) dielectric layer 9 or surperficial 9a of described dielectric layer 9 to the surperficial 7a of described track section 7.
Described dielectric layer 9 is positioned at described dielectric layer 9 around the lower conductive trace 7 of described lower circuit layer 8 and protuberance 15 or described lower circuit layer 8.The lower surface 7b of a described lower conductive trace 7 and surperficial 9b of described dielectric layer 9 is in fact in same plane.Described dielectric layer 9 has opening 9c, to manifest the protuberance 15 of described lower circuit layer 8, is electrically connected by the upper conductive trace 14 of conductive connecting material 17 with upper circuit layer 11 to make described protuberance 15.The material of described dielectric layer 9 can be photosensitive type dielectric layer, such as, be made up of photosensitive type non-conductive polymer.Described photosensitive type non-conductive polymer such as can be selected from but be not limited to: polyphenyl dioxazole (polyparaphenylenebenzobisoxazole, PBO), polyimides, benzyl ring butylene or its combination etc., whereby, dielectric layer 9 can utilize photoetching and etch process to form the protuberance 15 manifesting described lower circuit layer 8.In certain embodiments, described dielectric layer 9 can utilize rotary coating, spray coating or laminar manner formation.
Described upper circuit layer 11 is positioned on described dielectric layer 9, and described upper circuit layer 11 has multiple upper conductive trace 14, can be separated by each other with up-protective layer 13.At least one conductive trace 14 of described upper circuit layer 11 is electrically connected with the protuberance 15 of described lower circuit layer 8 by described conductive connecting material 17.As previously mentioned, surperficial 17a because of described conductive connecting material 17 is not more than or equal in fact in fact the average height h of surperficial 7a to the surperficial 17a of described conductive connecting material 17 of described track section 7 on average higher than the average height H of the surperficial 9a of (being less than or equal to) dielectric layer 9 or surperficial 9a of described dielectric layer 9 to the surperficial 7a of described track section 7, when described upper circuit layer 11 utilize lamination with in the opening 9c making portion lower surface 14b extend to described dielectric layer 9 and fit tightly with described conductive connecting material 17 time, so can reduce conductive connecting material 17 because overflowing caused short circuit or splash pollution problem by lamination.As long as the material of described upper circuit layer 11 be applicable to as circuit person all can, such as but not limited to copper.Except upper conductive trace 14, described upper circuit layer 11 separately can comprise connection pad.
Described up-protective layer 13 covers described upper circuit layer 11, and has at least one opening to manifest the described upper circuit layer 11 of part, and the part wherein appeared is connection pad 24 (asking for an interview Fig. 3), connects for bonding wire 21.In certain embodiments, described up-protective layer 13 can be extra dielectric layer or welding resisting layer (solderresist or soldermask).The material of described up-protective layer 13 such as can be but is not limited to polyimides.
With reference to figure 3, the schematic diagram of an embodiment of its display semiconductor packages of the present invention.Described semiconductor packages 4 comprises described substrate 1, chip 19, adhesion coating 20, connection pad 24 and many bonding wires 21.Described chip 19 is attached to described substrate 1 by adhesion coating 20, and described connection pad 24 is formed in the opening of described up-protective layer 13, connects for bonding wire 21.In certain embodiments, described chip 19 can be utilized and cover crystal type and be electrically connected with the upper circuit layer 11 of described substrate 1 by the upper conductive trace 14 of the described upper circuit layer 11 that exposes.
Encapsulating material 23 is comprised with reference to the semiconductor packages 4 shown in figure 4, Fig. 3.Described encapsulating material 23 is positioned on described up-protective layer 13, around described chip 19 and adhesion coating 20.In some embodiments, multiple soldered ball can after removing metal forming 3, is formed at the part of the described lower circuit layer 8 that the described opening 22 that is revealed in described lower protective layer 5 exposes to connect as exposed electrical.
With reference to figure 5A to 5X, show the schematic diagram of an embodiment of the manufacturing process of substrate of the present invention.
With reference to figure 5A, provide a carrier 2, described carrier 2 can have the first supporting layer 3a (as metal forming) thereon on the surface and the second supporting layer 3b (as metal forming) on its lower surface.
With reference to figure 5B, formed the first lower protective layer 25a on described first supporting layer 3a and formed the second lower protective layer 25b on described second supporting layer 3b.Described first lower protective layer 25a and described second lower protective layer 25b can be formed simultaneously.With reference to figure 5C; first lower protective layer 25a described in patterning and described second lower protective layer 25b is to form one first patterning lower protective layer 26a and one second patterning lower protective layer 26b respectively; wherein said first patterning lower protective layer 26a and described second patterning lower protective layer 26b defines at least one opening (28a, 28b) that lower conductive trace can be connected with exposed electrical.Described patterning process is reached by photoetching process.Described patterning first lower protective layer 26a and patterning second lower protective layer 26b can be formed simultaneously.
With reference to figure 5D, arrange that first time conductive foil 27a is on described first patterning lower protective layer 26a, and arrange that second time conductive foil 27b is on described second patterning lower protective layer 26b.Can utilize pressing (press) or other processing procedure of described first time conductive foil 27a and described second time conductive foil 27b are arranged on described protective layer.In certain embodiments, described first time conductive foil 27a utilizes lamination (lamination) Copper Foil to be formed on described first patterning lower protective layer 26a.Similarly, described second time conductive foil 27b can utilize lamination (lamination) Copper Foil to be formed on described first patterning lower protective layer 26b.
With reference to figure 5E, to be formed on first dry film 29a in described first time conductive foil 27a on and formation first time dry film 29b on described second time conductive foil 27b.With reference to figure 5F, dry film 29a and described first time dry film 29b on first described in patterning, to define the position for forming described protuberance 15 at described first time conductive foil 27a and described second time conductive foil 27b respectively.Described patterning first on dry film 29a and first time dry film 29b appear the described first time conductive foil 27a of part and described second time conductive foil 27b.Described patterning process is reached by photoetching process.Described patterning first on dry film 31a and described first time dry film 31b can be formed simultaneously.
With reference to figure 5G, remove described first time conductive foil 27a of part and described second time conductive foil 27b, to form protuberance 53a and 53b at dry film 31a on first of described patterning and described first time dry film 31b covering place respectively.Described first time conductive foil 27a and described second time conductive foil 27b removes by etching or alternate manner, and can carry out simultaneously.With reference to figure 5H, remove described patterning first on dry film 31a and described first time dry film 31b, as shown in the figure, described protuberance 53a and 53b protrudes from the surface of described first time patterning conductive foil 30a and described second time patterning conductive foil 30b respectively.As shown in the partial enlarged drawing of Fig. 5 P or Fig. 5 R, in certain embodiments, described first time patterning conductive foil 30a and described second time patterning conductive foil 30b is removed by etching direction from top to bottom, therefore produced protuberance 53a and 53b both sides all concave, and such as it can present from top to bottom toward interior arc.
With reference to figure 5I, to be formed on second dry film 33a in described first time patterning conductive foil 30a on and formation second time dry film 33b on described second time patterning conductive foil 30b, cover described lower patterning conductive foil and protuberance.With reference to figure 5J, dry film 33a and described second time dry film 33b on second described in patterning, to define in described first time patterning conductive foil 30a and described second time patterning conductive foil 30b for forming the part of lower conductive trace and/or connection pad.Described patterning second on second time dry film 35b of dry film 35a and described patterning manifest the described first time patterning conductive foil 30a of part and described second time patterning conductive foil 30b respectively.Described patterning process is reached by photoetching process.Described patterning second on second time dry film 35b of dry film 35a and described patterning can be formed simultaneously.
With reference to figure 5K, remove described first time patterning conductive foil 30a of part and described second time patterning conductive foil 30b, with the lower conductive trace of the lower conductive trace 57a and/or connection pad and second time circuit layer 8b that form first time circuit layer 8a and/or connection pad 57b.Described first time patterning conductive foil 30a and described second time patterning conductive foil 30b removes by etching or alternate manner, and can carry out simultaneously.With reference to figure 5L, remove described patterning second on second time dry film 35b of dry film 35a and described patterning, to complete the making of lower circuit layer.
As shown in the partial enlarged drawing of Fig. 5 P or Fig. 5 R, in certain embodiments, described first time patterning conductive foil 30a and described second time patterning conductive foil 30b removes to form lower conductive trace by etching direction from top to bottom, and remove by the etching of this direction lower conductive trace 57a both sides that described first time patterning conductive foil 30a and described second time patterning conductive foil 30b produce and lower conductive trace 57b both sides all concave, such as it can present from top to bottom toward interior arc.
In certain embodiments, described lower conductive trace and described protuberance remove lower patterning conductive foil and lower conductive foil by same etching direction respectively and are formed.In other words, as shown in Fig. 5 P, remove by equidirectional etching protuberance 53a both sides that described first time conductive foil 27a and lower patterning conductive foil 30a produce and lower conductive trace 57a both sides have similar structure.Such as, protuberance 53a both sides and lower conductive trace 57a both sides have the arc that can present from top to bottom toward interior.
With reference to figure 5M, formed the first dielectric layer 37a on described protuberance 53a and described lower conductive trace 8a and formed the second dielectric layer 37b on described protuberance 53b and described lower conductive trace 8b.In certain embodiments, described dielectric layer can utilize rotary coating, spray coating or laminar manner formation.With reference to figure 5N, utilize lithographic process to make described first dielectric layer 37a form opening 39a in the protuberance 53a place of described lower conductive trace 57a, and make the second dielectric layer 37b form opening 39b in the described protuberance 57b place of described lower conductive trace 53b.
With reference to figure 5O and 5P (Fig. 5 P is the partial enlarged drawing of specific region in Fig. 5 O), form conductive connecting material 51a in the opening 39a of the first dielectric layer 37a and formation conductive connecting material 51b in the opening 39b of the second dielectric layer 37b.The surface of described conductive connecting material 51a in fact not higher than (being less than or equal to) first dielectric layer 37a surface and the surface of described conductive connecting material 51b in fact not higher than (being less than or equal to) second surface of dielectric layer 37b;
Or the surface of described dielectric layer 37a is more than or equal in fact the average height h of surface to the surperficial 39a of described protuberance 53a of described conductive connecting material 51a to the average height H on the surface of described lower conductive trace 57a, and the surface of described dielectric layer 37b is more than or equal in fact the average height of surface to the surface of described protuberance 53b of described conductive connecting material to the average height on the surface of described lower conductive trace 57b.Described conductive connecting material is formed at the opening of described first dielectric layer 37a and described second dielectric layer 37b by dipping, plating, chemical plating, printing or alternate manner.
With reference to figure 5Q and 5R, arrange that on first, conductive foil 41a is on described first dielectric layer 37a and conductive connecting material 51a, and arrange that on second, conductive foil 41b is on described second dielectric layer 37b and conductive connecting material 51b, on wherein said first, on conductive foil 41a and described second, conductive foil 41b can utilize lamination (such as high-temperature laminating or low temperature pressing) or alternate manner to contact with conductive connecting material respectively, and then is electrically connected protuberance and lower conductive trace.In cause first, conductive foil 41a is by laminar manner and described conductive material contacts, and the surface on the surface of described conductive connecting material 51a is not in fact higher than (being less than or equal to) first surface of dielectric layer 37a, therefore the part of conductive foil 41a can extend to because of laminar manner in the first dielectric layer 37a on first.On described second, conductive foil 41b can utilize aforementioned same mode to be formed on described second dielectric layer 37b and conductive connecting material 51b.
With reference to figure 5S, to be formed on the 3rd dry film 43a on described first conductive foil 41a on and formation the 3rd time dry film 43b on described second on conductive foil 41b.With reference to figure 5T, dry film 43a and described 3rd time dry film 43b on the 3rd described in patterning, conductive foil 41b to define conductive foil 41a and described second position for forming conductive trace and/or connection pad respectively on described first.Described patterning the 3rd on the 3rd time dry film 45b of dry film 45a and described patterning to appear in part described second conductive foil 41b on conductive foil 41a and described second respectively.Described patterning process is reached by photoetching process.Described patterning the described 3rd on dry film 45a and described 3rd time dry film 45b can be formed simultaneously.
With reference to figure 5U, remove part described first on conductive foil 41b on conductive foil 41a and described second, with formed in dry film 45a covering place on the described 3rd of described patterning the upper conductive trace of circuit layer 11a and/or connection pad and described 3rd time dry film 45b covering place formed circuit layer 11b multiple on conductive trace and/or connection pad.At least one described multiple upper conductive trace and/or connection pad correspond at least one described lower conductive trace and/or connection pad, and are electrically connected by described conductive connecting material and at least one lower conductive trace and/or connection pad.On described second, on conductive foil 41a and described second, conductive foil 41b removes by etching mode, and can carry out simultaneously.
With reference to figure 5V, formed the first up-protective layer 47a on described upper circuit layer 11a and formed the second up-protective layer 47b on described upper circuit layer 11b.Described first up-protective layer 47a and described second up-protective layer 47b inserts opening that described upper conductive trace 49a defines and the opening that described upper conductive trace 49b defines respectively.Described first up-protective layer 47a and described second up-protective layer 47b can be formed simultaneously.Then, opening is formed, to define the part that can be connected with exposed electrical, as connection pad etc. at described first up-protective layer 47a and described second up-protective layer 47b.Described opening appears the described upper conductive trace 49a of part and described upper conductive trace 49b respectively.Described opening can utilize photoetching process to be formed.Described first up-protective layer 47a and described second up-protective layer 47b can form opening simultaneously.Then, remove dry film 43a and described 3rd time dry film 43b on the described 3rd, just form two substrates in described carrier 2 both sides.
With reference to figure 5W and 5X, unload described two panels substrate 1a and 1b from described carrier 2.
Above-described embodiment is only effect that principle of the present invention is described, and is not used to limit the present invention.Therefore, the personage practised in this technology modifies to above-described embodiment and changes still de-spirit of the present invention.

Claims (20)

1. a substrate, it comprises:
Lower circuit layer, has lower surface;
Upper circuit layer, is placed on described lower circuit layer;
Dielectric layer, between described upper circuit layer and described lower circuit layer, and defines multiple opening; And
Conductive connecting material, is arranged in described opening;
The part of wherein said upper circuit layer extends to described opening, and is connected with described lower circuit layer by described conductive connecting material.
2. substrate according to claim 1, wherein said lower circuit layer has conductive trace and protuberance, and described protuberance is given prominence to from described conductive trace.
3. substrate according to claim 2, wherein said conductive trace and described protuberance are integrally formed.
4. substrate according to claim 2, wherein said conductive connecting material is positioned on described protuberance.
5. substrate according to claim 2, the side of wherein said protuberance and the side of described conductive trace all concave.
6. substrate according to claim 2, wherein said protuberance and described conductive trace have concave side respectively, and described concave side is towards described upper circuit layer.
7. substrate according to claim 1, wherein said dielectric layer is photosensitive type dielectric layer.
8. substrate according to claim 1, the lower surface of wherein said lower circuit layer and the surface of described dielectric layer are positioned at same plane.
9. substrate according to claim 1, protective layer is settled further in the surface of wherein said dielectric layer.
10. substrate according to claim 9, wherein said protective layer has supporting layer to be settled thereon.
11. 1 kinds of semiconductor packages, it comprises:
Substrate, described substrate comprises:
Lower circuit layer, has lower surface;
Upper circuit layer, is placed on described lower circuit layer;
Dielectric layer, between described upper circuit layer and described lower circuit layer, and defines multiple opening; And
Conductive connecting material, is arranged in described opening, and the part of wherein said upper circuit layer extends to described opening, and is connected with described lower circuit layer by described conductive connecting material; And
Chip, is electrically connected at described upper circuit layer.
12. semiconductor packages according to claim 11, wherein said lower circuit layer has conductive trace and protuberance, and described protuberance is given prominence to from described conductive trace.
13. semiconductor packages according to claim 12, wherein said conductive trace and described protuberance are integrally formed.
14. semiconductor packages according to claim 12, wherein said conductive connecting material is positioned on described protuberance.
15. semiconductor packages according to claim 11, the lower surface of wherein said lower circuit layer and the surface of described dielectric layer are positioned at same plane.
16. semiconductor packages according to claim 11, wherein said protuberance and described conductive trace have concave side respectively, and described concave side is towards described upper circuit layer.
17. semiconductor packages according to claim 11, the side of wherein said protuberance and the side of described conductive trace all concave.
18. 1 kinds of techniques manufacturing substrate, it comprises:
There is provided lower circuit layer, described lower circuit layer comprises conductive trace and protuberance;
Form dielectric layer to cover described conductive trace and described protuberance, wherein said dielectric layer has opening to expose described protuberance;
Form conductive connecting material on the described described protuberance exposed;
Settle conductive foil on described dielectric layer; And
Conductive foil described in patterning, to form upper circuit layer.
The technique of 19. manufacture substrates according to claim 18, wherein provides described lower circuit layer more to comprise:
Another conductive foil is provided; And
Another conductive foil described in patterning is to form described protuberance and described conductive trace.
The technique of 20. manufacture substrates according to claim 19, wherein said conductive trace and described protuberance are that unidirectional etching is formed.
CN201410312237.3A 2014-07-02 2014-07-02 Substrate, its semiconductor packages and manufacturing process thereof Pending CN105226031A (en)

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