CN111148373B - Method for manufacturing circuit board - Google Patents
Method for manufacturing circuit board Download PDFInfo
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- CN111148373B CN111148373B CN201811314549.2A CN201811314549A CN111148373B CN 111148373 B CN111148373 B CN 111148373B CN 201811314549 A CN201811314549 A CN 201811314549A CN 111148373 B CN111148373 B CN 111148373B
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- layer
- metal layer
- resin layer
- metal
- resin
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/4007—Surface contacts, e.g. bumps
Abstract
A method of manufacturing a circuit board, comprising the operations of: providing a substrate, wherein the substrate comprises a bottom layer and a resin layer, the resin layer is positioned on the bottom layer, the resin layer comprises a first surface and a second surface opposite to the first surface, and the first surface is in contact with the bottom layer; forming a plurality of holes penetrating through the resin layer; depositing a first metal layer in the holes, wherein the first metal layer contacts the bottom layer and fills a part of each hole; depositing a second metal layer on the first metal layer, wherein the second metal layer is positioned in the hole; forming a patterned metal layer on the second metal layer, wherein the patterned metal layer extends from each hole to the second surface; separating the bottom layer from the resin layer; and removing part of the resin layer from the first surface so that the first metal layer protrudes out of the resin layer. The circuit board manufacturing method provided by the invention can manufacture the circuit board with smaller bump spacing, thereby greatly increasing the density of components.
Description
Technical Field
The invention relates to a method for manufacturing a circuit board.
Background
Fine bump pitch (fine bump pitch) of a circuit board is one of the major points of the current application development. However, since the exposure alignment accuracy cannot be reduced, forming metal bumps on a circuit board or a substrate by using a solder on pad (SPOP) method has faced a technical bottleneck. Therefore, a novel manufacturing method is required to greatly reduce the fine bump pitch.
Disclosure of Invention
The method of the invention is to provide a circuit board manufacturing method, comprising the following operations: providing a substrate, wherein the substrate comprises a bottom layer and a resin layer, the resin layer is positioned on the bottom layer, the resin layer comprises a first surface and a second surface opposite to the first surface, and the first surface is in contact with the bottom layer; forming a plurality of holes penetrating through the resin layer; depositing a first metal layer in the holes, wherein the first metal layer contacts the bottom layer and fills a part of each hole; depositing a second metal layer on the first metal layer, wherein the second metal layer is positioned in the hole; forming a patterned metal layer on the second metal layer, wherein the patterned metal layer extends from each hole to the second surface; separating the bottom layer from the resin layer; and removing part of the resin layer from the first surface so that the first metal layer protrudes out of the resin layer.
According to one or more embodiments of the present invention, the bottom layer includes a core layer, a first copper layer, a second copper layer and a release layer, wherein the first copper layer is on the core layer, the release layer is on the first copper layer, the second copper layer is on the release layer, and the resin layer is on the second copper layer.
According to one or more embodiments of the present invention, the separating of the substrate from the resin layer includes separating the first copper layer from the second copper layer by a release layer.
According to one or more embodiments of the present invention, the second copper layer is etched after the first copper layer and the second copper layer are separated by the release layer.
According to one or more embodiments of the invention, the aperture of each hole near the first face is smaller than the aperture of each hole near the second face.
According to one or more embodiments of the present invention, the forming of the hole is developing using laser drilling or exposure.
According to one or more embodiments of the present invention, the etching of the resin layer includes forming a void between the resin layer and the first metal layer.
According to one or more embodiments of the present invention, after etching the resin layer, reflowing the first metal layer is further included.
The invention provides a circuit board, which comprises a resin layer, a first metal layer, a second metal layer and a patterned metal layer. The resin layer includes first face and second face, and wherein the resin layer contains a plurality of holes, the hole runs through the resin layer. The first metal layer is configured in each hole, wherein the first metal layer protrudes out of the first surface of the resin layer, and a gap is formed between the first metal layer and the resin layer. The second metal layer is configured in each hole, wherein the first metal layer is positioned at one side of the second metal layer. The patterned metal layer is arranged in each hole and is positioned on the other side of the second metal layer relative to the side, and the patterned metal layer covers a part of the second surface of the resin layer.
According to one or more embodiments of the present invention, a material of the first metal layer is different from a material of the second metal layer.
According to one or more embodiments of the invention, the aperture of each hole near the first face is smaller than the aperture of each hole near the second face.
The circuit board manufacturing method provided by the invention can manufacture the circuit board with smaller bump spacing, thereby greatly increasing the density of components.
Drawings
The present invention will be best understood from the following detailed description when read in connection with the accompanying drawings. It is emphasized that, in accordance with the standard practice in the industry, various features are not drawn to scale and are used for illustrative purposes only. In fact, the dimensions of the features may be arbitrarily increased or reduced for clarity of discussion.
Fig. 1-14 show schematic cross-sectional views of a method of manufacturing a circuit board at various stages of the manufacturing process, according to various embodiments of the invention.
Detailed Description
The following disclosure provides many different embodiments, or examples, for implementing different features of the provided objects. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the dimensions of the device are not limited by the scope or value of the invention, but may depend on the processing conditions and/or desired characteristics of the device. Moreover, the description that a first feature is formed over or on a second feature encompasses embodiments in which the first and second features are in direct contact, as well as embodiments in which other features are formed between the first and second features such that the first and second features are not in direct contact. The various features may be arbitrarily illustrated in different sizes for simplicity and clarity.
Also, spatially relative terms, such as "below", "above" … "," above ", and the like, are used for ease of describing the relationship of elements or features shown in the drawings to other elements or features. Spatially relative terms may encompass different orientations of the component in use or operation in addition to the orientation depicted in the figures. The instrument may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted as such.
The invention provides a circuit board manufacturing method, which can manufacture a circuit board with narrow bump spacing and is suitable for more advanced packaging process.
Fig. 1-14 show schematic cross-sectional views of a method of manufacturing a circuit board at various stages of the manufacturing process according to various embodiments of the invention. First, as shown in fig. 1, a substrate 110 is provided. The substrate 110 includes a resin layer 120 and a primer layer 130. In some embodiments, the resin layer 120 is located on the bottom layer 130. The resin layer 120 includes a first surface 121 and a second surface 122, wherein the first surface 121 is in contact with the base layer 130. The first face 121 is opposite to the second face 122.
In some embodiments, the bottom layer 130 includes a core layer 131, a first copper layer 132, a second copper layer 134, and a release layer 133. The first copper layer 132 is located on the core layer 131, the release layer 133 is located on the first copper layer 132, the second copper layer 134 is located on the release layer 133, and the resin layer 120 is located on the second copper layer 134. In other words, the release layer 133 is located between the first copper layer 132 and the second copper layer 134. The second copper layer 134 is in contact with the first side 121 of the resin layer 120. In some embodiments, holes 123 may be formed using laser drilling. In other embodiments, the material of the resin layer 120 is a photosensitive dielectric material, and thus the hole 123 can be formed by exposure and development.
Then, as shown in fig. 2, a plurality of holes 123 are formed in the resin layer 120, wherein the holes 123 penetrate through the resin layer 120. Further, in some embodiments, aperture 123 is frustoconical. In the hole 123, the aperture R1 on the side close to the first face 121 is smaller than the aperture R2 on the side close to the second face 122. In some embodiments, the aperture 123 exposes a portion of the second copper layer 134.
Next, as shown in fig. 3, a first metal layer 140 is deposited in the hole 123, wherein the first metal layer 140 contacts the bottom layer 130 and fills a portion of the hole 123. In other words, the first metal layer 140 does not fill the entire hole 123. Since the hole 123 exposes a portion of the second copper layer 134, the first metal layer 140 is in contact with the exposed second copper layer 134. In some embodiments, first metal layer 140 is made using a metal other than copper. In more detail, the first metal layer 140 uses a metal having an etching selectivity with copper. In some embodiments, the first metal layer 140 is tin. In other embodiments, the first metal layer 140 may be deposited using electroplating.
Thereafter, as shown in fig. 4, a second metal layer 150 is deposited on the first metal layer 140, wherein the second metal layer 150 is located in the hole 123. In some embodiments, the second metal layer 150 may be made of a material capable of preventing the first metal layer 140 from interacting with copper, wherein the second metal layer 150 may be a metal or a conductive material. In still other embodiments, the second metal layer 150 may be deposited using electroplating. In some embodiments, the first metal layer 140 and the second metal layer 150 do not fill the hole 123. In some embodiments, the thickness D2 of the second metal layer 150 is less than the thickness D1 of the first metal layer 140.
Then, a patterned metal layer is formed on the second metal layer 150. Fig. 5-9 illustrate cross-sectional views of forming the patterned metal layer, according to some embodiments of the invention.
Referring to fig. 5, a seed layer 160 is formed on the resin layer 120 and the second metal layer 150. In some embodiments, the seed layer 160 is conformally deposited on the resin layer 120 and the second metal layer 150. The seed layer 160 covers the surfaces of the resin layer 120 and the second metal layer 150. In some embodiments, the seed layer 160 is copper.
In fig. 6, a patterned photoresist 165 is formed on the seed layer 160. In further detail, the patterned photoresist 165 covers only a portion of the seed layer 160, and exposes another portion of the seed layer 160. In some embodiments, forming patterned photoresist 165 includes steps of deposition, exposure, and development.
Next, in fig. 7, a metal block 170 is deposited on the seed layer 160 exposed outside the patterned photoresist 165. Part of the metal block 170 is located in the hole 123, and the rest part of the metal block 170 is located on the second surface 122 adjacent to the hole 123. In certain embodiments, metal block 170 is copper.
Then, in fig. 8, the patterned photoresist 165 is removed. Patterned photoresist 165 may be removed using any suitable method. After removing the patterned photoresist 165, a portion of the seed layer 160 is exposed.
In fig. 9, the seed layer 160 exposed outside the metal bump 170 is removed. Removing the seed layer 160 exposed outside of the metal blocks 170 may include performing an etching process on the seed layer 160. The metal slug 170 and the remaining seed layer 160 constitute a patterned metal layer 180. In some embodiments, patterned metal layer 180 is copper. The patterned metal layer 180 extends from each of the holes 123 to the second surface 122 of the resin layer 120. To be further described, a portion of the patterned metal layer 180 is disposed in the hole 123, and another portion of the patterned metal layer 180 is disposed outside the hole 123 (on the second surface 122). In other embodiments, any suitable process may be used to form patterned metal layer 180. That is, the process shown in fig. 5-9 is not limited to the process of forming the patterned metal layer 180.
After forming the patterned metal layer 180, a build-up process may be performed. As shown in fig. 10, a build-up layer is built up over patterned metal layer 180 to form build-up portion 185. In some embodiments, the build-up portion 185 surrounds the patterned metal layer 180 such that the patterned metal layer 180 is not etched away in a subsequent etching process. It is to be understood that the build-up portion 185 shown in FIG. 10 is merely an exemplary structure, and that the build-up portion 185 may have different structures as desired. In addition, the build-up process is selective, and the circuit board manufacturing method may not include the build-up process.
In fig. 11, the first copper layer 132 is separated from the second copper layer 134. Since the release layer 133 is disposed between the first copper layer 132 and the second copper layer 134, the two layers can be separated by the release layer 133. The separated second copper layer 134 and the resin layer 120 are still in contact with each other.
Next, as shown in fig. 12, after the first copper layer 132 and the second copper layer 134 are separated by the release layer 133, the second copper layer 134 is etched. It is noted that fig. 12 is shown rotated 180 deg. for clarity of illustration. After etching the second copper layer 134, the first surface 121 of the resin layer 120 is exposed. Since the build-up portion 185 surrounds the patterned metal layer 180, the patterned metal layer 180 is not etched when the second copper layer 134 is etched.
Referring to fig. 13, a portion of the resin layer 120 is removed from the first surface 121 of the resin layer 120. In some embodiments, an etching process may be used to remove a portion of the resin layer 120. After the first side 121 of the resin layer 120 is etched, the thickness D3 of the resin layer 120 is reduced. In other words, the resin layer 120 is etched to expose the first metal layer 140, such that the first metal layer 140 protrudes from the resin layer 120. In some embodiments, etching the resin layer 120 includes forming a void 190 between the resin layer 120 and the first metal layer 140. The voids 190 prevent a subsequent bonding process from inadvertently electrically connecting adjacent first metal layers 140, i.e., so-called "bridging".
Referring to fig. 14, the first metal layer 140 is reflowed. In some embodiments, reflowed first metal layer 140 fills voids 190. In other words, the gap 190 provides a space for the first metal layer 140 to flow during reflow, so as to prevent the first metal layer 140 from flowing out of the hole 123 and causing an unexpected electrical connection.
The circuit board manufacturing method provided by the invention can manufacture the circuit board with smaller bump pitch. Since the operations of forming the holes, the first metal layer and the second metal layer do not include exposure and development, the exposure and alignment margin is not required to be reserved, and thus the density of the device can be greatly increased. In some embodiments, the pitch of the first metal layer may be reduced to 40 μm.
The present invention has been described in detail with respect to certain embodiments, but other embodiments are possible. Therefore, the spirit and scope of the appended claims should not be limited to the description of the embodiments contained herein.
While the foregoing is directed to embodiments of the present invention, other and further embodiments of the invention may be devised without departing from the basic scope thereof, and the scope thereof is determined by the claims that follow.
Claims (10)
1. A method of manufacturing a circuit board, comprising the operations of:
providing a substrate, wherein the substrate comprises a bottom layer and a resin layer, the resin layer is positioned on the bottom layer, the resin layer comprises a first surface and a second surface opposite to the first surface, and the first surface is in contact with the bottom layer;
forming a plurality of holes penetrating through the resin layer;
depositing a first metal layer in the holes, wherein the first metal layer contacts the bottom layer and fills a part of each hole;
depositing a second metal layer on the first metal layer, wherein the second metal layer is positioned in the hole;
forming a patterned metal layer on the second metal layer, wherein the patterned metal layer extends from each of the holes to the second surface;
separating the bottom layer from the resin layer; and
removing part of the resin layer from the first surface to make the first metal layer protrude from the resin layer and form a gap between the resin layer and the first metal layer, wherein the reflowed first metal layer fills the gap.
2. The method of claim 1, wherein the bottom layer comprises a core layer, a first copper layer, a second copper layer and a release layer, wherein the first copper layer is on the core layer, the release layer is on the first copper layer, the second copper layer is on the release layer, and the resin layer is on the second copper layer.
3. The method of claim 2, wherein the separating the substrate from the resin layer comprises separating the first copper layer from the second copper layer by the release layer.
4. The method of claim 3, wherein the second copper layer is etched after the first copper layer and the second copper layer are separated by the release layer.
5. The method of claim 1, wherein the diameter of each hole near the first surface is smaller than the diameter of each hole near the second surface.
6. The method for manufacturing a circuit board according to claim 1, wherein the forming of the hole is carried out by drilling with a laser or developing by exposure.
7. The method of claim 1, further comprising reflowing the first metal layer after etching the resin layer.
8. A circuit board, comprising:
the resin layer comprises a first surface and a second surface, and the resin layer comprises a plurality of holes which penetrate through the resin layer;
a first metal layer disposed in each of the holes, wherein the first metal layer protrudes from the first surface of the resin layer, and a gap is formed between the first metal layer and the resin layer, and the reflowed first metal layer fills the gap;
a second metal layer disposed in each of the holes, wherein the first metal layer is disposed on one side of the second metal layer, and the second metal layer is deposited on the first metal layer; and
and the patterned metal layer is arranged in each hole and is positioned on the other side of the second metal layer relative to the one side, wherein the patterned metal layer covers a part of the second surface of the resin layer.
9. The circuit board of claim 8, wherein the material of the first metal layer is different from the material of the second metal layer.
10. The circuit board of claim 8, wherein an aperture of each of the holes near the first side is smaller than an aperture of each of the holes near the second side.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811314549.2A CN111148373B (en) | 2018-11-06 | 2018-11-06 | Method for manufacturing circuit board |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811314549.2A CN111148373B (en) | 2018-11-06 | 2018-11-06 | Method for manufacturing circuit board |
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| CN111148373A CN111148373A (en) | 2020-05-12 |
| CN111148373B true CN111148373B (en) | 2021-06-29 |
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1491076A (en) * | 2002-09-17 | 2004-04-21 | �¹������ҵ��ʽ���� | Method for preparing wiring placode |
| CN103857204A (en) * | 2012-11-28 | 2014-06-11 | 宏启胜精密电子(秦皇岛)有限公司 | Bearing plate and manufacture method for the same |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08124965A (en) * | 1994-10-27 | 1996-05-17 | Oki Electric Ind Co Ltd | Method of connecting semiconductor chip to multilayer wiring board |
| TWI393233B (en) * | 2009-08-18 | 2013-04-11 | Unimicron Technology Corp | Coreless package substrate and method of forming the same |
| CN103904050B (en) * | 2012-12-28 | 2017-04-19 | 碁鼎科技秦皇岛有限公司 | Package substrate, manufacturing method of package substrate and packaging structure |
| CN108257875B (en) * | 2016-12-28 | 2021-11-23 | 碁鼎科技秦皇岛有限公司 | Chip packaging substrate, chip packaging structure and manufacturing method of chip packaging substrate and chip packaging structure |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1491076A (en) * | 2002-09-17 | 2004-04-21 | �¹������ҵ��ʽ���� | Method for preparing wiring placode |
| CN103857204A (en) * | 2012-11-28 | 2014-06-11 | 宏启胜精密电子(秦皇岛)有限公司 | Bearing plate and manufacture method for the same |
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