JP5115241B2 - Electronic component mounting method - Google Patents

Electronic component mounting method Download PDF

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JP5115241B2
JP5115241B2 JP2008052745A JP2008052745A JP5115241B2 JP 5115241 B2 JP5115241 B2 JP 5115241B2 JP 2008052745 A JP2008052745 A JP 2008052745A JP 2008052745 A JP2008052745 A JP 2008052745A JP 5115241 B2 JP5115241 B2 JP 5115241B2
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electronic component
wiring layer
substrate
hole
mounting structure
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JP2009212250A (en
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広徳 大田
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NEC Corp
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NEC Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18165—Exposing the passive side of the semiconductor or solid-state body of a wire bonded chip

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  • Wire Bonding (AREA)

Description

この発明は、電子部品の実装方法に係り、詳しくは、配線層が形成された電子部品とその配線層に対応した導体層が形成された配線基板（以下、基板とも称する）とが、配線層及び導体層が対向するように配置されて、これら両層がろう材を介して接続される電子部品の実装方法に関する。 The present invention relates to a method for mounting an electronic component, and more specifically, an electronic component on which a wiring layer is formed and a wiring board (hereinafter also referred to as a board) on which a conductor layer corresponding to the wiring layer is formed. In addition, the present invention relates to a method for mounting an electronic component in which conductor layers are disposed so as to face each other and both layers are connected via a brazing material.

電子部品の代表として知られているＬＳＩなどの半導体装置が各種の電子機器に広く用いられているが、電子機器の軽薄短小化、高速化、高機能化及び多機能化などの要望に応じて、用いられるＬＳＩも小型化、薄型化及び外部電極の狭ピッチ化などへ進展している。このような観点から、最近のＬＳＩはベアチップ、ＣＳＰ（Ｃｈｉｐ Ｓｉｚｅ Ｐａｃｋａｇｅ）などの超小型のＬＳＩパッケージが採用されるようになってきている。さらに、より高密度実装を実現するためのＬＳＩとして、小型の高密度配線が形成された基板上に複数のＬＳＩチップを搭載したＭＣＭ（Ｍｕｌｔｉ Ｃｈｉｐ Ｍｏｄｕｌｅ）も実用化されている。このように、複数のＬＳＩチップを基板上に搭載する場合、各ＬＳＩチップは基板の平面方向に配置されるか、基板の垂直方向に積層される。   Semiconductor devices such as LSIs, which are known as representative electronic components, are widely used in various electronic devices. However, according to demands for electronic devices that are lighter, thinner, faster, more functional, and multifunctional. Further, LSIs used are also progressing toward downsizing, thinning, and narrowing of external electrodes. From this point of view, recent LSIs have adopted ultra-small LSI packages such as bare chips and CSP (Chip Size Package). Further, as an LSI for realizing higher density mounting, MCM (Multi Chip Module) in which a plurality of LSI chips are mounted on a substrate on which small high-density wiring is formed has been put into practical use. As described above, when a plurality of LSI chips are mounted on a substrate, the LSI chips are arranged in the plane direction of the substrate or stacked in the vertical direction of the substrate.

図１０は、ベアチップを用いた従来の電子部品の実装構造の一例を示すもので、この電子部品の実装構造１００は、表面側に電極パッド（図示せず）が形成されたＬＳＩチップ１０１が、裏面側に外部電極となるはんだボール１０２が形成された基板１０３上に搭載されて、ＬＳＩチップ１０１の前記電極パッドと基板１０３の対応した電極端子（図示せず）との間はボンディングワイヤ１０４により接続されるとともに、ＬＳＩチップ１０１の周囲は樹脂体１０５で封止されている。また、図１１は、ベアチップを用いた従来の電子部品の実装構造の他の例を示すもので、この電子部品の実装構造２００は、表面側にはんだバンプ２０４が形成されたＬＳＩチップ２０１が反転されて、裏面側にはんだボール２０２が形成された基板２０３上に搭載されて、ＬＳＩチップ２０１のはんだバンプ２０４と基板２０３の対応した電極端子（図示せず）との間はフリップチップボンディングにより接続されるとともに、ＬＳＩチップ２０１と基板２０３との隙間には樹脂体２０５が封入されている。   FIG. 10 shows an example of a conventional electronic component mounting structure using a bare chip. The electronic component mounting structure 100 includes an LSI chip 101 having electrode pads (not shown) formed on the surface side. A bonding wire 104 is provided between the electrode pad of the LSI chip 101 and a corresponding electrode terminal (not shown) of the LSI chip 101 mounted on a substrate 103 on which solder balls 102 to be external electrodes are formed on the back surface side. While being connected, the periphery of the LSI chip 101 is sealed with a resin body 105. FIG. 11 shows another example of a conventional electronic component mounting structure using a bare chip. The electronic component mounting structure 200 has an inverted LSI chip 201 with solder bumps 204 formed on the surface side. Then, it is mounted on a substrate 203 having a solder ball 202 formed on the back side, and the solder bump 204 of the LSI chip 201 and the corresponding electrode terminal (not shown) of the substrate 203 are connected by flip chip bonding. In addition, a resin body 205 is sealed in a gap between the LSI chip 201 and the substrate 203.

ところで、図１０及び図１１のそれぞれの実装構造１００，２００では、各ＬＳＩチップ１０１、２０１がそれぞれ基板１０３，２０３上に搭載されるので、各基板１０３、２０３の厚み分厚くなって薄型化を図るのが困難なので、それぞれ図１２及び図１３に示したような、キャビティ基板を用いる改良された実装構造１００Ａ、２００Ａが提供されている。すなわち、図１２の電子部品の実装構造１００Ａは、キャビティ基板１０３Ａを用いてそのキャビティ部１０６内にＬＳＩチップ１０１を配置し、一方、図１３の電子部品の実装構造２００Ａは、キャビティ基板２０３Ａを用いてそのキャビティ部２０６内の薄い別の基板２０７上にＬＳＩチップ２０１を搭載したものである。これらの構成により、各実装構造１００Ａ、２００Ａはそれぞれのキャビティ部１０６、２０６の略深さ分だけ薄型化が図れることになる。これらの電子部品の実装構造１００、１００Ａ、２００，２００Ａは、それぞれの外部電極としてのはんだボール１０２、２０２をリフローにより溶融させて、マザーボードに接続することによって、電子機器に組み込まれる。   By the way, in each of the mounting structures 100 and 200 of FIGS. 10 and 11, since the LSI chips 101 and 201 are mounted on the substrates 103 and 203, respectively, the thickness is reduced by the thickness of the substrates 103 and 203. Therefore, improved mounting structures 100A and 200A using a cavity substrate as shown in FIGS. 12 and 13, respectively, are provided. That is, the electronic component mounting structure 100A in FIG. 12 uses the cavity substrate 103A to place the LSI chip 101 in the cavity portion 106, while the electronic component mounting structure 200A in FIG. 13 uses the cavity substrate 203A. The LSI chip 201 is mounted on another thin substrate 207 in the cavity portion 206. With these configurations, the mounting structures 100A and 200A can be reduced in thickness by approximately the depth of the cavity portions 106 and 206, respectively. These electronic component mounting structures 100, 100A, 200, and 200A are incorporated in an electronic device by melting solder balls 102 and 202 as external electrodes by reflow and connecting them to a motherboard.

また、近年の技術の発展に伴って、ＬＳＩチップを搭載する基板としてフレキシブル基板やフィルムキャリア基板などの屈曲性基板を用いた電子部品の実装構造も提供されている。図１４は、例えば、フィルムキャリア基板を用いた他の従来例を示すもので、この電子部品の実装構造３００は、フィルムキャリア基板３０３上に複数のＬＳＩチップ３０１を搭載した後、フィルムキャリア基板３０３を折り曲げて、３次元的な実装構造を実現したものである（特許文献１）。符号３０２は、フィルムキャリア基板３０３上のＬＳＩチップ３０１の搭載面と反対面に形成されたはんだボールである。このような実装構造３００によれば、屈曲性基板の特長を生かすことにより、容易に３次元的な実装構造が得られるので、より高密度実装が可能になる。   Along with the development of technology in recent years, a mounting structure for electronic components using a flexible substrate such as a flexible substrate or a film carrier substrate as a substrate on which an LSI chip is mounted is also provided. FIG. 14 shows another conventional example using, for example, a film carrier substrate. This electronic component mounting structure 300 includes a plurality of LSI chips 301 mounted on a film carrier substrate 303 and then a film carrier substrate 303. Is folded to realize a three-dimensional mounting structure (Patent Document 1). Reference numeral 302 is a solder ball formed on the surface opposite to the mounting surface of the LSI chip 301 on the film carrier substrate 303. According to such a mounting structure 300, a three-dimensional mounting structure can be easily obtained by taking advantage of the characteristics of the flexible substrate, so that higher-density mounting is possible.

さらに、多数の半導体チップを基板上にフリップチップ実装した場合に、不良チップの局所的な修復作業を容易にするために、半導体チップを接続したキャリア基板を主基板に搭載し、キャリア基板の側壁に設けた接続部により両基板を接続するように構成した電子部品の実装構造が提供されている（特許文献２）。また、ＩＣチップを収容したリードレスパッケージを基板上に実装した場合に、接続不良部分の修正を容易にするために、穴を設けた基板のその穴にリードレスパッケージを装着し、穴の周囲に設けた応力吸収用の接続回路箔によりリードレスパッケージと基板とを接続するように構成した電子部品の実装構造が提供されている（特許文献３）。また、ＢＧＡ（Ｂａｌｌ Ｇｒｉｄ Ａｒｒａｙ）タイプのパッケージ構造を有する半導体装置において、低コスト化及び小型化を図るために、キャビティ部が形成された枠体のそのキャビティ部に、ＴＡＢ（Ｔａｐｅ Ａｕｔｏｍａｔｅｄ Ｂｏｎｄｉｎｇ）テープに搭載された半導体チップを収納し、ＴＡＢテープの外部電極としてのはんだボールを設けるとともに、半導体チップと枠体との間をボンディングワイヤで接続するようにした構成の電子部品の実装構造が提供されている（特許文献４）。
特開平１１−０４０６１８号公報 特開２００２−１５８５０９号公報 特開昭５６−１１０２４１号公報 特開平０９−００８０７４号公報 Further, when a large number of semiconductor chips are flip-chip mounted on a substrate, a carrier substrate to which the semiconductor chips are connected is mounted on the main substrate in order to facilitate local repair work of defective chips, and the side walls of the carrier substrate There is provided a mounting structure for an electronic component that is configured to connect both substrates by a connecting portion provided in (Patent Document 2). In addition, when a leadless package containing an IC chip is mounted on a substrate, the leadless package is attached to the hole of the substrate in which a hole is provided in order to facilitate correction of a defective connection portion, and the periphery of the hole There is provided a mounting structure of an electronic component configured to connect a leadless package and a substrate by a connection circuit foil for stress absorption provided in the circuit board (Patent Document 3). Further, in a semiconductor device having a BGA (Ball Grid Array) type package structure, a TAB (Tape Automated Bonding) tape is attached to the cavity portion of the frame body in which the cavity portion is formed in order to reduce cost and size. A mounting structure for an electronic component is provided in which a semiconductor chip mounted on the housing is housed, solder balls are provided as external electrodes of the TAB tape, and the semiconductor chip and the frame are connected by a bonding wire. (Patent Document 4).
JP-A-11-040618 JP 2002-158509 A Japanese Patent Laid-Open No. 56-110241 JP 09-008074 A

なお、特許文献２には、本願発明で必須の要件としている電子部品を配置するための貫通孔が形成された基板については開示されておらず、本願発明の従来技術（図１３）で説明した基板と同形状の貫通孔がない基板が開示されているだけなので、本願発明の従来欠点を解消することはできない。
特許文献３には、穴を設けた基板が開示されているが、穴の周囲に設けた接続回路箔により穴に装着したリードレスパッケージと基板とを接続しているだけで、本願発明で必須の要件としている電子部品の配線層と基板の貫通孔の内壁面の導体層とをろう材により接続することは開示されていない。
特許文献４には、基板（枠体）のキャビティ部に電子部品（半導体チップ）を収納することが開示されているが、特許文献３と同様に、本願発明で必須の要件としている電子部品の配線層と基板の貫通孔の内壁面の導体層とをろう材により接続することは開示されていない。また、この特許文献４では、半導体チップと枠体とをボンディングワイヤにより接続しているが、本願発明の実装構造では薄型化の妨げとなるのでボンディングワイヤは用いない。 Note that Patent Document 2 does not disclose a substrate on which a through hole for placing an electronic component, which is an essential requirement of the present invention, is disclosed, and has been described in the prior art of the present invention (FIG. 13). Since only a substrate having no through hole of the same shape as the substrate is disclosed, the conventional drawbacks of the present invention cannot be solved.
Patent Document 3 discloses a substrate provided with a hole, but it is essential in the present invention only by connecting the leadless package attached to the hole and the substrate with a connection circuit foil provided around the hole. It is not disclosed that the wiring layer of the electronic component and the conductor layer on the inner wall surface of the through hole of the substrate are connected by a brazing material as a requirement of the above.
Patent Document 4 discloses that an electronic component (semiconductor chip) is accommodated in a cavity portion of a substrate (frame body). Like Patent Document 3, an electronic component that is an essential requirement of the present invention is disclosed. It is not disclosed that the wiring layer and the conductor layer on the inner wall surface of the through hole of the substrate are connected by a brazing material. In Patent Document 4, the semiconductor chip and the frame body are connected by a bonding wire. However, in the mounting structure of the present invention, the bonding wire is not used because it hinders thinning.

ところで、前記した従来の電子部品の実装構造では、それぞれ次のような問題がある。
まず、図１２に示したような、キャビティ基板１０３Ａを用いた電子部品の実装構造１００Ａでは、キャビティ部１０６の略深さ分だけ薄型化を図ることが可能であるものの、ボンディングワイヤ１０４の高さはそのまま維持されているので、それほど薄型化の効果が得られない。また、図１３に示したような、フリップチップボンディングによるキャビティ基板２０３を用いた電子部品の実装構造２００Ａでは、実装構造１００Ａと同じくキャビティ部２０６の略深さ分だけ薄型化が可能であるものの、チップ２０１の直下部分に別の基板２０７が必要になるため、この基板２０７の厚さ分だけ薄型化が妨げられることになる。
次に、図１４に示したような、フィルムキャリア基板３０３を用いた電子部品の実装構造３００では、基板として折り曲げ可能なフィルムキャリア基板３０３を用いているので、必然的に配線層数が少なくなるため、多ピン（多外部電極）のＬＳＩチップを搭載することが困難になる。ここで、搭載するＬＳＩチップの多ピン化を図ろうとすると、多くの配線が必要となって、配層の細線化や多層化が避けられなくなるので、折り曲げ性が低下するようになる。したがって、限られた製品例えば、比較的ピン数が少ないメモリ製品などに適用対象が限られてくる。 However, the conventional electronic component mounting structure described above has the following problems.
First, in the electronic component mounting structure 100A using the cavity substrate 103A as shown in FIG. 12, it is possible to reduce the thickness by the substantial depth of the cavity portion 106, but the height of the bonding wire 104 can be reduced. Is maintained as it is, so that the effect of thinning cannot be obtained. In addition, in the electronic component mounting structure 200A using the cavity substrate 203 by flip-chip bonding as shown in FIG. 13, the thickness can be reduced by substantially the depth of the cavity portion 206 as in the mounting structure 100A. Since another substrate 207 is required immediately below the chip 201, the thickness reduction of the substrate 207 is hindered.
Next, in the electronic component mounting structure 300 using the film carrier substrate 303 as shown in FIG. 14, since the foldable film carrier substrate 303 is used as the substrate, the number of wiring layers is inevitably reduced. Therefore, it is difficult to mount an LSI chip with multiple pins (multiple external electrodes). Here, if an attempt is made to increase the number of pins of an LSI chip to be mounted, a large number of wirings are required, and thinning and multilayering of the distribution layer cannot be avoided, so that the bendability is lowered. Therefore, the target of application is limited to limited products such as memory products with a relatively small number of pins.

この発明は、上述の事情に鑑みてなされたもので、多ピン化が容易であり、かつ薄型化を図ることができるようにした電子部品の実装方法を提供することを目的としている。 The present invention has been made in view of the above-described circumstances, and an object thereof is to provide a method for mounting an electronic component that can be easily multi-pinned and can be thinned.

上記課題を解決するために、この発明の構成は、配線層が形成された電子部品と前記配線層に対応した導体層が形成された基板とを、前記配線層及び前記導体層が対向するように配置して、該両層をろう材を介して接続する電子部品の実装方法に係り、回路が形成された電子部品の回路形成面を絶縁性シート材により覆う工程と、前記絶縁性シート材を選択的に除去して前記電子部品の回路形成面を選択的に露出する開口を形成した後、該開口から前記絶縁性シート材に沿って前記電子部品の外部方向に引出すように配線層を形成する工程と、前記配線層のろう付け予定個所を露出し、かつ前記ろう付け予定個所以外をマスクするソルダーレジストを前記配線層上に形成する工程と、前記配線層及び前記絶縁性シート材を含む一体化構成部を前記電子部品の側面に向かって屈曲して、前記配線層の前記ろう付け予定個所を前記電子部品の側面に位置させる工程と、前記電子部品を配置する貫通孔が形成され、該貫通孔の内壁面に前記配線層に対応した導体層が形成された基板を用意して、該基板の前記貫通孔に前記電子部品を配置する工程と、前記電子部品の前記配線層と前記基板の導体層とをろう材により接続する工程と、を含むことを特徴としている。 In order to solve the above problems, the configuration of the present invention is such that the wiring layer and the conductor layer face each other between the electronic component on which the wiring layer is formed and the substrate on which the conductor layer corresponding to the wiring layer is formed. be placed relates to electronic part mounting method for connecting the both layers via a brazing material, comprising the steps of a circuit forming surface of the electronic component circuit is formed to cover the insulating sheet material, said insulating sheet material Are selectively removed to form an opening that selectively exposes the circuit forming surface of the electronic component, and then a wiring layer is drawn from the opening along the insulating sheet material to the outside of the electronic component. A step of forming, a step of forming a solder resist on the wiring layer for exposing a portion to be brazed of the wiring layer and masking a portion other than the portion to be brazed, and the wiring layer and the insulating sheet material. Including integrated components Bending toward the side surface of the electronic component, the step of positioning the brazed portion of the wiring layer on the side surface of the electronic component, and a through hole for arranging the electronic component are formed, Preparing a substrate on which a conductor layer corresponding to the wiring layer is formed on a wall surface, disposing the electronic component in the through-hole of the substrate; the wiring layer of the electronic component; and the conductor layer of the substrate; And a step of connecting them with a brazing material.

このように、この発明の構成によれば、配線層が形成された電子部品と配線層に対応した導体層が形成された基板とが、配線層及び導体層が対向するように配置されて、両層がろう材を介して接続される電子部品の実装構造において、配線層が側面に形成された電子部品が、電子部品を配置する貫通孔が形成されかつ貫通孔の内壁面に前記配線層に対応した導体層が形成された基板の前記貫通孔に配置されて、配線層と導体層とがろう材を介して接続されるので、従来のようなボンディングワイヤは用いないのでワイヤループの高さが生じない。また、従来のフリップチップボンディングのようなチップ直下部分の別な基板も不要になる。また、フィルムキャリア基板などの屈曲性基板も不要なので配線層数に制限を受けることもなくなる。したがって、多ピン化が容易であり、かつ薄型化を図ることができる電子部品の実装構造が得られる。   Thus, according to the configuration of the present invention, the electronic component on which the wiring layer is formed and the substrate on which the conductor layer corresponding to the wiring layer is formed are arranged so that the wiring layer and the conductor layer face each other, In an electronic component mounting structure in which both layers are connected via a brazing material, an electronic component in which a wiring layer is formed on a side surface has a through hole in which the electronic component is disposed and the wiring layer on the inner wall surface of the through hole. Since the wiring layer and the conductor layer are connected to each other through the brazing material and the bonding layer is not used, the wire loop height is increased. Does not occur. Further, a separate substrate directly under the chip as in the conventional flip chip bonding is not required. Further, since there is no need for a flexible substrate such as a film carrier substrate, the number of wiring layers is not limited. Therefore, it is possible to obtain a mounting structure of an electronic component that can be easily multi-pinned and can be thinned.

電子部品の実装構造１０は、第１配線層１Ａ、第２配線層１Ｂが表面側から側面に引出されるように形成されたＬＳＩチップ（電子部品）２が、略中央部に貫通孔３が形成されこの貫通孔３の内壁面４に第１導体層５Ａ、第２導体層５Ｂが形成された基板６の前記貫通孔３に配置されて、第１配線層１Ａと第１導体層５Ａとがはんだ（ろう材）７Ａを介して接続されるとともに、第２配線層１Ｂと第２導体層５Ｂとがはんだ７Ｂを介して接続される。   The electronic component mounting structure 10 includes an LSI chip (electronic component) 2 formed so that the first wiring layer 1A and the second wiring layer 1B are drawn from the surface side to the side surface. The first wiring layer 1A and the first conductor layer 5A are disposed in the through hole 3 of the substrate 6 formed and formed with the first conductor layer 5A and the second conductor layer 5B on the inner wall surface 4 of the through hole 3. Are connected via the solder (brazing material) 7A, and the second wiring layer 1B and the second conductor layer 5B are connected via the solder 7B.

実施形態１Embodiment 1

図１は、この発明の実施形態１である電子部品の実装構造の概略構成を示す平面図、図２は同電子部品の実装構造の概略構成を示す底面図、図３は図１のＡ‐Ａ矢視断面図、図４は同電子部品の実装構造の主要部の概略構成図を示す斜視図である。
この例の電子部品の実装構造１０は、図１〜図３に示すように、例えばＡｌから成る第１配線層１Ａ、第２配線層１Ｂが表面側から側面に引出されるように形成されたＬＳＩチップ（電子部品）２が、略中央部に貫通孔３が形成されこの貫通孔３の内壁面４に例えばＣｕから成る第１導体層５Ａ、第２導体層５Ｂが形成された基板６の前記貫通孔３に配置されて、第１配線層１Ａと第１導体層５Ａとがはんだ（ろう材）７Ａを介して接続されるとともに、第２配線層１Ｂと第２導体層５Ｂとがはんだ７Ｂを介して接続されている。 1 is a plan view showing a schematic configuration of a mounting structure for an electronic component according to a first embodiment of the present invention, FIG. 2 is a bottom view showing a schematic configuration of the mounting structure for the electronic component, and FIG. FIG. 4 is a perspective view showing a schematic configuration diagram of the main part of the mounting structure of the electronic component.
The electronic component mounting structure 10 in this example is formed so that the first wiring layer 1A and the second wiring layer 1B made of, for example, Al are drawn out from the surface side to the side surface as shown in FIGS. An LSI chip (electronic component) 2 has a through hole 3 formed in a substantially central portion, and a substrate 6 having a first conductor layer 5A and a second conductor layer 5B made of Cu, for example, formed on the inner wall surface 4 of the through hole 3. The first wiring layer 1A and the first conductor layer 5A are connected to each other via the solder (brazing material) 7A, and the second wiring layer 1B and the second conductor layer 5B are soldered. 7B is connected.

この実施形態では、一例として、ＬＳＩチップ２の側面には厚さ方向に第１及び第２配線層１Ａ、１Ｂの２つの配線層が形成されるとともに、基板６の貫通孔３の内壁面４には厚さ方向に、第１及び第２配線層１Ａ、１Ｂにそれぞれ対応した第１及び第２導体層５Ａ、５Ｂの２つの導体層が形成された例で示している。   In this embodiment, as an example, two wiring layers of the first and second wiring layers 1A and 1B are formed on the side surface of the LSI chip 2 in the thickness direction, and the inner wall surface 4 of the through hole 3 of the substrate 6 is formed. Shows an example in which two conductor layers of first and second conductor layers 5A and 5B corresponding to the first and second wiring layers 1A and 1B, respectively, are formed in the thickness direction.

ここで、図１及び図２から明らかなように、例えば正方形形状から成るＬＳＩチップ２の四辺の側面のいずれにも第１及び第２配線層１Ａ、１Ｂが形成されて、それぞれが対応した基板６の第１及び第２導体層５Ａ、５Ｂにはんだ７Ａ、７Ｂを介して接続されている。   Here, as is apparent from FIGS. 1 and 2, the first and second wiring layers 1A and 1B are formed on any of the four side surfaces of the LSI chip 2 having a square shape, for example, and the corresponding substrates. 6 are connected to the first and second conductor layers 5A and 5B via solders 7A and 7B.

ＬＳＩチップ２の表面側には半導体回路（回路機能部）が形成されて、第１及び第２配線層１Ａ、１Ｂはその半導体回路から引出されている。そして、ＬＳＩチップ２は半導体回路が形成された表面側が下方向となるように反転された状態で基板６の貫通孔３に配置されている。   A semiconductor circuit (circuit function unit) is formed on the surface side of the LSI chip 2, and the first and second wiring layers 1A and 1B are drawn from the semiconductor circuit. The LSI chip 2 is disposed in the through hole 3 of the substrate 6 in a state of being inverted so that the surface side on which the semiconductor circuit is formed is directed downward.

また、ＬＳＩチップ２の表面側の半導体回路から引出された第１及び第２配線層１Ａ、１Ｂ上には外部電極となるはんだボール９が形成され、さらに、基板６の裏面側にも同様に外部電極となるはんだボール１１が形成されて、このはんだボール１１は第１及び第２導体層５Ａ、５Ｂのいずれかと導通している。ＬＳＩチップ２の周囲は絶縁層１２で覆われるとともに、はんだ７及びはんだボール９が接続される個所以外の第１及び第２配線層１Ａ、１Ｂはソルダーレジスト１３で覆われている。ソルダーレジスト１３は、はんだ付けが不要な個所をマスクしてはんだが濡れ広がるのを防止する役割を担い、隣接したはんだボール９同士の短絡を防止する。はんだ７、はんだボール９，１１は、低融点ろう材として知られているＳｎ／Ｐｂ、Ｓｎ／Ｃｕ、Ｓｎ／Ａｇ，Ｓｎ／Ｚｎ合金などの中から適宜選ばれる。   In addition, solder balls 9 serving as external electrodes are formed on the first and second wiring layers 1A and 1B drawn from the semiconductor circuit on the front surface side of the LSI chip 2, and furthermore, similarly on the back surface side of the substrate 6. A solder ball 11 serving as an external electrode is formed, and this solder ball 11 is electrically connected to one of the first and second conductor layers 5A and 5B. The periphery of the LSI chip 2 is covered with an insulating layer 12, and the first and second wiring layers 1 </ b> A and 1 </ b> B other than the portion where the solder 7 and the solder balls 9 are connected are covered with a solder resist 13. The solder resist 13 plays a role of preventing the solder from spreading by masking a place where soldering is unnecessary, and prevents a short circuit between the adjacent solder balls 9. The solder 7 and the solder balls 9 and 11 are appropriately selected from Sn / Pb, Sn / Cu, Sn / Ag, Sn / Zn alloy and the like known as low melting point brazing materials.

基板６は、図４に示すように、例えば４層基板から成り、ＬＳＩチップ２と対向する側の内壁面４の具体的な構造は、半スルーホール構造１５から構成されている。この半スルーホール構造１５は、同図に示すように、第１配線層１６Ａ〜第４配線層１６Ｄ、第１絶縁層１７Ａ〜第３絶縁層１７Ｃ及び第１、第２導体層５Ａ、５Ｂから構成されている。第１配線層１６Ａと第２配線層１６Ｂは第１導体層５Ａで接続され、一方、第３配線層１６Ｃと第４配線層１６Ｄは第２導体層５Ｂで接続されている。すなわち、１つの半スルーホール構造１５で、第１導体層５Ａ及び第２導体層５Ｂの２つの導体層を有し、各導体層５Ａ、５ＢはＬＳＩチップ２の第１配線層１Ａ、第２配線層１Ｂと対向して、それぞれはんだ７Ａ、７Ｂによって接続されることになる。基板６の層数をさらに増加することにより、１つの半スルーホール構造によるはんだ接続部（導体層）をさらに増加することができるようになる。   As shown in FIG. 4, the substrate 6 is composed of, for example, a four-layer substrate, and a specific structure of the inner wall surface 4 on the side facing the LSI chip 2 is composed of a half-through-hole structure 15. As shown in the figure, the half through-hole structure 15 includes a first wiring layer 16A to a fourth wiring layer 16D, a first insulating layer 17A to a third insulating layer 17C, and first and second conductor layers 5A and 5B. It is configured. The first wiring layer 16A and the second wiring layer 16B are connected by the first conductor layer 5A, while the third wiring layer 16C and the fourth wiring layer 16D are connected by the second conductor layer 5B. That is, one half through-hole structure 15 has two conductor layers of the first conductor layer 5A and the second conductor layer 5B, and each of the conductor layers 5A and 5B is composed of the first wiring layer 1A and the second conductor layer 2 of the LSI chip 2. Opposite to the wiring layer 1B, they are connected by solders 7A and 7B, respectively. By further increasing the number of layers of the substrate 6, it is possible to further increase the solder connection portion (conductor layer) with one half through-hole structure.

次に、図４に示したような半スルーホール構造１５から構成される基板６の製造方法を説明する。この基板６は通常のプリント基板の製造方法を利用することにより製造することができる。
同図に示すような４層基板の場合、まず絶縁層にパラジウム触媒を含む銅張積層板を２枚用意する。１枚目は、図４において、第１配線層１６Ａ、第１絶縁層１７Ａ及び第２配線層１６Ｂから成る第１構成部を製造するための材料、２枚目は、第３配線層１６Ｃ、第３絶縁層１７Ｃ及び第４配線層１６Ｄから成る第２構成部を製造するための材料となる。 Next, a method for manufacturing the substrate 6 composed of the half through-hole structure 15 as shown in FIG. 4 will be described. The substrate 6 can be manufactured by using a normal printed circuit board manufacturing method.
In the case of a four-layer substrate as shown in the figure, first, two copper-clad laminates containing a palladium catalyst in the insulating layer are prepared. The first sheet is a material for manufacturing the first component part composed of the first wiring layer 16A, the first insulating layer 17A and the second wiring layer 16B in FIG. 4, and the second sheet is the third wiring layer 16C, This is a material for manufacturing the second component part composed of the third insulating layer 17C and the fourth wiring layer 16D.

次に、２枚の銅張積層板をそれぞれ孔開け、めっき処理を施して、内層面になる片面のみに回路形成を行う。次に、パラジウム触媒を含まない通常のプリプレグ材を用意して、図４における第２絶縁層１７Ｂを製造するための材料とする。続いて、２枚の銅張積層板をそれぞれ回路形成面を内側にして間にプリプレグ材を挟んで、全体を加圧、加熱処理を施して一体化する。次に、一体化物に孔開け、めっき処理を施して、外層面になる他面のみに回路形成を行う。ここで、貫通孔３となる部分にはスルーホールとして孔開けをする。   Next, the two copper-clad laminates are perforated, plated, and a circuit is formed only on one side that becomes the inner layer surface. Next, a normal prepreg material not containing a palladium catalyst is prepared and used as a material for manufacturing the second insulating layer 17B in FIG. Subsequently, the two copper-clad laminates are integrated by applying pressure and heat treatment to each other with the prepreg material sandwiched therebetween with the circuit forming surface inside. Next, the integrated product is perforated and plated to form a circuit only on the other surface that becomes the outer layer surface. Here, the through hole 3 is drilled as a through hole.

次に、内壁面４となるスルーホールにめっき処理を行うが、この場合めっき予定部分のみ触媒処理をしないで、無電解厚付けめっき処理を施す。この結果、スルーホールの中で、触媒を含む第１絶縁層１７Ａ及び第３絶縁層１７Ｃの壁面のみにめっきが析出され、一方、触媒を含まない第２絶縁層１７Ｂの壁面にはめっきが析出しない。次に、ＮＣルータやレーザーなどを用いて、スルーホールに沿って機械加工を施して不要部を除去することにより、図４に示したような半スルーホール構造１５から構成される基板６が得られる。めっきが析出した部分は第１及び第２導体層５Ａ、５Ｂとなる。   Next, a plating process is performed on the through hole serving as the inner wall surface 4. In this case, an electroless thick plating process is performed without performing a catalyst process only on a portion to be plated. As a result, plating is deposited only on the wall surfaces of the first insulating layer 17A and the third insulating layer 17C containing the catalyst in the through hole, while plating is deposited on the wall surfaces of the second insulating layer 17B not containing the catalyst. do not do. Next, by using an NC router, laser, or the like, machining is performed along the through hole to remove unnecessary portions, thereby obtaining the substrate 6 having the half through hole structure 15 as shown in FIG. It is done. The portion where the plating is deposited becomes the first and second conductor layers 5A and 5B.

このように、本実施形態１の電子部品の実装構造１０によれば、第１配線層１Ａ、第２配線層１Ｂが表面側から側面に引出されるように形成されたＬＳＩチップ（電子部品）２が、略中央部に貫通孔３が形成されこの貫通孔３の内壁面４に第１導体層５Ａ、第２導体層５Ｂが形成された基板６の前記貫通孔３に配置されて、第１配線層１Ａと第１導体層５Ａとがはんだ（ろう材）７Ａを介して接続されるとともに、第２配線層１Ｂと第２導体層５Ｂとがはんだ７Ｂを介して接続されているので、従来のようなボンディングワイヤは用いないのでワイヤループの高さが生じず、また、従来のフリップチップボンディングのようなチップ直下部分の別な基板も不要になる。また、フィルムキャリア基板などの屈曲性基板も不要なので配線層数に制限を受けることもなくなる。
したがって、多ピン化が容易であり、かつ薄型化を図ることができるようにした電子部品の実装構造を提供することができる。 As described above, according to the electronic component mounting structure 10 of the first embodiment, the LSI chip (electronic component) formed such that the first wiring layer 1A and the second wiring layer 1B are drawn from the surface side to the side surface. 2 is disposed in the through hole 3 of the substrate 6 in which the through hole 3 is formed in the substantially central portion and the first conductor layer 5A and the second conductor layer 5B are formed on the inner wall surface 4 of the through hole 3. Since the 1 wiring layer 1A and the first conductor layer 5A are connected via the solder (brazing material) 7A, the second wiring layer 1B and the second conductor layer 5B are connected via the solder 7B. Since a conventional bonding wire is not used, the height of the wire loop does not occur, and a separate substrate directly under the chip as in the conventional flip chip bonding is not required. Further, since there is no need for a flexible substrate such as a film carrier substrate, the number of wiring layers is not limited.
Therefore, it is possible to provide a mounting structure for an electronic component that can be easily multi-pinned and can be thinned.

実施形態２Embodiment 2

図５及び図６は、この発明の実施形態２である電子部品の実装方法を工程順に示す工程図である。以下、同図を参照して工程順に説明する。
まず、図５（ａ）に示すように、例えばＣｕなどから成る金属板２１を用意する。この金属板２１は、実装構造を組立てるための支持基板としての役割を担うためのもので、最終的な実装構造には存在しないものである。 5 and 6 are process diagrams showing the electronic component mounting method according to the second embodiment of the present invention in the order of processes. The process will be described below in the order of steps with reference to FIG.
First, as shown in FIG. 5A, a metal plate 21 made of, for example, Cu is prepared. The metal plate 21 serves as a support substrate for assembling the mounting structure, and does not exist in the final mounting structure.

次に、図５（ｂ）に示すように、金属板１上にＬＳＩチップ２を半導体回路の形成面（回路機能部形成面）を上にして裏面側を仮固定する。これには適当な接着剤を用いることが望ましい。   Next, as shown in FIG. 5B, the LSI chip 2 is temporarily fixed on the metal plate 1 with the semiconductor circuit formation surface (circuit function part formation surface) facing up. For this, it is desirable to use a suitable adhesive.

次に、図５（ｃ）に示すように、ＬＳＩチップ２の周囲の金属板２１上に液状の感光性樹脂を塗布した後、乾燥させて樹脂層２２を形成する。この樹脂層２２の厚さはＬＳＩチップ２の厚さと略等しくなるように形成するのが望ましい。これは感光性樹脂の塗布時のスピンナーの回転速度、乾燥時の温度、時間などの条件を調整することで可能となる。   Next, as shown in FIG. 5C, a liquid photosensitive resin is applied on the metal plate 21 around the LSI chip 2 and then dried to form a resin layer 22. The thickness of the resin layer 22 is preferably formed so as to be substantially equal to the thickness of the LSI chip 2. This can be achieved by adjusting conditions such as the spinner rotation speed at the time of application of the photosensitive resin, the temperature at the time of drying, and the time.

次に、図５（ｄ）に示すように、ＬＳＩチップ２の半導体回路形成面及び樹脂層２２を覆うように樹脂シート２３を貼り付ける。この樹脂シート２３はエポキシ樹脂、ポリイミド樹脂や、感光性樹脂などを用いることができる。あるいは、ガラスクロスやフィラーなどがそれらに含まれていてもよい。   Next, as illustrated in FIG. 5D, a resin sheet 23 is attached so as to cover the semiconductor circuit formation surface of the LSI chip 2 and the resin layer 22. As the resin sheet 23, an epoxy resin, a polyimide resin, a photosensitive resin, or the like can be used. Or glass cloth, a filler, etc. may be contained in them.

次に、図５（ｅ）に示すように、樹脂シート２３を選択的に除去してＬＳＩチップ２の半導体回路形成面を選択的に露出させるビア孔（開口）２４を形成する。このビア孔２４は、例えばレーザー光を利用して樹脂シート２３を選択的に加工することにより、容易に形成することができる。あるいは、樹脂シート２３として感光性樹脂を利用する場合には、通常の写真処理のように露光、現像を行ってビア孔２４を形成する。   Next, as shown in FIG. 5E, the resin sheet 23 is selectively removed to form a via hole (opening) 24 that selectively exposes the semiconductor circuit formation surface of the LSI chip 2. The via hole 24 can be easily formed by, for example, selectively processing the resin sheet 23 using laser light. Alternatively, when a photosensitive resin is used as the resin sheet 23, the via hole 24 is formed by performing exposure and development as in normal photographic processing.

次に、図５（ｆ）に示すように、メッキ処理を行ってビア孔２４から樹脂シート２３に沿ってＬＳＩチップ２の外部方向に引出すように例えばＣｕ層を形成した後、このＣｕ層のパターニングを行って第１配線層１Ａ及び第２配線層１Ｂを形成するとともに、所望の回路パターンを形成する。次に、選択的にソルダーレジスト１３を形成する。ソルダーレジスト１３は、はんだ付けが不要な個所をマスクしてはんだが濡れ広がるのを防止する役割を担い、隣接した電極同士の短絡を防止する。   Next, as shown in FIG. 5F, for example, a Cu layer is formed so as to be drawn out from the via hole 24 along the resin sheet 23 along the resin sheet 23 toward the outside of the LSI chip 2. Patterning is performed to form the first wiring layer 1A and the second wiring layer 1B, and a desired circuit pattern is formed. Next, a solder resist 13 is selectively formed. The solder resist 13 plays a role of preventing the solder from spreading by masking a portion where soldering is unnecessary, and prevents a short circuit between adjacent electrodes.

次に、図６（ａ）に示すように、図５（ｆ）における金属板２１をエッチングにより除去した後、樹脂層２２を剥離して除去する。ここで、金属板２１をエッチングするときは、第１及び第２配線層１Ａ、１Ｂの形成面側がエッチングされるのを防止するために、この面をエッチングレジストとなるフィルムで覆って保護しておく。   Next, as shown in FIG. 6A, after removing the metal plate 21 in FIG. 5F by etching, the resin layer 22 is peeled off and removed. Here, when the metal plate 21 is etched, in order to prevent the formation surface side of the first and second wiring layers 1A, 1B from being etched, this surface is covered and protected by a film serving as an etching resist. deep.

次に、図６（ｈ）に示すように、ソルダーレジスト１３により露出している第１及び第２配線層１Ａ、１Ｂの上方にはんだ７Ａ、７Ｂを供給する。これらのはんだ７Ａ、７Ｂは、後述するように第１及び第２配線層１Ａ、１Ｂと対応した基板２の第１及び第２導体層５Ａ、５Ｂとをはんだ付けするためのもので、前述したように周知のろう材の中から任意のものが選択される。これらのはんだ７Ａ、７Ｂの供給は、予めはんだボールを該当個所に搭載したり、あるいはクリームはんだを該当個所に印刷した後加熱により溶融させてボール状にする方法などをとることができる。   Next, as shown in FIG. 6H, solders 7A and 7B are supplied above the first and second wiring layers 1A and 1B exposed by the solder resist 13. These solders 7A and 7B are for soldering the first and second conductor layers 5A and 5B of the substrate 2 corresponding to the first and second wiring layers 1A and 1B, as will be described later. Thus, an arbitrary one is selected from known brazing materials. The supply of these solders 7A and 7B can be carried out by mounting a solder ball in a corresponding location in advance or by printing a cream solder on the corresponding location and then melting it by heating to form a ball.

次に、図６（ｉ）に示すように、樹脂シート２３、第１及び第２配線層１Ａ、１Ｂ、及びソルダーレジスト１３から成る一体化構成部をＬＳＩチップ２の側面方向に向かって、はんだ７Ａ、７ＢがＬＳＩチップ２の側面に位置するように屈曲させる。図１及び図２からも明らかなように、その一体化構成部はＬＳＩチップ２の四辺において屈曲されるので、予め一体化構成部を、ＬＳＩチップ２を中心にして、ＬＳＩチップ２と略同じ大きさで十字の形状に外形加工しておくことが望ましい。また、一体化構成部を屈曲させたとき、樹脂シート２３とＬＳＩチップ２の側面とは接着しても、しなくともよい。さらに、一体化構成部を屈曲させたときこの先端部がＬＳＩチップ２の裏面まで回り込まないように、余分の寸法分を外形加工して除去しておくことが望ましい。   Next, as shown in FIG. 6 (i), the integrated component composed of the resin sheet 23, the first and second wiring layers 1 A and 1 B, and the solder resist 13 is soldered toward the side surface of the LSI chip 2. Bending is performed so that 7A and 7B are located on the side surface of the LSI chip 2. As apparent from FIGS. 1 and 2, the integrated component is bent at four sides of the LSI chip 2, so that the integrated component is substantially the same as the LSI chip 2 with the LSI chip 2 as the center. It is desirable to process the outer shape into a cross shape in size. Further, when the integrated component is bent, the resin sheet 23 and the side surface of the LSI chip 2 may or may not be bonded. Further, it is desirable that the extra dimension is removed by external processing so that the tip portion does not reach the back surface of the LSI chip 2 when the integrated component is bent.

次に、図６（ｊ）に示すように、予め略中央部に貫通孔３が形成されこの貫通孔３の内壁面４に第１及び第２導体層５Ａ、５Ｂが形成された基板６を用意して、貫通孔３にＬＳＩチップ２を反転させて配置し、第１及び第２配線層１Ａ、１Ｂがはんだ７Ａ、７Ｂを介して第１及び第２導体層５Ａ、５Ｂと対向するように配置する。続いて、加熱処理によりはんだ７Ａ、７Ｂを溶融させて、第１及び第２配線層１Ａ、１Ｂとそれぞれ対応する第１及び第２導体層５Ａ、５Ｂとをはんだ７Ａ、７Ｂを介して接続する。ここで、基板６の貫通孔３の平面的な大きさは、図６（ｉ）において、一体化構成部を屈曲させたとき、屈曲の後のＬＳＩチップ２の平面的な大きさと略同じか、あるいは小さめになるように一体化構成部を屈曲させることが望ましい。また、はんだ７Ａ、７Ｂによるはんだ付けの前に、基板６の内壁面４をフラックスで濡らしておくと、はんだ７Ａ、７Ｂの基板６への濡れ性を良好にすることができ、ＬＳＩチップ２と基板６間のはんだ付けを確実に行うことができる。
最後に、ＬＳＩチップ２の表面側及び基板６の裏面側にそれぞれ外部電極となるはんだボール９、１１を接続することで、図１〜図３に示したような電子部品の実装構造１０が完成する。 Next, as shown in FIG. 6 (j), the substrate 6 in which the through hole 3 is formed in the substantially central portion in advance and the first and second conductor layers 5A and 5B are formed on the inner wall surface 4 of the through hole 3 is formed. The LSI chip 2 is inverted and arranged in the through hole 3 so that the first and second wiring layers 1A and 1B face the first and second conductor layers 5A and 5B through the solders 7A and 7B. To place. Subsequently, the solders 7A and 7B are melted by heat treatment, and the first and second wiring layers 1A and 1B are respectively connected to the corresponding first and second conductor layers 5A and 5B via the solders 7A and 7B. . Here, the planar size of the through hole 3 of the substrate 6 is substantially the same as the planar size of the LSI chip 2 after bending when the integrated component is bent in FIG. Alternatively, it is desirable to bend the integrated component so as to be smaller. If the inner wall surface 4 of the substrate 6 is wetted with a flux before soldering with the solders 7A and 7B, the wettability of the solder 7A and 7B to the substrate 6 can be improved, and the LSI chip 2 Soldering between the substrates 6 can be performed reliably.
Finally, by connecting solder balls 9 and 11 as external electrodes to the front surface side of the LSI chip 2 and the back surface side of the substrate 6, the electronic component mounting structure 10 as shown in FIGS. 1 to 3 is completed. To do.

このように、本実施形態２の電子部品の実装方法によれば、半導体回路が形成されたＬＳＩチップ２の半導体回路形成面を樹脂シート２３により覆う工程と、樹脂シート２３を選択的に除去してＬＳＩチップ２の半導体開口形成面を選択的に露出するビア孔２４を形成した後、ビア孔２４から樹脂シート２３に沿ってＬＳＩチップ２の外部方向に引出すように第１及び第２配線層１Ａ、１Ｂを形成する工程と、各配線層１Ａ、１Ｂのはんだ付け予定個所を露出し、かつはんだ付け予定個所以外をマスクするソルダーレジスト１３を各配線層１Ａ、１Ｂ上に形成する工程と、樹脂シート２３、各配線層１Ａ、１Ｂ及びソルダーレジスト１３から成る一体化構成部をＬＳＩチップ２の側面に向かって屈曲して、各配線層１Ａ、１Ｂのはんだ付け予定個所をＬＳＩチップ２の側面に位置させる工程と、ＬＳＩチップ２を配置する貫通孔３が形成され、この貫通孔３の内壁面４に各配線層１Ａ、１Ｂに対応した第１及び第２導体層５Ａ、５Ｂが形成された基板６を用意して、この基板６の貫通孔３にＬＳＩチップ２を配置する工程と、ＬＳＩチップ２の各配線層１Ａ、１Ｂと基板６の各導体層５Ａ、５Ｂとを第１及び第２はんだ７Ａ、７Ｂにより接続する工程とを含むので、周知の製造工程を組合わせるだけで、多ピン化が容易であり、かつ薄型化を図ることができる電子部品の実装構造を容易に提供できる。   As described above, according to the electronic component mounting method of the second embodiment, the step of covering the semiconductor circuit formation surface of the LSI chip 2 on which the semiconductor circuit is formed with the resin sheet 23 and the resin sheet 23 are selectively removed. First and second wiring layers are formed so as to be drawn out from the via hole 24 along the resin sheet 23 toward the outside of the LSI chip 2. A step of forming 1A and 1B, a step of forming a solder resist 13 on each wiring layer 1A and 1B that exposes portions to be soldered of the wiring layers 1A and 1B and masks portions other than the portions to be soldered; An integrated component composed of the resin sheet 23, the wiring layers 1A and 1B, and the solder resist 13 is bent toward the side surface of the LSI chip 2 to pre-solder the wiring layers 1A and 1B. A step of positioning the location on the side surface of the LSI chip 2 and a through hole 3 in which the LSI chip 2 is disposed are formed, and first and second conductors corresponding to the wiring layers 1A and 1B are formed on the inner wall surface 4 of the through hole 3. A step of preparing the substrate 6 on which the layers 5A and 5B are formed and placing the LSI chip 2 in the through hole 3 of the substrate 6, and the wiring layers 1A and 1B of the LSI chip 2 and the conductor layers 5A of the substrate 6 5B is connected with the first and second solders 7A and 7B, so that the number of pins can be easily reduced and the thickness can be reduced only by combining known manufacturing processes. The mounting structure can be easily provided.

図７は、本実施形態２の電子部品の実装方法の一部の変形例を示すものである。この変形例では、図５（ａ）における支持基板としての金属板２１を用いることなく、図７（ａ）に示すように、スタート材として樹脂シート２３を用いてこの樹脂シート２３にＬＳＩチップ２を半導体回路の形成面が接するように搭載する。続いて、ＬＳＩチップ２の周囲の樹脂シート２３上に液状の感光性樹脂を塗布した後、乾燥させて樹脂層２２を形成する。この樹脂層２２の厚さはＬＳＩチップ２の厚さと略等しくなるように形成するのが望ましい。次に、図７（ｂ）に示すように、樹脂シート２３を選択的に除去してＬＳＩチップ２の半導体回路形成面を露出させるビア孔２４を形成する。以下、図５（ｆ）以下の工程に準じた工程を経ることにより、図１〜図３に示したような電子部品の実装構造１０を完成させる。   FIG. 7 shows a modification of a part of the electronic component mounting method according to the second embodiment. In this modification, without using the metal plate 21 as the support substrate in FIG. 5A, as shown in FIG. 7A, a resin sheet 23 is used as a starting material, and the LSI chip 2 is attached to the resin sheet 23. Is mounted so that the formation surface of the semiconductor circuit is in contact therewith. Subsequently, a liquid photosensitive resin is applied on the resin sheet 23 around the LSI chip 2 and then dried to form the resin layer 22. The thickness of the resin layer 22 is preferably formed so as to be substantially equal to the thickness of the LSI chip 2. Next, as shown in FIG. 7B, the resin sheet 23 is selectively removed to form a via hole 24 that exposes the semiconductor circuit formation surface of the LSI chip 2. Thereafter, the electronic component mounting structure 10 as shown in FIGS. 1 to 3 is completed through steps similar to those shown in FIG.

実施形態３Embodiment 3

図８は、この発明の実施形態３である電子部品の実装構造の概略構成を示す断面図である。この例の電子部品の実装構造の構成が、上述の実施形態１のそれと大きく異なるところは、電子部品の側面だけでなく裏面にまで配線層を位置させるようにした点である。また、電子部品と基板とのろう付けは１個所のみで行う例で示している。
この実施形態３の電子部品の実装構造２０は、図８に示すように、実施形態１の図５（ｆ）の工程に相当した工程で、Ｃｕ層のパターニングを行って第１配線層１４Ａ、第２配線層１４Ｂ及び第３配線層１４Ｃを形成した後、図６（ｉ）の工程に相当した工程で、樹脂シート２３、第１〜第３配線層１４Ａ〜１４Ｃ及びソルダーレジスト１３から成る一体化構成部をＬＳＩチップ２の側面方向に向かって、第３配線層１３Ｃ及びはんだ７がＬＳＩチップ２の側面に位置するように屈曲させた後に、さらに一体化構成材をＬＳＩチップ２の裏面方向に向かって屈曲させたＬＳＩチップ２を用いて、基板６の貫通孔３に反転して配置し、第３配線層１４Ｃと基板６の対応した導体層５とをはんだ７を介して接続したものである。このような電子部品の実装構造２０によれば、ＬＳＩチップ２の裏面にも第１及び第２配線層１４Ａ、１４Ｂが形成されているので、この実装構造２０を単位実装構造として複数積層して新たな電子部品の実装構造を実現することにより、３次元的な実装構造を得ることができ、高密度実装が可能になる。
これ以外は、上述した実施形態１と略同様である。それゆえ、図８において、図３の構成部分と対応する各部には、同一の番号を付してその説明を省略する。 FIG. 8 is a cross-sectional view showing a schematic configuration of an electronic component mounting structure according to Embodiment 3 of the present invention. The configuration of the electronic component mounting structure in this example is greatly different from that of the first embodiment described above in that the wiring layer is positioned not only on the side surface but also on the back surface of the electronic component. In addition, an example in which the electronic component and the substrate are brazed at only one place is shown.
As shown in FIG. 8, the electronic component mounting structure 20 according to the third embodiment performs patterning of the Cu layer in a process corresponding to the process of FIG. After the formation of the second wiring layer 14B and the third wiring layer 14C, the resin sheet 23, the first to third wiring layers 14A to 14C, and the solder resist 13 are integrated in a step corresponding to the step of FIG. The integrated component is bent so that the third wiring layer 13C and the solder 7 are located on the side surface of the LSI chip 2 in the direction toward the side surface of the LSI chip 2, and then the integrated component is further formed in the rear surface direction of the LSI chip 2. Inverted and arranged in the through hole 3 of the substrate 6 using the LSI chip 2 bent toward the surface, and the third wiring layer 14C and the corresponding conductor layer 5 of the substrate 6 are connected via the solder 7 It is. According to such an electronic component mounting structure 20, since the first and second wiring layers 14A and 14B are also formed on the back surface of the LSI chip 2, a plurality of the mounting structures 20 are stacked as a unit mounting structure. By realizing a new electronic component mounting structure, a three-dimensional mounting structure can be obtained, and high-density mounting becomes possible.
Except this, it is substantially the same as the first embodiment described above. Therefore, in FIG. 8, the same reference numerals are given to the respective parts corresponding to the constituent parts of FIG.

このように、実施形態３による電子部品の実装構造２０によっても、実施形態１と略同様な効果を得ることができ、加えて３次元実装が可能な実装構造を得ることができる。   As described above, the electronic component mounting structure 20 according to the third embodiment can provide substantially the same effect as that of the first embodiment, and can also provide a mounting structure that can be three-dimensionally mounted.

実施形態４Embodiment 4

図９は、この発明の実施形態４である電子部品の実装構造の概略構成を示す断面図である。この例の電子部品の実装構造の構成が、上述の実施形態３のそれと大きく異なるところは、具体的に３次元実装を実現するようにした点である。
この実施形態４の電子部品の実装構造３０は、実施形態３の電子部品の実装構造２０を単位実装構造として、その実装構造２０と構成が異なる他の電子部品の実装構造２５を組合わせて複数の実装構造を積層したものである。他の電子部品の実装構造２５は、実装構造２０と同様にＬＳＩチップ２の側面に第３配線層１８Ｃが形成されるとともに、その裏面に第１及び第２配線層１８Ａ、１８Ｂが形成されている。そして、実装構造２０と実装構造２５とははんだボール９，１１を介して積層されて電子部品の実装構造３０が構成されている。 FIG. 9 is a cross-sectional view showing a schematic configuration of an electronic component mounting structure according to Embodiment 4 of the present invention. The configuration of the electronic component mounting structure in this example is significantly different from that of the third embodiment described above in that three-dimensional mounting is specifically realized.
The electronic component mounting structure 30 according to the fourth embodiment includes the electronic component mounting structure 20 according to the third embodiment as a unit mounting structure, and a combination of other electronic component mounting structures 25 having different configurations from the mounting structure 20. These mounting structures are laminated. Similar to the mounting structure 20, the other electronic component mounting structure 25 has the third wiring layer 18C formed on the side surface of the LSI chip 2 and the first and second wiring layers 18A and 18B formed on the back surface thereof. Yes. The mounting structure 20 and the mounting structure 25 are stacked via solder balls 9 and 11 to form an electronic component mounting structure 30.

このように、実施形態４による電子部品の実装構造３０によれば、具体的な３次元実装を実現できる実装構造を得ることができるので、高密度実装を図ることができる。   As described above, according to the electronic component mounting structure 30 according to the fourth embodiment, a mounting structure capable of realizing a specific three-dimensional mounting can be obtained, so that high-density mounting can be achieved.

以上、この発明の実施形態を図面により詳述してきたが、具体的な構成はこの実施形態に限られるものではなく、この発明の要旨を逸脱しない範囲の設計の変更等があってもこの発明に含まれる。例えば、各実施形態では電子部品としてＬＳＩに例をあげて説明したが、これに限らずにキャパシタ、インダクタなどの受動素子を含めた他の回路素子に対しても同様に適用することができる。また、ＬＳＩチップの平面形状は正方形、長方形などの四辺を有する方形形状であれば適用することができる。また、電子部品と基板とのろう付けに用いるろう材は、実施形態で例示した合金材料に限らずに目的に応じて任意のものを選択することができる。   The embodiment of the present invention has been described in detail with reference to the drawings. However, the specific configuration is not limited to this embodiment, and the present invention can be changed even if there is a design change or the like without departing from the gist of the present invention. include. For example, in each embodiment, an LSI is described as an example of an electronic component. However, the present invention is not limited to this, and the present invention can be similarly applied to other circuit elements including passive elements such as capacitors and inductors. The planar shape of the LSI chip can be applied as long as it is a square shape having four sides such as a square and a rectangle. Further, the brazing material used for brazing the electronic component and the substrate is not limited to the alloy material exemplified in the embodiment, and any material can be selected according to the purpose.

この発明の実施形態１である電子部品の実装構造の概略構成を示す平面図である。It is a top view which shows schematic structure of the mounting structure of the electronic component which is Embodiment 1 of this invention. 同電子部品の実装構造の概略構成を示す底面図である。It is a bottom view which shows schematic structure of the mounting structure of the same electronic component. 図１のＡ‐Ａ矢視断面図である。It is AA arrow sectional drawing of FIG. 同電子部品の実装構造の主要部の概略構成図を示す斜視図である。It is a perspective view which shows schematic structure figure of the principal part of the mounting structure of the same electronic component. この発明の実施形態２である電子部品の実装方法を工程順に示す断面図である。It is sectional drawing which shows the mounting method of the electronic component which is Embodiment 2 of this invention in order of a process. 同電子部品の実装方法を工程順に示す断面図である。It is sectional drawing which shows the mounting method of the same electronic component in process order. 同電子部品の実装方法の一部の変形例を工程順に示す断面図である。It is sectional drawing which shows the one part modification of the mounting method of the electronic component to process order. この発明の実施形態３である電子部品の実装構造の概略構成を示す断面図である。It is sectional drawing which shows schematic structure of the mounting structure of the electronic component which is Embodiment 3 of this invention. この発明の実施形態４である電子部品の実装構造の概略構成を示す断面図である。It is sectional drawing which shows schematic structure of the mounting structure of the electronic component which is Embodiment 4 of this invention. 従来の電子部品の実装構造の概略構成を示す断面図である。It is sectional drawing which shows schematic structure of the mounting structure of the conventional electronic component. 従来の電子部品の実装構造の概略構成を示す断面図である。It is sectional drawing which shows schematic structure of the mounting structure of the conventional electronic component. 従来の電子部品の実装構造の概略構成を示す断面図である。It is sectional drawing which shows schematic structure of the mounting structure of the conventional electronic component. 従来の電子部品の実装構造の概略構成を示す断面図である。It is sectional drawing which shows schematic structure of the mounting structure of the conventional electronic component. 従来の電子部品の実装構造の概略構成を示す断面図であるIt is sectional drawing which shows schematic structure of the mounting structure of the conventional electronic component.

符号の説明Explanation of symbols

１Ａ、１Ｂ、１６Ａ〜１６Ｃ、１８Ａ〜１８Ｃ 配線層
２ ＬＳＩチップ（電子部品）
３ 貫通孔
４ 基板の内壁面
５、５Ａ、５Ｂ、１４Ａ〜１４Ｃ 導体層
６ 基板（基板）
７、７Ａ、７Ｂ はんだ（ろう材）
９，１１ はんだボール
１０、２０、２５，３０ 電子部品の実装構造
１２、１７Ａ〜１７Ｃ 絶縁層
１３ ソルダーレジスト
１５ 半スルーホール構造
２１ 金属板（支持基板）
２２ 樹脂層
２３ 樹脂シート（絶縁性シート材）
２４ ビア孔（開口） 1A, 1B, 16A-16C, 18A-18C Wiring layer 2 LSI chip (electronic component)
3 Through-hole 4 Inner wall surface of substrate 5, 5A, 5B, 14A-14C Conductor layer 6 Substrate (substrate)
7, 7A, 7B Solder (brazing material)
9, 11 Solder balls 10, 20, 25, 30 Electronic component mounting structure 12, 17A to 17C Insulating layer 13 Solder resist 15 Half-through-hole structure 21 Metal plate (support substrate)
22 Resin layer 23 Resin sheet (insulating sheet material)
24 Via hole (opening)

Claims (3)

配線層が形成された電子部品と前記配線層に対応した導体層が形成された基板とを、前記配線層及び前記導体層が対向するように配置して、該両層をろう材を介して接続する電子部品の実装方法であって、
回路が形成された電子部品の回路形成面を絶縁性シート材により覆う工程と、
前記絶縁性シート材を選択的に除去して前記電子部品の回路形成面を選択的に露出する開口を形成した後、該開口から前記絶縁性シート材に沿って前記電子部品の外部方向に引出すように配線層を形成する工程と、
前記配線層のろう付け予定個所を露出し、かつ前記ろう付け予定個所以外をマスクするソルダーレジストを前記配線層上に形成する工程と、
前記配線層及び前記絶縁性シート材を含む一体化構成部を前記電子部品の側面に向かって屈曲して、前記配線層の前記ろう付け予定個所を前記電子部品の側面に位置させる工程と、
前記電子部品を配置する貫通孔が形成され、該貫通孔の内壁面に前記配線層に対応した導体層が形成された基板を用意して、該基板の前記貫通孔に前記電子部品を配置する工程と、
前記電子部品の前記配線層と前記基板の導体層とをろう材により接続する工程と、
を含むことを特徴とする電子部品の実装方法。 An electronic component on which a wiring layer is formed and a substrate on which a conductor layer corresponding to the wiring layer is formed are arranged so that the wiring layer and the conductor layer face each other, and the two layers are interposed via a brazing material. A method of mounting electronic components to be connected,
Covering the circuit forming surface of the electronic component on which the circuit is formed with an insulating sheet material;
After the insulating sheet material is selectively removed to form an opening that selectively exposes the circuit forming surface of the electronic component, the opening is drawn from the opening along the insulating sheet material to the outside of the electronic component. A step of forming a wiring layer,
Forming a solder resist on the wiring layer for exposing the portions to be brazed of the wiring layer and masking portions other than the portions to be brazed;
Bending the integrated component including the wiring layer and the insulating sheet material toward the side surface of the electronic component, and positioning the planned brazing point of the wiring layer on the side surface of the electronic component;
A substrate in which a through hole for arranging the electronic component is formed and a conductor layer corresponding to the wiring layer is formed on an inner wall surface of the through hole is prepared, and the electronic component is arranged in the through hole of the substrate. Process,
Connecting the wiring layer of the electronic component and the conductor layer of the substrate with a brazing material;
A method for mounting an electronic component, comprising: 前記配線層の前記ろう付け予定個所を前記電子部品の側面に位置させる工程の前に、
前記配線層の前記ろう付け予定個所にろう材を供給する工程と、
を含むことを特徴とする請求項１記載の電子部品の実装方法。 Before the step of positioning the wiring layer to be brazed on the side surface of the electronic component,
Supplying a brazing material to the portion to be brazed of the wiring layer;
Electronic part mounting method according to claim 1, characterized in that it comprises a. 前記配線層の前記ろう付け予定個所を前記電子部品の側面に位置させる工程において
前記基板の前記貫通孔の平面的な大きさが前記屈曲の後の前記電子部品の平面的な大きさと略同じか、あるいは小さめになるように前記一体化構成部を屈曲させる、
ことを特徴とする請求項１又は２記載の電子部品の実装方法。 In the step of positioning the portion to be brazed of the wiring layer on the side surface of the electronic component, whether the planar size of the through hole of the substrate is substantially the same as the planar size of the electronic component after the bending Or bend the integrated component to be smaller,
3. The electronic component mounting method according to claim 1, wherein the electronic component is mounted.
JP2008052745A 2008-03-03 2008-03-03 Electronic component mounting method Expired - Fee Related JP5115241B2 (en)

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