JP4629912B2 - Method of forming solder bump - Google Patents

Method of forming solder bump Download PDF

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Publication number
JP4629912B2
JP4629912B2 JP2001157076A JP2001157076A JP4629912B2 JP 4629912 B2 JP4629912 B2 JP 4629912B2 JP 2001157076 A JP2001157076 A JP 2001157076A JP 2001157076 A JP2001157076 A JP 2001157076A JP 4629912 B2 JP4629912 B2 JP 4629912B2
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bump electrodes
group
bump
electrode
solder paste
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JP2002353272A (en
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城次 藤森
一郎 山口
政廣 吉川
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Fujitsu Semiconductor Ltd
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Fujitsu Semiconductor Ltd
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
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    • H01—ELECTRIC ELEMENTS
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
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    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
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    • H01L2924/01005—Boron [B]
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Description

【０００１】
【発明の属する技術分野】
本発明は基板上に設けられた電極パッド上にバンプ電極を形成する方法に関する。
【０００２】
【従来の技術】
近年、電子部品実装には、高密度化が要求されているが、さらなる高密度化として、複数の機能を一体化させたシステムＬＳＩが要求されてきた。この要求に答えるべく、単一の半導体素子に複数の機能をもたせようとしたが、製造上の問題点が多く現在実用されていない。これに代わり、それぞれの機能を有する半導体素子を３次元的に実装した半導体装置が注目されている。例えば２つの半導体チップを積層し、この積層体を基板に実装する。このような３次元的な実装形態の半導体装置では、半導体素子と半導体素子との間及び半導体素子と基板との間の接続は従来はほとんどワイヤボンディングによって行われている。このような接続をバンプ電極によって行うことができれば、より高密度で高速化が可能になる。
【０００３】
【発明が解決しようとする課題】
しかしながら、バンプ電極を用いて３次元的な実装形態の半導体装置を得るには、個々の半導体素子にバンプ電極を形成し、それから２つの半導体素子をバンプ電極を用いて実装し、こうして得られた積層体をさらなる半導体素子又は基板にバンプ電極を用いて実装することが必要となる。このような３次元的な実装形態は、製造工程数や製造コストのアップにつながってしまう。
【０００４】
さらに、バンプ電極の狭ピッチ化に伴い、バンプ電極の高さのバラツキが大きいと、接合不良が発生する確率が高くなる危険性もあり、効率的な方法ではないと思われる。
また、実装上の問題点としては、単一組成のバンプ電極であると、半導体の実装時における荷重のバラツキ等によりバンプ電極同志でショートが発生する可能性がある。特に、この傾向は、共晶組成のはんだバンプ電極の場合に見られることがある。さらに、熱ストレスに脆く、バンプ電極により接合された半導体が剥がれてしまうという問題も抱えている。
【０００５】
本発明の目的は、より簡単に且つ確実に３次元的な実装形態の半導体装置を得ることのできるはんだバンプの形成方法を提供することである。
【０００６】
【課題を解決するための手段】
本発明によるはんだバンプの形成方法は、複数の群の電極パッドを有する基板の表面を覆う膜を形成する工程と、該膜に各電極パッドに対応し且つ該電極パッドの群毎に大きさの異なる開口部を形成する工程と、該開口部内にはんだペーストを充填し、それからリフローを行うことにより、該開口部内で電極パッドに固定されたバンプ電極を形成する工程と、該膜を除去する工程と、からなり、複数の群の電極パッドは少なくとも第１群の電極パッド及び第２群の電極パッドを含み、ｎを自然数とするとき、第１群の電極パッド上のバンプ電極の形成はｎ回のはんだペーストの充填及びリフローにより実施され、第２群の電極パッド上のバンプ電極の形成はｎ回とは異なる回数のはんだペーストの充填及びリフローにより実施されることを特徴とするものである。
【０００７】
この方法によれば、基板上に複数の群のバンプ電極が形成される。例えば、第１の群のバンプ電極は第１の半導体素子を接合するためのものであり、第２の群のバンプ電極は第２の半導体素子を接合するためのものである。このようにして、１つの基板に２つの半導体素子を容易に実装することができる。そして、第２の群のバンプ電極が第１の群のバンプ電極よりも高いと、最初に第１の半導体素子を第１の群のバンプ電極によって基板に実装し、それから第２の半導体素子を第１の半導体素子の上に載せた状態で第２の群のバンプ電極によって基板に実装することができる。さらに、第１の群のバンプ電極と第２の群のバンプ電極とは組成が異なるようにすることもできる。こうすれば、第１の半導体素子の実装と、第２の半導体素子の実装とを温度を変えて行うことができ、製造不良の発生を抑え、コストアップを防止することができる。さらに、各バンプ電極は高融点コアを有する構造とすることもでき、実装時のバンプショートを防止するとともに、実装時もしくは実装後のストレスを緩和する。
【０００８】
【発明の実施の形態】
以下本発明の実施例について図面を参照して説明する。
図１は本発明の実施例の半導体装置を示す断面図である。図２は図１の半導体装置を示す略解的平面図である。半導体装置１０は、プリント配線基板１２と、第１の半導体素子１４と、第２の半導体素子１６と、第３の半導体素子１８とからなる。第１、第２、第３の半導体素子１４，１６，１８はそれぞれに異なった機能を有する。
【０００９】
図１及び図２においては、基板としてプリント配線基板１２が例示されているが、本発明の基板はプリント配線基板１２に限定されるものではない。本明細書で単に基板というときは、プリント配線基板や半導体ウエハなどの狭義の基板ばかりでなく、バンプ電極の形成対象となりうるその他の全てのものを指すものである。
【００１０】
プリント配線基板１２は、第１群のバンプ電極２０と、第２群のバンプ電極２２と、第３群のバンプ電極２４とを含む。第１群のバンプ電極２０はプリント配線基板１２の中央部に位置し、最も背が低く、且つ最も面積が小さい。第２群のバンプ電極２２は第１群のバンプ電極２０の外側に位置し、第１群のバンプ電極２０よりも背が高く、且つ面積が大きい。第３群のバンプ電極２４は第２群のバンプ電極２２の外側に位置し、第２群のバンプ電極２２よりも背が高く、且つ面積が大きい。
【００１１】
第１の半導体素子１４は第１群のバンプ電極２０によってプリント配線基板１２に実装される。第２の半導体素子１６は第１の半導体素子１４に載った状態で第２群のバンプ電極２２によってプリント配線基板１２に実装される。第２の半導体素子１８は第２の半導体素子１６に載った状態で第３群のバンプ電極２４によってプリント配線基板１２に実装される。このようにして、３次元的に実装された３つの半導体素子１４，１６，１８からなる半導体装置１０を簡単に且つ確実に製造することができる。本実施例では、複数の半導体素子用のバンプ電極が単一基板へ一括して形成されている。
【００１２】
図３は本発明の実施例のはんだバンプの形成方法を示す図である。図４は図３のはんだバンプの形成方法の続きの工程を示す図である。図５は図３のはんだバンプの形成方法の続きの工程を示す図である。
図３（Ａ）において、複数の群の電極パッド２０Ａ，２２Ａ，２４Ａを有するプリント配線基板１２を準備する。第１群の電極パッド２０Ａは図１の第１群のバンプ電極２０に対応する位置に形成されている。第２群の電極パッド２２Ａは図１の第２群のバンプ電極２２に対応する位置に形成されている。第３群の電極パッド２４Ａは図１の第３群のバンプ電極２４に対応する位置に形成されている。第３群の電極パッド２４Ａの面積は第２群の電極パッド２２Ａの面積よりも大きく、第２群の電極パッド２２Ａの面積は第１群の電極パッド２０Ａの面積よりも大きい。
【００１３】
樹脂の膜２６が電極パッド２０Ａ，２２Ａ，２４Ａを覆うようにプリント配線基板１２の表面を覆って形成される。樹脂の膜２６は好ましくはレジストからなる。一例においては、樹脂の膜２６はプリント配線基板１２の表面にラミネートされたドライフィルムレジストからなる。また、樹脂の膜２６はプリント配線基板１２の表面に塗布されたレジストでもよい。
【００１４】
図３（Ｂ）において、樹脂の膜２６に各電極パッド２０Ａ，２２Ａ，２４Ａに対応し且つ該電極パッド２０Ａ，２２Ａ，２４Ａ群毎に大きさの異なる開口部２０Ｂ，２２Ｂ，２４Ｂを形成する。開口部２０Ｂ，２２Ｂ，２４Ｂは、レジストからなる樹脂の膜２６に、露光及び現像により形成される。このとき、２段目に実装される第２の半導体素子１６を接合するためのバンプ電極２２を形成するための開口部２２Ｂの大きさは、１段目に実装される第１の半導体素子１４を接合するためバンプ電極２０を形成するための開口部２０Ａの大きさよりも大きく形成しておく。同様に、３段目に実装される第３の半導体素子１８を接合するためのバンプ電極２４を形成するための開口部２４Ｂの大きさは、２段目に実装される第２の半導体素子１６を接合するためバンプ電極２２を形成するための開口部２２Ａの大きさよりも大きく形成しておく。
【００１５】
図３（Ｃ）において、樹脂の膜２６の表面にバンプ電極となる金属を含むはんだペースト２８を供給し、スキージングによりはんだペースト２８を開口部２０Ｂ，２２Ｂ，２４Ｂに充填する。
図３（Ｄ）において、はんだペースト２８をリフローし、はんだペースト２８中の金属によりバンプ電極２０，２２，２４を形成する。バンプ電極２０，２２，２４は電極パッド２０Ａ，２２Ａ，２４Ａにそれぞれ溶着される。その後、はんだペースト２８中のフラックス成分は洗浄される。
【００１６】
図４（Ａ）において、２段目に実装される第２の半導体素子１６を接合するためのバンプ電極２２を形成するための開口部２２Ｂに相当する位置にのみ開口部を有するメタルマスク３０を被せ、スキージングにより開口部２２Ｂにはんだペースト３２を充填する。このはんだペースト３２中の金属の融点は、最初に充填されたはんだペースト２８中の金属の融点より低い。例えば、１回目に充填されたはんだペースト２８中の金属は、Ｓｎ：Ｐｂ＝９０〜９５：１０〜５の合金である。２回目に充填されたはんだペースト３２中の金属は、Ｓｎ：Ａｇ＝９９〜９５：１〜５の合金である。
【００１７】
図４（Ｂ）において、メタルマスク３０を剥がす。
図４（Ｃ）において、はんだペースト３２をリフローし、バンプ電極２２を再形成する。リフローは、最初に充填されたはんだペースト２８中の金属の融点より低く、今回充填されたはんだペースト３２中の金属の融点よりも高い温度で加熱することにより実施される。はんだペースト３２中の金属が溶融し、前に形成したはんだペースト２８中の金属で形成されたバンプ電極２０，２４及びバンプ電極２２の部分（コア）は溶融しない。こうして、高融点のコアを有するバンプ電極２２を形成する。バンプ電極２２の高さはバンプ電極２０の高さよりも高くなる。その後、はんだペースト３２中のフラックス成分は洗浄される。
【００１８】
さらに、図５（Ａ）において、３段目に実装される第３の半導体素子１８を接合するためのバンプ電極２４を形成するための開口部２４Ｂに相当する位置にのみ開口部を有するメタルマスク３４を被せ、スキージングにより開口部２４Ｂにはんだペースト３６を充填する。このはんだペースト３６は、２回目に充填されたはんだペースト３２中の金属の融点より低い融点を有する金属を含む。例えば、３回目に充填されたはんだペースト３６中の金属は、Ｓｎ：Ｐｂ＝６０〜７０：４０〜３０の合金である。
【００１９】
図５（Ｂ）において、メタルマスク３４を剥がす。
図５（Ｃ）において、はんだペースト３６をリフローし、バンプ電極２４を再形成する。リフローは、２回目に充填されたはんだペースト３２中の金属の融点より低く、今回充填されたはんだペースト３６中の金属の融点よりも高い温度で加熱することにより実施される。はんだペースト３６中の金属が溶融し、前に形成したはんだペースト２８，３２中の金属で形成されたバンプ電極２０，２２及びバンプ電極２４のコアは溶融しない。こうして、高融点のコアを有するバンプ電極２４を形成する。バンプ電極２４の高さはバンプ電極２２，２０の高さよりも高くなる。その後、はんだペースト３２中のフラックス成分は洗浄される。
【００２０】
図５（Ｄ）において、プリント配線基板１２を覆っていた樹脂の膜２６を剥離する。これによって、プリント配線基板１２は、サイズ、組成、高さの異なる複数のバンプ電極２０，２２，２４を有することになる。
これらのバンプ電極２０，２２，２４の組成に適応した温度で、第１、第２、第３の半導体素子１４，１６，１８をプリント配線基板１２にフリップチップ実装することにより、図１及び図２に示された３次元な実装構造の半導体装置１０を得ることができる。この場合、第１、第２、第３の半導体素子１４，１６，１８は、バンプ電極２０，２２，２４の融点に合わせて、段階的に実装される。積層実装される上段の半導体素子１６，１８は、下段の半導体素子１４，１６に比べ長辺を有している。
【００２１】
上記方法により形成されたバンプ電極を用い、チップオンチップパッケージ、システムインパッケージ、及びチップオンチップモジュールとともに、積層実装されたパッケージ及びモジュール化形態の半導体装置を製造することが可能である。
以上説明したように、単一基板上へサイズ、組成、高さの異なるバンプ電極を形成することにより、ベアチップ実装を行うために個々の半導体素子へバンプ電極を形成する工程を省略することができる。バンプ電極を形成する基板の簡略化も可能である。上段に実装される半導体素子用の電極パッド及びバンプ電極のサイズが大きいため、実装ストレスによるバンプ電極と電極パッドの間での剥がれによる電気的な接触不良を防止できる。また、各バンプ電極は、高融点コアを有しているため、実装時のバンプ電極間のショートを防止できるとともに、実装時及び実装後にかかるストレスによるバンプの変移を吸収でき、効果は大きい。
【００２２】
また、本実施例では、樹脂の膜２６に複数の群に分けられる開口部を形成した後、その開口部にはんだペーストを充填し、リフローによりバンプ電極を形成する。そして、樹脂の膜２６の開口部へのはんだペーストの充填は、樹脂の膜２６の表面ではんだペーストをスキージングすることにより行う方法と、又はメタルマスクを被せてスキージングにより充填する方法とがある。本実施例では、これらの２つのスキージングを併用している。上記方法により形成されるバンプ電極は、最後の工程で形成されたバンプ電極以外の全てのバンプ電極が、樹脂の膜よりも突出していない。
【００２３】
図６は本発明の他の実施例の半導体装置を示す略解的平面図である。半導体装置４０は、プリント配線基板４２と、第１の半導体素子２４と、第２の半導体素子２６と、第３の半導体素子２８とからなる。第２、第３の半導体素子２６，１８は互いに同じ機能を有する。プリント配線基板４２は、第１群のバンプ電極５０と、第２群のバンプ電極５２と、第３群のバンプ電極５４とを含む。第１群のバンプ電極５０はプリント配線基板４２の中央部に位置し、最も背が低く、且つ最も面積が小さい。第２、第３群のバンプ電極５２，５４は第１群のバンプ電極５０の外側に互いに対称に位置し、第１群のバンプ電極５０よりも背が高く、且つ面積が大きい。第１の半導体素子４４は第１群のバンプ電極５０によってプリント配線基板４２に実装される。第２、第３の半導体素子４６，４８は第１の半導体素子４４に載った状態で第２、第３群のバンプ電極５２，５４によってプリント配線基板４２に実装される。バンプ電極５０，５２，５４はプリント配線基板４２に図３から図５を参照して説明したようにして形成される。ただし、第２、第３群のバンプ電極５２，５４は同時に形成されるので、はんだペーストの充填及びリフローは２回でよい。このように、同一機能又は異なった機能をもった複数の半導体素子を並列的に形成することもできる。
【００２４】
図７は本発明の他の実施例の半導体装置を示す略解的平面図である。半導体装置６０は、プリント配線基板６２と、第１の半導体素子６４と、第２の半導体素子６６とからなる。プリント配線基板６２は、第１群のバンプ電極６８と、第２群のバンプ電極７０とを含む。第１群のバンプ電極６８はプリント配線基板６２の中央部に位置し、最も背が低く、且つ最も面積が小さい。第２群のバンプ電極７０は第１群のバンプ電極６８の外側でプリント配線基板６２の対角線上に位置する。第１の半導体素子６４は第１群のバンプ電極６８によってプリント配線基板６２に実装される。第２の半導体素子６６は第１の半導体素子６４に載った状態で第２群のバンプ電極７０によってプリント配線基板６２に実装される。バンプ電極６８，７０はプリント配線基板６２に図３から図５を参照して説明したようにして形成される。ただし、はんだペーストの充填及びリフローは２回でよい。このように、基板の面積、スペース、配線の状況に応じて、半導体をあらゆる角度で実装することが可能になる。この積層の実施例は一例であり、２段や３段に限定されるものではない。それ以上の多段実装が可能である。各群のバンプ電極は、２個以上のバンプ電極で構成されており、且つ複数列、ジクザク配列等、あらゆる配置が可能である。
【００２５】
【発明の効果】
以上説明したように、本発明によれば、単一の基板へ複数の特徴をもったバンプ電極を形成することにより、積層実装する半導体素子へのバンプ電極形成工程を省略することができる。また、基板上に設けた膜に開口部を設けてバンプ電極を形成することにより、バンプ電極を簡単且つ確実に形成することができる。また、バンプ電極を有する基板の簡略化も可能である。
【図面の簡単な説明】
【図１】本発明の実施例の半導体装置を示す断面図である。
【図２】図１の半導体装置を示す略解的平面図である。
【図３】本発明の実施例のはんだバンプの形成方法を示す図である。
【図４】図２のはんだバンプの形成方法の続きの工程を示す図である。
【図５】図２のはんだバンプの形成方法の続きの工程を示す図である。
【図６】本発明の他の実施例の半導体装置を示す略解的平面図である。
【図７】本発明の他の実施例の半導体装置を示す略解的平面図である。
【符号の説明】
１０…半導体装置
１２…プリント配線基板
１４…半導体素子
１６…半導体素子
１８…半導体素子
２０…バンプ電極
２０Ａ…電極パッド
２０Ｂ…開口部
２２…バンプ電極
２２Ａ…電極パッド
２２Ｂ…開口部
２４…バンプ電極
２４Ａ…電極パッド
２４Ｂ…開口部
２６…膜
２８…はんだペースト
３０…メタルマスク
３２…はんだペースト
３４…メタルマスク
３６…はんだペースト[0001]
BACKGROUND OF THE INVENTION
The present invention is related to a method of forming a bump electrode on the electrode pad provided on the substrate.
[0002]
[Prior art]
In recent years, higher density is required for electronic component mounting, but for higher density, a system LSI in which a plurality of functions are integrated has been required. In order to meet this requirement, an attempt was made to provide a single semiconductor element with a plurality of functions, but there are many problems in manufacturing and it is not practically used at present. Instead, a semiconductor device in which semiconductor elements having respective functions are three-dimensionally mounted has attracted attention. For example, two semiconductor chips are stacked, and this stacked body is mounted on a substrate. In the semiconductor device having such a three-dimensional mounting configuration, the connection between the semiconductor element and the semiconductor element and between the semiconductor element and the substrate is conventionally performed by wire bonding. If such a connection can be made with bump electrodes, higher speed and higher speed can be achieved.
[0003]
[Problems to be solved by the invention]
However, in order to obtain a semiconductor device in a three-dimensional mounting form using bump electrodes, bump electrodes are formed on individual semiconductor elements, and then two semiconductor elements are mounted using bump electrodes, and thus obtained. It is necessary to mount the laminate on a further semiconductor element or substrate using bump electrodes. Such a three-dimensional mounting form leads to an increase in the number of manufacturing steps and manufacturing cost.
[0004]
Furthermore, if the bump electrode has a large variation in height due to the narrow pitch of the bump electrode, there is a risk that the probability of occurrence of a bonding failure is high, which is not an efficient method.
Further, as a mounting problem, if the bump electrode has a single composition, there is a possibility that a short circuit occurs between the bump electrodes due to variations in the load during mounting of the semiconductor. In particular, this tendency may be observed in the case of a solder bump electrode having a eutectic composition. Furthermore, there is a problem that the semiconductor bonded by the bump electrode is peeled off because it is vulnerable to thermal stress.
[0005]
An object of the present invention is to provide a form how the solder bumps can be obtained a semiconductor device more easily and reliably three-dimensional implementation.
[0006]
[Means for Solving the Problems]
The method for forming solder bumps according to the present invention includes a step of forming a film covering a surface of a substrate having a plurality of groups of electrode pads, and a film corresponding to each electrode pad and having a size for each group of electrode pads. A step of forming different openings, a step of filling the openings with solder paste, and then reflowing to form bump electrodes fixed to the electrode pads in the openings, and a step of removing the film If, Tona is, the electrode pads of the plurality of groups includes an electrode pad of the at least first group of electrode pads and the second group, when n is a natural number, the formation of bump electrodes on the electrode pads of the first group It is carried out by filling and reflowing the n times of the solder paste, especially to be performed by filling and reflowing the different times of the solder paste and form the n times of the bump electrodes on the electrode pads of the second group It is an.
[0007]
According to this method, a plurality of groups of bump electrodes are formed on the substrate. For example, the first group of bump electrodes is for bonding a first semiconductor element, and the second group of bump electrodes is for bonding a second semiconductor element. In this way, two semiconductor elements can be easily mounted on one substrate. When the second group of bump electrodes is higher than the first group of bump electrodes, the first semiconductor element is first mounted on the substrate by the first group of bump electrodes, and then the second semiconductor element is mounted. The semiconductor device can be mounted on the substrate by the second group of bump electrodes in a state of being placed on the first semiconductor element. Further, the first group of bump electrodes and the second group of bump electrodes may have different compositions. In this way, the mounting of the first semiconductor element and the mounting of the second semiconductor element can be performed at different temperatures, and the occurrence of manufacturing defects can be suppressed and the increase in cost can be prevented. Further, each bump electrode can also have a structure having a high melting point core, which prevents a bump short circuit during mounting and relieves stress during mounting or after mounting.
[0008]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings.
FIG. 1 is a sectional view showing a semiconductor device according to an embodiment of the present invention. FIG. 2 is a schematic plan view showing the semiconductor device of FIG. The semiconductor device 10 includes a printed wiring board 12, a first semiconductor element 14, a second semiconductor element 16, and a third semiconductor element 18. The first, second, and third semiconductor elements 14, 16, and 18 have different functions.
[0009]
In FIGS. 1 and 2, the printed wiring board 12 is illustrated as the board, but the board of the present invention is not limited to the printed wiring board 12. In the present specification, the term “substrate” refers not only to a narrowly defined substrate such as a printed wiring board or a semiconductor wafer, but also to all other objects that can be formed with bump electrodes.
[0010]
The printed wiring board 12 includes a first group of bump electrodes 20, a second group of bump electrodes 22, and a third group of bump electrodes 24. The first group of bump electrodes 20 is located at the center of the printed wiring board 12 and has the shortest height and the smallest area. The second group of bump electrodes 22 is located outside the first group of bump electrodes 20 and is taller and larger in area than the first group of bump electrodes 20. The third group of bump electrodes 24 is located outside the second group of bump electrodes 22 and is taller and larger in area than the second group of bump electrodes 22.
[0011]
The first semiconductor element 14 is mounted on the printed wiring board 12 by a first group of bump electrodes 20. The second semiconductor element 16 is mounted on the printed wiring board 12 by the second group of bump electrodes 22 while being placed on the first semiconductor element 14. The second semiconductor element 18 is mounted on the printed wiring board 12 by the third group of bump electrodes 24 while being placed on the second semiconductor element 16. In this manner, the semiconductor device 10 including the three semiconductor elements 14, 16, and 18 mounted three-dimensionally can be easily and reliably manufactured. In this embodiment, bump electrodes for a plurality of semiconductor elements are collectively formed on a single substrate.
[0012]
FIG. 3 is a diagram showing a method for forming solder bumps according to an embodiment of the present invention. FIG. 4 is a diagram showing a subsequent process of the solder bump forming method of FIG. FIG. 5 is a diagram showing a subsequent process of the solder bump forming method of FIG.
In FIG. 3A, a printed wiring board 12 having a plurality of groups of electrode pads 20A, 22A, 24A is prepared. The first group of electrode pads 20A is formed at a position corresponding to the first group of bump electrodes 20 in FIG. The second group of electrode pads 22A is formed at a position corresponding to the second group of bump electrodes 22 in FIG. The third group of electrode pads 24A are formed at positions corresponding to the third group of bump electrodes 24 in FIG. The area of the third group of electrode pads 24A is larger than the area of the second group of electrode pads 22A, and the area of the second group of electrode pads 22A is larger than the area of the first group of electrode pads 20A.
[0013]
A resin film 26 is formed to cover the surface of the printed wiring board 12 so as to cover the electrode pads 20A, 22A, and 24A. The resin film 26 is preferably made of a resist. In one example, the resin film 26 is made of a dry film resist laminated on the surface of the printed wiring board 12. The resin film 26 may be a resist coated on the surface of the printed wiring board 12.
[0014]
In FIG. 3B, openings 20B, 22B, and 24B corresponding to the electrode pads 20A, 22A, and 24A and having different sizes for each group of the electrode pads 20A, 22A, and 24A are formed in the resin film. The openings 20B, 22B and 24B are formed in the resin film 26 made of resist by exposure and development. At this time, the size of the opening 22B for forming the bump electrode 22 for joining the second semiconductor element 16 mounted on the second stage is the same as that of the first semiconductor element 14 mounted on the first stage. Is formed larger than the size of the opening 20A for forming the bump electrode 20. Similarly, the size of the opening 24B for forming the bump electrode 24 for joining the third semiconductor element 18 mounted on the third stage is the second semiconductor element 16 mounted on the second stage. Is formed larger than the size of the opening 22 </ b> A for forming the bump electrode 22.
[0015]
In FIG. 3C, a solder paste 28 containing a metal serving as a bump electrode is supplied to the surface of the resin film 26, and the solder paste 28 is filled into the openings 20B, 22B, and 24B by squeezing.
In FIG. 3D, the solder paste 28 is reflowed, and the bump electrodes 20, 22, 24 are formed from the metal in the solder paste 28. The bump electrodes 20, 22, and 24 are welded to the electrode pads 20A, 22A, and 24A, respectively. Thereafter, the flux component in the solder paste 28 is washed.
[0016]
In FIG. 4A, a metal mask 30 having an opening only at a position corresponding to the opening 22B for forming the bump electrode 22 for joining the second semiconductor element 16 mounted in the second stage. The opening 22B is filled with the solder paste 32 by covering and squeezing. The melting point of the metal in the solder paste 32 is lower than the melting point of the metal in the solder paste 28 filled first. For example, the metal in the solder paste 28 filled in the first time is an alloy of Sn: Pb = 90 to 95: 10-5. The metal in the solder paste 32 filled in the second time is an alloy of Sn: Ag = 99 to 95: 1 to 5.
[0017]
In FIG. 4B, the metal mask 30 is peeled off.
In FIG. 4C, the solder paste 32 is reflowed, and the bump electrode 22 is formed again. The reflow is performed by heating at a temperature lower than the melting point of the metal in the solder paste 28 initially filled and higher than the melting point of the metal in the solder paste 32 filled this time. The metal in the solder paste 32 is melted, and the bump electrodes 20 and 24 and the bump electrode 22 portion (core) formed of the metal in the solder paste 28 formed previously are not melted. Thus, the bump electrode 22 having a high melting point core is formed. The height of the bump electrode 22 is higher than the height of the bump electrode 20. Thereafter, the flux component in the solder paste 32 is washed.
[0018]
Further, in FIG. 5A, a metal mask having an opening only at a position corresponding to the opening 24B for forming the bump electrode 24 for bonding the third semiconductor element 18 mounted in the third stage. 34, and the solder paste 36 is filled into the opening 24B by squeezing. The solder paste 36 includes a metal having a melting point lower than that of the metal in the solder paste 32 filled in the second time. For example, the metal in the solder paste 36 filled in the third time is an alloy of Sn: Pb = 60-70: 40-30.
[0019]
In FIG. 5B, the metal mask 34 is peeled off.
In FIG. 5C, the solder paste 36 is reflowed, and the bump electrode 24 is formed again. The reflow is performed by heating at a temperature lower than the melting point of the metal in the solder paste 32 filled in the second time and higher than the melting point of the metal in the solder paste 36 filled this time. The metal in the solder paste 36 melts and the cores of the bump electrodes 20 and 22 and the bump electrode 24 formed of the metal in the solder pastes 28 and 32 formed previously do not melt. Thus, the bump electrode 24 having a high melting point core is formed. The height of the bump electrode 24 is higher than the height of the bump electrodes 22 and 20. Thereafter, the flux component in the solder paste 32 is washed.
[0020]
In FIG. 5D, the resin film 26 covering the printed wiring board 12 is peeled off. As a result, the printed wiring board 12 has a plurality of bump electrodes 20, 22, and 24 having different sizes, compositions, and heights.
By flip-chip mounting the first, second and third semiconductor elements 14, 16 and 18 on the printed wiring board 12 at a temperature suitable for the composition of the bump electrodes 20, 22 and 24, FIG. 1 and FIG. The semiconductor device 10 having the three-dimensional mounting structure shown in 2 can be obtained. In this case, the first, second, and third semiconductor elements 14, 16, and 18 are mounted in stages in accordance with the melting points of the bump electrodes 20, 22, and 24. The upper semiconductor elements 16 and 18 stacked and mounted have longer sides than the lower semiconductor elements 14 and 16.
[0021]
By using the bump electrodes formed by the above method, it is possible to manufacture a stack-mounted package and a modularized semiconductor device together with a chip-on-chip package, a system-in-package, and a chip-on-chip module.
As described above, by forming bump electrodes of different sizes, compositions, and heights on a single substrate, the step of forming bump electrodes on individual semiconductor elements for bare chip mounting can be omitted. . It is also possible to simplify the substrate on which the bump electrodes are formed. Since the size of the electrode pad and bump electrode for the semiconductor element mounted on the upper stage is large, it is possible to prevent electrical contact failure due to peeling between the bump electrode and the electrode pad due to mounting stress. Further, since each bump electrode has a high melting point core, it is possible to prevent a short circuit between the bump electrodes at the time of mounting, and also to absorb the transition of the bump due to stress applied at the time of mounting and after mounting, and the effect is great.
[0022]
Further, in this embodiment, after forming openings divided into a plurality of groups in the resin film 26, the openings are filled with solder paste, and bump electrodes are formed by reflow. The filling of the solder paste into the opening of the resin film 26 is performed by squeezing the solder paste on the surface of the resin film 26 or by filling the opening with a metal mask by squeezing. is there. In this embodiment, these two squeegees are used in combination. In the bump electrode formed by the above method, all the bump electrodes other than the bump electrode formed in the last step are not protruded from the resin film.
[0023]
FIG. 6 is a schematic plan view showing a semiconductor device according to another embodiment of the present invention. The semiconductor device 40 includes a printed wiring board 42, a first semiconductor element 24, a second semiconductor element 26, and a third semiconductor element 28. The second and third semiconductor elements 26 and 18 have the same function. The printed wiring board 42 includes a first group of bump electrodes 50, a second group of bump electrodes 52, and a third group of bump electrodes 54. The first group of bump electrodes 50 is located in the central portion of the printed wiring board 42 and has the shortest height and the smallest area. The second and third groups of bump electrodes 52 and 54 are symmetrically positioned on the outside of the first group of bump electrodes 50, are taller and have a larger area than the first group of bump electrodes 50. The first semiconductor element 44 is mounted on the printed wiring board 42 by the first group of bump electrodes 50. The second and third semiconductor elements 46 and 48 are mounted on the printed wiring board 42 by the second and third groups of bump electrodes 52 and 54 while being placed on the first semiconductor element 44. The bump electrodes 50, 52 and 54 are formed on the printed wiring board 42 as described with reference to FIGS. However, since the second and third groups of bump electrodes 52 and 54 are formed at the same time, the solder paste filling and reflow may be performed twice. Thus, a plurality of semiconductor elements having the same function or different functions can be formed in parallel.
[0024]
FIG. 7 is a schematic plan view showing a semiconductor device according to another embodiment of the present invention. The semiconductor device 60 includes a printed wiring board 62, a first semiconductor element 64, and a second semiconductor element 66. The printed wiring board 62 includes a first group of bump electrodes 68 and a second group of bump electrodes 70. The first group of bump electrodes 68 is located at the center of the printed wiring board 62 and has the shortest height and the smallest area. The second group of bump electrodes 70 is located on the diagonal line of the printed wiring board 62 outside the first group of bump electrodes 68. The first semiconductor element 64 is mounted on the printed wiring board 62 by a first group of bump electrodes 68. The second semiconductor element 66 is mounted on the printed wiring board 62 by the second group of bump electrodes 70 in a state of being placed on the first semiconductor element 64. The bump electrodes 68 and 70 are formed on the printed wiring board 62 as described with reference to FIGS. However, the solder paste filling and reflow may be performed twice. As described above, the semiconductor can be mounted at any angle according to the area of the substrate, the space, and the wiring situation. This embodiment of the lamination is an example, and is not limited to two or three stages. More multi-stage mounting is possible. Each group of bump electrodes is composed of two or more bump electrodes, and can be arranged in various ways such as a plurality of rows and a zigzag arrangement.
[0025]
【The invention's effect】
As described above, according to the present invention, by forming bump electrodes having a plurality of features on a single substrate, it is possible to omit a bump electrode forming step on a semiconductor element to be stacked and mounted. Further, the bump electrode can be easily and reliably formed by providing the opening in the film provided on the substrate to form the bump electrode. In addition, the substrate having the bump electrodes can be simplified.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view showing a semiconductor device according to an embodiment of the present invention.
2 is a schematic plan view showing the semiconductor device of FIG. 1; FIG.
FIG. 3 is a diagram showing a solder bump forming method according to an embodiment of the present invention.
FIG. 4 is a diagram illustrating a subsequent process of the method for forming solder bumps of FIG. 2;
FIG. 5 is a diagram showing a subsequent process of the method for forming solder bumps of FIG. 2;
FIG. 6 is a schematic plan view showing a semiconductor device according to another embodiment of the present invention.
FIG. 7 is a schematic plan view showing a semiconductor device according to another embodiment of the present invention.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 10 ... Semiconductor device 12 ... Printed wiring board 14 ... Semiconductor element 16 ... Semiconductor element 18 ... Semiconductor element 20 ... Bump electrode 20A ... Electrode pad 20B ... Opening part 22 ... Bump electrode 22A ... Electrode pad 22B ... Opening part 24 ... Bump electrode 24A ... Electrode pad 24B ... Opening 26 ... Film 28 ... Solder paste 30 ... Metal mask 32 ... Solder paste 34 ... Metal mask 36 ... Solder paste

Claims (1)

複数の群の電極パッドを有する基板の表面を覆う膜を形成する工程と、
該膜に各電極パッドに対応し且つ該電極パッドの群毎に大きさの異なる開口部を形成する工程と、
該開口部内にはんだペーストを充填し、それからリフローを行うことにより、該開口部内で電極パッドに固定されたバンプ電極を形成する工程と、
該膜を除去する工程と、からなり、
複数の群の電極パッドは少なくとも第１群の電極パッド及び第２群の電極パッドを含み、ｎを自然数とするとき、第１群の電極パッド上のバンプ電極の形成はｎ回のはんだペーストの充填及びリフローにより実施され、第２群の電極パッド上のバンプ電極の形成はｎ回とは異なる回数のはんだペーストの充填及びリフローにより実施されることを特徴とするはんだバンプの形成方法。Forming a film covering the surface of the substrate having a plurality of groups of electrode pads;
Forming an opening corresponding to each electrode pad in the film and having a different size for each group of the electrode pads;
Forming a bump electrode fixed to the electrode pad in the opening by filling the opening with a solder paste and then performing reflow;
And removing the film,
The plurality of groups of electrode pads include at least a first group of electrode pads and a second group of electrode pads. When n is a natural number, formation of bump electrodes on the first group of electrode pads is performed by n times of solder paste. A method for forming solder bumps, wherein the bump electrodes are formed by filling and reflowing, and the formation of bump electrodes on the second group of electrode pads is performed by filling and reflowing the solder paste differently from n times.
JP2001157076A 2001-05-25 2001-05-25 Method of forming solder bump Expired - Fee Related JP4629912B2 (en)

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JP4110992B2 (en) 2003-02-07 2008-07-02 セイコーエプソン株式会社 Semiconductor device, electronic device, electronic apparatus, semiconductor device manufacturing method, and electronic device manufacturing method
JP4096774B2 (en) 2003-03-24 2008-06-04 セイコーエプソン株式会社 SEMICONDUCTOR DEVICE, ELECTRONIC DEVICE, ELECTRONIC DEVICE, SEMICONDUCTOR DEVICE MANUFACTURING METHOD, AND ELECTRONIC DEVICE MANUFACTURING METHOD
JP2004349495A (en) 2003-03-25 2004-12-09 Seiko Epson Corp Semiconductor device and its manufacturing method, and electronic device and electronic equipment
JP4094982B2 (en) 2003-04-15 2008-06-04 ハリマ化成株式会社 Solder deposition method and solder bump formation method
WO2005081064A1 (en) * 2004-02-20 2005-09-01 Jsr Corporation Bilayer laminated film for bump formation and method of bump formation
JP4906563B2 (en) * 2007-04-04 2012-03-28 新光電気工業株式会社 Semiconductor device, wiring board, and manufacturing method thereof
JP5338572B2 (en) * 2009-08-31 2013-11-13 凸版印刷株式会社 Manufacturing method of semiconductor device
JP5781825B2 (en) * 2011-04-27 2015-09-24 日本特殊陶業株式会社 Wiring board manufacturing method

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