JPH0644175U - Electronic component mounting structure - Google Patents
Electronic component mounting structureInfo
- Publication number
- JPH0644175U JPH0644175U JP8000892U JP8000892U JPH0644175U JP H0644175 U JPH0644175 U JP H0644175U JP 8000892 U JP8000892 U JP 8000892U JP 8000892 U JP8000892 U JP 8000892U JP H0644175 U JPH0644175 U JP H0644175U
- Authority
- JP
- Japan
- Prior art keywords
- component
- pad
- substrate
- mounting structure
- components
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
Abstract
(57)【要約】
【目的】電子部品の実装構造に係り、特に基板上にＴＡ
Ｂ実装される電子部品の実装構造に関し、実装領域が限
られている基板上に有効に部品を実装させることを目的
とする。
【構成】第１のパッド２が表面に形成された基板１と、
該第１のパッド２と電気的に接合されて、該基板１上に
実装される第１の部品３と、該第１のパッド２が形成さ
れた面で、且つ当該第１のパッド２の周囲に形成された
第２のパッド５と、該第２のパッド５と電気的に接合さ
れ、且つ前記第１の部品３に重ね合わされて実装される
第２の部品７と、該第１の部品３と該第２の部品７との
接触面に介在される絶縁シート４とを有するよう構成す
る。
(57) [Abstract] [Purpose] Related to the mounting structure of electronic parts, especially TA on the board.
Regarding a mounting structure of an electronic component to be mounted B, an object thereof is to effectively mount the component on a substrate having a limited mounting area. [Structure] A substrate 1 having a first pad 2 formed on its surface,
A first component 3 that is electrically bonded to the first pad 2 and is mounted on the substrate 1, and a surface on which the first pad 2 is formed, and A second pad 5 formed on the periphery, a second component 7 electrically joined to the second pad 5 and mounted on the first component 3 by being superposed on the first component 3, and the first component 7. It is configured to have the insulating sheet 4 interposed on the contact surface between the component 3 and the second component 7.
Description
【０００１】[0001]
本考案は、電子部品の実装構造に係り、特に基板上にＴＡＢ実装される電子部 品の実装構造に関するものである。 The present invention relates to a mounting structure for electronic components, and more particularly to a mounting structure for electronic components that are TAB mounted on a substrate.
【０００２】 近年、例えば、プリント回路基板上その部品実装は高密度化が要求されており 、同時に各部品も小型化，高集積化となってきた。 このため、高集積回路であるＴＡＢが製品化されているが、部品面積が比較的 大きいため、高密度化するには実装形式を工夫する必要がある。In recent years, for example, the mounting of components on a printed circuit board has been required to have a high density, and at the same time, each component has become smaller and highly integrated. For this reason, TAB, which is a highly integrated circuit, has been commercialized, but since the component area is relatively large, it is necessary to devise a mounting format to achieve high density.
【０００３】[0003]
従来は、図２に示すように，基板３０上に部品２２，２４を実装するには、そ の部品２２，２４対応にパッド２１，２３を形成しておき、そのパッド２１，２ ３に部品２２，２４を電気的に接合するようにしていた Conventionally, as shown in FIG. 2, in order to mount the components 22 and 24 on the substrate 30, pads 21 and 23 are formed corresponding to the components 22 and 24, and the components are attached to the pads 21 and 23. 22 and 24 were electrically connected
【０００４】[0004]
しかしながら、従来では基板上に実装する部品は必ず二次元的に実装されるも のであるため、部品の実装数が多くなればその部品実装領域が二次元的に増加す るため、実装領域が限られている基板には制約を受けてしまうものであった。 However, conventionally, the components mounted on the board are always mounted two-dimensionally. Therefore, if the number of mounted components increases, the component mounting area increases two-dimensionally. The substrates used are limited.
【０００５】 従って、本考案では、実装領域が限られている基板上に有効に部品を実装させ ることを目的とするものである。Therefore, the object of the present invention is to effectively mount components on a substrate having a limited mounting area.
【０００６】[0006]
上記目的は、第１のパッド２が表面に形成された基板１と、 該第１のパッド２と電気的に接合されて、該基板１上に実装される第１の部品 ３と、 該第１のパッド２が形成された面で、且つ当該第１のパッド２の周囲に形成さ れた第２のパッド５と、 該第２のパッド５と電気的に接合され、且つ前記第１の部品３に重ね合わされ て実装される第２の部品７と、 該第１の部品３と該第２の部品７との接触面に介在される絶縁シート４と、 からなることを特徴とする電子部品の実装構造、によって達成することができ る。 The object is to provide a substrate 1 having a first pad 2 formed on the surface thereof, a first component 3 electrically connected to the first pad 2 and mounted on the substrate 1, A second pad 5 formed on the surface on which the first pad 2 is formed and around the first pad 2, the second pad 5 and the second pad 5 are electrically joined, and An electronic device comprising: a second component 7 mounted on the component 3 in a superposed manner; and an insulating sheet 4 interposed on a contact surface between the first component 3 and the second component 7. It can be achieved by the mounting structure of parts.
【０００７】[0007]
即ち、本考案によれば、第１の部品および第２の部品の三次元的に実装してい るため、限られた実装領域を有効に使用することができ、またそれら部品間に絶 縁シートを介在していることにより、部品間接触によるショート等が発生しない 。 That is, according to the present invention, since the first component and the second component are three-dimensionally mounted, a limited mounting area can be effectively used, and an insulating sheet is provided between these components. With the interposition of, the short circuit due to contact between parts does not occur.
【０００８】[0008]
以下、本考案の実施例について図面を用いて詳細に説明する。 図１に示すように、基板１の実装面には、第１のパッド２が枠状に規則正しく 形成されており、その第１のパッド２には、第１のパッドと対応する位置に端子 を有する第１の部品３が接合される。 Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. As shown in FIG. 1, the first pad 2 is regularly formed in a frame shape on the mounting surface of the substrate 1, and the first pad 2 has terminals at positions corresponding to the first pad. The first component 3 it has is joined.
【０００９】 そして、第１のパッド２の外側周囲には同じく枠状に第２のパッド５が規則正 しく形成されており、その第２のパッド５には、第２のパッド５と対応する位置 に端子を有する第２の部品７がバンプ６を介して接合される。The second pad 5 is also regularly formed in a frame shape around the outer periphery of the first pad 2, and the second pad 5 corresponds to the second pad 5. The second component 7 having the terminal at the position is joined via the bump 6.
【００１０】 即ち、本実施例では、第１の部品３の上に重ね合うように第２の部品７が実装 されることで、複数の部品が三次元的に実装されることとなる。よって、限られ た実装領域を有効に利用することができる。That is, in the present embodiment, the second component 7 is mounted on the first component 3 so as to be superposed on the first component 3, so that a plurality of components are three-dimensionally mounted. Therefore, it is possible to effectively use the limited mounting area.
【００１１】 重ね合わされる第１の部品３と第２の部品７との間にはその面が均一な絶縁シ ート４を介在させることで、各部品が接触することによるショート等を防止する ことが可能となると共に、第２の部品７の高さ出しを行っている。An insulating sheet 4 having a uniform surface is interposed between the first component 3 and the second component 7 which are overlapped with each other to prevent a short circuit or the like due to the contact of each component. This makes it possible to raise the height of the second component 7.
【００１２】 尚、本実施例においては、２つの部品を重ね合わせて実装する例について説明 したが、これ以上、即ち３つ，４つ，の部品を重畳させて更に三次元的に実装す ることも可能である。In the present embodiment, an example in which two parts are mounted in an overlapping manner has been described, but more than three parts, that is, three or four parts are superimposed and mounted in a three-dimensional manner. It is also possible.
【００１３】[0013]
以上述べた様に本考案によれば、基板に実装される部品の実装密度をアップす ることができ、高密度実装に寄与することろが大きい。 As described above, according to the present invention, it is possible to increase the mounting density of the components mounted on the board, which greatly contributes to high-density mounting.
【図１】本考案の実施例を示す図である。FIG. 1 is a diagram showing an embodiment of the present invention.
【図２】従来例を示す図である。FIG. 2 is a diagram showing a conventional example.
１ 基板， ２ 第１のパッド， ３ 第１の部品， ４ 絶縁シート， ５ 第２のパッド， ７ 第２の部品， 1 board, 2 1st pad, 3 1st part, 4 insulating sheet, 5 2nd pad, 7 2nd part,
Claims (1)
基板（１）と、 該第１のパッド（２）と電気的に接合されて、該基板
（１）上に実装される第１の部品（３）と、 該第１のパッド（２）が形成された面で、且つ当該第１
のパッド（２）の周囲に形成された第２のパッド（５）
と、 該第２のパッド（５）と電気的に接合され、且つ前記第
１の部品（３）に重ね合わされて実装される第２の部品
（７）と、 該第１の部品（３）と該第２の部品（７）との接触面に
介在される絶縁シート（４）と、 からなることを特徴とする電子部品の実装構造。1. A substrate (1) having a first pad (2) formed on the surface thereof, and being electrically bonded to the first pad (2) and mounted on the substrate (1). A surface on which the first component (3) and the first pad (2) are formed, and
Second pad (5) formed around the pad (2) of the
A second component (7) electrically bonded to the second pad (5) and mounted on the first component (3) by being superposed on the first component (3); and the first component (3). And an insulating sheet (4) interposed on the contact surface between the second component (7) and the second component (7).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8000892U JPH0644175U (en) | 1992-11-19 | 1992-11-19 | Electronic component mounting structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8000892U JPH0644175U (en) | 1992-11-19 | 1992-11-19 | Electronic component mounting structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0644175U true JPH0644175U (en) | 1994-06-10 |
Family
ID=13706306
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8000892U Withdrawn JPH0644175U (en) | 1992-11-19 | 1992-11-19 | Electronic component mounting structure |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0644175U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002353272A (en) * | 2001-05-25 | 2002-12-06 | Fujitsu Ltd | Solder bump forming method and semiconductor device |
-
1992
- 1992-11-19 JP JP8000892U patent/JPH0644175U/en not_active Withdrawn
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002353272A (en) * | 2001-05-25 | 2002-12-06 | Fujitsu Ltd | Solder bump forming method and semiconductor device |
| JP4629912B2 (en) * | 2001-05-25 | 2011-02-09 | 富士通セミコンダクター株式会社 | Method of forming solder bump |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A300 | Withdrawal of application because of no request for examination |
Free format text: JAPANESE INTERMEDIATE CODE: A300 Effective date: 19970306 |