JP2002353272A - Solder bump forming method and semiconductor device - Google Patents

Solder bump forming method and semiconductor device

Info

Publication number
JP2002353272A
JP2002353272A JP2001157076A JP2001157076A JP2002353272A JP 2002353272 A JP2002353272 A JP 2002353272A JP 2001157076 A JP2001157076 A JP 2001157076A JP 2001157076 A JP2001157076 A JP 2001157076A JP 2002353272 A JP2002353272 A JP 2002353272A
Authority
JP
Japan
Prior art keywords
bump
electrode
group
bump electrodes
forming
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2001157076A
Other languages
Japanese (ja)
Other versions
JP4629912B2 (en
Inventor
Kuniji Fujimori
城次 藤森
Ichiro Yamaguchi
一郎 山口
Masahiro Yoshikawa
政廣 吉川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP2001157076A priority Critical patent/JP4629912B2/en
Publication of JP2002353272A publication Critical patent/JP2002353272A/en
Application granted granted Critical
Publication of JP4629912B2 publication Critical patent/JP4629912B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/11Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32135Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73253Bump and layer connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01005Boron [B]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01006Carbon [C]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01033Arsenic [As]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01047Silver [Ag]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01082Lead [Pb]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013Alloys
    • H01L2924/0132Binary Alloys
    • H01L2924/01322Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013Alloys
    • H01L2924/014Solder alloys

Abstract

PROBLEM TO BE SOLVED: To provide a solder bump forming method by which a semiconductor device having a three-dimensional mounting configuration can be easily and surely obtained with regard to the solder bump forming method and the semiconductor device. SOLUTION: The solder bump forming method comprises a process for forming a film 26 covering a surface of a substrate 12 having a plurality of groups of electrode pads 20A, 22A and 24A, a process for forming openings 20B, 22B and 24B corresponding to each electrode pad and having different sizes in each corresponding electrode pad group in the film 26, a process of forming bump electrodes 20, 22 and 24 which are fixed in the electrode pads within the openings, and a process of removing the film.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は基板上に設けられた
電極パッド上にバンプ電極を形成する方法に関する。ま
た、本発明はバンプ電極を有する基板と、電極パッドを
有する電気素子とをバンプ電極によって接合してなる半
導体装置に関する。
The present invention relates to a method for forming a bump electrode on an electrode pad provided on a substrate. Further, the present invention relates to a semiconductor device in which a substrate having bump electrodes and an electric element having electrode pads are joined by bump electrodes.

【0002】[0002]

【従来の技術】近年、電子部品実装には、高密度化が要
求されているが、さらなる高密度化として、複数の機能
を一体化させたシステムLSIが要求されてきた。この
要求に答えるべく、単一の半導体素子に複数の機能をも
たせようとしたが、製造上の問題点が多く現在実用され
ていない。これに代わり、それぞれの機能を有する半導
体素子を3次元的に実装した半導体装置が注目されてい
る。例えば2つの半導体チップを積層し、この積層体を
基板に実装する。このような3次元的な実装形態の半導
体装置では、半導体素子と半導体素子との間及び半導体
素子と基板との間の接続は従来はほとんどワイヤボンデ
ィングによって行われている。このような接続をバンプ
電極によって行うことができれば、より高密度で高速化
が可能になる。
2. Description of the Related Art In recent years, higher density has been required for mounting electronic components. For higher density, a system LSI integrating a plurality of functions has been required. In order to respond to this demand, a single semiconductor device has been tried to have a plurality of functions, but there are many manufacturing problems and it is not practically used at present. Instead, a semiconductor device in which semiconductor elements having respective functions are three-dimensionally mounted has attracted attention. For example, two semiconductor chips are stacked, and the stacked body is mounted on a substrate. In such a three-dimensionally mounted semiconductor device, connection between a semiconductor element and a semiconductor element and between a semiconductor element and a substrate are conventionally mostly performed by wire bonding. If such a connection can be made by using bump electrodes, higher density and higher speed can be achieved.

【0003】[0003]

【発明が解決しようとする課題】しかしながら、バンプ
電極を用いて3次元的な実装形態の半導体装置を得るに
は、個々の半導体素子にバンプ電極を形成し、それから
2つの半導体素子をバンプ電極を用いて実装し、こうし
て得られた積層体をさらなる半導体素子又は基板にバン
プ電極を用いて実装することが必要となる。このような
3次元的な実装形態は、製造工程数や製造コストのアッ
プにつながってしまう。
However, in order to obtain a three-dimensionally mounted semiconductor device using bump electrodes, bump electrodes are formed on individual semiconductor elements, and then two semiconductor elements are connected to the bump electrodes. It is necessary to mount the obtained laminate on a further semiconductor element or substrate using bump electrodes. Such a three-dimensional mounting mode leads to an increase in the number of manufacturing steps and manufacturing costs.

【0004】さらに、バンプ電極の狭ピッチ化に伴い、
バンプ電極の高さのバラツキが大きいと、接合不良が発
生する確率が高くなる危険性もあり、効率的な方法では
ないと思われる。また、実装上の問題点としては、単一
組成のバンプ電極であると、半導体の実装時における荷
重のバラツキ等によりバンプ電極同志でショートが発生
する可能性がある。特に、この傾向は、共晶組成のはん
だバンプ電極の場合に見られることがある。さらに、熱
ストレスに脆く、バンプ電極により接合された半導体が
剥がれてしまうという問題も抱えている。
Further, as the pitch of the bump electrodes becomes narrower,
If there is a large variation in the height of the bump electrodes, there is a risk that the probability of occurrence of a bonding failure will increase, and this is not considered to be an efficient method. Also, as a problem in mounting, if the bump electrodes have a single composition, there is a possibility that short-circuits may occur between the bump electrodes due to a variation in load at the time of mounting the semiconductor. In particular, this tendency may be observed in the case of a eutectic solder bump electrode. Furthermore, there is also a problem that the semiconductor bonded by the bump electrode is fragile due to thermal stress and peels off.

【0005】本発明の目的は、より簡単に且つ確実に3
次元的な実装形態の半導体装置を得ることのできるはん
だバンプの形成方法およびそのようなはんだバンプの形
成方法で製造された半導体装置を提供することである。
It is an object of the present invention to make it easier and more reliable
An object of the present invention is to provide a solder bump forming method capable of obtaining a semiconductor device having a three-dimensional mounting form, and a semiconductor device manufactured by such a solder bump forming method.

【0006】[0006]

【課題を解決するための手段】本発明によるはんだバン
プの形成方法は、複数の群の電極パッドを有する基板の
表面を覆う膜を形成する工程と、該膜に各電極パッドに
対応し且つ該電極パッドの群毎に大きさの異なる開口部
を形成する工程と、該開口部内で電極パッドに固定され
たバンプ電極を形成する工程と、該膜を除去する工程と
からなることを特徴とするものである。
According to the present invention, there is provided a method of forming a solder bump, comprising the steps of: forming a film covering a surface of a substrate having a plurality of groups of electrode pads; Forming an opening having a different size for each group of electrode pads, forming a bump electrode fixed to the electrode pad in the opening, and removing the film. Things.

【0007】この方法によれば、基板上に複数の群のバ
ンプ電極が形成される。例えば、第1の群のバンプ電極
は第1の半導体素子を接合するためのものであり、第2
の群のバンプ電極は第2の半導体素子を接合するための
ものである。このようにして、1つの基板に2つの半導
体素子を容易に実装することができる。そして、第2の
群のバンプ電極が第1の群のバンプ電極よりも高いと、
最初に第1の半導体素子を第1の群のバンプ電極によっ
て基板に実装し、それから第2の半導体素子を第1の半
導体素子の上に載せた状態で第2の群のバンプ電極によ
って基板に実装することができる。さらに、第1の群の
バンプ電極と第2の群のバンプ電極とは組成が異なるよ
うにすることもできる。こうすれば、第1の半導体素子
の実装と、第2の半導体素子の実装とを温度を変えて行
うことができ、製造不良の発生を抑え、コストアップを
防止することができる。さらに、各バンプ電極は高融点
コアを有する構造とすることもでき、実装時のバンプシ
ョートを防止するとともに、実装時もしくは実装後のス
トレスを緩和する。
According to this method, a plurality of groups of bump electrodes are formed on a substrate. For example, the first group of bump electrodes is for joining the first semiconductor element, and the second group of bump electrodes is for the second group.
The group of bump electrodes is for bonding the second semiconductor element. In this manner, two semiconductor elements can be easily mounted on one substrate. And if the second group of bump electrodes is higher than the first group of bump electrodes,
First, the first semiconductor element is mounted on the substrate by the first group of bump electrodes, and then the second semiconductor element is mounted on the substrate by the second group of bump electrodes while mounted on the first semiconductor element. Can be implemented. Further, the composition of the first group of bump electrodes and the composition of the second group of bump electrodes may be different. In this case, the mounting of the first semiconductor element and the mounting of the second semiconductor element can be performed while changing the temperature, so that the occurrence of manufacturing defects can be suppressed, and the cost can be prevented. Further, each bump electrode may have a structure having a high melting point core, thereby preventing a short circuit of the bump at the time of mounting and reducing a stress at the time of mounting or after mounting.

【0008】[0008]

【発明の実施の形態】以下本発明の実施例について図面
を参照して説明する。図1は本発明の実施例の半導体装
置を示す断面図である。図2は図1の半導体装置を示す
略解的平面図である。半導体装置10は、プリント配線
基板12と、第1の半導体素子14と、第2の半導体素
子16と、第3の半導体素子18とからなる。第1、第
2、第3の半導体素子14,16,18はそれぞれに異
なった機能を有する。
Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a sectional view showing a semiconductor device according to an embodiment of the present invention. FIG. 2 is a schematic plan view showing the semiconductor device of FIG. The semiconductor device 10 includes a printed wiring board 12, a first semiconductor element 14, a second semiconductor element 16, and a third semiconductor element 18. The first, second, and third semiconductor elements 14, 16, and 18 have different functions.

【0009】図1及び図2においては、基板としてプリ
ント配線基板12が例示されているが、本発明の基板は
プリント配線基板12に限定されるものではない。本明
細書で単に基板というときは、プリント配線基板や半導
体ウエハなどの狭義の基板ばかりでなく、バンプ電極の
形成対象となりうるその他の全てのものを指すものであ
る。
1 and 2, a printed wiring board 12 is illustrated as a substrate, but the substrate of the present invention is not limited to the printed wiring board 12. In this specification, the term “substrate” means not only a substrate in a narrow sense, such as a printed wiring board or a semiconductor wafer, but also all other objects that can be formed with bump electrodes.

【0010】プリント配線基板12は、第1群のバンプ
電極20と、第2群のバンプ電極22と、第3群のバン
プ電極24とを含む。第1群のバンプ電極20はプリン
ト配線基板12の中央部に位置し、最も背が低く、且つ
最も面積が小さい。第2群のバンプ電極22は第1群の
バンプ電極20の外側に位置し、第1群のバンプ電極2
0よりも背が高く、且つ面積が大きい。第3群のバンプ
電極24は第2群のバンプ電極22の外側に位置し、第
2群のバンプ電極22よりも背が高く、且つ面積が大き
い。
The printed wiring board 12 includes a first group of bump electrodes 20, a second group of bump electrodes 22, and a third group of bump electrodes 24. The first group of bump electrodes 20 is located at the center of the printed wiring board 12 and is the shortest and has the smallest area. The second group of bump electrodes 22 is located outside the first group of bump electrodes 20, and the first group of bump electrodes 2
Taller than 0 and large in area. The third group of bump electrodes 24 is located outside the second group of bump electrodes 22 and is taller and larger in area than the second group of bump electrodes 22.

【0011】第1の半導体素子14は第1群のバンプ電
極20によってプリント配線基板12に実装される。第
2の半導体素子16は第1の半導体素子14に載った状
態で第2群のバンプ電極22によってプリント配線基板
12に実装される。第2の半導体素子18は第2の半導
体素子16に載った状態で第3群のバンプ電極24によ
ってプリント配線基板12に実装される。このようにし
て、3次元的に実装された3つの半導体素子14,1
6,18からなる半導体装置10を簡単に且つ確実に製
造することができる。本実施例では、複数の半導体素子
用のバンプ電極が単一基板へ一括して形成されている。
The first semiconductor element 14 is mounted on the printed wiring board 12 by the first group of bump electrodes 20. The second semiconductor element 16 is mounted on the printed wiring board 12 by the second group of bump electrodes 22 while being placed on the first semiconductor element 14. The second semiconductor element 18 is mounted on the printed wiring board 12 by the third group of bump electrodes 24 while being placed on the second semiconductor element 16. In this manner, the three semiconductor elements 14, 1 mounted three-dimensionally.
The semiconductor device 10 including the semiconductor devices 6 and 18 can be easily and reliably manufactured. In this embodiment, a plurality of bump electrodes for semiconductor elements are collectively formed on a single substrate.

【0012】図3は本発明の実施例のはんだバンプの形
成方法を示す図である。図4は図3のはんだバンプの形
成方法の続きの工程を示す図である。図5は図3のはん
だバンプの形成方法の続きの工程を示す図である。図3
(A)において、複数の群の電極パッド20A,22
A,24Aを有するプリント配線基板12を準備する。
第1群の電極パッド20Aは図1の第1群のバンプ電極
20に対応する位置に形成されている。第2群の電極パ
ッド22Aは図1の第2群のバンプ電極22に対応する
位置に形成されている。第3群の電極パッド24Aは図
1の第3群のバンプ電極24に対応する位置に形成され
ている。第3群の電極パッド24Aの面積は第2群の電
極パッド22Aの面積よりも大きく、第2群の電極パッ
ド22Aの面積は第1群の電極パッド20Aの面積より
も大きい。
FIG. 3 is a diagram showing a method of forming a solder bump according to an embodiment of the present invention. FIG. 4 is a view showing a subsequent step of the method for forming the solder bumps of FIG. FIG. 5 is a view showing a subsequent step of the method for forming the solder bumps of FIG. FIG.
In (A), a plurality of groups of electrode pads 20A, 22
A, a printed wiring board 12 having 24A is prepared.
The first group of electrode pads 20A is formed at a position corresponding to the first group of bump electrodes 20 in FIG. The second group of electrode pads 22A is formed at a position corresponding to the second group of bump electrodes 22 in FIG. The third group of electrode pads 24A is formed at a position corresponding to the third group of bump electrodes 24 in FIG. The area of the third group of electrode pads 24A is larger than the area of the second group of electrode pads 22A, and the area of the second group of electrode pads 22A is larger than the area of the first group of electrode pads 20A.

【0013】樹脂の膜26が電極パッド20A,22
A,24Aを覆うようにプリント配線基板12の表面を
覆って形成される。樹脂の膜26は好ましくはレジスト
からなる。一例においては、樹脂の膜26はプリント配
線基板12の表面にラミネートされたドライフィルムレ
ジストからなる。また、樹脂の膜26はプリント配線基
板12の表面に塗布されたレジストでもよい。
The resin film 26 is formed on the electrode pads 20A and 22A.
A and 24A are formed so as to cover the surface of the printed wiring board 12. The resin film 26 is preferably made of a resist. In one example, the resin film 26 is made of a dry film resist laminated on the surface of the printed wiring board 12. The resin film 26 may be a resist applied to the surface of the printed wiring board 12.

【0014】図3(B)において、樹脂の膜26に各電
極パッド20A,22A,24Aに対応し且つ該電極パ
ッド20A,22A,24A群毎に大きさの異なる開口
部20B,22B,24Bを形成する。開口部20B,
22B,24Bは、レジストからなる樹脂の膜26に、
露光及び現像により形成される。このとき、2段目に実
装される第2の半導体素子16を接合するためのバンプ
電極22を形成するための開口部22Bの大きさは、1
段目に実装される第1の半導体素子14を接合するため
バンプ電極20を形成するための開口部20Aの大きさ
よりも大きく形成しておく。同様に、3段目に実装され
る第3の半導体素子18を接合するためのバンプ電極2
4を形成するための開口部24Bの大きさは、2段目に
実装される第2の半導体素子16を接合するためバンプ
電極22を形成するための開口部22Aの大きさよりも
大きく形成しておく。
In FIG. 3B, openings 20B, 22B, 24B corresponding to the respective electrode pads 20A, 22A, 24A and having different sizes for each group of the electrode pads 20A, 22A, 24A are formed in the resin film 26. Form. Opening 20B,
22B and 24B are formed on a resin film 26 made of a resist.
It is formed by exposure and development. At this time, the size of the opening 22B for forming the bump electrode 22 for joining the second semiconductor element 16 mounted on the second stage is 1
An opening 20A for forming the bump electrode 20 for bonding the first semiconductor element 14 to be mounted on the step is formed larger than the size of the opening 20A. Similarly, the bump electrode 2 for bonding the third semiconductor element 18 mounted on the third stage
The size of the opening 24B for forming the second semiconductor element 16 is larger than the size of the opening 22A for forming the bump electrode 22 for bonding the second semiconductor element 16 mounted on the second stage. deep.

【0015】図3(C)において、樹脂の膜26の表面
にバンプ電極となる金属を含むはんだペースト28を供
給し、スキージングによりはんだペースト28を開口部
20B,22B,24Bに充填する。図3(D)におい
て、はんだペースト28をリフローし、はんだペースト
28中の金属によりバンプ電極20,22,24を形成
する。バンプ電極20,22,24は電極パッド20
A,22A,24Aにそれぞれ溶着される。その後、は
んだペースト28中のフラックス成分は洗浄される。
In FIG. 3C, a solder paste 28 containing a metal to be a bump electrode is supplied to the surface of the resin film 26, and the openings 20B, 22B and 24B are filled with the solder paste 28 by squeezing. In FIG. 3D, the solder paste 28 is reflowed, and the bump electrodes 20, 22, and 24 are formed using the metal in the solder paste 28. The bump electrodes 20, 22, and 24 are electrode pads 20.
A, 22A and 24A, respectively. Thereafter, the flux components in the solder paste 28 are washed.

【0016】図4(A)において、2段目に実装される
第2の半導体素子16を接合するためのバンプ電極22
を形成するための開口部22Bに相当する位置にのみ開
口部を有するメタルマスク30を被せ、スキージングに
より開口部22Bにはんだペースト32を充填する。こ
のはんだペースト32中の金属の融点は、最初に充填さ
れたはんだペースト28中の金属の融点より低い。例え
ば、1回目に充填されたはんだペースト28中の金属
は、Sn:Pb=90〜95:10〜5の合金である。
2回目に充填されたはんだペースト32中の金属は、S
n:Ag=99〜95:1〜5の合金である。
In FIG. 4A, a bump electrode 22 for joining the second semiconductor element 16 mounted on the second stage is formed.
Is covered with a metal mask 30 having an opening only at a position corresponding to the opening 22B for forming a hole, and the opening 22B is filled with a solder paste 32 by squeezing. The melting point of the metal in the solder paste 32 is lower than the melting point of the metal in the solder paste 28 initially filled. For example, the metal in the solder paste 28 filled for the first time is an alloy of Sn: Pb = 90-95: 10-5.
The metal in the solder paste 32 filled for the second time is S
n: An alloy of Ag = 99-95: 1-5.

【0017】図4(B)において、メタルマスク30を
剥がす。図4(C)において、はんだペースト32をリ
フローし、バンプ電極22を再形成する。リフローは、
最初に充填されたはんだペースト28中の金属の融点よ
り低く、今回充填されたはんだペースト32中の金属の
融点よりも高い温度で加熱することにより実施される。
はんだペースト32中の金属が溶融し、前に形成したは
んだペースト28中の金属で形成されたバンプ電極2
0,24及びバンプ電極22の部分(コア)は溶融しな
い。こうして、高融点のコアを有するバンプ電極22を
形成する。バンプ電極22の高さはバンプ電極20の高
さよりも高くなる。その後、はんだペースト32中のフ
ラックス成分は洗浄される。
In FIG. 4B, the metal mask 30 is peeled off. In FIG. 4C, the solder paste 32 is reflowed, and the bump electrodes 22 are formed again. Reflow is
Heating is performed by heating at a temperature lower than the melting point of the metal in the solder paste 28 filled first and higher than the melting point of the metal in the solder paste 32 filled this time.
The metal in the solder paste 32 is melted, and the bump electrode 2 formed of the metal in the solder paste 28 previously formed is formed.
The portions (cores) 0, 24 and the bump electrodes 22 do not melt. Thus, a bump electrode 22 having a high melting point core is formed. The height of the bump electrode 22 is higher than the height of the bump electrode 20. Thereafter, the flux component in the solder paste 32 is washed.

【0018】さらに、図5(A)において、3段目に実
装される第3の半導体素子18を接合するためのバンプ
電極24を形成するための開口部24Bに相当する位置
にのみ開口部を有するメタルマスク34を被せ、スキー
ジングにより開口部24Bにはんだペースト36を充填
する。このはんだペースト36は、2回目に充填された
はんだペースト32中の金属の融点より低い融点を有す
る金属を含む。例えば、3回目に充填されたはんだペー
スト36中の金属は、Sn:Pb=60〜70:40〜
30の合金である。
Further, in FIG. 5A, an opening is formed only at a position corresponding to an opening 24B for forming a bump electrode 24 for bonding the third semiconductor element 18 mounted on the third stage. The opening 24B is filled with a solder paste 36 by squeezing. This solder paste 36 includes a metal having a melting point lower than the melting point of the metal in the solder paste 32 filled second time. For example, the metal in the solder paste 36 filled for the third time is Sn: Pb = 60-70: 40-
30 alloys.

【0019】図5(B)において、メタルマスク34を
剥がす。図5(C)において、はんだペースト36をリ
フローし、バンプ電極24を再形成する。リフローは、
2回目に充填されたはんだペースト32中の金属の融点
より低く、今回充填されたはんだペースト36中の金属
の融点よりも高い温度で加熱することにより実施され
る。はんだペースト36中の金属が溶融し、前に形成し
たはんだペースト28,32中の金属で形成されたバン
プ電極20,22及びバンプ電極24のコアは溶融しな
い。こうして、高融点のコアを有するバンプ電極24を
形成する。バンプ電極24の高さはバンプ電極22,2
0の高さよりも高くなる。その後、はんだペースト32
中のフラックス成分は洗浄される。
In FIG. 5B, the metal mask 34 is peeled off. In FIG. 5C, the solder paste 36 is reflowed, and the bump electrodes 24 are formed again. Reflow is
This is performed by heating at a temperature lower than the melting point of the metal in the solder paste 32 filled second time and higher than the melting point of the metal in the solder paste 36 filled this time. The metal in the solder paste 36 is melted, and the cores of the bump electrodes 20 and 22 and the bump electrode 24 formed of the metal in the solder pastes 28 and 32 formed earlier do not melt. Thus, a bump electrode 24 having a high melting point core is formed. The height of the bump electrode 24 is the same as that of the bump electrodes 22 and 2.
It is higher than the height of 0. Then, the solder paste 32
The flux components therein are washed.

【0020】図5(D)において、プリント配線基板1
2を覆っていた樹脂の膜26を剥離する。これによっ
て、プリント配線基板12は、サイズ、組成、高さの異
なる複数のバンプ電極20,22,24を有することに
なる。これらのバンプ電極20,22,24の組成に適
応した温度で、第1、第2、第3の半導体素子14,1
6,18をプリント配線基板12にフリップチップ実装
することにより、図1及び図2に示された3次元な実装
構造の半導体装置10を得ることができる。この場合、
第1、第2、第3の半導体素子14,16,18は、バ
ンプ電極20,22,24の融点に合わせて、段階的に
実装される。積層実装される上段の半導体素子16,1
8は、下段の半導体素子14,16に比べ長辺を有して
いる。
In FIG. 5D, the printed wiring board 1
The resin film 26 that has covered the second resin 2 is peeled off. Thus, the printed wiring board 12 has a plurality of bump electrodes 20, 22, and 24 having different sizes, compositions, and heights. At a temperature suitable for the composition of these bump electrodes 20, 22, 24, the first, second, and third semiconductor elements 14, 1
By mounting flip chips 6 and 18 on the printed wiring board 12, the semiconductor device 10 having the three-dimensional mounting structure shown in FIGS. 1 and 2 can be obtained. in this case,
The first, second, and third semiconductor elements 14, 16, 18 are mounted stepwise according to the melting points of the bump electrodes 20, 22, 24. Upper semiconductor elements 16 and 1 stacked and mounted
8 has longer sides than the lower semiconductor elements 14 and 16.

【0021】上記方法により形成されたバンプ電極を用
い、チップオンチップパッケージ、システムインパッケ
ージ、及びチップオンチップモジュールとともに、積層
実装されたパッケージ及びモジュール化形態の半導体装
置を製造することが可能である。以上説明したように、
単一基板上へサイズ、組成、高さの異なるバンプ電極を
形成することにより、ベアチップ実装を行うために個々
の半導体素子へバンプ電極を形成する工程を省略するこ
とができる。バンプ電極を形成する基板の簡略化も可能
である。上段に実装される半導体素子用の電極パッド及
びバンプ電極のサイズが大きいため、実装ストレスによ
るバンプ電極と電極パッドの間での剥がれによる電気的
な接触不良を防止できる。また、各バンプ電極は、高融
点コアを有しているため、実装時のバンプ電極間のショ
ートを防止できるとともに、実装時及び実装後にかかる
ストレスによるバンプの変移を吸収でき、効果は大き
い。
By using the bump electrode formed by the above method, it is possible to manufacture a package mounted and a modularized semiconductor device together with a chip-on-chip package, a system-in-package, and a chip-on-chip module. . As explained above,
By forming bump electrodes having different sizes, compositions, and heights on a single substrate, it is possible to omit the step of forming bump electrodes on individual semiconductor elements in order to perform bare chip mounting. The substrate on which the bump electrodes are formed can be simplified. Since the size of the electrode pads and bump electrodes for the semiconductor element mounted on the upper stage is large, it is possible to prevent electrical contact failure due to peeling between the bump electrodes and the electrode pads due to mounting stress. In addition, since each bump electrode has a high melting point core, it is possible to prevent a short circuit between the bump electrodes during mounting, and to absorb a change in the bump due to stress applied during and after mounting, which is highly effective.

【0022】また、本実施例では、樹脂の膜26に複数
の群に分けられる開口部を形成した後、その開口部には
んだペーストを充填し、リフローによりバンプ電極を形
成する。そして、樹脂の膜26の開口部へのはんだペー
ストの充填は、樹脂の膜26の表面ではんだペーストを
スキージングすることにより行う方法と、又はメタルマ
スクを被せてスキージングにより充填する方法とがあ
る。本実施例では、これらの2つのスキージングを併用
している。上記方法により形成されるバンプ電極は、最
後の工程で形成されたバンプ電極以外の全てのバンプ電
極が、樹脂の膜よりも突出していない。
In this embodiment, after forming openings divided into a plurality of groups in the resin film 26, the openings are filled with solder paste and bump electrodes are formed by reflow. The filling of the solder paste into the opening of the resin film 26 is performed by squeezing the solder paste on the surface of the resin film 26, or by filling with a metal mask by squeezing. is there. In this embodiment, these two squeezing methods are used together. In the bump electrode formed by the above method, all the bump electrodes other than the bump electrode formed in the last step do not protrude from the resin film.

【0023】図6は本発明の他の実施例の半導体装置を
示す略解的平面図である。半導体装置40は、プリント
配線基板42と、第1の半導体素子24と、第2の半導
体素子26と、第3の半導体素子28とからなる。第
2、第3の半導体素子26,18は互いに同じ機能を有
する。プリント配線基板42は、第1群のバンプ電極5
0と、第2群のバンプ電極52と、第3群のバンプ電極
54とを含む。第1群のバンプ電極50はプリント配線
基板42の中央部に位置し、最も背が低く、且つ最も面
積が小さい。第2、第3群のバンプ電極52,54は第
1群のバンプ電極50の外側に互いに対称に位置し、第
1群のバンプ電極50よりも背が高く、且つ面積が大き
い。第1の半導体素子44は第1群のバンプ電極50に
よってプリント配線基板42に実装される。第2、第3
の半導体素子46,48は第1の半導体素子44に載っ
た状態で第2、第3群のバンプ電極52,54によって
プリント配線基板42に実装される。バンプ電極50,
52,54はプリント配線基板42に図3から図5を参
照して説明したようにして形成される。ただし、第2、
第3群のバンプ電極52,54は同時に形成されるの
で、はんだペーストの充填及びリフローは2回でよい。
このように、同一機能又は異なった機能をもった複数の
半導体素子を並列的に形成することもできる。
FIG. 6 is a schematic plan view showing a semiconductor device according to another embodiment of the present invention. The semiconductor device 40 includes a printed wiring board 42, a first semiconductor element 24, a second semiconductor element 26, and a third semiconductor element 28. The second and third semiconductor elements 26 and 18 have the same function. The printed wiring board 42 includes the first group of bump electrodes 5.
0, a second group of bump electrodes 52, and a third group of bump electrodes 54. The first group of bump electrodes 50 is located at the center of the printed wiring board 42, is the shortest, and has the smallest area. The second and third groups of bump electrodes 52 and 54 are located symmetrically outside the first group of bump electrodes 50 and are taller and larger in area than the first group of bump electrodes 50. The first semiconductor element 44 is mounted on the printed wiring board 42 by the first group of bump electrodes 50. Second, third
The semiconductor elements 46 and 48 are mounted on the printed wiring board 42 by the second and third groups of bump electrodes 52 and 54 while being mounted on the first semiconductor element 44. Bump electrode 50,
The reference numerals 52 and 54 are formed on the printed wiring board 42 as described with reference to FIGS. However, the second,
Since the third group of bump electrodes 52 and 54 are formed at the same time, the filling and reflow of the solder paste may be performed twice.
In this way, a plurality of semiconductor elements having the same function or different functions can be formed in parallel.

【0024】図7は本発明の他の実施例の半導体装置を
示す略解的平面図である。半導体装置60は、プリント
配線基板62と、第1の半導体素子64と、第2の半導
体素子66とからなる。プリント配線基板62は、第1
群のバンプ電極68と、第2群のバンプ電極70とを含
む。第1群のバンプ電極68はプリント配線基板62の
中央部に位置し、最も背が低く、且つ最も面積が小さ
い。第2群のバンプ電極70は第1群のバンプ電極68
の外側でプリント配線基板62の対角線上に位置する。
第1の半導体素子64は第1群のバンプ電極68によっ
てプリント配線基板62に実装される。第2の半導体素
子66は第1の半導体素子64に載った状態で第2群の
バンプ電極70によってプリント配線基板62に実装さ
れる。バンプ電極68,70はプリント配線基板62に
図3から図5を参照して説明したようにして形成され
る。ただし、はんだペーストの充填及びリフローは2回
でよい。このように、基板の面積、スペース、配線の状
況に応じて、半導体をあらゆる角度で実装することが可
能になる。この積層の実施例は一例であり、2段や3段
に限定されるものではない。それ以上の多段実装が可能
である。各群のバンプ電極は、2個以上のバンプ電極で
構成されており、且つ複数列、ジクザク配列等、あらゆ
る配置が可能である。
FIG. 7 is a schematic plan view showing a semiconductor device according to another embodiment of the present invention. The semiconductor device 60 includes a printed wiring board 62, a first semiconductor element 64, and a second semiconductor element 66. The printed wiring board 62 includes a first
A group of bump electrodes 68 and a second group of bump electrodes 70 are included. The first group of bump electrodes 68 is located at the center of the printed wiring board 62, is the shortest, and has the smallest area. The second group of bump electrodes 70 is the first group of bump electrodes 68.
And on the diagonal of the printed wiring board 62.
The first semiconductor element 64 is mounted on the printed wiring board 62 by the first group of bump electrodes 68. The second semiconductor element 66 is mounted on the printed wiring board 62 by the second group of bump electrodes 70 while being placed on the first semiconductor element 64. The bump electrodes 68 and 70 are formed on the printed wiring board 62 as described with reference to FIGS. However, the filling and reflow of the solder paste may be performed twice. In this way, it is possible to mount the semiconductor at any angle according to the area, space, and wiring conditions of the substrate. The embodiment of this lamination is an example, and is not limited to two or three stages. More multi-stage mounting is possible. Each group of bump electrodes is composed of two or more bump electrodes, and can be arranged in a plurality of rows, in a zigzag arrangement, or in any other arrangement.

【0025】[0025]

【発明の効果】以上説明したように、本発明によれば、
単一の基板へ複数の特徴をもったバンプ電極を形成する
ことにより、積層実装する半導体素子へのバンプ電極形
成工程を省略することができる。また、基板上に設けた
膜に開口部を設けてバンプ電極を形成することにより、
バンプ電極を簡単且つ確実に形成することができる。ま
た、バンプ電極を有する基板の簡略化も可能である。
As described above, according to the present invention,
By forming a bump electrode having a plurality of features on a single substrate, a step of forming a bump electrode on a semiconductor element to be stacked and mounted can be omitted. Also, by providing an opening in the film provided on the substrate to form a bump electrode,
Bump electrodes can be formed easily and reliably. In addition, it is possible to simplify the substrate having the bump electrodes.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の実施例の半導体装置を示す断面図であ
る。
FIG. 1 is a sectional view showing a semiconductor device according to an embodiment of the present invention.

【図2】図1の半導体装置を示す略解的平面図である。FIG. 2 is a schematic plan view showing the semiconductor device of FIG. 1;

【図3】本発明の実施例のはんだバンプの形成方法を示
す図である。
FIG. 3 is a diagram illustrating a method of forming a solder bump according to an embodiment of the present invention.

【図4】図2のはんだバンプの形成方法の続きの工程を
示す図である。
FIG. 4 is a view illustrating a subsequent step of the method of forming the solder bumps in FIG. 2;

【図5】図2のはんだバンプの形成方法の続きの工程を
示す図である。
FIG. 5 is a view showing a subsequent step of the method of forming the solder bumps of FIG. 2;

【図6】本発明の他の実施例の半導体装置を示す略解的
平面図である。
FIG. 6 is a schematic plan view showing a semiconductor device according to another embodiment of the present invention.

【図7】本発明の他の実施例の半導体装置を示す略解的
平面図である。
FIG. 7 is a schematic plan view showing a semiconductor device according to another embodiment of the present invention.

【符号の説明】[Explanation of symbols]

10…半導体装置 12…プリント配線基板 14…半導体素子 16…半導体素子 18…半導体素子 20…バンプ電極 20A…電極パッド 20B…開口部 22…バンプ電極 22A…電極パッド 22B…開口部 24…バンプ電極 24A…電極パッド 24B…開口部 26…膜 28…はんだペースト 30…メタルマスク 32…はんだペースト 34…メタルマスク 36…はんだペースト DESCRIPTION OF SYMBOLS 10 ... Semiconductor device 12 ... Printed wiring board 14 ... Semiconductor element 16 ... Semiconductor element 18 ... Semiconductor element 20 ... Bump electrode 20A ... Electrode pad 20B ... Opening 22 ... Bump electrode 22A ... Electrode pad 22B ... Opening 24 ... Bump electrode 24A ... Electrode pad 24B ... Opening 26 ... Film 28 ... Solder paste 30 ... Metal mask 32 ... Solder paste 34 ... Metal mask 36 ... Solder paste

───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.7 識別記号 FI テーマコート゛(参考) H05K 3/34 505 (72)発明者 吉川 政廣 神奈川県川崎市中原区上小田中4丁目1番 1号 富士通株式会社内 Fターム(参考) 5E319 AA03 AB05 AC01 BB04 BB05 CC33 CD04 CD26 GG03 GG15 5F044 KK17 KK19 LL01 LL04 RR03──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. 7 Identification symbol FI Theme Court ゛ (Reference) H05K 3/34 505 (72) Inventor Masahiro Yoshikawa 4-1-1 Uedanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture Fujitsu F term in the company (reference) 5E319 AA03 AB05 AC01 BB04 BB05 CC33 CD04 CD26 GG03 GG15 5F044 KK17 KK19 LL01 LL04 RR03

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】 複数の群の電極パッドを有する基板の表
面を覆う膜を形成する工程と、 該膜に各電極パッドに対応し且つ該電極パッドの群毎に
大きさの異なる開口部を形成する工程と、 該開口部内で電極パッドに固定されたバンプ電極を形成
する工程と、 該膜を除去する工程とからなることを特徴とするはんだ
バンプの形成方法。
1. A step of forming a film covering the surface of a substrate having a plurality of groups of electrode pads, and forming openings in the film corresponding to the respective electrode pads and having different sizes for each group of the electrode pads. Forming a bump electrode fixed to an electrode pad in the opening, and removing the film.
【請求項2】 該バンプ電極を形成する工程は、該開口
部内にはんだペーストを充填し、それからリフローを行
うことを含むことを特徴とする請求項1に記載のはんだ
バンプ電極の形成方法。
2. The method according to claim 1, wherein the step of forming the bump electrode includes filling the opening with a solder paste and performing reflow.
【請求項3】 複数の群の電極パッドは少なくとも第1
群の電極パッド及び第2群の電極パッドを含み、nを自
然数とするとき、第1群の電極パッド上のバンプ電極の
形成はn回のはんだペーストの充填及びリフローにより
実施され、第2群の電極パッド上のバンプ電極の形成は
n回とは異なる回数のはんだペーストの充填及びリフロ
ーにより実施されることを特徴とする請求項2に記載の
はんだバンプの形成方法。
3. The method according to claim 1, wherein the plurality of groups of electrode pads are at least first.
When the electrode group includes a group of electrode pads and a second group of electrode pads, and n is a natural number, the formation of the bump electrodes on the first group of electrode pads is performed by solder paste filling and reflowing n times. 3. The method of claim 2, wherein the forming of the bump electrode on the electrode pad is performed by filling and reflowing the solder paste a different number of times from n.
【請求項4】 請求項1から3のいずれかに記載のはん
だバンプの形成方法で形成されてバンプ電極を有する基
板と、電極パッドを有する電気素子とをバンプ電極によ
って接合してなる半導体装置。
4. A semiconductor device comprising a substrate formed by the method for forming a solder bump according to claim 1 and having a bump electrode, and an electric element having an electrode pad joined by the bump electrode.
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US7230329B2 (en) 2003-02-07 2007-06-12 Seiko Epson Corporation Semiconductor device, electronic device, electronic equipment, method of manufacturing semiconductor device, and method of manufacturing electronic device
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JP2011054652A (en) * 2009-08-31 2011-03-17 Toppan Printing Co Ltd Semiconductor device and method of manufacturing the same
KR101118348B1 (en) * 2004-02-20 2012-03-09 제이에스알 가부시끼가이샤 2 bilayer laminated film for bump formation and method of bump formation
JP2012231038A (en) * 2011-04-27 2012-11-22 Ngk Spark Plug Co Ltd Wiring board manufacturing method

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Publication number Priority date Publication date Assignee Title
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JP4633971B2 (en) * 2001-07-11 2011-02-16 ルネサスエレクトロニクス株式会社 Semiconductor device
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KR101118348B1 (en) * 2004-02-20 2012-03-09 제이에스알 가부시끼가이샤 2 bilayer laminated film for bump formation and method of bump formation
JP2008258380A (en) * 2007-04-04 2008-10-23 Shinko Electric Ind Co Ltd Semiconductor device and wiring substrate used therein
JP2011054652A (en) * 2009-08-31 2011-03-17 Toppan Printing Co Ltd Semiconductor device and method of manufacturing the same
JP2012231038A (en) * 2011-04-27 2012-11-22 Ngk Spark Plug Co Ltd Wiring board manufacturing method

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