JPH06204272A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH06204272A JPH06204272A JP5001040A JP104093A JPH06204272A JP H06204272 A JPH06204272 A JP H06204272A JP 5001040 A JP5001040 A JP 5001040A JP 104093 A JP104093 A JP 104093A JP H06204272 A JPH06204272 A JP H06204272A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor element
- circuit board
- sealing resin
- resin
- sealing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/831—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
- H01L2224/83102—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus using surface energy, e.g. capillary forces
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/921—Connecting a surface with connectors of different types
- H01L2224/9212—Sequential connecting processes
- H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
- H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01004—Beryllium [Be]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15151—Shape the die mounting substrate comprising an aperture, e.g. for underfilling, outgassing, window type wire connections
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、半導体素子をフェイス
ダウンで回路基板に搭載し、樹脂封止する工程に特徴を
有する半導体装置の製造方法に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device having a step of mounting a semiconductor element face down on a circuit board and sealing with a resin.
【０００２】[0002]
【従来の技術】従来より半導体装置は、半導体素子の周
辺に設けられたアルミ電極からＡｕまたはＡｌの極細線
で一本ずつ順次回路基板の外部端子に接続し、また機械
的保護のためにパッケージング（樹脂封止）されたもの
を利用するのが主流である。通常、半導体素子のパッケ
ージングには、エポキシ樹脂をモールド成形したものが
用いられている。しかし、メモリー、マイクロコンピュ
ータ等の半導体素子と連結するＩｎｐｕｔ／Ｏｕｔｐｕ
ｔ（Ｉ／Ｏ）のある半導体素子では、機能数の増加とと
もに、チップサイズ、および電極端子数の増大に伴いパ
ッケージサイズも大きくなっている。しかしながら昨
今、小型化、軽量化、薄型化する電子機器においてはパ
ッケージサイズの増大は問題となっている。この問題を
解決する上で、従来より半導体素子の高密度実装性に優
れている方法の一手段として、半導体素子をフェイスダ
ウンにて搭載するフリップチップ実装工法がある。2. Description of the Related Art Conventionally, a semiconductor device has been constructed such that aluminum electrodes provided in the periphery of a semiconductor element are sequentially connected to an external terminal of a circuit board one by one with an ultrafine wire of Au or Al, and a package is provided for mechanical protection. The mainstream is to use a resin (sealed with resin). In general, a semiconductor element is packaged by molding an epoxy resin. However, Input / Output that connects with semiconductor devices such as memories and microcomputers
In a semiconductor device with t (I / O), the package size is increasing with the increase in the number of functions, the chip size, and the number of electrode terminals. However, in recent years, the increase in package size has become a problem in electronic devices that are becoming smaller, lighter, and thinner. In order to solve this problem, a flip-chip mounting method for mounting the semiconductor element face down is known as one means of the method which is excellent in high-density mounting property of the semiconductor element in the related art.
【０００３】従来の半導体装置の製造方法として、前記
フリップチップ工法の封止工程を、図を用いて説明す
る。図４，図５，図６および図７は、従来の半導体装置
の製造方法において、フリップチップ工法の封止工程を
示す工程図である。図４、図５，図６および図７におい
て、１は突起電極を有した半導体素子、２は回路基板、
３は封止樹脂供給用ノズル、４はエポキシ、シリコン系
等の封止樹脂である。As a conventional method of manufacturing a semiconductor device, the sealing step of the flip chip method will be described with reference to the drawings. 4, FIG. 5, FIG. 6 and FIG. 7 are process diagrams showing a sealing process of a flip chip method in a conventional method of manufacturing a semiconductor device. 4, 5, 6, and 7, 1 is a semiconductor element having a protruding electrode, 2 is a circuit board,
Reference numeral 3 is a nozzle for supplying a sealing resin, and 4 is a sealing resin such as epoxy or silicon.
【０００４】以下、図４，図５，図６および図７を参照
しながら従来の半導体装置の製造方法における封止方法
について説明する。Hereinafter, a sealing method in the conventional method of manufacturing a semiconductor device will be described with reference to FIGS. 4, 5, 6 and 7.
【０００５】まず図４（ａ），（ｂ）に示すように、突
起電極を有した半導体素子１を回路基板２にフリップチ
ップ実装し、はんだ材などにより回路基板２上の電極と
接続した後、一辺毎に前記半導体素子１の側面に封止樹
脂供給ノズル３をセットし、平行移動させながらエポキ
シ、シリコン系等の封止樹脂４を供給し、毛細管現象を
利用し、前記半導体素子１と前記回路基板２との隙間に
前記封止樹脂４を充填するものである。First, as shown in FIGS. 4 (a) and 4 (b), a semiconductor element 1 having protruding electrodes is flip-chip mounted on a circuit board 2 and connected to electrodes on the circuit board 2 by a solder material or the like. The sealing resin supply nozzle 3 is set on the side surface of the semiconductor element 1 for each side, and the sealing resin 4 such as epoxy or silicon is supplied while moving in parallel, and by utilizing the capillary phenomenon, The gap between the circuit board 2 and the sealing resin 4 is filled.
【０００６】次に図５（ａ），（ｂ）に示すように、対
向側面において、前記封止方法により前記半導体素子１
と前記回路基板２との隙間に前記封止樹脂４を充填す
る。Next, as shown in FIGS. 5A and 5B, the semiconductor element 1 is formed on the opposite side surface by the sealing method.
The sealing resin 4 is filled in a gap between the circuit board 2 and the circuit board 2.
【０００７】次に図６（ａ），（ｂ）に示すように、後
部側面に前記封止方法により前記半導体素子１と前記回
路基板２との隙間に前記封止樹脂４を充填する。Next, as shown in FIGS. 6A and 6B, the sealing resin 4 is filled in the gap between the semiconductor element 1 and the circuit board 2 on the rear side surface by the sealing method.
【０００８】最後に図７（ａ），（ｂ）に示すように、
未封止部分である前部面に前記封止方法により、前記半
導体素子１と前記回路基板２との隙間に前記封止樹脂４
を充填し、樹脂硬化させて半導体装置が完成する。Finally, as shown in FIGS. 7 (a) and 7 (b),
The sealing resin 4 is provided in the gap between the semiconductor element 1 and the circuit board 2 on the front surface which is an unsealed portion by the sealing method.
And the resin is cured to complete the semiconductor device.
【０００９】[0009]
【発明が解決しようとする課題】しかしながら前記従来
の半導体装置の製造方法では、一辺方向からエポキシ、
シリコン系等の封止樹脂４を供給し、前記封止樹脂４を
毛細管現象を利用することにより供給するため、突起電
極を有した半導体素子１と回路基板２との隙間に前記封
止樹脂４を充填される過程において、気泡がその隙間に
残る場合がある。前記気泡は、半導体装置の信頼性試験
において、半導体素子間でのリーク電流不良や、前記半
導体素子１の電極部の腐食によるコンタクト不良を生
じ、半導体装置の信頼性を著しく低下させる原因となっ
ていた。このため、回路基板に空気抜き貫通孔を設けた
回路基板を用い、封止樹脂を充填することにより、隙間
中の気泡を除去する手段が考えられるが、この場合、回
路基板下面から空気抜き貫通孔を通じて封止樹脂がたれ
ることがあり、この処理に多大の工数を要していた。However, in the conventional method of manufacturing a semiconductor device, the epoxy is
Since the sealing resin 4 such as a silicon-based resin is supplied and the sealing resin 4 is supplied by utilizing the capillary phenomenon, the sealing resin 4 is provided in the gap between the semiconductor element 1 having the protruding electrode and the circuit board 2. Bubbles may remain in the gap in the process of being filled. In the reliability test of the semiconductor device, the air bubble causes a leak current defect between semiconductor elements and a contact defect due to corrosion of the electrode portion of the semiconductor element 1, which causes a significant decrease in reliability of the semiconductor device. It was For this reason, it is conceivable to use a circuit board provided with an air vent through hole in the circuit board and to fill the sealing resin to remove the air bubbles in the gap. The sealing resin may drip, and this process requires a great number of man-hours.
【００１０】本発明は、前記従来の課題を解決するもの
で、樹脂封止工程時に発生する気泡の防止と封止樹脂の
たれ防止、および封止作業の容易化が可能となる半導体
装置の製造方法を提供することを目的とする。The present invention solves the above-mentioned conventional problems, and manufactures a semiconductor device capable of preventing bubbles generated during a resin sealing step, preventing sagging of a sealing resin, and facilitating a sealing operation. The purpose is to provide a method.
【００１１】[0011]
【課題を解決するための手段】前記課題を解決するため
に、本発明に係る半導体装置の製造方法は、以下のよう
な構成を有している。すなわち、半導体素子をフェイス
ダウンさせて少なくとも１個以上の貫通孔を有した回路
基板に搭載する工程と、前記搭載した半導体素子の平面
方向において左右両側面端部から封止樹脂供給ノズルを
前記半導体素子に対して平行移動させながら封止樹脂を
供給し、前記半導体素子と前記少なくとも１個以上の貫
通孔を有した回路基板との隙間および半導体素子の周辺
部に前記封止樹脂を充填被覆する工程と、前記搭載した
半導体素子の平面方向において前後両側両端部から封止
樹脂供給ノズルを前記半導体素子に対して平行移動させ
ながら封止樹脂を供給し、前記半導体素子と前記１個以
上の貫通孔を有した回路基板との隙間および半導体素子
の周辺部に前記封止樹脂を充填被覆する工程とよりなる
ことを特徴とする。In order to solve the above problems, a method of manufacturing a semiconductor device according to the present invention has the following structure. That is, a step of mounting a semiconductor element face down on a circuit board having at least one or more through holes, and a step of mounting a sealing resin supply nozzle from the left and right side end portions in the plane direction of the mounted semiconductor element to the semiconductor The sealing resin is supplied while moving in parallel to the element, and the gap between the semiconductor element and the circuit board having at least one or more through holes and the peripheral portion of the semiconductor element are filled and covered with the sealing resin. Step, and while supplying the sealing resin while moving the sealing resin supply nozzle in parallel with the semiconductor element from both front and rear ends in the plane direction of the mounted semiconductor element, the semiconductor element and the one or more penetrating holes are penetrated. It is characterized by comprising the step of filling and covering the gap with the circuit board having the holes and the peripheral portion of the semiconductor element with the sealing resin.
【００１２】[0012]
【作用】前記構成により、封止工程において半導体素子
と回路基板との隙間を封止樹脂で充填する際、前記回路
基板が適切な穴径を有した少なくとも１個以上の貫通孔
を備えているため、気泡は前記貫通孔から逃げ、前記隙
間に気泡残りを防止し、しかも封止樹脂のたれを防止し
て封止作業を容易にすることが可能となる。With the above construction, when the gap between the semiconductor element and the circuit board is filled with the sealing resin in the sealing step, the circuit board has at least one through hole having an appropriate hole diameter. Therefore, air bubbles can escape from the through holes, prevent air bubbles from remaining in the gap, and prevent sagging of the sealing resin to facilitate the sealing operation.
【００１３】[0013]
【実施例】以下、本発明の一実施例について、図面を参
照しながら説明する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.
【００１４】図１，図２および図３は、本発明の一実施
例における半導体装置の製造方法を示す工程図であり、
図１の（ａ）は断面図、（ｂ）は底面図である。図２の
（ａ）は断面図、（ｂ）は平面図である。図３の（ａ）
は断面図、（ｂ）は平面図である。図１，図２および図
３において、１は突起電極を有した半導体素子、３は封
止樹脂供給ノズル、４はエポキシ系の封止樹脂、５は空
気抜き貫通孔、６は回路基板、７は気泡である。FIGS. 1, 2 and 3 are process diagrams showing a method of manufacturing a semiconductor device according to an embodiment of the present invention.
1A is a sectional view and FIG. 1B is a bottom view. 2A is a sectional view and FIG. 2B is a plan view. FIG. 3 (a)
Is a cross-sectional view and (b) is a plan view. 1, 2 and 3, 1 is a semiconductor element having a protruding electrode, 3 is a sealing resin supply nozzle, 4 is an epoxy type sealing resin, 5 is an air vent through hole, 6 is a circuit board, and 7 is It is a bubble.
【００１５】まず図１（ａ），（ｂ）に示すように、空
気抜き貫通孔５を底面に有した回路基板６に突起電極を
有した半導体素子１を高精度位置決め装置により、フェ
イスダウンにて実装し、回路基板６と前記半導体素子１
とをはんだ材などの導電性接着剤により接続する。First, as shown in FIGS. 1 (a) and 1 (b), a semiconductor element 1 having protruding electrodes is face-down by a high-precision positioning device on a circuit board 6 having an air vent through hole 5 on its bottom surface. After mounting, the circuit board 6 and the semiconductor element 1
And are connected by a conductive adhesive such as a solder material.
【００１６】次に図２（ａ），（ｂ）に示すように、前
記回路基板６と前記半導体素子１を接続した製品の機械
的性質、信頼性向上を図るために樹脂封止を行なう。そ
の方法としては、前記回路基板６を加熱テーブル上に置
き、前記回路基板６の下面より加熱し、かつ加熱テーブ
ル上の前記回路基板６を真空吸着で固定する。次に、前
記半導体素子１の左右両側面に封止樹脂供給ノズル３を
各々一辺毎にセットする。そして、封止樹脂供給ノズル
３を平行移動させながらエポキシ系の封止樹脂４を供給
し、前記半導体素子１と前記回路基板６の隙間（５０μ
ｍから１００μｍの範囲）に前記封止樹脂４を充填す
る。Next, as shown in FIGS. 2A and 2B, resin sealing is performed in order to improve the mechanical properties and reliability of the product in which the circuit board 6 and the semiconductor element 1 are connected. As a method thereof, the circuit board 6 is placed on a heating table, the lower surface of the circuit board 6 is heated, and the circuit board 6 on the heating table is fixed by vacuum suction. Next, the encapsulating resin supply nozzles 3 are set on each of the left and right side surfaces of the semiconductor element 1 for each side. Then, the epoxy-based sealing resin 4 is supplied while moving the sealing resin supply nozzle 3 in parallel, and the gap (50 μm) between the semiconductor element 1 and the circuit board 6 is supplied.
The range of m to 100 μm) is filled with the sealing resin 4.
【００１７】次に図３（ａ），（ｂ）に示すように、未
封止部分である前後両側面に封止樹脂供給ノズル３を各
々一辺毎にセットし、前記封止樹脂供給ノズル３を平行
移動させながら前記封止樹脂４を供給することにより、
前記半導体素子１と前記回路基板６との隙間に前記封止
樹脂４を充填し、かつ前記半導体素子１の周囲に前記封
止樹脂４を充填し、前記充填した封止樹脂４を硬化させ
て封止が完了する。Next, as shown in FIGS. 3 (a) and 3 (b), the sealing resin supply nozzles 3 are set on each of the front and rear side surfaces, which are unsealed portions, for each side. By supplying the sealing resin 4 while moving in parallel,
The gap between the semiconductor element 1 and the circuit board 6 is filled with the sealing resin 4, the periphery of the semiconductor element 1 is filled with the sealing resin 4, and the filled sealing resin 4 is cured. The sealing is completed.
【００１８】なお前記充填０する場合の封止樹脂４とし
ては、前記エポキシ系の樹脂として液状エポキシ樹脂以
外にも、シリコン系の樹脂でも封止樹脂として使用でき
る。また前記充填する場合の封止樹脂の溶融粘度は、エ
ポキシ系の樹脂である場合、２５［℃］で８０〜３００
［ｃＰ］であり、半導体素子１と前記回路基板２の隙間
に容易に充填することができる。As the sealing resin 4 in the case of the filling 0, a silicone resin other than the liquid epoxy resin as the epoxy resin can be used as the sealing resin. Further, the melt viscosity of the sealing resin in the case of filling is 80 to 300 at 25 [° C.] when it is an epoxy resin.
Since it is [cP], the gap between the semiconductor element 1 and the circuit board 2 can be easily filled.
【００１９】以下に実施例に示す製造方法により、数種
類の径を有した空気抜き貫通孔５を２個、４個、５個、
１０個設けた回路基板６に突起電極を有した半導体素子
１をフリップチップ実装して接続した後、エポキシ系の
封止樹脂４を半導体素子と回路基板との隙間に充填し、
樹脂封止を行なった場合の半導体素子１と回路基板６と
の隙間にできた気泡と、前記封止樹脂４の前記回路基板
６からのたれを測定した結果を（表１），（表２），
（表３）および（表４）に示す。According to the manufacturing method shown in the embodiment below, two, four, and five air vent through holes 5 having several kinds of diameters are formed.
After the semiconductor element 1 having the protruding electrodes is flip-chip mounted and connected to ten provided circuit boards 6, epoxy-based encapsulating resin 4 is filled in the gap between the semiconductor element and the circuit board.
The air bubbles formed in the gap between the semiconductor element 1 and the circuit board 6 and the sagging of the sealing resin 4 from the circuit board 6 when the resin sealing is performed are shown in Table 1 and Table 2 ),
It shows in (Table 3) and (Table 4).
【００２０】[0020]
【表１】 [Table 1]
【００２１】[0021]
【表２】 [Table 2]
【００２２】[0022]
【表３】 [Table 3]
【００２３】[0023]
【表４】 [Table 4]
【００２４】以上のように、本実施例に係る半導体装置
の製造方法において、回路基板６の構造条件としては、
前記回路基板６に設けられた空気抜き貫通孔５の数を４
個または５個とし、そしてその穴径はφ５０μｍからφ
３００μｍの範囲が適していることがわかる。また空気
抜き貫通孔５の配置位置は、前記回路基板２の配線パタ
ーン、突起電極を有した半導体素子１のサイズ等に依存
して変わるため限定しない。As described above, in the method of manufacturing the semiconductor device according to this embodiment, the structural condition of the circuit board 6 is as follows.
The number of the air vent through holes 5 provided on the circuit board 6 is 4
Or 5 holes, and the hole diameter is φ50μm to φ
It can be seen that the range of 300 μm is suitable. The arrangement position of the air vent through hole 5 is not limited because it changes depending on the wiring pattern of the circuit board 2, the size of the semiconductor element 1 having the protruding electrode, and the like.
【００２５】[0025]
【発明の効果】以上のように本発明は、半導体素子のフ
リップチップ実装の封止工程において、適切な穴径を有
した空気抜き貫通孔を少なくとも１個以上設けた回路基
板を用いることにより、半導体素子と回路基板との隙間
に残る気泡を効率よく除去することができる半導体装置
の製造方法を実現するものである。As described above, according to the present invention, in a flip chip mounting sealing process of a semiconductor device, by using a circuit board provided with at least one air vent through hole having an appropriate hole diameter, It is intended to realize a method for manufacturing a semiconductor device capable of efficiently removing bubbles remaining in a gap between an element and a circuit board.
【図１】本発明の一実施例における半導体装置の製造方
法を示す工程図FIG. 1 is a process diagram showing a method for manufacturing a semiconductor device according to an embodiment of the present invention.
【図２】本発明の一実施例における半導体装置の製造方
法を示す工程図FIG. 2 is a process diagram showing a method for manufacturing a semiconductor device according to an embodiment of the present invention.
【図３】本発明の一実施例における半導体装置の製造方
法を示す工程図FIG. 3 is a process chart showing a method for manufacturing a semiconductor device according to an embodiment of the present invention.
【図４】従来の半導体装置の製造方法を示す工程図FIG. 4 is a process diagram showing a conventional method for manufacturing a semiconductor device.
【図５】従来の半導体装置の製造方法を示す工程図FIG. 5 is a process diagram showing a conventional method for manufacturing a semiconductor device.
【図６】従来の半導体装置の製造方法を示す工程図FIG. 6 is a process diagram showing a conventional method for manufacturing a semiconductor device.
【図７】従来の半導体装置の製造方法を示す工程図FIG. 7 is a process diagram showing a conventional method for manufacturing a semiconductor device.
１ 半導体素子 ２ 回路基板 ３ 封止樹脂供給ノズル ４ 封止樹脂 ５ 空気抜き貫通孔 ６ 回路基板 ７ 気泡 1 Semiconductor Element 2 Circuit Board 3 Sealing Resin Supply Nozzle 4 Sealing Resin 5 Air Vent Through Hole 6 Circuit Board 7 Bubbles
Claims (1)
とも１個以上の貫通孔を有した回路基板に搭載する工程
と、前記搭載した半導体素子の平面方向において左右両
側面端部から封止樹脂供給ノズルを前記半導体素子に対
して平行移動させながら封止樹脂を供給し、前記半導体
素子と前記少なくとも１個以上の貫通孔を有した回路基
板との隙間および半導体素子の周辺部に前記封止樹脂を
充填被覆する工程と、前記搭載した半導体素子の平面方
向において前後両側両端部から封止樹脂供給ノズルを前
記半導体素子に対して平行移動させながら封止樹脂を供
給し、前記半導体素子と前記少なくとも１個以上の貫通
孔を有した回路基板との隙間および半導体素子の周辺部
に前記封止樹脂を充填被覆する工程とよりなることを特
徴とする半導体装置の製造方法。1. A step of mounting a semiconductor element face down on a circuit board having at least one or more through holes, and a sealing resin supply nozzle from left and right side end portions in a plane direction of the mounted semiconductor element. Is supplied to the semiconductor element while moving in parallel to the semiconductor element, and the sealing resin is applied to the gap between the semiconductor element and the circuit board having at least one or more through holes and the peripheral portion of the semiconductor element. The step of filling and covering, and supplying the sealing resin while moving the sealing resin supply nozzle in parallel with respect to the semiconductor element from both front and rear end portions in the plane direction of the mounted semiconductor element, and the semiconductor element and the at least 1 A semiconductor device comprising a step of filling and covering the gap between the circuit board having at least one through hole and the peripheral portion of the semiconductor element with the sealing resin. The method of production.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5001040A JP2962385B2 (en) | 1993-01-07 | 1993-01-07 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5001040A JP2962385B2 (en) | 1993-01-07 | 1993-01-07 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH06204272A true JPH06204272A (en) | 1994-07-22 |
| JP2962385B2 JP2962385B2 (en) | 1999-10-12 |
Family
ID=11490455
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5001040A Expired - Fee Related JP2962385B2 (en) | 1993-01-07 | 1993-01-07 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2962385B2 (en) |
Cited By (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0805486A1 (en) * | 1996-05-01 | 1997-11-05 | Lucent Technologies Inc. | Integrated circuit bonding method and apparatus |
| WO1999003145A1 (en) * | 1997-07-08 | 1999-01-21 | Robert Bosch Gmbh | Method for making a glued joint between an electronic component and a supporting substrate |
| US6107689A (en) * | 1996-07-30 | 2000-08-22 | Kabushiki Kaisha Toshiba | Semiconductor device |
| US6324069B1 (en) * | 1997-10-29 | 2001-11-27 | Hestia Technologies, Inc. | Chip package with molded underfill |
| US6495083B2 (en) | 1997-10-29 | 2002-12-17 | Hestia Technologies, Inc. | Method of underfilling an integrated circuit chip |
| GB2387562A (en) * | 2002-04-16 | 2003-10-22 | Agilent Technologies Inc | Method of attaching componenets and component structure |
| US6815830B2 (en) | 2000-03-10 | 2004-11-09 | Seiko Epson Corporation | Semiconductor device and method of manufacturing the same, circuit board and electronic instrument |
| KR100545881B1 (en) * | 1998-03-24 | 2006-01-25 | 세이코 엡슨 가부시키가이샤 | A mounting structure of a semiconductor chip, a liquid crystal device, and an electronic device |
| JP2006032622A (en) * | 2004-07-15 | 2006-02-02 | Mitsubishi Electric Corp | Mounted structure of leadless package |
| US8371026B2 (en) | 2006-06-02 | 2013-02-12 | Murata Manufacturing Co., Ltd. | Method for manufacturing multilayer ceramic electronic device |
| JP2015156733A (en) * | 2014-02-20 | 2015-08-27 | 株式会社オートネットワーク技術研究所 | circuit structure |
| JP2017123410A (en) * | 2016-01-07 | 2017-07-13 | トヨタ自動車株式会社 | Method of manufacturing semiconductor device |
| CN108063123A (en) * | 2017-10-30 | 2018-05-22 | 张延赤 | The structure design of cracking is prevented during plastic packaging electronic device Reflow Soldering |
-
1993
- 1993-01-07 JP JP5001040A patent/JP2962385B2/en not_active Expired - Fee Related
Cited By (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0805486A1 (en) * | 1996-05-01 | 1997-11-05 | Lucent Technologies Inc. | Integrated circuit bonding method and apparatus |
| US6107689A (en) * | 1996-07-30 | 2000-08-22 | Kabushiki Kaisha Toshiba | Semiconductor device |
| WO1999003145A1 (en) * | 1997-07-08 | 1999-01-21 | Robert Bosch Gmbh | Method for making a glued joint between an electronic component and a supporting substrate |
| US6324069B1 (en) * | 1997-10-29 | 2001-11-27 | Hestia Technologies, Inc. | Chip package with molded underfill |
| US6495083B2 (en) | 1997-10-29 | 2002-12-17 | Hestia Technologies, Inc. | Method of underfilling an integrated circuit chip |
| US6560122B2 (en) | 1997-10-29 | 2003-05-06 | Hestia Technologies, Inc. | Chip package with molded underfill |
| KR100545881B1 (en) * | 1998-03-24 | 2006-01-25 | 세이코 엡슨 가부시키가이샤 | A mounting structure of a semiconductor chip, a liquid crystal device, and an electronic device |
| US6815830B2 (en) | 2000-03-10 | 2004-11-09 | Seiko Epson Corporation | Semiconductor device and method of manufacturing the same, circuit board and electronic instrument |
| GB2387562B (en) * | 2002-04-16 | 2005-06-15 | Agilent Technologies Inc | Method of attaching componenets and component structure |
| GB2387562A (en) * | 2002-04-16 | 2003-10-22 | Agilent Technologies Inc | Method of attaching componenets and component structure |
| JP2006032622A (en) * | 2004-07-15 | 2006-02-02 | Mitsubishi Electric Corp | Mounted structure of leadless package |
| US8371026B2 (en) | 2006-06-02 | 2013-02-12 | Murata Manufacturing Co., Ltd. | Method for manufacturing multilayer ceramic electronic device |
| JP2015156733A (en) * | 2014-02-20 | 2015-08-27 | 株式会社オートネットワーク技術研究所 | circuit structure |
| JP2017123410A (en) * | 2016-01-07 | 2017-07-13 | トヨタ自動車株式会社 | Method of manufacturing semiconductor device |
| CN108063123A (en) * | 2017-10-30 | 2018-05-22 | 张延赤 | The structure design of cracking is prevented during plastic packaging electronic device Reflow Soldering |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2962385B2 (en) | 1999-10-12 |
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