JP2758115B2 - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JP2758115B2 JP2758115B2 JP4360574A JP36057492A JP2758115B2 JP 2758115 B2 JP2758115 B2 JP 2758115B2 JP 4360574 A JP4360574 A JP 4360574A JP 36057492 A JP36057492 A JP 36057492A JP 2758115 B2 JP2758115 B2 JP 2758115B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor element
- resin
- semiconductor device
- substrate
- dam
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/27—Manufacturing methods
- H01L2224/27011—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature
- H01L2224/27013—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature for holding or confining the layer connector, e.g. solder flow barrier
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/83009—Pre-treatment of the layer connector or the bonding area
- H01L2224/83051—Forming additional members, e.g. dam structures
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Wire Bonding (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Description
【０００１】[0001]
【産業上の利用分野】本発明は、主として高速動作用の
半導体装置や、マイクロ波を発振、増幅する半導体装置
に係り、特に、半導体素子がフリップチップ方式で基板
上に組み込まれた半導体装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device for high-speed operation and a semiconductor device for oscillating and amplifying microwaves, and more particularly to a semiconductor device in which a semiconductor element is incorporated on a substrate by a flip-chip method. .
【０００２】[0002]
【従来の技術】従来、半導体素子を基板上に実装する方
式として、ワイヤーボンディング方式とフリップチップ
方式とがある。ワイヤーボンディング方式は、確立され
た適用容易な実装方式ではあるが、上記のような動作周
波数の高い半導体装置に適用すると、半導体素子の電極
と基板とを電気接続する金属細線がインダクタンス成分
をもつので、インピーダンスマッチング不良による入出
力反射率の増加や、信号の減衰を引き起こすという難点
がある。2. Description of the Related Art Conventionally, as a method of mounting a semiconductor element on a substrate, there are a wire bonding method and a flip chip method. The wire bonding method is an established easy-to-apply mounting method.However, when applied to a semiconductor device having a high operating frequency as described above, a thin metal wire for electrically connecting an electrode of a semiconductor element and a substrate has an inductance component. However, there is a problem in that the input / output reflectivity increases due to poor impedance matching and signal attenuation occurs.
【０００３】そこで、上記のような動作周波数の高い半
導体装置の実装方式としては、フリップチップ方式が適
している。以下、図５を参照して、フリップチップ方式
で実装された半導体装置の構成を説明する。Therefore, a flip-chip method is suitable as a method for mounting a semiconductor device having a high operating frequency as described above. Hereinafter, the configuration of the semiconductor device mounted by the flip-chip method will be described with reference to FIG.
【０００４】図中、符号１は実装基板であり、その表面
にリードパッド２が形成されている。符号３は半導体素
子で、その表面（図では下面）に、電極としての金属バ
ンプ４が形成されている。上記のような半導体素子３を
フェイスダウンボンディング（表面を下にして行うボン
ディング）することにより、各金属バンプ４が所定のリ
ードパッド２に一括接続される。半導体素子３のボンデ
ィング後、金属バンプ４への応力集中を避けるととも
に、半導体素子３の耐湿性を確保するために、半導体素
子３を樹脂５で封止している。In FIG. 1, reference numeral 1 denotes a mounting substrate, on which lead pads 2 are formed. Reference numeral 3 denotes a semiconductor element, and a metal bump 4 as an electrode is formed on a surface (a lower surface in the figure) of the semiconductor element. By performing the face-down bonding (bonding performed with the surface down) of the semiconductor element 3 as described above, each metal bump 4 is collectively connected to a predetermined lead pad 2. After the bonding of the semiconductor element 3, the semiconductor element 3 is sealed with a resin 5 in order to avoid stress concentration on the metal bumps 4 and secure the moisture resistance of the semiconductor element 3.
【０００５】[0005]
【発明が解決しようとする課題】しかしながら、上述し
たフリップチップ方式の実装方式によれば、封止用の樹
脂５が半導体素子３と実装基板１との間に流れ込むの
で、半導体素子３の信号線路間の寄生容量が増加し、例
えば図６に示すように、高周波数域で電力利得が低下す
るなどといった電気特性の劣化を招くという問題があ
る。However, according to the flip-chip type mounting method described above, the sealing resin 5 flows between the semiconductor element 3 and the mounting substrate 1, so that the signal line of the semiconductor element 3 is formed. There is a problem in that the parasitic capacitance between them increases, for example, as shown in FIG. 6, the electrical characteristics deteriorate, such as a decrease in power gain in a high frequency range.
【０００６】このような問題点を解決するために、フェ
イスダウンボンディングされた半導体素子を高粘度の樹
脂で封止することにより、半導体素子と基板間に樹脂が
流れ込むのを防止した半導体装置が提案されている（特
開平４−２１７３３５号公報）。In order to solve such a problem, a semiconductor device in which resin is prevented from flowing between a semiconductor element and a substrate by sealing a semiconductor element which has been face-down bonded with a high-viscosity resin has been proposed. (JP-A-4-217335).
【０００７】しかしながら、高粘度の樹脂を使って封止
すると、基板表面と樹脂との密着性が低くなるので、十
分な耐湿性を得ることができず、また、温度サイクルを
加えると、基板表面と樹脂との界面が剥離するおそれも
ある。However, if sealing is performed using a high-viscosity resin, the adhesion between the substrate surface and the resin is reduced, so that sufficient moisture resistance cannot be obtained. There is also a risk that the interface between the resin and the resin may peel off.
【０００８】本発明は、このような事情に鑑みてなされ
たものであって、半導体装置の電気的特性を劣化させる
ことなく、しかも高い信頼性を得ることができる半導体
装置を提供することを目的としている。The present invention has been made in view of such circumstances, and has as its object to provide a semiconductor device capable of obtaining high reliability without deteriorating electrical characteristics of the semiconductor device. And
【０００９】[0009]
【課題を解決するための手段】本発明は、このような目
的を達成するために、次のような構成をとる。すなわ
ち、本発明は、半導体素子がその表面を下側にして基板
上に実装され、前記表面に形成された金属バンプと前記
基板上に形成されたリードパッドとが電気的に接続され
る半導体装置において、前記半導体素子は低粘度の樹脂
で封止されており、かつ、前記半導体素子は前記封止樹
脂の内部への流れ込みを防止する、前記金属バンプと同
じ材料で形成された畝状突起（ダム）を備えたものであ
る。The present invention has the following configuration in order to achieve the above object. That is, the present invention provides a semiconductor device in which a semiconductor element is mounted on a substrate with its surface facing down, and a metal bump formed on the surface is electrically connected to a lead pad formed on the substrate. In the above, the semiconductor element is sealed with a low-viscosity resin, and the semiconductor element is the same as the metal bump, which prevents the sealing resin from flowing into the inside.
It is provided with ridge-shaped protrusions (dams) formed of the same material .
【００１０】[0010]
【作用】本発明の作用は次のとおりである。本発明によ
れば、半導体素子の表面に形成された畝状突起によっ
て、低粘度の封止樹脂の内部への流れ込みが阻止され
る。The operation of the present invention is as follows. According to the present invention, the ridge-shaped projections formed on the surface of the semiconductor element prevent the low-viscosity sealing resin from flowing into the inside.
【００１１】[0011]
【実施例】本発明の実施例を説明する前に、本発明の実
施例と共通する構成を一部に備えた比較例を説明する。 ＜比較例＞ 図１は比較例に用いられる半導体素子の外観斜視図、図
２は実装状態を示す断面図である。図１に示すように、
半導体素子１０は、その表面の周辺部に複数個の金属バ
ンプ１１が形成されている。金属バンプ１１としては、
ハンダあるいは金などの金属材料が用いられる。金属バ
ンプ１１の形成手法は特に限定しないが、半導体ウエハ
状態において、メッキ法、蒸着法、あるいはスクリーン
印刷法などによって形成される。DESCRIPTION OF THE PREFERRED EMBODIMENTS Before describing the embodiments of the present invention, the present invention will be described.
A comparative example in which a configuration common to the example is partially provided will be described. < Comparative Example > FIG. 1 is an external perspective view of a semiconductor element used in a comparative example , and FIG. 2 is a cross-sectional view showing a mounted state. As shown in FIG.
The semiconductor element 10 has a plurality of metal bumps 11 formed on the periphery of the surface. As the metal bump 11,
A metal material such as solder or gold is used. The method for forming the metal bumps 11 is not particularly limited, but is formed by a plating method, a vapor deposition method, a screen printing method, or the like in a semiconductor wafer state.
【００１２】各金属バンプ１１の間に、本発明における
畝状突起に相当するダム１２が形成されている。ダム１
２は、例えばポリイミド樹脂などのように耐熱性があ
り、比較的誘電率の低い樹脂で形成されており、その高
さは金属バンプ１１よりも若干（５μｍ程度）低くなっ
ている。ダム１２は、半導体ウエハ状態において感光性
のポリイミド樹脂をスピンコートし、これを露光・現像
することにより形成される。Between each metal bump 11, a dam 12 corresponding to a ridge-shaped projection in the present invention is formed. Dam 1
2 is made of a resin having heat resistance such as a polyimide resin and having a relatively low dielectric constant, and its height is slightly (about 5 μm) lower than that of the metal bump 11. The dam 12 is formed by spin-coating a photosensitive polyimide resin in a semiconductor wafer state, and exposing and developing this.
【００１３】上述した半導体素子１０を、図２に示すよ
うに、表面を下側にして実装基板１上に搭載し、加熱下
で押圧することにより、各金属バンプ１１と基板１のリ
ードパッド２とを接続する。半導体素子１０をフィイス
ダウンボンディングした後、エポキシ樹脂などの低粘度
の樹脂１３を滴下し、これを熱硬化することによって半
導体素子１０を封止する。図２では、半導体素子１０の
周辺部のみを樹脂１３で覆っているが、半導体素子１０
の全体を覆ってもよい。樹脂１３の粘度は、５０００〜
５００００ｃＰが好ましい。粘度が低すぎると、滴下さ
れた樹脂が基板表面に拡がり、半導体素子１０を覆う樹
脂量が少なくなるので、封止効果および補強効果が小さ
くなる。また、粘度が高くなると、上述したように基板
１との密着性が低下し十分な信頼性が得られない。As shown in FIG. 2, the above-described semiconductor element 10 is mounted on a mounting substrate 1 with its surface facing downward, and is pressed under heating, so that each metal bump 11 and the lead pad 2 of the substrate 1 are pressed. And connect. After the semiconductor element 10 is subjected to face-down bonding, a low-viscosity resin 13 such as an epoxy resin is dropped, and the semiconductor element 10 is sealed by thermosetting the resin. In FIG. 2, only the peripheral portion of the semiconductor element 10 is covered with the resin 13.
May be entirely covered. The viscosity of the resin 13 is 5,000 to
50,000 cP is preferred. If the viscosity is too low, the dropped resin spreads on the substrate surface, and the amount of resin covering the semiconductor element 10 decreases, so that the sealing effect and the reinforcing effect decrease. When the viscosity is high, the adhesion to the substrate 1 is reduced as described above, and sufficient reliability cannot be obtained.
【００１４】上記のような低粘度の樹脂１３が滴下され
たとき、金属バンプ１１間のダム１２によって、前記樹
脂１３が実装基板１と半導体素子１０との間へ流れ込む
のが阻止され、両者間に空間が形成されるので、半導体
装置の動作周波数が低下するということはない。なお、
ダム１２は実装基板１の表面に必ずしも密着させる必要
はなく、実装基板１との間に数μｍ程度の間隙があって
も、樹脂１３の粘性によって内部への樹脂の流入を防止
することができる。When the low-viscosity resin 13 is dropped, the resin 13 is prevented from flowing between the mounting substrate 1 and the semiconductor element 10 by the dam 12 between the metal bumps 11. Since the space is formed in the semiconductor device, the operating frequency of the semiconductor device does not decrease. In addition,
The dam 12 does not necessarily have to be in close contact with the surface of the mounting substrate 1. Even if there is a gap of about several μm between the dam 12 and the mounting substrate 1, the resin 13 can prevent the resin from flowing into the inside due to the viscosity of the resin 13. .
【００１５】以下に、本発明の一実施例を説明する。図
３は本実施例に用いられる半導体素子の外観斜視図、図
４は実装状態を示す断面図である。図３に示すように、
本実施例の半導体素子２０は、金属バンプ２１の内側に
リング状のダム２２を備えている。ダム２２は、本実施
例では、金属バンプ２１と同じ金属材料で形成してい
る。そうすることにより、半導体ウエハ状態において、
メッキ法、蒸着法、あるいはスクリーン印刷法などによ
って、ダム２２と金属バンプ２１とを同時に形成するこ
とができるので、比較例よりも工程数を削減することが
できる。 An embodiment of the present invention will be described below. FIG. 3 is an external perspective view of a semiconductor element used in this embodiment, and FIG. 4 is a cross-sectional view showing a mounted state. As shown in FIG.
The semiconductor element 20 of this embodiment includes a ring-shaped dam 22 inside a metal bump 21. In this embodiment , the dam 22 is formed of the same metal material as the metal bump 21. By doing so, in the semiconductor wafer state,
Since the dam 22 and the metal bump 21 can be simultaneously formed by a plating method, a vapor deposition method, a screen printing method, or the like, the number of steps can be reduced as compared with the comparative example .
【００１６】図４に示すように、本実施例によっても、
比較例と同様に、低粘度の封止樹脂１３が実装基板１と
半導体素子２０との間へ流れ込むのを有効に防止するこ
とができる。As shown in FIG. 4, according to this embodiment,
Similarly to the comparative example , it is possible to effectively prevent the low-viscosity sealing resin 13 from flowing between the mounting substrate 1 and the semiconductor element 20.
【００１７】なお、リング状のダム２２は、樹脂が流入
することにより動作周波数の低下をきたすような半導体
素子の主要回路部分を取り囲めば十分であり、必ずしも
半導体素子２０の全回路領域を取り囲む必要性はない。
逆に、主要回路部分のみを取り囲むようにすれば、それ
だけ樹脂１３で封止される領域が増えるので、半導体素
子２０の信頼性を向上することができる。It is sufficient that the ring-shaped dam 22 surrounds the main circuit portion of the semiconductor element whose operating frequency is reduced by the inflow of the resin, and necessarily surrounds the entire circuit area of the semiconductor element 20. There is no need.
Conversely, if only the main circuit portion is surrounded, the area sealed with the resin 13 increases accordingly, so that the reliability of the semiconductor element 20 can be improved.
【００１８】また、本実施例では、金属バンプ２１の内
側にリング状のダム２２を配設したが、金属バンプ２１
の外側にリング状のダム２２を配設しても同様の効果を
得ることができる。In this embodiment, the ring-shaped dam 22 is provided inside the metal bump 21.
The same effect can be obtained even if the ring-shaped dam 22 is provided outside of the above.
【００１９】[0019]
【発明の効果】以上の説明から明らかなように、本発明
によれば、半導体素子が低粘度の樹脂で封止されるの
で、前記封止樹脂と実装基板との密着性が高まり、信頼
性を向上することができる。しかも、半導体素子の表面
に形成された畝状突起（ダム）によって、低粘度の封止
樹脂が実装基板と半導体素子との間に流れ込むのを防止
できるので、半導体装置の電気的特性が劣化することも
ない。しかも、畝状突起は、半導体素子の金属バンプと
同じ材料で形成されているので、畝状突起と金属パンプ
とを同時に作成することが可能であり、畝状突起を作成
する工程数を削減することができる。 As is apparent from the above description, according to the present invention, since the semiconductor element is sealed with a low-viscosity resin, the adhesion between the sealing resin and the mounting substrate is increased, and the reliability is improved. Can be improved. In addition, the ridge-shaped protrusions (dams) formed on the surface of the semiconductor element can prevent the low-viscosity sealing resin from flowing between the mounting substrate and the semiconductor element, thereby deteriorating the electrical characteristics of the semiconductor device. Not even. Moreover, the ridge-shaped protrusions are in contact with the metal bumps of the semiconductor element.
Since they are made of the same material, ridges and metal pumps
Can be created at the same time, creating ridge-shaped projections
The number of steps to be performed can be reduced.
【図１】比較例で使用される半導体素子の外観斜視図で
ある。FIG. 1 is an external perspective view of a semiconductor element used in a comparative example .
【図２】比較例に係る半導体装置の断面図である。FIG. 2 is a cross-sectional view of a semiconductor device according to a comparative example .
【図３】本発明の一実施例で使用される半導体素子の外
観斜視図である。FIG. 3 is an external perspective view of a semiconductor device used in one embodiment of the present invention .
【図４】本発明の一実施例に係る半導体装置の断面図で
ある。FIG. 4 is a sectional view of a semiconductor device according to one embodiment of the present invention .
【図５】従来の半導体装置の断面図である。FIG. 5 is a sectional view of a conventional semiconductor device.
【図６】樹脂コートの有無による周波数−電力利得特性
を比較した特性図である。FIG. 6 is a characteristic diagram comparing frequency-power gain characteristics with and without a resin coat.
１…実装基板 ２…リードパッド １０，２０…半導体素子 １１，２１…金属バンプ １２，２２…ダム（畝状突起） １３…低粘度封止樹脂 DESCRIPTION OF SYMBOLS 1 ... Mounting board 2: Lead pad 10, 20 ... Semiconductor element 11, 21 ... Metal bump 12, 22 ... Dam (ridge-shaped protrusion) 13 ... Low-viscosity sealing resin
Claims (1)
上に実装され、前記表面に形成された金属バンプと前記
基板上に形成されたリードパッドとが電気的に接続され
る半導体装置において、 前記半導体素子は低粘度の樹脂で封止されており、か
つ、前記半導体素子は前記封止樹脂の内部への流れ込み
を防止する、前記金属バンプと同じ材料で形成された畝
状突起（ダム）を備えていることを特徴とする半導体装
置。1. A semiconductor device wherein a semiconductor element is mounted on a substrate with its surface facing down, and a metal bump formed on the surface is electrically connected to a lead pad formed on the substrate. The semiconductor element is sealed with a low-viscosity resin, and the semiconductor element is prevented from flowing into the sealing resin by a ridge-shaped protrusion (dam ) formed of the same material as the metal bump. A) a semiconductor device comprising:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4360574A JP2758115B2 (en) | 1992-12-28 | 1992-12-28 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4360574A JP2758115B2 (en) | 1992-12-28 | 1992-12-28 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH06204291A JPH06204291A (en) | 1994-07-22 |
| JP2758115B2 true JP2758115B2 (en) | 1998-05-28 |
Family
ID=18469997
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4360574A Expired - Fee Related JP2758115B2 (en) | 1992-12-28 | 1992-12-28 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2758115B2 (en) |
Families Citing this family (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3538526B2 (en) * | 1997-07-03 | 2004-06-14 | 三菱電機株式会社 | Semiconductor integrated circuit device |
| JP4179038B2 (en) | 2002-06-03 | 2008-11-12 | 株式会社村田製作所 | Surface acoustic wave device |
| WO2005038911A1 (en) * | 2003-10-15 | 2005-04-28 | Koninklijke Philips Electronics N.V. | Device, system and electric element |
| JP5556808B2 (en) * | 2009-03-24 | 2014-07-23 | 日本電気株式会社 | Electronic device, substrate, and method of manufacturing electronic device |
| JP5577734B2 (en) * | 2010-02-17 | 2014-08-27 | 日本電気株式会社 | Electronic device and method for manufacturing electronic device |
| JP5620698B2 (en) * | 2010-03-29 | 2014-11-05 | 株式会社テラプローブ | Semiconductor structure and manufacturing method of semiconductor structure |
| JP2011210808A (en) * | 2010-03-29 | 2011-10-20 | Casio Computer Co Ltd | Semiconductor structure and semiconductor device |
| JP6422296B2 (en) * | 2014-10-09 | 2018-11-14 | 新日本無線株式会社 | Electronic component and manufacturing method thereof |
| JP7410381B2 (en) * | 2019-12-18 | 2024-01-10 | 日亜化学工業株式会社 | Light emitting element and light emitting device |
| CN115579300B (en) * | 2022-11-24 | 2023-03-28 | 河北北芯半导体科技有限公司 | Flip chip packaging and stacking method |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3207222B2 (en) * | 1991-08-29 | 2001-09-10 | 株式会社東芝 | Electronic component equipment |
-
1992
- 1992-12-28 JP JP4360574A patent/JP2758115B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH06204291A (en) | 1994-07-22 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR940008327B1 (en) | Semiconductor package and mounting method thereof | |
| US6124636A (en) | MMIC package | |
| US5869886A (en) | Flip chip semiconductor mounting structure with electrically conductive resin | |
| JP2571024B2 (en) | Multi-chip module | |
| US6467139B1 (en) | Mounting structure and mounting method for surface acoustic wave element | |
| JP2002368157A (en) | Monolithic microwave integrated circuit package | |
| JP2758115B2 (en) | Semiconductor device | |
| JP2830351B2 (en) | Semiconductor device connection method | |
| US6323552B1 (en) | Semiconductor device having bumps | |
| JPH06204293A (en) | Semiconductor device | |
| JP2771086B2 (en) | Semiconductor device and manufacturing method thereof | |
| US6291893B1 (en) | Power semiconductor device for “flip-chip” connections | |
| JPH06120296A (en) | Semiconductor integrated circuit device | |
| JP2646989B2 (en) | Chip carrier | |
| JP3078773B2 (en) | Electronic component and method of manufacturing the same | |
| JPH09232366A (en) | Mounting equipment of semiconductor chip and its mounting method | |
| JP3019065B2 (en) | Semiconductor device connection method | |
| JPH09260441A (en) | Semiconductor device | |
| KR100503277B1 (en) | Method for manufacturing flip-chip package | |
| JPH04217335A (en) | Semiconductor element and fabrication thereof | |
| JP2003124402A (en) | Semiconductor package and method for producing it | |
| KR20000003000A (en) | Ball grid array(bga) package having insulated dummy solder ball | |
| JP3514149B2 (en) | Projection electrode formation method | |
| JPH1197584A (en) | Semiconductor device | |
| JP2748776B2 (en) | LSI package |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |