JP2771086B2 - Semiconductor device and manufacturing method thereof - Google Patents
Semiconductor device and manufacturing method thereofInfo
- Publication number
- JP2771086B2 JP2771086B2 JP4360575A JP36057592A JP2771086B2 JP 2771086 B2 JP2771086 B2 JP 2771086B2 JP 4360575 A JP4360575 A JP 4360575A JP 36057592 A JP36057592 A JP 36057592A JP 2771086 B2 JP2771086 B2 JP 2771086B2
- Authority
- JP
- Japan
- Prior art keywords
- resin
- substrate
- semiconductor device
- semiconductor element
- viscosity
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/83909—Post-treatment of the layer connector or bonding area
- H01L2224/83951—Forming additional members, e.g. for reinforcing, fillet sealant
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Wire Bonding (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Description
【０００１】[0001]
【産業上の利用分野】本発明は、主として高速動作用の
半導体装置や、マイクロ波を発振、増幅する半導体装置
に係り、特に、半導体素子がフリップチップ方式で基板
上に組み込まれた半導体装置およびその製造方法に関す
る。BACKGROUND OF THE INVENTION The present invention is primarily and semiconductor device for high-speed operation, generating microwaves, relates to a semiconductor device to amplify, in particular, a semiconductor device and a semiconductor device is incorporated on the substrate by a flip chip method The manufacturing method is described .
【０００２】[0002]
【従来の技術】従来、半導体素子を基板上に実装する方
式として、ワイヤーボンディング方式とフリップチップ
方式とがある。ワイヤーボンディング方式は、確立され
た適用容易な実装方式ではあるが、上記のような動作周
波数の高い半導体装置に適用すると、半導体素子の電極
と基板とを電気接続する金属細線がインダクタンス成分
をもつので、インピーダンスマッチング不良による入出
力反射率の増加や、信号の減衰を引き起こすという難点
がある。2. Description of the Related Art Conventionally, as a method of mounting a semiconductor element on a substrate, there are a wire bonding method and a flip chip method. The wire bonding method is an established easy-to-apply mounting method.However, when applied to a semiconductor device having a high operating frequency as described above, a thin metal wire for electrically connecting an electrode of a semiconductor element and a substrate has an inductance component. However, there is a problem in that the input / output reflectivity increases due to poor impedance matching and signal attenuation occurs.
【０００３】そこで、上記のような動作周波数の高い半
導体装置の実装方式としては、フリップチップ方式が適
している。以下、図５を参照して、フリップチップ方式
で実装された半導体装置の構成を説明する。Therefore, a flip-chip method is suitable as a method for mounting a semiconductor device having a high operating frequency as described above. Hereinafter, the configuration of the semiconductor device mounted by the flip-chip method will be described with reference to FIG.
【０００４】図中、符号１は実装基板であり、その表面
にリードパッド２が形成されている。符号３は半導体素
子で、その表面（図では下面）に、電極としての金属バ
ンプ４が形成されている。上記のような半導体素子３を
フェイスダウンボンディング（表面を下にして行うボン
ディング）することにより、各金属バンプ４が所定のリ
ードパッド２に一括接続される。半導体素子３のボンデ
ィング後、金属バンプ４への応力集中を避けるととも
に、半導体素子３の耐湿性を確保するために、半導体素
子３を樹脂５で封止している。In FIG. 1, reference numeral 1 denotes a mounting substrate, on which lead pads 2 are formed. Reference numeral 3 denotes a semiconductor element, and a metal bump 4 as an electrode is formed on a surface (a lower surface in the figure) of the semiconductor element. By performing the face-down bonding (bonding performed with the surface down) of the semiconductor element 3 as described above, each metal bump 4 is collectively connected to a predetermined lead pad 2. After the bonding of the semiconductor element 3, the semiconductor element 3 is sealed with a resin 5 in order to avoid stress concentration on the metal bumps 4 and secure the moisture resistance of the semiconductor element 3.
【０００５】[0005]
【発明が解決しようとする課題】しかしながら、上述し
たフリップチップ方式の実装方式によれば、封止用の樹
脂５が半導体素子３と実装基板１との間に流れ込むの
で、半導体素子３の信号線路間の寄生容量が増加し、例
えば図６に示すように、高周波数域で電力利得が低下す
るなどといった電気特性の劣化を招くという問題があ
る。However, according to the flip-chip type mounting method described above, the sealing resin 5 flows between the semiconductor element 3 and the mounting substrate 1, so that the signal line of the semiconductor element 3 is formed. There is a problem in that the parasitic capacitance between them increases, for example, as shown in FIG. 6, the electrical characteristics deteriorate, such as a decrease in power gain in a high frequency range.
【０００６】このような問題点を解決するために、フェ
イスダウンボンディングされた半導体素子を高粘度の樹
脂で封止することにより、半導体素子と基板間に樹脂が
流れ込むのを防止した半導体装置が提案されている（特
開平４−２１７３３５号公報）。In order to solve such a problem, a semiconductor device in which resin is prevented from flowing between a semiconductor element and a substrate by sealing a semiconductor element which has been face-down bonded with a high-viscosity resin has been proposed. (JP-A-4-217335).
【０００７】しかしながら、高粘度の樹脂を使って封止
すると、基板表面と樹脂との密着性が低くなるので、十
分な耐湿性を得ることができず、また、温度サイクルを
加えると、基板表面と樹脂との界面が剥離するおそれも
ある。However, if sealing is performed using a high-viscosity resin, the adhesion between the substrate surface and the resin is reduced, so that sufficient moisture resistance cannot be obtained. There is also a risk that the interface between the resin and the resin may peel off.
【０００８】本発明は、このような事情に鑑みてなされ
たものであって、半導体装置の電気的特性を劣化させる
ことなく、しかも高い信頼性を得ることができる半導体
装置およびその製造方法を提供することを目的としてい
る。The present invention has been made in view of such circumstances, and provides a semiconductor device capable of obtaining high reliability without deteriorating the electrical characteristics of the semiconductor device and a method of manufacturing the same. It is intended to be.
【０００９】[0009]
【課題を解決するための手段】本発明は、このような目
的を達成するために、次のような構成をとる。すなわ
ち、請求項１に記載の発明は、半導体素子がその表面を
下側にして基板上に実装され、前記表面に形成された金
属バンプと前記基板上に形成されたリードパッドとが電
気的に接続される半導体装置において、前記半導体素子
と基板との間隙が、半導体素子の周縁よりも外側で、か
つ半導体素子の周囲を巡るように配置された高粘度の樹
脂によって閉塞され、さらに、前記高粘度の樹脂が低粘
度の樹脂で覆われることにより、全体として前記半導体
素子が、重なり合った２層構造の高粘度の樹脂と低粘度
の樹脂によって封止されていることを特徴とする。 ま
た、請求項２に記載の発明は、半導体素子がその表面を
下側にして基板上に実装され、前記表面に形成された金
属バンプと前記基板上に形成されたリードパッドとが電
気的に接続される半導体装置の製造方法において、 半導
体素子の表面を下側にして基板上に搭載し、半導体素子
の表面に形成された金属バンプと基板上に形成されたリ
ードパッドとを電気的に接続するフェイスダウンボンデ
ィング工程と、 基板上にフェイスダウンボンディングさ
れた半導体素子の周縁よりも外側で、かつ半導体素子の
周囲を巡るように高粘度の樹脂を供給して、半導体素子
と基板との間隙を閉塞する第１の封止工程と、 前記第１
の封止工程で形成された高粘度の樹脂の上から低粘度の
樹脂を供給して、前記高粘度の樹脂を低粘度の樹脂で覆
う第２の封止工程と を備えたことを特徴とする。 The present invention has the following configuration in order to achieve the above object. That is, according to the first aspect of the present invention, a semiconductor element is mounted on a substrate with its surface facing down, and a metal bump formed on the surface and a lead pad formed on the substrate are electrically connected. In the semiconductor device to be connected, the semiconductor element
The gap between the substrate and the substrate is outside the periphery of the semiconductor element.
High-viscosity tree arranged around one semiconductor element
Oil, and the high-viscosity resin has a low viscosity.
The entirety of the semiconductor is covered by the resin
The element is a two-layered high-viscosity resin with a low viscosity
Characterized by being sealed by a resin. Ma
According to the second aspect of the present invention, the semiconductor element is provided on the surface thereof.
Gold mounted on the substrate with the lower side mounted on the substrate
Metal bumps and the lead pads formed on the substrate
In a method for manufacturing a pneumatically connected semiconductor device,
The semiconductor device is mounted on a substrate with the surface of the
Metal bumps formed on the surface of the
Face-down bond electrically connecting to the pad
Face-down bonding on the substrate
Outside the periphery of the semiconductor device and
Supplying high-viscosity resin to go around the semiconductor device
A first sealing step of closing the gap between the substrate and the first
From the high-viscosity resin formed in the encapsulation process
Supply resin and cover the high viscosity resin with low viscosity resin.
And a second sealing step .
【００１０】[0010]
【作用】本発明の作用は次のとおりである。すなわち、
請求項１に記載の発明によれば、半導体素子と基板との
間隙が、半導体素子の周縁よりも外側で、かつ半導体素
子の周囲を巡るように配置された高粘度の樹脂によって
閉塞され、さらに、前記高粘度の樹脂が低粘度の樹脂で
覆われることにより、全体として前記半導体素子が、重
なり合った２層構造の高粘度の樹脂と低粘度の樹脂によ
って封止されているので、低粘度の樹脂が半導体素子と
基板との間に流れ込むのが防止される。また、高粘度の
樹脂は、流動性が低いので、半導体素子と基板間に流入
することはない。請求項２に記載の発明によれば、フェ
イスダウンボンディング工程の後に、半導体素子の周囲
に高粘度の樹脂を供給し、その後、高粘度樹脂を覆うよ
うに低粘度の樹脂を供給することにより、請求項１に記
載の半導体装置を実現できる。 The operation of the present invention is as follows. That is,
According to the invention described in claim 1, the semiconductor device and the substrate
The gap is outside the periphery of the semiconductor element and the semiconductor element
With a high-viscosity resin placed around the child
Closed, and the high-viscosity resin is a low-viscosity resin.
By being covered, the semiconductor element as a whole
Two layers of high-viscosity resin and low-viscosity resin
Thus, low-viscosity resin is prevented from flowing between the semiconductor element and the substrate. Further, since the high-viscosity resin has low fluidity, it does not flow between the semiconductor element and the substrate. According to the second aspect of the present invention,
After the is down bonding process, around the semiconductor device
Supply the high-viscosity resin and then cover the high-viscosity resin.
By supplying a low-viscosity resin as described above,
The semiconductor device described above can be realized.
【００１１】[0011]
【実施例】以下、図面を参照して本発明の一実施例を説
明する。 ＜第１実施例＞図１は第１実施例に係る半導体装置の断
面図、図２は製造方法を示す図である。半導体素子１０
は、その表面（図では下面）の周辺部に複数個の金属バ
ンプ１１が形成されている。金属バンプ１１としては、
ハンダあるいは金などの金属材料が用いられる。金属バ
ンプ１１の形成手法は特に限定しないが、半導体ウエハ
状態において、メッキ法、蒸着法、あるいはスクリーン
印刷法などによって形成される。An embodiment of the present invention will be described below with reference to the drawings. <First Embodiment> FIG. 1 is a sectional view of a semiconductor device according to a first embodiment, and FIG. 2 is a view showing a manufacturing method. Semiconductor element 10
Has a plurality of metal bumps 11 formed on the periphery of the surface (the lower surface in the figure). As the metal bump 11,
A metal material such as solder or gold is used. The method for forming the metal bumps 11 is not particularly limited, but is formed by a plating method, a vapor deposition method, a screen printing method, or the like in a semiconductor wafer state.
【００１２】上述した半導体素子１０を、その表面を下
側にして実装基板１上に搭載し、加熱下で押圧すること
により、各金属バンプ１１と基板１のリードパッド２と
を接続する。半導体素子１０をフィイスダウンボンディ
ングした後、図２（ａ）に示すように、半導体素子１０
の周縁よりも外側で、かつ半導体素子１０の周囲を巡る
ように例えば５００００〜５０００００ｃＰ程度の高粘
度の樹脂（例えば、エポキシ樹脂）１２を定量吐出機２
０で滴下して、これを熱硬化することによって、半導体
素子１０の周辺部と実装基板１との間隙を閉塞する。続
いて、図２（ｂ）に示すように、例えば５０００〜５０
０００ｃＰ程度の低粘度の樹脂（例えば、エポキシ樹
脂）１３を定量吐出機２１で滴下して、半導体素子１０
および高粘度樹脂１２を覆う。上述のように、実装基板
１と半導体素子１０との間隙は、上記高粘度の樹脂１２
で閉塞されているので、滴下された低粘度樹脂１３が実
装基板１と半導体素子１０との間に流れ込むのが阻止さ
れる。低粘度樹脂１３を滴下した後、この樹脂１３を熱
硬化する。The above-described semiconductor element 10 is mounted on the mounting substrate 1 with its surface facing downward, and pressed under heating to connect each metal bump 11 to the lead pad 2 of the substrate 1. After the semiconductor element 10 is subjected to the face-down bonding, as shown in FIG.
Around the periphery of the semiconductor element 10 outside the periphery of
As example of the high viscosity of about 50000~500000cP resin (e.g., epoxy resin) 12 dispensing machine 2
The gap between the peripheral portion of the semiconductor element 10 and the mounting board 1 is closed by dropping at 0 and thermally curing the drop. Subsequently, as shown in FIG.
A low-viscosity resin (for example, epoxy resin) 13 having a viscosity of about 000 cP is dropped by a constant-rate dispenser 21 so that
And the high viscosity resin 12. As described above, the gap between the mounting substrate 1 and the semiconductor element 10 is
Thus, the dropped low-viscosity resin 13 is prevented from flowing between the mounting substrate 1 and the semiconductor element 10. After the low-viscosity resin 13 is dropped, the resin 13 is thermally cured.
【００１３】以上のように、本実施例によれば、低粘度
の樹脂１３で半導体素子１０を封止しているので、樹脂
１３と実装基板１との密着性が高く、半導体装置の信頼
性を確保することができる。しかも、樹脂１３が実装基
板１と半導体素子１０との間に流れ込むこともないの
で、半導体装置の電気的特性を劣化させることがない。As described above, according to the present embodiment, since the semiconductor element 10 is sealed with the low-viscosity resin 13, the adhesion between the resin 13 and the mounting substrate 1 is high, and the reliability of the semiconductor device is improved. Can be secured. In addition, since the resin 13 does not flow between the mounting substrate 1 and the semiconductor element 10, the electrical characteristics of the semiconductor device do not deteriorate.
【００１４】＜第２実施例＞ 図３は第２実施例に係る半導体装置の製造方法を示して
いる。本実施例では、図３（ａ）に示すように、予め棒
状あるいはリング状に成形された未硬化の高粘度樹脂１
２を、フェイスダウンボンディングされた半導体素子１
０の周縁よりも外側で、かつ半導体素子１０の周囲を巡
るように配置する。続いて、加熱処理を施すと、樹脂１
２が軟化することにより実装基板１と半導体素子１０と
の間隙が閉塞され、この状態で樹脂１２は熱硬化する。
樹脂１２は高粘度樹脂であるので、実装基板１と半導体
素子１０の間隙に流れ込むことはない。そして、図３
（ｃ）に示すように、低粘度の樹脂１３を滴下して、こ
れを熱硬化する。本実施例によっても、第１実施例と同
様の効果を得ることができる。<Second Embodiment> FIG. 3 shows a method of manufacturing a semiconductor device according to a second embodiment. In this embodiment, as shown in FIG. 3A, an uncured high-viscosity resin 1 previously formed into a rod shape or a ring shape.
2 is a face-down bonded semiconductor element 1
0 and around the semiconductor element 10.
So that Subsequently, when heat treatment is performed, the resin 1
2 is softened, the gap between the mounting substrate 1 and the semiconductor element 10 is closed, and the resin 12 is thermally cured in this state.
Since the resin 12 is a high-viscosity resin, it does not flow into the gap between the mounting board 1 and the semiconductor element 10. And FIG.
As shown in (c), a low-viscosity resin 13 is dropped and thermally cured. According to this embodiment, the same effect as that of the first embodiment can be obtained.
【００１５】なお、本実施例では、未硬化の高粘度樹脂
を棒状あるいはリング状に成形したが、これに替えて、
棒状あるいはリング状の基材（セラミックなど）に未硬
化の高粘度樹脂を被着したものを用いてもよい。In the present embodiment, the uncured high-viscosity resin is molded into a rod or ring shape.
A rod-shaped or ring-shaped substrate (ceramic or the like) coated with an uncured high-viscosity resin may be used.
【００１６】＜第３実施例＞ 図４は第３実施例に係る半導体装置の製造方法を示して
いる。本実施例では、図４（ａ）に示すように、半導体
素子１０よりも大きい板状に成形さた未硬化の高粘度樹
脂１２を、フェイスダウンボンディングされた半導体素
子１０の上に載置する。続いて、加熱処理を施すと、図
４（ｂ）に示すように、樹脂１２が軟化することによ
り、樹脂１２が半導体素子１０の周縁よりも外側で、か
つ半導体素子１０の周囲を巡るように垂れ下がって、実
装基板１と半導体素子１０との間隙が閉塞され、この状
態で樹脂１２は熱硬化する。樹脂１２は高粘度樹脂であ
るので、実装基板１と半導体素子１０の間隙に流れ込む
ことはない。そして、図４（ｃ）に示すように、低粘度
の樹脂１３を滴下して、これを熱硬化する。本実施例に
よっても、第１および第２実施例と同様の効果を得るこ
とができる。<Third Embodiment> FIG. 4 shows a method of manufacturing a semiconductor device according to a third embodiment. In this embodiment, as shown in FIG. 4A, an uncured high-viscosity resin 12 formed into a plate shape larger than the semiconductor element 10 is placed on the face-down bonded semiconductor element 10. . Subsequently, when heat treatment is performed, as shown in FIG. 4B, the resin 12 is softened, so that the resin 12 is located outside the periphery of the semiconductor element 10.
In this state, the gap between the mounting substrate 1 and the semiconductor element 10 is closed, and the resin 12 is thermally cured in this state. Since the resin 12 is a high-viscosity resin, it does not flow into the gap between the mounting board 1 and the semiconductor element 10. Then, as shown in FIG. 4C, a low-viscosity resin 13 is dropped and thermally cured. According to this embodiment, the same effects as those of the first and second embodiments can be obtained.
【００１７】なお、本実施例では、未硬化の高粘度樹脂
を板状に成形したもの用いたが、これに替えて、未硬化
の高粘度樹脂を布などに含浸させたものを用いてもよ
い。In this embodiment, an uncured high-viscosity resin molded into a plate is used. Alternatively, a cloth impregnated with an uncured high-viscosity resin may be used. Good.
【００１８】[0018]
【発明の効果】以上の説明から明らかなように、請求項
１に記載の発明によれば、半導体素子が低粘度の樹脂で
封止されるので、前記封止樹脂と実装基板との密着性が
高まり、信頼性を向上することができる。しかも、半導
体素子と基板との間隙が、半導体素子の周縁よりも外側
で、かつ半導体素子の周囲を巡るように配置された高粘
度の樹脂によって閉塞されているので、低粘度の封止樹
脂が実装基板と半導体素子との間に流れ込むことがない
ので、半導体装置の電気的特性が劣化することはない。
また、請求項２に記載の発明によれば、フェイスダウン
ボンディング工程の後に、半導体素子の周囲に高粘度の
樹脂を供給し、その後、高粘度樹脂を覆うように低粘度
の樹脂を供給しているので、請求項１に記載の半導体装
置を容易に実現することができる。 As is apparent from the above description, the claims
According to the first aspect of the invention , since the semiconductor element is sealed with the low-viscosity resin, the adhesion between the sealing resin and the mounting substrate is increased, and the reliability can be improved. Moreover, semi-conductive
The gap between the body element and the substrate is outside the periphery of the semiconductor element
And high viscosity arranged around the semiconductor element
Since the low-viscosity sealing resin does not flow between the mounting substrate and the semiconductor element, the electrical characteristics of the semiconductor device do not deteriorate.
According to the second aspect of the present invention, the face down
After the bonding process, a highly viscous
Supply the resin and then lower the viscosity to cover the higher viscosity resin
2. The semiconductor device according to claim 1, wherein
Can be easily realized.
【図１】本発明に係る半導体装置の第１実施例の断面図
である。FIG. 1 is a sectional view of a first embodiment of a semiconductor device according to the present invention.
【図２】第１実施例に係る半導体装置の製造方法を示す
図である。FIG. 2 is a diagram illustrating a method of manufacturing the semiconductor device according to the first embodiment.
【図３】第２実施例に係る半導体装置の製造方法を示す
図である。FIG. 3 is a view illustrating a method for manufacturing a semiconductor device according to a second embodiment.
【図４】第３実施例に係る半導体装置の製造方法を示す
図である。FIG. 4 is a view illustrating a method for manufacturing a semiconductor device according to a third embodiment.
【図５】従来の半導体装置の断面図である。FIG. 5 is a sectional view of a conventional semiconductor device.
【図６】樹脂コートの有無による周波数−電力利得特性
を比較した特性図である。FIG. 6 is a characteristic diagram comparing frequency-power gain characteristics with and without a resin coat.
１…実装基板 ２…リードパッド １０…半導体素子 １１…金属バンプ １２…高粘度樹脂 １３…低粘度樹脂 DESCRIPTION OF SYMBOLS 1 ... Mounting board 2 ... Lead pad 10 ... Semiconductor element 11 ... Metal bump 12 ... High viscosity resin 13 ... Low viscosity resin
───────────────────────────────────────────────────── フロントページの続き (58)調査した分野(Int.Cl.6，ＤＢ名) H01L 21/60 311 H01L 21/56 H01L 23/29 H01L 23/31──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. 6 , DB name) H01L 21/60 311 H01L 21/56 H01L 23/29 H01L 23/31
Claims (2)
上に実装され、前記表面に形成された金属バンプと前記
基板上に形成されたリードパッドとが電気的に接続され
る半導体装置において、前記半導体素子と基板との間隙が、半導体素子の周縁よ
りも外側で、かつ半導体素子の周囲を巡るように配置さ
れた高粘度の樹脂によって閉塞され、さらに、前記高粘
度の樹脂が低粘度の樹脂で覆われることにより、全体と
して前記半導体素子が、重なり合った２層構造の高粘度
の樹脂と低粘度の樹脂によって封止されている ことを特
徴とする半導体装置。1. A semiconductor device wherein a semiconductor element is mounted on a substrate with its surface facing down, and a metal bump formed on the surface is electrically connected to a lead pad formed on the substrate. The gap between the semiconductor element and the substrate is closer to the periphery of the semiconductor element.
Outside the device and around the semiconductor device.
Blocked by the high-viscosity resin,
Is covered with low-viscosity resin,
And the semiconductor element has a high viscosity of an overlapping two-layer structure.
A semiconductor device sealed with a resin having a low viscosity and a resin having a low viscosity .
上に実装され、前記表面に形成された金属バンプと前記Mounted on the metal bumps formed on the surface and the
基板上に形成されたリードパッドとが電気的に接続されThe lead pads formed on the substrate are electrically connected
る半導体装置の製造方法において、In the method for manufacturing a semiconductor device, 半導体素子の表面を下側にして基板上に搭載し、半導体The semiconductor device is mounted on a substrate with the surface of the
素子の表面に形成された金属バンプと基板上に形成されMetal bump formed on the surface of the device and formed on the substrate
たリードパッドとを電気的に接続するフェイスダウンボFace down button to electrically connect the
ンディング工程と、Binding process, 基板上にフェイスダウンボンディングされた半導体素子Semiconductor device face-down bonded on substrate
の周縁よりも外側で、かつ半導体素子の周囲を巡るようAround the periphery of the semiconductor element outside the periphery of
に高粘度の樹脂を供給して、半導体素子と基板との間隙High-viscosity resin to the gap between the semiconductor element and the substrate.
を閉塞する第１の封止工程と、A first sealing step of closing 前記第１の封止工程で形成された高粘度の樹脂の上からFrom above the high-viscosity resin formed in the first sealing step
低粘度の樹脂を供給して、前記高粘度の樹脂を低粘度のSupplying a low-viscosity resin and converting the high-viscosity resin to a low-viscosity resin
樹脂で覆う第２の封止工程とA second sealing step of covering with resin を備えたことを特徴とするCharacterized by having
半導体装置の製造方法。A method for manufacturing a semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4360575A JP2771086B2 (en) | 1992-12-28 | 1992-12-28 | Semiconductor device and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4360575A JP2771086B2 (en) | 1992-12-28 | 1992-12-28 | Semiconductor device and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH06204292A JPH06204292A (en) | 1994-07-22 |
| JP2771086B2 true JP2771086B2 (en) | 1998-07-02 |
Family
ID=18470002
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4360575A Expired - Fee Related JP2771086B2 (en) | 1992-12-28 | 1992-12-28 | Semiconductor device and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2771086B2 (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5515391A (en) * | 1994-03-07 | 1996-05-07 | Sdl, Inc. | Thermally balanced diode laser package |
| WO2003005436A1 (en) * | 2001-07-03 | 2003-01-16 | Fujitsu Limited | Coating material of semiconductor chip for controlling magnetic disc drive and method of coating semiconductor chip for controlling magnetic disc drive |
| JP5040804B2 (en) * | 2008-05-16 | 2012-10-03 | 日本電気株式会社 | Semiconductor device manufacturing method and semiconductor element inspection structure |
| WO2012124539A1 (en) * | 2011-03-11 | 2012-09-20 | 株式会社村田製作所 | Electronic component, and method for producing same |
| JP5658088B2 (en) * | 2011-05-23 | 2015-01-21 | パナソニックＩｐマネジメント株式会社 | Semiconductor package component mounting structure and manufacturing method |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6313337A (en) * | 1986-07-04 | 1988-01-20 | Fuji Electric Co Ltd | Process of mounting semiconductor element |
-
1992
- 1992-12-28 JP JP4360575A patent/JP2771086B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH06204292A (en) | 1994-07-22 |
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