JPH08213425A - Semiconductor device and manufacture thereof - Google Patents

Semiconductor device and manufacture thereof

Info

Publication number
JPH08213425A
JPH08213425A JP7016831A JP1683195A JPH08213425A JP H08213425 A JPH08213425 A JP H08213425A JP 7016831 A JP7016831 A JP 7016831A JP 1683195 A JP1683195 A JP 1683195A JP H08213425 A JPH08213425 A JP H08213425A
Authority
JP
Japan
Prior art keywords
circuit board
electrode
semiconductor element
bump
wiring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP7016831A
Other languages
Japanese (ja)
Other versions
JP3243956B2 (en
Inventor
Hisashi Nakaoka
久 中岡
Tsugio Murayama
次雄 村山
Yoshihiko Motoi
義彦 元井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electronics Corp filed Critical Matsushita Electronics Corp
Priority to JP01683195A priority Critical patent/JP3243956B2/en
Publication of JPH08213425A publication Critical patent/JPH08213425A/en
Application granted granted Critical
Publication of JP3243956B2 publication Critical patent/JP3243956B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • H01L2224/113Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1133Manufacturing methods by local deposition of the material of the bump connector in solid form
    • H01L2224/1134Stud bumping, i.e. using a wire-bonding apparatus
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119Arrangement of the bump connectors prior to mounting
    • H01L2224/81191Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119Arrangement of the bump connectors prior to mounting
    • H01L2224/81193Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body

Landscapes

  • Wire Bonding (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

PURPOSE: To provide a mounting structure in which a semiconductor element is directly connected to a circuit board wiring by bump. CONSTITUTION: The semiconductor device comprises a semiconductor chip 1 provided with a first bump 8 on its electrode pad 2, a wiring circuit board 5 provided at a second bump 9 connected to the bump 8 on the chip 1 on a board wiring 6, and sealing resin 7 filled in the gap between the chip 1 and the board 5, wherein the bumps 8, 9 are connected in contact between the chip 1 and the board 5 at a high bump 10. According to the structure, adhesive is eliminated, the chip 1 can be connected to the board, and the connecting structure of the element 1 to the board 6 corresponding to a thermal stress can be realized.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、半導体チップと配線回
路基板とのバンプ(突起電極)接続構造の半導体装置お
よびその製造方法に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a bump (projection electrode) connection structure between a semiconductor chip and a printed circuit board, and a method for manufacturing the same.

【0002】[0002]

【従来の技術】近年、半導体素子の高密度実装傾向が著
しく、プリント配線板上に半導体素子を直接接合するC
OB(Chip On Board)法が多用されるようになってき
ている。また、MPU・ロジック用素子では接続端子数
が超多ピン化の傾向にあり、200ピンを超える超多ピ
ン半導体素子では、従来一般的に使用されていたQFP
等のパッケージに組み立てた場合、実装が容易なアウタ
ーリードピッチ0.65mm以上では外形寸法が非常に
大型化し、またアウターリードピッチ0.5mm以下で
は実装が非常に困難となるため、COB技術の応用とし
て半導体素子を中間基板上に接合してグリッド状のアウ
ターリードで基板に実装するCSP(ChipSize Packag
e)等のパッケージが提案されている。これらの工程で
は、従来のワイヤボンディング法による接続に加えてバ
ンプにより基板に直接に実装するフリップチップ工法が
採用される場合があり、本発明は新しいフリップチップ
工法の提案に関するものである。
2. Description of the Related Art In recent years, the tendency of high density mounting of semiconductor elements is remarkable, and C for directly bonding semiconductor elements onto a printed wiring board is used.
The OB (Chip On Board) method has been widely used. In addition, the number of connection terminals in MPU / logic devices tends to increase, and QFP, which has been commonly used in the past, is used in ultra-high pin semiconductor devices with more than 200 pins.
If the outer lead pitch is 0.65 mm or more, which is easy to mount when assembled into a package, etc., the external dimensions will be extremely large, and if the outer lead pitch is 0.5 mm or less, mounting will be very difficult. As a semiconductor device, CSP (ChipSize Packag) is used to bond the semiconductor element on the intermediate board and mount it on the board with grid-shaped outer leads.
e) and other packages have been proposed. In these steps, in addition to the conventional connection by the wire bonding method, a flip chip method in which the bumps are directly mounted on the substrate may be adopted, and the present invention relates to the proposal of a new flip chip method.

【0003】従来のバンプ接続による半導体装置の実装
構造の例を図5を参照しながら説明する。図5におい
て、従来の実装構造は、半導体チップ1の電極パッド2
上に形成された金・はんだ等のバンプ3を介して、導電
性接着剤4により配線回路基板5上の基板配線6に接合
されているものである。そして半導体チップ1と配線回
路基板5との間隙および周囲に封止樹脂7を塗布し、実
装構造として完成するものであった。
An example of a conventional mounting structure of a semiconductor device by bump connection will be described with reference to FIG. In FIG. 5, the conventional mounting structure is the electrode pad 2 of the semiconductor chip 1.
It is joined to the board wiring 6 on the printed circuit board 5 by the conductive adhesive 4 through the bumps 3 made of gold, solder or the like formed above. Then, the sealing resin 7 is applied to the gap between the semiconductor chip 1 and the printed circuit board 5 and the periphery thereof to complete the mounting structure.

【0004】[0004]

【発明が解決しようとする課題】しかしながら上述の従
来の構成では、バンプと基板配線との接合に導電性接着
剤を用いており、これをすべてのバンプ頭頂部に均等に
塗布する工程が必要であり、スキージ等を用いて接着剤
を薄い膜状にして転写する方法による場合など、接着剤
が硬化しやすくなるため、連続生産を行うために常時接
着剤膜を除去して再び形成する手法等によりオープンタ
イムを長くする必要があった。また同様の理由により接
着剤の特性が変動しやすく、接着強度がばらつくという
信頼性上の課題もあった。
However, in the above-mentioned conventional structure, the conductive adhesive is used for bonding the bump and the substrate wiring, and the step of applying the conductive adhesive evenly to all the tops of the bumps is required. Yes, in the case of using a method such as a squeegee to transfer the adhesive in a thin film, the adhesive is likely to harden, so a method to constantly remove the adhesive film and re-form it for continuous production, etc. Therefore, it was necessary to lengthen the open time. Further, due to the same reason, there is a problem in reliability that the characteristics of the adhesive are likely to change and the adhesive strength varies.

【0005】[0005]

【課題を解決するための手段】上述の課題を解決するた
めに、本発明の半導体装置は、半導体チップの電極パッ
ド上と配線回路基板の基板配線上の両方とにバンプ(突
起電極)を形成し、これらのバンプを互いに当接・圧接
・熱圧着・融接させる実装構造である。すなわち、第1
の突起電極がその電極パッド上に設けられた半導体素子
と、この半導体素子上の第1の突起電極に接合した第2
の突起電極がその基板配線上に設けられた配線回路基板
と、半導体素子と配線回路基板との間隙を充填した封止
樹脂とよりなる半導体装置であって、半導体素子と配線
回路基板との間には第1の突起電極と第2の突起電極と
が互いに当接して接合して高背バンプが設けられている
ことを特徴とする。また第1の2段突起電極がその電極
パッド上に設けられた半導体素子と、半導体素子上の第
1の2段突起電極に接合した第2の2段突起電極がその
基板配線上に設けられた配線回路基板と、半導体素子と
配線回路基板との間隙を充填した封止樹脂とよりなる半
導体装置であって、半導体素子と配線回路基板との間に
は第1の2段突起電極と第2の2段突起電極とが互いに
当接して接合して中央部が括れた略鼓形状の高背バンプ
が設けられていることを特徴とする。
In order to solve the above problems, the semiconductor device of the present invention has bumps (protruding electrodes) formed on both the electrode pads of the semiconductor chip and the substrate wiring of the printed circuit board. In this mounting structure, these bumps are brought into contact, pressure contact, thermocompression bonding, and fusion contact with each other. That is, the first
Of the semiconductor element having the protruding electrode of the second electrode provided on the electrode pad, and the second protruding electrode connected to the first protruding electrode on the semiconductor element.
Is a semiconductor device including a printed circuit board having protruding electrodes provided on the board wiring and a sealing resin filling a gap between the semiconductor element and the printed circuit board. Is characterized in that the first bump electrode and the second bump electrode are in contact with each other and joined to each other to form a high-height bump. In addition, a semiconductor element having a first two-step protruding electrode provided on its electrode pad and a second two-step protruding electrode joined to the first two-step protruding electrode on the semiconductor element are provided on the substrate wiring. A wiring circuit board, and a sealing resin that fills a gap between the semiconductor element and the wiring circuit board, wherein a first two-step protruding electrode and a first step electrode are provided between the semiconductor element and the wiring circuit board. It is characterized in that a substantially drum-shaped high-back bump whose central portion is constricted is provided by abutting and joining the two two-stage protruding electrodes.

【0006】製造方法においては、半導体素子上の電極
パッドに第1の突起電極を形成する工程と、配線回路基
板上の基板配線上であって、半導体素子上に形成された
第1の突起電極に対向する位置に第2の突起電極を形成
する工程と、半導体素子上の第1の突起電極と配線回路
基板上の第2の突起電極とを互いに接合する工程と、半
導体素子と配線回路基板との間隙に封止樹脂を流し込
み、充填する工程とを有することを特徴とする。また半
導体素子上の電極パッドに第1の金突起電極を形成する
工程と、配線回路基板上の基板配線上であって、半導体
素子上に形成された第1の突起電極に対向する位置に第
2の金突起電極を形成する工程と、半導体素子および配
線回路基板の温度を低く保ったままで加圧し、半導体素
子上の第1の金突起電極と配線回路基板上の第2の金突
起電極とを圧接接合し、半導体素子と配線回路基板との
間を接続する高背突起電極を形成する工程と、半導体素
子と配線回路基板との間隙に封止樹脂を流し込み、充填
する工程とを有することを特徴とする。さらに、半導体
素子上の電極パッドに第1の2段金突起電極を形成する
工程と、配線回路基板上の基板配線上であって、半導体
素子上に形成された第1の2段金突起電極に対向する位
置に第2の2段金突起電極を形成する工程と、半導体素
子および配線回路基板の温度を低く保ったままで加圧
し、半導体素子上の第1の2段金突起電極と配線回路基
板上の第2の2段金突起電極とを圧接接合し、半導体素
子と配線回路基板との間を接続する中央部が括れた略鼓
状形状の高背突起電極を形成する工程と、半導体素子と
配線回路基板との間隙に封止樹脂を流し込み、充填する
工程とを有することを特徴とする。
In the manufacturing method, the step of forming the first protruding electrode on the electrode pad on the semiconductor element, and the first protruding electrode formed on the semiconductor element on the substrate wiring on the printed circuit board. Forming a second projecting electrode at a position facing each other, joining the first projecting electrode on the semiconductor element to the second projecting electrode on the printed circuit board, and the semiconductor element and the printed circuit board. And a step of pouring a sealing resin into the gap between the and. In addition, a step of forming the first gold protruding electrode on the electrode pad on the semiconductor element, and a step of forming a first gold protruding electrode on the substrate wiring on the printed circuit board at a position facing the first protruding electrode formed on the semiconductor element. The step of forming the second gold bump electrode on the semiconductor element and the second gold bump electrode on the wiring circuit board is performed by applying pressure while keeping the temperature of the semiconductor element and the wiring circuit board low. And a step of forming a high back protrusion electrode for connecting between the semiconductor element and the printed circuit board by pressure welding, and a step of pouring and filling a sealing resin into a gap between the semiconductor element and the printed circuit board. Is characterized by. Further, a step of forming a first two-step gold bump electrode on an electrode pad on the semiconductor element, and a first two-step gold bump electrode formed on the semiconductor element on the substrate wiring on the printed circuit board. Forming a second two-step gold bump electrode on the semiconductor element and pressing the wire while keeping the temperature of the semiconductor element and the printed circuit board low. A step of pressure-bonding a second two-step gold bump electrode on the substrate to form a high-back bump electrode having a substantially drum shape with a constricted central portion connecting the semiconductor element and the printed circuit board; And a step of pouring and filling a sealing resin into a gap between the element and the printed circuit board.

【0007】[0007]

【作用】上述の構成により接合のための導電性接着剤が
不要となるので、従来の接着剤均等塗布機構が不要とな
り、設備を簡略化することができる。また導電性接着剤
の管理も不要になり、量産工場での配慮が少なくても安
定した生産が可能である。この場合、両方のバンプを塑
性変形機能に優れた金(Au)で形成することにより、
接合温度を低く保った状態で圧接接合することが可能に
なる。さらに、この金バンプを金ワイヤのボールボンデ
ィング法を応用した方法で2段形状に形成し、それぞれ
を接合させることにより、温度変動時の接合部への応力
発生を緩和するのに有利な鼓状に近い形状の接続部を得
ることができ、接合部分の信頼性を向上させることがで
きる。
With the above construction, the conductive adhesive for joining is not required, so that the conventional uniform adhesive coating mechanism is not required and the facility can be simplified. In addition, there is no need to manage the conductive adhesive, and stable production is possible even if there is little consideration at the mass production plant. In this case, by forming both bumps with gold (Au) having an excellent plastic deformation function,
It is possible to perform pressure welding while keeping the joining temperature low. Furthermore, the gold bumps are formed into a two-step shape by a method applying a ball bonding method of gold wires, and by bonding each of them, an hourglass shape that is advantageous for alleviating the stress generation at the bonding portion when the temperature changes. It is possible to obtain a connection portion having a shape close to that of, and improve the reliability of the joint portion.

【0008】[0008]

【実施例】本発明の一実施例について図面を参照しなが
ら説明する。本実施例においては、プロセス的に構造、
製造方法について説明する。
DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described with reference to the drawings. In the present embodiment, the process-like structure,
The manufacturing method will be described.

【0009】図1,図2は本発明の第1の実施例を示す
断面図である。図1に示すように、半導体チップ1の電
極パッド2上に第1バンプ8が形成され、また配線回路
基板5上の基板配線6上に第2バンプ9が形成されてい
る。これら第1バンプ8,第2バンプ9の材質は、金、
銅、半田、またはアルミニウム等であり、第1バンプ8
と第2バンプ9との材質は同じであっても、あるいは互
いに異なっていてもよい。さらに第1バンプ8,第2バ
ンプ9上に適宜メッキを施し、共晶形成による接合性の
向上を図ることもできる。第1バンプ8や第2バンプ9
の形成方法としては、バンプの組成によりメッキ法や、
ワイヤーボンディング時に用いるボールボンダーによ
り、金属細線を使用したボールボンディング法により形
成する。
1 and 2 are sectional views showing a first embodiment of the present invention. As shown in FIG. 1, the first bump 8 is formed on the electrode pad 2 of the semiconductor chip 1, and the second bump 9 is formed on the substrate wiring 6 on the printed circuit board 5. The material of the first bump 8 and the second bump 9 is gold,
First bump 8 made of copper, solder, aluminum, or the like
The second bump 9 and the second bump 9 may be made of the same material or different materials. Further, the first bump 8 and the second bump 9 may be appropriately plated to improve the bondability by forming a eutectic crystal. First bump 8 and second bump 9
As a method of forming the
It is formed by a ball bonding method using a fine metal wire with a ball bonder used at the time of wire bonding.

【0010】次に、図2に示すように、配線回路基板5
を適当なステージ上に載せ、半導体チップ1をツールに
より真空吸着し、半導体チップ1上の第1バンプ8と配
線回路基板5上の第2バンプ9とをそれぞれ当接させて
電気的導通を得る。これによって、半導体チップ1と配
線回路基板5との間には、第1バンプ8と第2バンプ9
とによりハイバンプ10が形成される。この後、半導体
チップ1と配線回路基板5との間隙および周囲に封止樹
脂7を塗布して実装構造を完成する。
Next, as shown in FIG. 2, the printed circuit board 5
Is placed on an appropriate stage, the semiconductor chip 1 is vacuum-sucked by a tool, and the first bumps 8 on the semiconductor chip 1 and the second bumps 9 on the printed circuit board 5 are brought into contact with each other to obtain electrical conduction. . As a result, the first bump 8 and the second bump 9 are provided between the semiconductor chip 1 and the printed circuit board 5.
Thus, the high bump 10 is formed. After that, the sealing resin 7 is applied to the gap between the semiconductor chip 1 and the printed circuit board 5 and the periphery thereof to complete the mounting structure.

【0011】図2に示す本実施例の実装構造は、第1の
バンプ8がその電極パッド2上に設けられた半導体チッ
プ1と、半導体チップ1上の第1のバンプ8に接合した
第2のバンプ9がその基板配線6上に設けられた配線回
路基板5と、半導体チップ1と配線回路基板5との間隙
を充填した封止樹脂7とよりなるもので、半導体チップ
1と配線回路基板5との間には第1のバンプ8と第2の
バンプ9とが互いに当接して接合してハイバンプ10が
設けられているものである。
In the mounting structure of this embodiment shown in FIG. 2, the semiconductor chip 1 having the first bumps 8 provided on the electrode pads 2 thereof and the second bumps 8 bonded to the first bumps 8 on the semiconductor chip 1 are provided. The bump 9 of the wiring circuit board 5 provided on the substrate wiring 6 and the sealing resin 7 filling the gap between the semiconductor chip 1 and the wiring circuit board 5. The first bump 8 and the second bump 9 are in contact with each other and bonded to each other, and a high bump 10 is provided therebetween.

【0012】なお、第1バンプ8と第2バンプ9を塑性
変形機能に優れた金同士として、配線回路基板5、半導
体チップ1の温度を低く保ったままで、押圧ツールによ
り加圧することにより、容易に第1バンプ8と第2バン
プ9とを圧接構造とすることができる。また、この際押
圧ツールを加熱すれば熱圧着構造とすることができ、第
1バンプ8、第2バンプ9を半田等の低融点金属、また
は金と錫等の共晶形成組成の金属を選ぶことで、溶融接
構造の接合部(ハイバンプ)を得ることもできる。
It should be noted that the first bump 8 and the second bump 9 are made of gold having excellent plastic deformation function, and are easily pressed by pressing with a pressing tool while keeping the temperature of the wiring circuit board 5 and the semiconductor chip 1 low. In addition, the first bump 8 and the second bump 9 can have a pressure contact structure. Further, at this time, the pressing tool can be heated to form a thermocompression bonding structure, and the first bumps 8 and the second bumps 9 are selected from low melting point metals such as solder or metals having a eutectic formation composition such as gold and tin. By doing so, it is also possible to obtain a bonded portion (high bump) having a fused contact structure.

【0013】本実施例においては、半導体チップ1上の
第1バンプ8と配線回路基板5上の第2バンプ9とによ
り接合しているので、導電性接着剤等の接着剤手段を用
いずとも半導体チップを基板に直接実装できる。また半
導体チップ1と配線回路基板5との間には、第1バンプ
8と第2バンプ9とによりハイバンプ10が形成され、
間隙がバンプ1つの場合に比べて大きいので、封止樹脂
7を半導体チップ1と配線回路基板5との間隙に充填す
る際、粘度の高い封止樹脂7を用いても、間隙に気泡等
の発生を抑えて充分に充填することができる。
In this embodiment, since the first bumps 8 on the semiconductor chip 1 and the second bumps 9 on the printed circuit board 5 are joined together, it is possible to use an adhesive means such as a conductive adhesive. The semiconductor chip can be directly mounted on the substrate. A high bump 10 is formed between the semiconductor chip 1 and the printed circuit board 5 by the first bump 8 and the second bump 9.
Since the gap is larger than that in the case of one bump, when filling the gap between the semiconductor chip 1 and the printed circuit board 5 with the sealing resin 7, even if the sealing resin 7 having a high viscosity is used, bubbles or the like are generated in the gap. Generation can be suppressed and sufficient filling can be performed.

【0014】次に図3,図4は本発明の第2の実施例を
示す断面図である。図3に示すように、半導体チップ1
の電極パッド2上および配線回路基板5の基板配線6上
にそれぞれ第1の2段バンプ11および第2の2段バン
プ12が形成されているが、第1の2段バンプ11およ
び第2の2段バンプ12は、ボールボンダーにより金属
細線を使用してボールボンディング法で形成したため、
2段形状の高背型バンプとなっている。
Next, FIGS. 3 and 4 are sectional views showing a second embodiment of the present invention. As shown in FIG. 3, the semiconductor chip 1
The first two-stage bump 11 and the second two-stage bump 12 are formed on the electrode pad 2 and the substrate wiring 6 of the printed circuit board 5, respectively. Since the two-step bump 12 is formed by the ball bonding method using a fine metal wire with a ball bonder,
It is a two-stage high-profile bump.

【0015】次に、図4に示すように、配線回路基板5
を適当なステージ上に載せ、半導体チップ1をツールに
より真空吸着し、半導体チップ1上の第1の2段バンプ
11と配線回路基板5上の第2の2段バンプ12とをそ
れぞれ当接させて電気的導通を得る。これによって、半
導体チップ1と配線回路基板5との間には、第1の2段
バンプ11と第2の2段バンプ12とによりハイバンプ
13が形成される。この後、半導体チップ1と配線回路
基板5との間隙および周囲に封止樹脂7を塗布して実装
構造を完成する。
Next, as shown in FIG. 4, the printed circuit board 5
On a suitable stage, the semiconductor chip 1 is vacuum-sucked by a tool, and the first two-stage bump 11 on the semiconductor chip 1 and the second two-stage bump 12 on the printed circuit board 5 are brought into contact with each other. To obtain electrical continuity. As a result, a high bump 13 is formed between the semiconductor chip 1 and the printed circuit board 5 by the first two-stage bump 11 and the second two-stage bump 12. After that, the sealing resin 7 is applied to the gap between the semiconductor chip 1 and the printed circuit board 5 and the periphery thereof to complete the mounting structure.

【0016】図4に示す本実施例の実装構造は、第1の
2段バンプ11がその電極パッド2上に設けられた半導
体チップ1と、半導体チップ1上の第1の2段バンプ1
1に接合した第2の2段バンプ12がその基板配線6上
に設けられた配線回路基板5と、半導体チップ1と配線
回路基板5との間隙を充填した封止樹脂7とよりなるも
のであり、半導体チップ1と配線回路基板5との間には
第1の2段バンプ11と第2の2段バンプ12とが互い
に当接して接合して中央部が括れた略鼓形状のハイバン
プ13が設けられているものである。
In the mounting structure of this embodiment shown in FIG. 4, the semiconductor chip 1 in which the first two-stage bumps 11 are provided on the electrode pads 2 thereof, and the first two-stage bumps 1 on the semiconductor chip 1 are provided.
The second two-stage bump 12 bonded to the wiring board 1 is composed of the wiring circuit board 5 provided on the board wiring 6, and the sealing resin 7 filling the gap between the semiconductor chip 1 and the wiring circuit board 5. There is a substantially drum-shaped high bump 13 in which the first two-stage bump 11 and the second two-stage bump 12 are in contact with each other and bonded to each other between the semiconductor chip 1 and the printed circuit board 5 and the central portion is constricted. Is provided.

【0017】なお、第1の2段バンプ11と第2の2段
バンプ12を第1の実施例と同様に、塑性変形機能に優
れた金同士として、配線回路基板5、半導体チップ1の
温度を低く保ったままで、押圧ツールにより加圧するこ
とにより、容易に第1の2段バンプ11と第2の2段バ
ンプ12とを圧接構造とすることができる。また、この
際押圧ツールを加熱すれば熱圧着構造とすることがで
き、第1の2段バンプ11、第2の2段バンプ12を半
田等の低融点金属、または金と錫等の共晶形成組成の金
属を選ぶことで、溶融接構造の接合部を得ることもでき
る。
As in the case of the first embodiment, the first two-stage bump 11 and the second two-stage bump 12 are formed of gold having excellent plastic deformation functions, and the temperature of the printed circuit board 5 and the semiconductor chip 1 is controlled. By keeping pressure at a low value and applying pressure with a pressing tool, the first two-stage bump 11 and the second two-stage bump 12 can be easily brought into a pressure contact structure. Further, at this time, the pressing tool can be heated to form a thermocompression bonding structure, and the first two-stage bump 11 and the second two-stage bump 12 are formed of a low melting point metal such as solder, or a eutectic such as gold and tin. By selecting a metal having a forming composition, it is possible to obtain a joint having a fusion-welded structure.

【0018】本実施例においては、半導体チップ1上の
第1の2段バンプ11と配線回路基板5上の第2の2段
バンプ12とにより接合しているので、導電性接着剤等
の接着剤手段を用いずとも半導体チップを基板に直接実
装できる。また半導体チップ1と配線回路基板5との間
には、第1の2段バンプ11と第2の2段バンプ12と
によりハイバンプ13が形成され、間隙がバンプ1つの
場合に比べて大きいので、封止樹脂7を半導体チップ1
と配線回路基板5との間隙に充填する際、粘度の高い封
止樹脂7を用いても、間隙に気泡等の発生を抑えて充分
に充填することができる。
In the present embodiment, since the first two-stage bumps 11 on the semiconductor chip 1 and the second two-stage bumps 12 on the printed circuit board 5 are joined together, a conductive adhesive or the like is adhered. The semiconductor chip can be directly mounted on the substrate without using a chemical means. Further, a high bump 13 is formed between the semiconductor chip 1 and the printed circuit board 5 by the first two-stage bump 11 and the second two-stage bump 12, and the gap is larger than that in the case of one bump. The sealing resin 7 is used as the semiconductor chip 1
When the gap between the wiring circuit board 5 and the printed circuit board 5 is filled, even if the sealing resin 7 having a high viscosity is used, the gap can be filled sufficiently while suppressing the generation of bubbles and the like.

【0019】また第1の2段バンプ11と第2の2段バ
ンプ12とにより形成されたハイバンプ13の形状は、
中央部が括れた鼓状に近い形状となり、半導体チップ1
と回路基板5との材料の違いによる熱膨張率の差を吸収
するのに有利な形状となっている。したがって、ハイバ
ンプ13により、半導体チップと配線回路基板との接合
部分の信頼性を向上させることができる。
The shape of the high bump 13 formed by the first two-stage bump 11 and the second two-stage bump 12 is as follows.
The semiconductor chip 1 has a drum-like shape with the central portion constricted.
The shape is advantageous for absorbing the difference in the coefficient of thermal expansion due to the difference in the materials of the circuit board 5 and the circuit board 5. Therefore, the high bumps 13 can improve the reliability of the joint portion between the semiconductor chip and the printed circuit board.

【0020】以上、本発明の一実施例について述べた
が、たとえば第1バンプ8、第2バンプ9、第1の2段
バンプ11、第2の2段バンプ12の材質を金とした場
合に、ツールに超音波を印加して接合性を向上させ、低
温下で融接的構造として強固な接合部を得ることもでき
る。さらに、第2の実施例で2段形状の高背型バンプを
形成する手段として、ボールボンディング法のかわりに
レジストフィルムを複数回使用するメッキ工法によって
形成してもよい。
The embodiment of the present invention has been described above. For example, when the material of the first bump 8, the second bump 9, the first two-stage bump 11 and the second two-stage bump 12 is gold. It is also possible to apply ultrasonic waves to the tool to improve the bondability and obtain a strong bonded portion as a fusion-bonded structure at low temperatures. Further, instead of the ball bonding method, a plating method may be used in which the resist film is used a plurality of times as a means for forming the two-tiered high-height bump in the second embodiment.

【0021】[0021]

【発明の効果】以上のように本発明の半導体装置は、半
導体チップ、配線回路基板の双方に形成したバンプ同士
を接合することにより、半導体チップの直接接合構造を
得ることができ、生産性・信頼性の高いフリップチップ
工法を実現するものである。
As described above, in the semiconductor device of the present invention, the bumps formed on both the semiconductor chip and the printed circuit board can be joined to each other to obtain a direct joining structure of the semiconductor chips. It realizes a highly reliable flip chip method.

【0022】また製造方法においては、半導体チップ、
配線回路基板の双方に形成したバンプ同士を低温で単に
圧接して接合することができるため、容易に半導体チッ
プを配線回路基板に接合することができる。
In the manufacturing method, the semiconductor chip,
Since the bumps formed on both of the wiring circuit boards can be simply joined by pressure contact at a low temperature, the semiconductor chip can be easily joined to the wiring circuit board.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の半導体装置における第1の実施例の断
面図
FIG. 1 is a cross-sectional view of a first embodiment of a semiconductor device of the present invention.

【図2】本発明の半導体装置における第1の実施例の断
面図
FIG. 2 is a sectional view of a semiconductor device according to a first embodiment of the present invention.

【図3】本発明の半導体装置における第2の実施例の断
面図
FIG. 3 is a sectional view of a second embodiment of the semiconductor device of the present invention.

【図4】本発明の半導体装置における第2の実施例の断
面図
FIG. 4 is a sectional view of a second embodiment of the semiconductor device of the present invention.

【図5】従来の半導体装置の断面図FIG. 5 is a sectional view of a conventional semiconductor device.

【符号の説明】[Explanation of symbols]

1 半導体チップ 2 電極パッド 3 バンプ 4 導電性接着剤 5 配線回路基板 6 基板配線 7 封止樹脂 8 第1バンプ 9 第2バンプ 10 ハイバンプ 11 第1の2段バンプ 12 第2の2段バンプ 13 ハイバンプ 1 Semiconductor Chip 2 Electrode Pad 3 Bump 4 Conductive Adhesive 5 Wiring Circuit Board 6 Board Wiring 7 Sealing Resin 8 First Bump 9 Second Bump 10 High Bump 11 First 2nd Step Bump 12 Second 2nd Step Bump 13 High Bump

Claims (7)

【特許請求の範囲】[Claims] 【請求項1】 第1の突起電極がその電極パッド上に設
けられた半導体素子と、前記半導体素子上の第1の突起
電極に接合した第2の突起電極がその基板配線上に設け
られた配線回路基板と、前記半導体素子と前記配線回路
基板との間隙を充填した封止樹脂とよりなる半導体装置
であって、前記半導体素子と配線回路基板との間には前
記第1の突起電極と前記第2の突起電極とが互いに当接
して接合して高背バンプが設けられていることを特徴と
する半導体装置。
1. A semiconductor element having a first projecting electrode provided on its electrode pad, and a second projecting electrode bonded to the first projecting electrode on the semiconductor element is provided on its substrate wiring. A semiconductor device comprising: a wiring circuit board; and a sealing resin filling a gap between the semiconductor element and the wiring circuit board, wherein the first protruding electrode is provided between the semiconductor element and the wiring circuit board. A semiconductor device, wherein high bumps are provided by being brought into contact with and joined to the second protruding electrodes.
【請求項2】 半導体素子上および配線回路基板上に設
けられた第1の突起電極および第2の突起電極の材質が
共に金であることを特徴とする請求項1記載の半導体装
置。
2. The semiconductor device according to claim 1, wherein the material of the first protruding electrode and the second protruding electrode provided on the semiconductor element and the printed circuit board is gold.
【請求項3】 第1の2段突起電極がその電極パッド上
に設けられた半導体素子と、前記半導体素子上の第1の
2段突起電極に接合した第2の2段突起電極がその基板
配線上に設けられた配線回路基板と、前記半導体素子と
前記配線回路基板との間隙を充填した封止樹脂とよりな
る半導体装置であって、前記半導体素子と配線回路基板
との間には前記第1の2段突起電極と前記第2の2段突
起電極とが互いに当接して接合して中央部が括れた略鼓
形状の高背バンプが設けられていることを特徴とする半
導体装置。
3. A semiconductor element having a first two-step protruding electrode provided on an electrode pad thereof, and a second two-step protruding electrode bonded to the first two-step protruding electrode on the semiconductor element of the substrate. A semiconductor device comprising: a wiring circuit board provided on wiring; and a sealing resin filling a gap between the semiconductor element and the wiring circuit board, wherein the semiconductor element and the wiring circuit board are provided with A semiconductor device, wherein the first two-step protruding electrode and the second two-step protruding electrode are in contact with each other to be joined to each other, and a substantially drum-shaped high-back bump having a central portion constricted is provided.
【請求項4】 半導体素子上および配線回路基板上に設
けられた第1の2段突起電極および第2の2段突起電極
の材質が共に金であることを特徴とする請求項3記載の
半導体装置。
4. The semiconductor according to claim 3, wherein the materials of the first two-step protruding electrode and the second two-step protruding electrode provided on the semiconductor element and the printed circuit board are both gold. apparatus.
【請求項5】 半導体素子上の電極パッドに第1の突起
電極を形成する工程と、配線回路基板上の基板配線上で
あって、前記半導体素子上に形成された第1の突起電極
に対向する位置に第2の突起電極を形成する工程と、前
記半導体素子上の第1の突起電極と前記配線回路基板上
の第2の突起電極とを互いに接合する工程と、前記半導
体素子と配線回路基板との間隙に封止樹脂を流し込み、
充填する工程とを有することを特徴とする半導体装置の
製造方法。
5. A step of forming a first projecting electrode on an electrode pad on a semiconductor element, and a substrate wiring on a printed circuit board, facing the first projecting electrode formed on the semiconductor element. Forming a second projecting electrode at a desired position, joining the first projecting electrode on the semiconductor element and the second projecting electrode on the printed circuit board, and the semiconductor element and the wiring circuit. Pour the sealing resin into the gap between the board and
And a step of filling the semiconductor device.
【請求項6】 半導体素子上の電極パッドに第1の金突
起電極を形成する工程と、配線回路基板上の基板配線上
であって、前記半導体素子上に形成された第1の突起電
極に対向する位置に第2の金突起電極を形成する工程
と、前記半導体素子および前記配線回路基板の温度を低
く保ったままで加圧し、前記半導体素子上の第1の金突
起電極と前記配線回路基板上の第2の金突起電極とを圧
接接合し、半導体素子と配線回路基板との間を接続する
高背突起電極を形成する工程と、前記半導体素子と配線
回路基板との間隙に封止樹脂を流し込み、充填する工程
とを有することを特徴とする半導体装置の製造方法。
6. A step of forming a first gold protruding electrode on an electrode pad on a semiconductor element, and a step of forming a first gold protruding electrode on a substrate wiring on a printed circuit board, the first protruding electrode being formed on the semiconductor element. A step of forming a second gold bump electrode at a position facing each other, and pressing while keeping the temperature of the semiconductor element and the wiring circuit board low, and the first gold bump electrode on the semiconductor element and the wiring circuit board. A step of pressure-bonding the upper second gold protruding electrode to form a high-back protruding electrode for connecting between the semiconductor element and the wiring circuit board; and a sealing resin in the gap between the semiconductor element and the wiring circuit board. A method of manufacturing a semiconductor device, comprising the steps of pouring and filling.
【請求項7】 半導体素子上の電極パッドに第1の2段
金突起電極を形成する工程と、配線回路基板上の基板配
線上であって、前記半導体素子上に形成された第1の2
段金突起電極に対向する位置に第2の2段金突起電極を
形成する工程と、前記半導体素子および前記配線回路基
板の温度を低く保ったままで加圧し、前記半導体素子上
の第1の2段金突起電極と前記配線回路基板上の第2の
2段金突起電極とを圧接接合し、半導体素子と配線回路
基板との間を接続する中央部が括れた略鼓状形状の高背
突起電極を形成する工程と、前記半導体素子と配線回路
基板との間隙に封止樹脂を流し込み、充填する工程とを
有することを特徴とする半導体装置の製造方法。
7. A step of forming a first two-step gold bump electrode on an electrode pad on a semiconductor element, and a first step formed on the semiconductor element on a substrate wiring on a printed circuit board.
A step of forming a second two-step gold bump electrode at a position facing the step gold bump electrode; and pressing while keeping the temperature of the semiconductor element and the wiring circuit board low, A high back protrusion having a substantially drum shape with a central portion constricted by pressure-bonding the stepped gold protruding electrode and the second second step gold protruding electrode on the wiring circuit board to connect between the semiconductor element and the wiring circuit board. A method of manufacturing a semiconductor device, comprising: a step of forming an electrode; and a step of pouring and filling a sealing resin into a gap between the semiconductor element and the printed circuit board.
JP01683195A 1995-02-03 1995-02-03 Semiconductor device and manufacturing method thereof Expired - Fee Related JP3243956B2 (en)

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JPH08213425A true JPH08213425A (en) 1996-08-20
JP3243956B2 JP3243956B2 (en) 2002-01-07

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