JPH06204292A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH06204292A JPH06204292A JP36057592A JP36057592A JPH06204292A JP H06204292 A JPH06204292 A JP H06204292A JP 36057592 A JP36057592 A JP 36057592A JP 36057592 A JP36057592 A JP 36057592A JP H06204292 A JPH06204292 A JP H06204292A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor element
- resin
- semiconductor device
- viscosity resin
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/83909—Post-treatment of the layer connector or bonding area
- H01L2224/83951—Forming additional members, e.g. for reinforcing, fillet sealant
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Wire Bonding (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、主として高速動作用の
半導体装置や、マイクロ波を発振、増幅する半導体装置
に係り、特に、半導体素子がフリップチップ方式で基板
上に組み込まれた半導体装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device for high speed operation and a semiconductor device for oscillating and amplifying microwaves, and more particularly to a semiconductor device in which semiconductor elements are incorporated on a substrate by a flip chip method. .
【０００２】[0002]
【従来の技術】従来、半導体素子を基板上に実装する方
式として、ワイヤーボンディング方式とフリップチップ
方式とがある。ワイヤーボンディング方式は、確立され
た適用容易な実装方式ではあるが、上記のような動作周
波数の高い半導体装置に適用すると、半導体素子の電極
と基板とを電気接続する金属細線がインダクタンス成分
をもつので、インピーダンスマッチング不良による入出
力反射率の増加や、信号の減衰を引き起こすという難点
がある。2. Description of the Related Art Conventionally, as a method for mounting a semiconductor element on a substrate, there are a wire bonding method and a flip chip method. The wire bonding method is an established and easy-to-apply mounting method, but when applied to a semiconductor device having a high operating frequency as described above, the thin metal wire that electrically connects the electrode of the semiconductor element and the substrate has an inductance component. However, there is a problem that input / output reflectance is increased and signal is attenuated due to poor impedance matching.
【０００３】そこで、上記のような動作周波数の高い半
導体装置の実装方式としては、フリップチップ方式が適
している。以下、図５を参照して、フリップチップ方式
で実装された半導体装置の構成を説明する。Therefore, the flip-chip method is suitable as a method of mounting the semiconductor device having a high operating frequency as described above. The configuration of the semiconductor device mounted by the flip chip method will be described below with reference to FIG.
【０００４】図中、符号１は実装基板であり、その表面
にリードパッド２が形成されている。符号３は半導体素
子で、その表面（図では下面）に、電極としての金属バ
ンプ４が形成されている。上記のような半導体素子３を
フェイスダウンボンディング（表面を下にして行うボン
ディング）することにより、各金属バンプ４が所定のリ
ードパッド２に一括接続される。半導体素子３のボンデ
ィング後、金属バンプ４への応力集中を避けるととも
に、半導体素子３の耐湿性を確保するために、半導体素
子３を樹脂５で封止している。In the figure, reference numeral 1 is a mounting substrate, on the surface of which a lead pad 2 is formed. Reference numeral 3 is a semiconductor element, and a metal bump 4 as an electrode is formed on its surface (lower surface in the figure). Each metal bump 4 is collectively connected to a predetermined lead pad 2 by face-down bonding (bonding performed with the surface facing down) of the semiconductor element 3 as described above. After the semiconductor element 3 is bonded, the semiconductor element 3 is sealed with a resin 5 in order to avoid stress concentration on the metal bumps 4 and to secure the moisture resistance of the semiconductor element 3.
【０００５】[0005]
【発明が解決しようとする課題】しかしながら、上述し
たフリップチップ方式の実装方式によれば、封止用の樹
脂５が半導体素子３と実装基板１との間に流れ込むの
で、半導体素子３の信号線路間の寄生容量が増加し、例
えば図６に示すように、高周波数域で電力利得が低下す
るなどといった電気特性の劣化を招くという問題があ
る。However, according to the above-mentioned flip-chip mounting method, the sealing resin 5 flows between the semiconductor element 3 and the mounting substrate 1, and therefore the signal line of the semiconductor element 3 is formed. There is a problem in that the parasitic capacitance between them increases, and as shown in FIG. 6, for example, the electrical characteristics deteriorate such that the power gain decreases in a high frequency range.
【０００６】このような問題点を解決するために、フェ
イスダウンボンディングされた半導体素子を高粘度の樹
脂で封止することにより、半導体素子と基板間に樹脂が
流れ込むのを防止した半導体装置が提案されている（特
開平４−２１７３３５号公報）。In order to solve such a problem, a semiconductor device is proposed in which a semiconductor element bonded by face-down bonding is sealed with a highly viscous resin to prevent the resin from flowing between the semiconductor element and the substrate. (Japanese Patent Laid-Open No. 4-217335).
【０００７】しかしながら、高粘度の樹脂を使って封止
すると、基板表面と樹脂との密着性が低くなるので、十
分な耐湿性を得ることができず、また、温度サイクルを
加えると、基板表面と樹脂との界面が剥離するおそれも
ある。However, if a resin having a high viscosity is used for sealing, the adhesion between the surface of the substrate and the resin becomes low, so that sufficient moisture resistance cannot be obtained, and if a temperature cycle is applied, the surface of the substrate becomes inferior. There is a possibility that the interface between the resin and the resin may peel off.
【０００８】本発明は、このような事情に鑑みてなされ
たものであって、半導体装置の電気的特性を劣化させる
ことなく、しかも高い信頼性を得ることができる半導体
装置を提供することを目的としている。The present invention has been made in view of such circumstances, and an object thereof is to provide a semiconductor device which can obtain high reliability without deteriorating the electrical characteristics of the semiconductor device. I am trying.
【０００９】[0009]
【課題を解決するための手段】本発明は、このような目
的を達成するために、次のような構成をとる。すなわ
ち、本発明は、半導体素子がその表面を下側にして基板
上に実装され、前記表面に形成された金属バンプと前記
基板上に形成されたリードパッドとが電気的に接続され
る半導体装置において、前記半導体素子は、少なくとも
その周辺部が高粘度の樹脂で覆われ、さらに、その上か
ら低粘度の樹脂で封止されたものである。The present invention has the following constitution in order to achieve such an object. That is, the present invention is a semiconductor device in which a semiconductor element is mounted on a substrate with its surface facing down and the metal bumps formed on the surface and the lead pads formed on the substrate are electrically connected. In the above semiconductor device, at least the peripheral portion thereof is covered with a high-viscosity resin, and is further sealed with a low-viscosity resin from above.
【００１０】[0010]
【作用】本発明の作用は次のとおりである。すなわち、
本発明によれは、半導体素子の周辺部が高粘度の樹脂で
覆われているので、その上から低粘度の樹脂を滴下した
場合、前記低粘度の樹脂が半導体素子と基板との間に流
れ込むのが防止される。また、高粘度の樹脂は、流動性
が低いので、半導体素子と基板間に流入することはな
い。The operation of the present invention is as follows. That is,
According to the present invention, since the peripheral portion of the semiconductor element is covered with the high-viscosity resin, when the low-viscosity resin is dropped from above, the low-viscosity resin flows between the semiconductor element and the substrate. Is prevented. Further, since the high-viscosity resin has low fluidity, it does not flow between the semiconductor element and the substrate.
【００１１】[0011]
【実施例】以下、図面を参照して本発明の一実施例を説
明する。 ＜第１実施例＞図１は第１実施例に係る半導体装置の断
面図、図２は製造方法を示す図である。半導体素子１０
は、その表面（図では下面）の周辺部に複数個の金属バ
ンプ１１が形成されている。金属バンプ１１としては、
ハンダあるいは金などの金属材料が用いられる。金属バ
ンプ１１の形成手法は特に限定しないが、半導体ウエハ
状態において、メッキ法、蒸着法、あるいはスクリーン
印刷法などによって形成される。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. <First Embodiment> FIG. 1 is a sectional view of a semiconductor device according to the first embodiment, and FIG. 2 is a view showing a manufacturing method. Semiconductor device 10
A plurality of metal bumps 11 are formed on the peripheral portion of the surface (lower surface in the figure). As the metal bump 11,
A metal material such as solder or gold is used. The method of forming the metal bumps 11 is not particularly limited, but they are formed by a plating method, a vapor deposition method, a screen printing method, or the like in a semiconductor wafer state.
【００１２】上述した半導体素子１０を、その表面を下
側にして実装基板１上に搭載し、加熱下で押圧すること
により、各金属バンプ１１と基板１のリードパッド２と
を接続する。半導体素子１０をフィイスダウンボンディ
ングした後、図２（ａ）に示すように、半導体素子１０
の周囲に例えば５００００〜５０００００ｃＰ程度の高
粘度の樹脂（例えば、エポキシ樹脂）１２を定量吐出機
２０で滴下して、これを熱硬化することによって、半導
体素子１０の周辺部と実装基板１との間隙を閉塞する。
続いて、図２（ｂ）に示すように、例えば５０００〜５
００００ｃＰ程度の低粘度の樹脂（例えば、エポキシ樹
脂）１３を定量吐出機２１で滴下して、半導体素子１０
および高粘度樹脂１２を覆う。上述のように、実装基板
１と半導体素子１０との間隙は、上記高粘度の樹脂１２
で閉塞されているので、滴下された低粘度樹脂１３が実
装基板１と半導体素子１０との間に流れ込むのが阻止さ
れる。低粘度樹脂１３を滴下した後、この樹脂１３を熱
硬化する。The semiconductor element 10 described above is mounted on the mounting substrate 1 with the surface thereof facing down, and is pressed under heating to connect the metal bumps 11 to the lead pads 2 of the substrate 1. After the face-down bonding of the semiconductor element 10, as shown in FIG.
A high-viscosity resin (for example, an epoxy resin) 12 having a viscosity of, for example, about 50,000 to 500,000 cP is dropped by a constant-volume dispenser 20 and heat-cured, so that the peripheral portion of the semiconductor element 10 and the mounting substrate 1 are separated. Close the gap.
Then, as shown in FIG. 2B, for example, 5000 to 5
A low-viscosity resin (for example, epoxy resin) 13 having a viscosity of about 0000 cP is dropped by the constant-volume dispenser 21 to obtain the semiconductor element 10
And covers the high-viscosity resin 12. As described above, the gap between the mounting substrate 1 and the semiconductor element 10 has the high-viscosity resin 12
Since it is blocked by, the dropped low-viscosity resin 13 is prevented from flowing between the mounting substrate 1 and the semiconductor element 10. After dropping the low-viscosity resin 13, the resin 13 is thermally cured.
【００１３】以上のように、本実施例によれば、低粘度
の樹脂１３で半導体素子１０を封止しているので、樹脂
１３と実装基板１との密着性が高く、半導体装置の信頼
性を確保することができる。しかも、樹脂１３が実装基
板１と半導体素子１０との間に流れ込むこともないの
で、半導体装置の電気的特性を劣化させることがない。As described above, according to this embodiment, since the semiconductor element 10 is sealed with the low-viscosity resin 13, the adhesion between the resin 13 and the mounting substrate 1 is high, and the reliability of the semiconductor device is high. Can be secured. Moreover, since the resin 13 does not flow between the mounting substrate 1 and the semiconductor element 10, the electrical characteristics of the semiconductor device are not deteriorated.
【００１４】＜第２実施例＞図３は第２実施例に係る半
導体装置の製造方法を示している。本実施例では、図３
（ａ）に示すように、予め棒状あるいはリング状に成形
された未硬化の高粘度樹脂１２を、フェイスダウンボン
ディングされた半導体素子１０の周囲に配置する。続い
て、加熱処理を施すと、樹脂１２が軟化することにより
実装基板１と半導体素子１０との間隙が閉塞され、この
状態で樹脂１２は熱硬化する。樹脂１２は高粘度樹脂で
あるので、実装基板１と半導体素子１０の間隙に流れ込
むことはない。そして、図３（ｃ）に示すように、低粘
度の樹脂１３を滴下して、これを熱硬化する。本実施例
によっても、第１実施例と同様の効果を得ることができ
る。<Second Embodiment> FIG. 3 shows a method of manufacturing a semiconductor device according to a second embodiment. In this embodiment, FIG.
As shown in (a), an uncured high-viscosity resin 12 which has been molded into a rod shape or a ring shape in advance is arranged around the face-down-bonded semiconductor element 10. Subsequently, when heat treatment is performed, the resin 12 is softened to close the gap between the mounting substrate 1 and the semiconductor element 10, and the resin 12 is thermoset in this state. Since the resin 12 is a high-viscosity resin, it does not flow into the gap between the mounting substrate 1 and the semiconductor element 10. Then, as shown in FIG. 3C, the low-viscosity resin 13 is dropped, and this is thermally cured. According to this embodiment, the same effect as that of the first embodiment can be obtained.
【００１５】なお、本実施例では、未硬化の高粘度樹脂
を棒状あるいはリング状に成形したが、これに替えて、
棒状あるいはリング状の基材（セラミックなど）に未硬
化の高粘度樹脂を被着したものを用いてもよい。In this embodiment, the uncured high-viscosity resin is molded into a rod shape or a ring shape. However, instead of this,
A rod-shaped or ring-shaped substrate (ceramic or the like) coated with an uncured high-viscosity resin may be used.
【００１６】＜第３実施例＞図４は第３実施例に係る半
導体装置の製造方法を示している。本実施例では、図４
（ａ）に示すように、半導体素子１０よりも大きい板状
に成形さた未硬化の高粘度樹脂１２を、フェイスダウン
ボンディングされた半導体素子１０の上に載置する。続
いて、加熱処理を施すと、図４（ｂ）に示すように、樹
脂１２が軟化することにより、実装基板１と半導体素子
１０との間隙が閉塞され、この状態で樹脂１２は熱硬化
する。樹脂１２は高粘度樹脂であるので、実装基板１と
半導体素子１０の間隙に流れ込むことはない。そして、
図４（ｃ）に示すように、低粘度の樹脂１３を滴下し
て、これを熱硬化する。本実施例によっても、第１およ
び第２実施例と同様の効果を得ることができる。<Third Embodiment> FIG. 4 shows a method of manufacturing a semiconductor device according to a third embodiment. In this embodiment, FIG.
As shown in (a), an uncured high-viscosity resin 12 formed in a plate shape larger than the semiconductor element 10 is placed on the face-down bonded semiconductor element 10. Subsequently, when heat treatment is performed, the resin 12 is softened to close the gap between the mounting substrate 1 and the semiconductor element 10 as shown in FIG. 4B, and the resin 12 is thermoset in this state. . Since the resin 12 is a high-viscosity resin, it does not flow into the gap between the mounting substrate 1 and the semiconductor element 10. And
As shown in FIG. 4C, a low-viscosity resin 13 is dropped and heat-cured. Also according to this embodiment, the same effect as that of the first and second embodiments can be obtained.
【００１７】なお、本実施例では、未硬化の高粘度樹脂
を板状に成形したもの用いたが、これに替えて、未硬化
の高粘度樹脂を布などに含浸させたものを用いてもよ
い。In this embodiment, the uncured high-viscosity resin is used in the form of a plate. However, instead of this, a uncured high-viscosity resin impregnated with cloth may be used. Good.
【００１８】[0018]
【発明の効果】以上の説明から明らかなように、本発明
によれば、半導体素子が低粘度の樹脂で封止されるの
で、前記封止樹脂と実装基板との密着性が高まり、信頼
性を向上することができる。しかも、半導体素子の周辺
部を覆う高粘度の樹脂によって、実装基板と半導体素子
との間隙が閉塞されており、低粘度の封止樹脂が実装基
板と半導体素子との間に流れ込むことがないので、半導
体装置の電気的特性が劣化することはない。As is apparent from the above description, according to the present invention, since the semiconductor element is sealed with the low-viscosity resin, the adhesiveness between the sealing resin and the mounting substrate is increased, and the reliability is improved. Can be improved. Moreover, since the gap between the mounting substrate and the semiconductor element is closed by the high-viscosity resin that covers the peripheral portion of the semiconductor element, the low-viscosity sealing resin does not flow between the mounting substrate and the semiconductor element. Therefore, the electric characteristics of the semiconductor device are not deteriorated.
【図１】本発明に係る半導体装置の第１実施例の断面図
である。FIG. 1 is a sectional view of a first embodiment of a semiconductor device according to the present invention.
【図２】第１実施例に係る半導体装置の製造方法を示す
図である。FIG. 2 is a diagram showing the method of manufacturing the semiconductor device according to the first embodiment.
【図３】第２実施例に係る半導体装置の製造方法を示す
図である。FIG. 3 is a diagram showing a method for manufacturing a semiconductor device according to a second embodiment.
【図４】第３実施例に係る半導体装置の製造方法を示す
図である。FIG. 4 is a diagram showing a method for manufacturing a semiconductor device according to a third embodiment.
【図５】従来の半導体装置の断面図である。FIG. 5 is a cross-sectional view of a conventional semiconductor device.
【図６】樹脂コートの有無による周波数−電力利得特性
を比較した特性図である。FIG. 6 is a characteristic diagram comparing frequency-power gain characteristics with and without a resin coat.
１…実装基板 ２…リードパッド １０…半導体素子 １１…金属バンプ １２…高粘度樹脂 １３…低粘度樹脂 1 ... Mounting board 2 ... Lead pad 10 ... Semiconductor element 11 ... Metal bump 12 ... High viscosity resin 13 ... Low viscosity resin
Claims (1)
上に実装され、前記表面に形成された金属バンプと前記
基板上に形成されたリードパッドとが電気的に接続され
る半導体装置において、 前記半導体素子は、少なくともその周辺部が高粘度の樹
脂で覆われ、さらに、その上から低粘度の樹脂で封止さ
れていることを特徴とする半導体装置。1. A semiconductor device in which a semiconductor element is mounted on a substrate with its surface facing down and a metal bump formed on the surface is electrically connected to a lead pad formed on the substrate. The semiconductor device is characterized in that at least a peripheral portion of the semiconductor element is covered with a high-viscosity resin and further sealed with a low-viscosity resin from above.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4360575A JP2771086B2 (en) | 1992-12-28 | 1992-12-28 | Semiconductor device and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4360575A JP2771086B2 (en) | 1992-12-28 | 1992-12-28 | Semiconductor device and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH06204292A true JPH06204292A (en) | 1994-07-22 |
| JP2771086B2 JP2771086B2 (en) | 1998-07-02 |
Family
ID=18470002
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4360575A Expired - Fee Related JP2771086B2 (en) | 1992-12-28 | 1992-12-28 | Semiconductor device and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2771086B2 (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5515391A (en) * | 1994-03-07 | 1996-05-07 | Sdl, Inc. | Thermally balanced diode laser package |
| WO2003005441A1 (en) * | 2001-07-03 | 2003-01-16 | Fujitsu Limited | Coating material of semiconductor chip, coating method of semiconductor chip and semiconductor device |
| JP2009277955A (en) * | 2008-05-16 | 2009-11-26 | Nec Corp | Method of manufacturing semiconductor device and structure for inspecting semiconductor chip |
| WO2012124539A1 (en) * | 2011-03-11 | 2012-09-20 | 株式会社村田製作所 | Electronic component, and method for producing same |
| JP2012244034A (en) * | 2011-05-23 | 2012-12-10 | Panasonic Corp | Mounting structure of semiconductor package component and manufacturing method thereof |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6313337A (en) * | 1986-07-04 | 1988-01-20 | Fuji Electric Co Ltd | Process of mounting semiconductor element |
-
1992
- 1992-12-28 JP JP4360575A patent/JP2771086B2/en not_active Expired - Fee Related
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6313337A (en) * | 1986-07-04 | 1988-01-20 | Fuji Electric Co Ltd | Process of mounting semiconductor element |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5515391A (en) * | 1994-03-07 | 1996-05-07 | Sdl, Inc. | Thermally balanced diode laser package |
| WO2003005441A1 (en) * | 2001-07-03 | 2003-01-16 | Fujitsu Limited | Coating material of semiconductor chip, coating method of semiconductor chip and semiconductor device |
| JP2009277955A (en) * | 2008-05-16 | 2009-11-26 | Nec Corp | Method of manufacturing semiconductor device and structure for inspecting semiconductor chip |
| WO2012124539A1 (en) * | 2011-03-11 | 2012-09-20 | 株式会社村田製作所 | Electronic component, and method for producing same |
| JP2012244034A (en) * | 2011-05-23 | 2012-12-10 | Panasonic Corp | Mounting structure of semiconductor package component and manufacturing method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2771086B2 (en) | 1998-07-02 |
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