JP2003086620A - Semiconductor device having protruding electrode and manufacturing method therefor - Google Patents

Semiconductor device having protruding electrode and manufacturing method therefor

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Publication number
JP2003086620A
JP2003086620A JP2002199714A JP2002199714A JP2003086620A JP 2003086620 A JP2003086620 A JP 2003086620A JP 2002199714 A JP2002199714 A JP 2002199714A JP 2002199714 A JP2002199714 A JP 2002199714A JP 2003086620 A JP2003086620 A JP 2003086620A
Authority
JP
Japan
Prior art keywords
electrode
semiconductor device
semiconductor
protruding
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2002199714A
Other languages
Japanese (ja)
Other versions
JP3931749B2 (en
JP2003086620A5 (en
Inventor
Takashi Otsuka
隆 大塚
Kazuhiko Matsumura
和彦 松村
Tetsuo Kawakita
哲郎 河北
Hiroaki Fujimoto
博昭 藤本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
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Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP2002199714A priority Critical patent/JP3931749B2/en
Publication of JP2003086620A publication Critical patent/JP2003086620A/en
Publication of JP2003086620A5 publication Critical patent/JP2003086620A5/ja
Application granted granted Critical
Publication of JP3931749B2 publication Critical patent/JP3931749B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13109—Indium [In] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29199—Material of the matrix
    • H01L2224/2929—Material of the matrix with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298—Fillers
    • H01L2224/29299—Base material
    • H01L2224/293—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
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    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H01L2224/83851—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester being an anisotropic conductive adhesive
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H01L2224/83855—Hardening the adhesive by curing, i.e. thermosetting
    • H01L2224/83874—Ultraviolet [UV] curing
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
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    • H01L2924/097—Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701—Low temperature co-fired ceramic [LTCC]

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  • Wire Bonding (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device suitable for miniaturization. SOLUTION: A protection layer is formed by covering the active layer of a semiconductor element. An opening part confronted with an element electrode arranged in the active face of the semiconductor element is formed in the protection layer. A barrier layer covering the element electrode, a diffusion preventing layer covering the barrier layer and a protruding electrode are formed inside the opening part. A material whose hardness is preferably lower than that of the barrier layer and that of the element electrode is used for the protruding electrode.

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【発明の属する技術分野】この発明は半導体装置に関
し、特に他の半導体装置あるいは配線基板の基板電極と
接続される突起電極を有する半導体装置に関する。また
この発明はさらにこれら半導体装置の製造方法に関す
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a protruding electrode connected to another semiconductor device or a substrate electrode of a wiring board. The present invention also relates to a method of manufacturing these semiconductor devices.

【０００２】[0002]

【従来の技術】近年、ＴＡＢ方式あるいはフリップチッ
プ方式と呼ばれる方法によって、一対の半導体装置、あ
るいは半導体装置と配線基板とを接続する方法が知られ
ている。ここで言う配線基板とは、例えば絶縁性基板に
導電性の基板電極を配置したプリント基板の他、ＴＦ
Ｔ、圧電素子等の電気素子等、半導体装置と電気的結合
がなされる電気素子全般を指すものである。2. Description of the Related Art In recent years, a method of connecting a pair of semiconductor devices or a semiconductor device and a wiring board by a method called a TAB method or a flip chip method has been known. The wiring board referred to here is, for example, a printed circuit board in which conductive board electrodes are arranged on an insulating board, or a TF.
It refers to all electric elements such as T and electric elements such as piezoelectric elements that are electrically coupled to a semiconductor device.

【０００３】このうちフリップチップ方式においては、
実装される半導体装置に半田（すずと鉛の合金）からな
る突起電極が設けられており、この突起電極を他の半導
体装置あるいは配線基板の電極に接続する。図１８は、
かかる半導体装置の一例の概略を示す断面図であり、半
導体素子１１はトランジスタや配線、コンタクトなどが
形成された能動層１６及び素子電極１３を有する。素子
電極１３は、半導体素子１１の能動面１６を被覆した低
融点ガラスやシリコン窒化膜などからなる保護層１２に
形成された開口部から露出している。開口部の内外に
は、ＴｉＷ／Ａｕ等からなるバリア層１４が形成されて
おり、バリア層１４の上に突起電極１５が電解めっき法
や蒸着法により形成される。かかる突起電極１５は接続
されるべき他の半導体装置あるいは配線基板に接続され
る。Of these, in the flip chip system,
The semiconductor device to be mounted is provided with a protruding electrode made of solder (an alloy of tin and lead), and this protruding electrode is connected to another semiconductor device or an electrode of a wiring board. Figure 18
FIG. 3 is a cross-sectional view schematically showing an example of such a semiconductor device, in which a semiconductor element 11 has an active layer 16 on which transistors, wirings, contacts, etc. are formed, and an element electrode 13. The device electrode 13 is exposed from an opening formed in the protective layer 12 made of low melting point glass or a silicon nitride film that covers the active surface 16 of the semiconductor device 11. A barrier layer 14 made of TiW / Au or the like is formed inside and outside the opening, and a protruding electrode 15 is formed on the barrier layer 14 by electrolytic plating or vapor deposition. The bump electrode 15 is connected to another semiconductor device or wiring board to be connected.

【０００４】また図１９は、他の半導体装置の組み合わ
せの一例の概略を示す断面図であり、半導体素子２４に
は、表面がＡｕからなる突起電極２６が設けられてお
り、この突起電極２６は接続されるべき配線基板２５に
形成されたＡｌからなる基板電極２７に接続されてい
る。突起電極２６と基板電極２７の周辺にはＡｕ−Ａｌ
合金層２８が形成される。FIG. 19 is a sectional view showing an outline of an example of a combination of other semiconductor devices. The semiconductor element 24 is provided with a bump electrode 26 having a surface made of Au. It is connected to a substrate electrode 27 made of Al formed on the wiring substrate 25 to be connected. Au-Al is formed around the protruding electrode 26 and the substrate electrode 27.
The alloy layer 28 is formed.

【０００５】[0005]

【発明が解決しようとする課題】図１８を参照して説明
した従来の半導体装置は、次のような問題点を有する。
まず、バリア層１４は予め半導体ウエハの全面に亘って
形成され、その後、突起電極１５を除く不要部分がエッ
チングにより除去される。従ってオーバーエッチングを
防止する都合上、バリア層１４は開口部の周辺部まで広
がった形状となる。このような複雑な工程が必要とされ
るばかりでなく、突起電極１５同士のピッチを細かくす
ることが難しく、もっては半導体素子１１の小型化に限
界が生じている。図１８に示した実施例の場合、隣り合
う開口部のピッチは２０μｍ、開口部径は１００μｍ、
突起電極の高さは１００μｍ程度である。The conventional semiconductor device described with reference to FIG. 18 has the following problems.
First, the barrier layer 14 is formed over the entire surface of the semiconductor wafer in advance, and thereafter, unnecessary portions except the protruding electrodes 15 are removed by etching. Therefore, in order to prevent overetching, the barrier layer 14 has a shape that extends to the peripheral portion of the opening. Not only is such a complicated process required, but it is difficult to make the pitch between the protruding electrodes 15 fine, which limits the miniaturization of the semiconductor element 11. In the case of the embodiment shown in FIG. 18, the pitch between adjacent openings is 20 μm, the opening diameter is 100 μm,
The height of the protruding electrode is about 100 μm.

【０００６】また図１９を参照して説明した従来の半導
体装置は次のような問題点を有する。先に述べたよう
に、半導体素子２４と基板電極２７との接続工程にあっ
ては、高温加熱や高荷重が半導体素子２４に加えられ
る。このため、半導体素子２４の破壊や信頼性の劣化を
招く可能性があり、完成品の歩留まりが悪くなる恐れが
ある。The conventional semiconductor device described with reference to FIG. 19 has the following problems. As described above, in the process of connecting the semiconductor element 24 and the substrate electrode 27, high temperature heating and high load are applied to the semiconductor element 24. For this reason, the semiconductor element 24 may be broken or reliability may be deteriorated, and the yield of finished products may be deteriorated.

【０００７】本発明は、小型化に適した半導体装置及び
その製造方法を提供することを目的とする。本発明はさ
らに、機械的ストレスに強い半導体装置及びその製造方
法を提供することを目的とする。An object of the present invention is to provide a semiconductor device suitable for miniaturization and a manufacturing method thereof. A further object of the present invention is to provide a semiconductor device that is resistant to mechanical stress and a method for manufacturing the same.

【０００８】[0008]

【課題を解決するための手段】上記の問題点を解決する
ため、本発明にかかる半導体装置は、半導体素子の能動
面に設けられ、素子電極を臨ませた開口部を有する保護
層の内部に、バリア層、拡散防止層及び突起電極が形成
され、好ましくは突起電極の硬度は、素子電極及びバリ
ア層よりも低いものとされている。このような構成を有
することでバリア層が開口部の外側に広がることなく、
小型化に適し、かつ突起電極に加えられる機械的ストレ
スが素子電極及び能動層に伝達されにくい半導体装置を
提供することが可能になる。In order to solve the above problems, a semiconductor device according to the present invention has a protective layer provided on an active surface of a semiconductor element and having an opening facing an element electrode. The barrier layer, the diffusion preventing layer and the protruding electrode are formed, and the hardness of the protruding electrode is preferably lower than that of the device electrode and the barrier layer. By having such a configuration, the barrier layer does not spread outside the opening,
It is possible to provide a semiconductor device suitable for miniaturization and in which mechanical stress applied to the protruding electrodes is less likely to be transmitted to the element electrode and the active layer.

【０００９】また、本発明にかかる半導体装置は、第一
の突起電極を有する半導体装置と、第一の突起電極より
も硬度の低い第二の突起電極を有する配線基板あるいは
第二の半導体装置とを備え、第一の突起電極の少なくと
も一部が第二の突起電極に埋没すされている。このよう
な構成を有することで、機械的ストレスが第二の突起電
極によって吸収される。A semiconductor device according to the present invention includes a semiconductor device having a first protruding electrode and a wiring substrate or a second semiconductor device having a second protruding electrode having a hardness lower than that of the first protruding electrode. And at least a part of the first protruding electrode is buried in the second protruding electrode. With such a configuration, mechanical stress is absorbed by the second protruding electrode.

【００１０】また、本発明にかかる半導体装置は、第一
の半導体装置及び第二の半導体装置のそれぞれに、開口
部を有する保護層を有し、それぞれの開口部の内部には
バリア層、拡散防止層が形成され、それぞれの拡散防止
層の間を突起電極にて接合した構成からなる。この様な
構成を有することで、バリア層が開口部の外側に広がる
ことなく、小型化に適した半導体装置を提供することが
可能となる。In the semiconductor device according to the present invention, each of the first semiconductor device and the second semiconductor device has a protective layer having an opening, and a barrier layer and a diffusion layer are provided inside each opening. The prevention layer is formed, and the diffusion prevention layers are joined together by the projection electrodes. With such a structure, it is possible to provide a semiconductor device suitable for miniaturization without the barrier layer spreading outside the opening.

【００１１】また、本発明にかかる半導体装置の製造方
法は、半導体素子の能動面を被覆して形成された保護層
の開口部から露出した素子電極上にバリア層及び拡散防
止層形成用膜を無電解めっき法によって形成し、拡散防
止層形成用膜上に突起電極を形成すると共に、突起電極
と拡散防止層形成用膜との相互拡散により拡散防止層を
形成するものである。このようにすることで、バリア層
が開口部の外部に広がることなく、小型化に適した半導
体装置を製造することが可能になる。Further, in the method for manufacturing a semiconductor device according to the present invention, a barrier layer and a diffusion prevention layer forming film are formed on the element electrode exposed from the opening of the protective layer formed by covering the active surface of the semiconductor element. The diffusion prevention layer is formed by electroless plating, the projection electrode is formed on the diffusion prevention layer forming film, and the diffusion prevention layer is formed by mutual diffusion of the projection electrode and the diffusion prevention layer forming film. By doing so, it is possible to manufacture a semiconductor device suitable for miniaturization without the barrier layer spreading outside the opening.

【００１２】また本発明の半導体装置の製造方法は、第
一の半導体装置に形成された突起電極と、及び第二の半
導体装置または配線基板に形成された拡散防止層形成用
膜とをそれぞれ接触させて、突起電極と拡散防止層形成
用膜との相互拡散により拡散防止層を形成し、かつ第一
の半導体装置及び第二の半導体装置又は配線基板とを突
起電極により接合するものである。このようにすること
で、第一の半導体装置及び第二の半導体装置又は配線基
板が、突起電極を介して接続される。Further, in the method of manufacturing a semiconductor device of the present invention, the protruding electrode formed on the first semiconductor device and the diffusion preventing layer forming film formed on the second semiconductor device or the wiring board are respectively brought into contact with each other. Then, the diffusion preventing layer is formed by mutual diffusion of the protruding electrode and the diffusion preventing layer forming film, and the first semiconductor device and the second semiconductor device or the wiring substrate are joined by the protruding electrode. By doing so, the first semiconductor device and the second semiconductor device or the wiring substrate are connected to each other through the protruding electrodes.

【００１３】また本発明の半導体装置の製造方法は、そ
れぞれ硬度の異なる第一及び第二の突起電極を、それぞ
れ第一の半導体素子及び第二の半導体素子または配線基
板上に形成し、これら第一及び第二の突起電極を位置あ
わせして、硬度の高い突起電極の少なくとも一部を他方
の突起電極に埋没するように接続するものである。この
様にすることで、機械的ストレスが硬度の低い突起電極
により吸収される。According to the method of manufacturing a semiconductor device of the present invention, the first and second bump electrodes having different hardness are formed on the first semiconductor element and the second semiconductor element or the wiring board, respectively, The first and second protrusion electrodes are aligned and connected so that at least a part of the protrusion electrode having high hardness is buried in the other protrusion electrode. By doing so, mechanical stress is absorbed by the protruding electrodes having low hardness.

【００１４】また本発明の半導体装置の製造方法は、突
起電極を基板電極に接触させるにあたり、還元剤が混入
された絶縁性樹脂を塗布する工程を含むものである。こ
うすることにより、突起電極と基板電極との間で還元剤
が破砕され、突起電極及び基板電極の表面に付着する酸
化物が還元剤により除去される。Further, the method for manufacturing a semiconductor device of the present invention includes a step of applying an insulating resin mixed with a reducing agent when bringing the protruding electrode into contact with the substrate electrode. By doing so, the reducing agent is crushed between the protruding electrode and the substrate electrode, and the oxide attached to the surfaces of the protruding electrode and the substrate electrode is removed by the reducing agent.

【００１５】[0015]

【発明の実施の形態】本発明の請求項１に記載の半導体
装置は、半導体素子の能動面を被覆して形成され、半導
体素子の能動面に設けられた素子電極を臨ませた開口部
を有する保護層と、開口部の内部において素子電極を被
覆するバリア層と、バリア層を被覆した拡散防止層と、
拡散防止層上に設けられた突起電極とを有することを特
徴とするものであり、バリア層を開口部の内部に形成し
たことで小型化に適した半導体装置を提供することがで
きるものである。DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor device according to claim 1 of the present invention is formed by covering an active surface of a semiconductor element, and has an opening portion facing the element electrode provided on the active surface of the semiconductor element. A protective layer having, a barrier layer that covers the device electrode inside the opening, a diffusion prevention layer that covers the barrier layer,
The present invention is characterized in that it has a bump electrode provided on the diffusion prevention layer, and by forming the barrier layer inside the opening, it is possible to provide a semiconductor device suitable for miniaturization. .

【００１６】本発明の請求項２に記載の半導体装置は、
請求項１に記載された半導体装置において、突起電極は
素子電極及びバリア層よりも硬度の低い材料で形成され
ていることを特徴とするものであり、機械的ストレスが
素子電極により吸収される。本発明の請求項３に記載の
半導体装置は、請求項１に記載された半導体装置におい
て、バリア層及び拡散防止層の厚みの合計は、保護層の
厚みとほぼ等しいことを特徴とするものであり、半導体
装置同士の接合、または半導体装置と配線基板との接合
における接合状態が規制されて安定する。A semiconductor device according to claim 2 of the present invention is
The semiconductor device according to claim 1 is characterized in that the protruding electrode is formed of a material having a hardness lower than that of the element electrode and the barrier layer, and mechanical stress is absorbed by the element electrode. A semiconductor device according to a third aspect of the present invention is the semiconductor device according to the first aspect, wherein the total thickness of the barrier layer and the diffusion prevention layer is substantially equal to the thickness of the protective layer. Therefore, the bonding state of the bonding between the semiconductor devices or the bonding between the semiconductor devices and the wiring board is regulated and stabilized.

【００１７】本発明の請求項４に記載の半導体装置は、
第一の突起電極を有する第一の半導体装置と、第一の突
起電極よりも硬度の低い第二の突起電極を有する配線基
板あるいは第二の半導体装置とを備え、第一の突起電極
の少なくとも一部が前記第二の突起電極に埋没した構造
を有することを特徴とするものであり、第一の突起電極
の少なくとも一部が第二の突起電極に埋没することで、
加えられる機械的ストレスが吸収される。A semiconductor device according to a fourth aspect of the present invention is
A first semiconductor device having a first bump electrode and a wiring board or a second semiconductor device having a second bump electrode having a hardness lower than that of the first bump electrode are provided, and at least the first bump electrode is provided. It is characterized in that it has a structure in which a part is buried in the second protruding electrode, by at least a part of the first protruding electrode is buried in the second protruding electrode,
The applied mechanical stress is absorbed.

【００１８】本発明の請求項５に記載の半導体装置は、
請求項４に記載の半導体装置において、第一の半導体装
置と、第二の半導体装置あるいは配線基板との間に介在
する絶縁性樹脂をさらに備えることを特徴とするもので
あり、絶縁性樹脂は隣接する突起電極同士を絶縁する作
用を有すると共に、第一の半導体装置と第二の半導体装
置あるいは配線基板との接続をより強化する作用を有す
る。A semiconductor device according to claim 5 of the present invention is
The semiconductor device according to claim 4, further comprising an insulating resin interposed between the first semiconductor device and the second semiconductor device or the wiring board, wherein the insulating resin is It has a function of insulating adjacent protruding electrodes from each other and a function of further strengthening the connection between the first semiconductor device and the second semiconductor device or the wiring board.

【００１９】本発明の請求項６に記載の半導体装置は、
請求項４に記載の半導体装置において、第一及び／又は
第二の半導体装置は、半導体素子の能動面を被覆して形
成され、半導体素子の能動面に設けられた素子電極を臨
ませた開口部を有する保護層と、開口部の内部において
前記素子電極を被覆するバリア層と、バリア層を被覆し
た拡散防止層とを備えることを特徴とするものであり、
一対の半導体装置のうち、少なくとも一方は、保護層の
開口部内にバリア層と拡散防止層を形成したので、小型
化に適した半導体装置を提供することが可能となる。A semiconductor device according to claim 6 of the present invention is
The semiconductor device according to claim 4, wherein the first and / or second semiconductor device is formed by covering the active surface of the semiconductor element, and the opening facing the element electrode provided on the active surface of the semiconductor element. A protective layer having a portion, a barrier layer that covers the element electrode inside the opening, and a diffusion prevention layer that covers the barrier layer,
Since at least one of the pair of semiconductor devices has the barrier layer and the diffusion prevention layer formed in the opening of the protective layer, it is possible to provide a semiconductor device suitable for miniaturization.

【００２０】本発明の請求項７に記載の半導体装置は、
請求項４に記載の半導体装置において、第一の突起電極
は金、パラジウム、白金、銅及びこれらを主成分とする
合金のうちのいずれかであることを特徴とするものであ
り、これら硬度の高い金属を使用することで、少なくと
も第一の突起電極の一部が第二の突起電極に、埋没でき
るようにした。A semiconductor device according to claim 7 of the present invention is
The semiconductor device according to claim 4, wherein the first protruding electrode is any one of gold, palladium, platinum, copper, and an alloy containing them as a main component. By using a high metal, at least a part of the first protruding electrode can be buried in the second protruding electrode.

【００２１】本発明の請求項８に記載の半導体装置は、
請求項４に記載の半導体装置において、第二の突起電極
は、インジウム、インジウムを主成分とする合金、鉛、
鉛を主成分とする合金のうちのいずれかであること特徴
とするものであり、これら硬度の低い金属を使用するこ
とで、機械的ストレスが吸収され得るようにしたもので
ある。A semiconductor device according to claim 8 of the present invention is
The semiconductor device according to claim 4, wherein the second protruding electrode is indium, an alloy containing indium as a main component, lead,
It is characterized by being one of alloys containing lead as a main component, and by using these metals having low hardness, mechanical stress can be absorbed.

【００２２】本発明の請求項９に記載の半導体装置は、
第一及び第二の半導体装置を備え、第一及び第二の半導
体装置のそれぞれは、半導体素子の能動面を被覆して形
成され、半導体素子の能動面に設けられた素子電極を臨
ませた開口部を有する保護層と、開口部の内部において
素子電極を被覆するバリア層と、バリア層を被覆した拡
散防止層とを備えると共に、第一の半導体装置の拡散防
止層と、第二の半導体装置の拡散防止層との間を、突起
電極にて接合したことを特徴とするものであり、第一及
び第二の半導体装置は突起電極を介して互いに接合され
る。A semiconductor device according to claim 9 of the present invention is
First and second semiconductor devices are provided, and each of the first and second semiconductor devices is formed by covering the active surface of the semiconductor element and faces the element electrode provided on the active surface of the semiconductor element. A protective layer having an opening, a barrier layer covering the element electrode inside the opening, and a diffusion prevention layer covering the barrier layer are provided, and a diffusion prevention layer of the first semiconductor device and a second semiconductor The present invention is characterized in that a bump electrode is joined to the diffusion prevention layer of the device, and the first and second semiconductor devices are joined to each other via the bump electrode.

【００２３】本発明の請求項１０に記載の半導体装置
は、請求項９に記載の半導体装置において、突起電極は
素子電極及びバリア層よりも硬度の低い材料で形成され
ていることを特徴とするものであり、機械的ストレスが
硬度の低い突起電極により吸収され得ることになる。本
発明の請求項１１に記載の半導体装置は、請求項９に記
載の半導体装置において、第一及び第二の半導体装置と
の間に介在する絶縁材をさらに備えることを特徴とする
ものであり、絶縁材は第一と第二の半導体装置の接合を
さらに強化する。According to a tenth aspect of the present invention, in the semiconductor device according to the ninth aspect, the protruding electrode is formed of a material having a hardness lower than that of the element electrode and the barrier layer. However, mechanical stress can be absorbed by the protruding electrodes having low hardness. A semiconductor device according to an eleventh aspect of the present invention is the semiconductor device according to the ninth aspect, further comprising an insulating material interposed between the first and second semiconductor devices. The insulating material further strengthens the bonding between the first and second semiconductor devices.

【００２４】本発明の請求項１２に記載の半導体装置
は、請求項１１に記載の半導体装置において、絶縁材
は、還元剤が混入された熱硬化性の絶縁性樹脂であるこ
とを特徴とするものであり、還元剤による酸化物の除去
作用を期待することが可能となる。本発明の請求項１３
に記載の半導体装置は、請求項１２に記載の半導体装置
において、還元剤の絶縁性樹脂に対する配合比率は４０
〜８０体積％であることを特徴とするものであり、還元
剤による酸化物の除去作用を確実に期待することが可能
となるばかりでなく、還元剤の混入過多による絶縁作用
の阻害を招来することがない。According to a twelfth aspect of the present invention, in the semiconductor device according to the eleventh aspect, the insulating material is a thermosetting insulating resin mixed with a reducing agent. Therefore, it is possible to expect the action of removing the oxide by the reducing agent. Claim 13 of the present invention
The semiconductor device according to claim 12, wherein the compounding ratio of the reducing agent to the insulating resin is 40.
It is characterized in that the content is ˜80% by volume, and not only it is possible to reliably expect the action of removing the oxide by the reducing agent, but also the inhibition of the insulating action is caused by the excessive mixing of the reducing agent. Never.

【００２５】本発明の請求項１４に記載の半導体装置の
製造方法は、半導体素子の能動面を被覆して形成された
保護層の開口部から露出した素子電極上にバリア層及び
拡散防止層形成用膜を無電解めっき法によって形成する
工程と、拡散防止層形成用膜上に突起電極を形成すると
共に、突起電極と前記拡散防止層形成用膜との相互拡散
によって拡散防止層を形成する工程とを含むことを特徴
とするものであり、無電解めっき法によりバリア層及び
拡散防止層形成用膜が保護層の内部にのみ形成されるの
で、小型化に適した半導体装置を製造することができ
る。According to a fourteenth aspect of the present invention, in the method of manufacturing a semiconductor device, the barrier layer and the diffusion prevention layer are formed on the element electrode exposed from the opening of the protective layer formed by covering the active surface of the semiconductor element. Forming a diffusion barrier film by electroless plating, forming a projection electrode on the diffusion barrier layer forming film, and forming a diffusion barrier layer by mutual diffusion of the protrusion electrode and the diffusion barrier layer forming film. Since the barrier layer and the diffusion prevention layer forming film are formed only inside the protective layer by the electroless plating method, it is possible to manufacture a semiconductor device suitable for miniaturization. it can.

【００２６】本発明の請求項１５に記載の半導体装置の
製造方法は、突起電極の形成された第一の半導体装置
と、拡散防止層形成用膜を備えた第二の半導体装置また
は配線基板とを接合する方法であって、突起電極及び拡
散防止層形成用膜とを接触させる工程と、突起電極と拡
散防止層形成用膜との相互拡散によって拡散防止層を形
成し、かつ第一の半導体装置と、第二の半導体装置又は
配線基板とを突起電極により接合する工程とを含むこと
を特徴とするものであり、拡散防止層は突起電極と拡散
防止層形成用膜との相互拡散により自動的に生成され
る。According to a fifteenth aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: a first semiconductor device having a bump electrode formed thereon; and a second semiconductor device or wiring board provided with a diffusion preventing layer forming film. A step of contacting the protruding electrode and the diffusion preventing layer forming film with each other, and forming a diffusion preventing layer by mutual diffusion of the protruding electrode and the diffusion preventing layer forming film, and The present invention is characterized in that it includes a step of joining the device and a second semiconductor device or a wiring substrate by a projection electrode, wherein the diffusion prevention layer is automatically formed by mutual diffusion of the projection electrode and the diffusion prevention layer forming film. Are generated automatically.

【００２７】本発明の請求項１６に記載の半導体装置の
製造方法は、第一の半導体素子及び第二の半導体素子又
は配線基板上に硬度が異なる第一と第二の突起電極をそ
れぞれ形成する工程と、第一の突起電極と、第二の突起
電極とを位置あわせする工程と、第一と第二の突起電極
のうち硬度が高い突起電極の少なくとも一部を他の突起
電極に埋設するように接続する工程とを含むことを特徴
とするものであり、硬度の高い突起電極が硬度の低い突
起電極に埋没することで、機械的ストレスが吸収され得
る。According to a sixteenth aspect of the present invention, in the method of manufacturing a semiconductor device, first and second protruding electrodes having different hardness are formed on the first semiconductor element and the second semiconductor element or the wiring board, respectively. A step of aligning the first bump electrode and the second bump electrode, and embedding at least a part of the bump electrode having a high hardness in the other bump electrodes among the first and second bump electrodes. Thus, the mechanical stress can be absorbed by the protruding electrode having a high hardness being buried in the protruding electrode having a low hardness.

【００２８】本発明の請求項１７に記載の半導体装置の
製造方法は、第一の半導体素子及び第二の半導体素子又
は配線基板上に硬度が異なる第一と第二の突起電極をそ
れぞれ形成する工程と、第一の突起電極と、第二の突起
電極とを位置あわせする工程と、第一と第二の突起電極
のうち硬度が高い突起電極の少なくとも一部を他の突起
電極に埋設するように接続する工程と、第一及び第二の
突起電極の周囲に絶縁材を充填する工程を含むことを特
徴とするものであり、絶縁材は第一及び第二の突起電極
の接続をより強化する。In the method of manufacturing a semiconductor device according to a seventeenth aspect of the present invention, first and second protruding electrodes having different hardness are formed on the first semiconductor element and the second semiconductor element or the wiring board, respectively. A step of aligning the first bump electrode and the second bump electrode, and embedding at least a part of the bump electrode having a high hardness in the other bump electrodes among the first and second bump electrodes. And a step of filling an insulating material around the first and second protruding electrodes, the insulating material further improves the connection between the first and second protruding electrodes. Strengthen.

【００２９】本発明の請求項１８に記載の半導体装置の
製造方法は、第一の半導体素子と第二の半導体素子又は
配線基板上に、硬度が異なる第一と第二の突起電極をそ
れぞれ形成する工程と、第一の突起電極と、第二の突起
電極とを位置あわせする工程と、第一及び／又は第二の
突起電極の周囲に絶縁性樹脂を塗布する工程と、第一と
第二の突起電極のうち硬度が高い突起電極の少なくとも
一部を他の突起電極に埋設するように接続する工程と、
絶縁性樹脂を硬化させる工程とを含むことを特徴とする
ものであり、絶縁性樹脂を塗布した後に絶縁性樹脂を効
果させることにより、第一と第二の突起電極同士の接続
がより強化される。In the method of manufacturing a semiconductor device according to the eighteenth aspect of the present invention, first and second protruding electrodes having different hardness are formed on the first semiconductor element and the second semiconductor element or the wiring board, respectively. The step of aligning the first protruding electrode with the second protruding electrode, the step of applying an insulating resin around the first and / or the second protruding electrode, A step of connecting at least a part of the protrusion electrode having high hardness among the two protrusion electrodes so as to be embedded in another protrusion electrode;
It is characterized by including a step of curing the insulating resin, the connection between the first and second protruding electrodes is further strengthened by applying the insulating resin and then applying the effect of the insulating resin. It

【００３０】本発明の請求項１９に記載の半導体装置の
製造方法は、第一の半導体素子と第二の半導体素子又は
配線基板上に、硬度が異なる第一と第二の突起電極をそ
れぞれ形成する工程と、第一の突起電極と、第二の突起
電極とを位置あわせする工程と、第一及び／又は第二の
突起電極上に還元剤を含む絶縁性樹脂を塗布する工程
と、第一と第二の突起電極のうち硬度が高い突起電極の
少なくとも一部を他の突起電極に埋設するように接続す
る工程と、絶縁性樹脂を硬化させる工程とを含むことを
特徴とするものであり、絶縁性樹脂に含まれる還元剤が
第一及び第二の突起電極の接合により破砕され、これに
より第一及び第二の突起電極の表面に付着する酸化物を
除去する作用を期待することができる。According to a nineteenth aspect of the present invention, in the method of manufacturing a semiconductor device, first and second bump electrodes having different hardness are formed on the first semiconductor element and the second semiconductor element or the wiring board, respectively. A step of aligning the first protruding electrode and the second protruding electrode with each other, a step of applying an insulating resin containing a reducing agent on the first and / or the second protruding electrode, One of the first and second projecting electrodes, which has a step of connecting at least a part of the projecting electrode having a high hardness so as to be embedded in another projecting electrode, and a step of curing the insulating resin. Yes, expect that the reducing agent contained in the insulating resin will be crushed by the bonding of the first and second protruding electrodes, thereby removing the oxide adhering to the surface of the first and second protruding electrodes. You can

【００３１】本発明の請求項２０に記載の半導体装置の
製造方法は、第一の半導体装置の突起電極と、第二の半
導体装置又は配線基板上の基板電極を接触させる工程
と、還元剤が混入された絶縁性樹脂を第一の半導体装置
の突起電極及び／または第二の半導体装置または配線基
板の基板電極に塗布する工程と、絶縁性樹脂を硬化する
工程を含むことを特徴とするものであり、絶縁性樹脂に
含まれる還元剤がそれぞれの突起電極により破砕され、
それぞれの突起電極の表面に付着する酸化物が除去され
る作用を有する。According to a twentieth aspect of the present invention, there is provided a method of manufacturing a semiconductor device, wherein a step of bringing the protruding electrode of the first semiconductor device into contact with the substrate electrode of the second semiconductor device or the wiring substrate, Characterized by including a step of applying the mixed insulating resin to the projecting electrodes of the first semiconductor device and / or the substrate electrode of the second semiconductor device or the wiring substrate, and a step of curing the insulating resin. And the reducing agent contained in the insulating resin is crushed by each protruding electrode,
It has a function of removing oxides attached to the surface of each bump electrode.

【００３２】本発明の請求項２１に記載の半導体装置
は、互いの素子電極が電気的に接合されてなる第一及び
第二の半導体装置又は配線基板と、第一の半導体装置
と、第二の半導体装置又は配線基板の間に充填され、酸
化物を除去する還元剤を含む絶縁性樹脂層とを備えるこ
とを特徴とするものであり、互いの素子電極に付着する
酸化物が還元剤により除去された半導体装置を提供する
ことが可能となる。According to a twenty-first aspect of the present invention, there is provided a semiconductor device comprising: a first and a second semiconductor device or a wiring substrate having element electrodes electrically joined to each other; a first semiconductor device; and a second semiconductor device. And an insulating resin layer containing a reducing agent for removing oxides, which is filled between the semiconductor device or the wiring board, and the oxides attached to each other's element electrodes are reduced by the reducing agent. It is possible to provide a semiconductor device that has been removed.

【００３３】本発明の請求項２２に記載の半導体装置
は、半導体素子の能動面を被覆して形成され、半導体素
子の能動面に設けられた素子電極を臨ませた開口部を有
する保護層と、開口部の内部において素子電極を被覆す
るバリア層と、バリア層を被覆した拡散防止層と、拡散
防止層上に設けられ、素子電極及び前記バリア層よりも
硬度が低い突起電極とを備えた第一の半導体装置と、突
起電極と結合された電極を備えた第二の半導体装置と、
突起電極と電極との近傍に充填され、還元剤が混入され
てなる絶縁性樹脂とを備えることを特徴とするものであ
り、バリア層は保護層に形成された開口部内部のみに形
成されるため小型化に適した半導体装置を提供すること
ができるとともに、突起電極によって機械的ストレスは
吸収され、かつ還元剤により突起電極の表面に付着した
酸化物が除去された半導体装置を提供することが可能と
なる。A semiconductor device according to a twenty-second aspect of the present invention includes a protective layer formed by covering the active surface of the semiconductor element and having an opening facing the element electrode provided on the active surface of the semiconductor element. A barrier layer that covers the device electrode inside the opening, a diffusion prevention layer that covers the barrier layer, and a projection electrode that is provided on the diffusion prevention layer and has a hardness lower than that of the device electrode and the barrier layer. A first semiconductor device, a second semiconductor device having an electrode coupled to the protruding electrode,
The barrier layer is formed only inside the opening formed in the protective layer, and is provided with an insulating resin filled in the vicinity of the projecting electrode and the reducing agent and mixed with a reducing agent. Therefore, it is possible to provide a semiconductor device suitable for miniaturization, and to provide a semiconductor device in which mechanical stress is absorbed by the protruding electrodes and oxides attached to the surfaces of the protruding electrodes are removed by a reducing agent. It will be possible.

【００３４】（実施例）図１は本発明の半導体装置の好
適な一実施例の断面図を示す。半導体素子３１の内部に
はトランジスタや配線、コンタクトなどの能動層３２が
設けられる。またこの半導体素子３１の能動面上にはＡ
ｌ電極などのような素子電極３３が３０μｍ程度の間隔
で形成されている。ここでの素子電極３３はＡｌ中に
０．５％のＣｕを混合させた材料からなり、０．６μｍ
程度の厚みを有するものである。しかしながら素子電極
３３の材料はＡｌを主成分とする電極のみに限られるこ
とはなく、Ｃｕを主成分とする電極などであっても差し
支えない。(Embodiment) FIG. 1 is a sectional view of a preferred embodiment of the semiconductor device of the present invention. Inside the semiconductor element 31, an active layer 32 such as a transistor, wiring, and contact is provided. In addition, A is formed on the active surface of the semiconductor element 31.
Element electrodes 33 such as 1-electrodes are formed at intervals of about 30 μm. The element electrode 33 here is made of a material in which 0.5% Cu is mixed in Al and has a thickness of 0.6 μm.
It has a certain thickness. However, the material of the element electrode 33 is not limited to the electrode containing Al as a main component, and an electrode containing Cu as a main component may be used.

【００３５】また、この半導体素子３１の能動面上には
０．８μｍ程度の厚みのＳｉ窒化膜である保護層３４が
形成されている。さらに保護層３４には、１５μｍ程度
の内径を有し、かつ半導体素子３１の素子電極３３を露
出させる開口部が互いに離間して形成されている。この
保護層３４は低融点ガラスを用いたものを用いても差し
支えない。さらにそれぞれの開口部の内部には厚みが
０．３μｍ程度のＮｉめっき層がバリア層３５として素
子電極３３を被覆するように設けられている。さらに
０．５μｍ程度の厚みを有する拡散防止層３６がバリア
層３５を被覆するように設けられている。さらにこの拡
散防止層３６上には高さ１０μｍ程度の突起電極３７が
形成されている。A protective layer 34, which is a Si nitride film and has a thickness of about 0.8 μm, is formed on the active surface of the semiconductor element 31. Further, in the protective layer 34, openings having an inner diameter of about 15 μm and exposing the element electrodes 33 of the semiconductor element 31 are formed apart from each other. The protective layer 34 may be made of low melting point glass. Further, a Ni plating layer having a thickness of about 0.3 μm is provided inside each of the openings as a barrier layer 35 so as to cover the element electrode 33. Further, a diffusion prevention layer 36 having a thickness of about 0.5 μm is provided so as to cover the barrier layer 35. Further, a projection electrode 37 having a height of about 10 μm is formed on the diffusion prevention layer 36.

【００３６】ところで、この好適な実施例においては、
バリア層３５と拡散防止層３６との厚みの合計が保護層
３４の厚みとほぼ合致するようにしているが、バリア層
３５および拡散防止層３６が保護層３４の開口部内にの
み形成されていればよいので、バリア層３５及び拡散防
止層３６の厚みの合計が保護層３４の厚みよりも小とな
るようにしても差し支えない。しかしながら、バリア層
３５及び拡散防止層３６の厚みの合計が、保護層３４の
厚みとほぼ合致していると、配線基板への実装、あるい
は半導体装置同士の接合の場合に、接合状態が規制され
ることになって安定することが期待される。またさらに
バリア層３５、拡散防止層３６及び突起電極３７は、開
口部の内径と実質的に同じ径を有するように構成される
ことが好ましい。By the way, in this preferred embodiment,
Although the total thickness of the barrier layer 35 and the diffusion prevention layer 36 is made to substantially match the thickness of the protective layer 34, the barrier layer 35 and the diffusion prevention layer 36 may be formed only in the opening of the protective layer 34. Therefore, the total thickness of the barrier layer 35 and the diffusion prevention layer 36 may be smaller than the thickness of the protective layer 34. However, if the total thickness of the barrier layer 35 and the diffusion prevention layer 36 is substantially equal to the thickness of the protective layer 34, the bonding state is restricted when mounting on a wiring board or when bonding semiconductor devices. It is expected that it will be stable. Furthermore, it is preferable that the barrier layer 35, the diffusion prevention layer 36, and the bump electrode 37 are configured to have a diameter substantially the same as the inner diameter of the opening.

【００３７】このとき、突起電極３７はＡｌやＮｉより
も硬度の低い材料であるＩｎ等により形成されている。
このようにすると、後述するように、半導体装置を他の
電極に押圧した時に、バリア層や素子電極を介して能動
層に伝達される機械的ストレスが突起電極により吸収さ
れる。例えばＮｉのビッカース硬度は４５０〜５００Ｈ
ｖ程度、Ｉｎのビッカース硬度は１〜４Ｈｖ程度である
ので、Ｉｎよりなる突起電極３７が主として塑性変形
し、バリア層３５、素子電極３３を介して能動層３２に
伝達される機械的ストレスが減少される。At this time, the protruding electrode 37 is formed of In, which is a material having a hardness lower than that of Al or Ni.
With this configuration, as will be described later, when the semiconductor device is pressed against another electrode, the mechanical stress transmitted to the active layer via the barrier layer or the element electrode is absorbed by the protruding electrode. For example, the Vickers hardness of Ni is 450-500H
v, and the Vickers hardness of In is about 1 to 4 Hv. Therefore, the protruding electrode 37 made of In is mainly plastically deformed, and the mechanical stress transmitted to the active layer 32 via the barrier layer 35 and the device electrode 33 is reduced. To be done.

【００３８】ここで拡散防止層３６は次のようにして形
成される。まずバリア層３５を構成するＮｉめっき膜上
に、図２に示すように０．１μｍ程度の厚みのＡｕのフ
ラッシュめっき膜である拡散防止層形成用膜３８を形成
する。Ａｕのビッカース硬度は３０〜４０Ｈｖ程度であ
る。この拡散防止層形成用膜３８上にＩｎからなる突起
電極３７を接続すると、ＡｕおよびＩｎの相互拡散によ
って厚みが０．５μｍ程度まで増大した金属間化合物で
あるＡｕＩｎ2が形成され、これが拡散防止層３６とな
る。Here, the diffusion prevention layer 36 is formed as follows. First, as shown in FIG. 2, a diffusion prevention layer forming film 38, which is a flash plating film of Au having a thickness of about 0.1 μm, is formed on the Ni plating film forming the barrier layer 35. The Vickers hardness of Au is about 30 to 40 Hv. When the bump electrode 37 made of In is connected to the diffusion prevention layer forming film 38, AuIn 2 which is an intermetallic compound having a thickness increased to about 0.5 μm is formed by mutual diffusion of Au and In, and this prevents diffusion. It becomes the layer 36.

【００３９】この拡散防止層３６は、Ｎｉ及びＩｎの相
互拡散を防止し、かつ、バリア層３５と突起電極３７と
の密着状態を確保するために形成されたものである。さ
らに、突起電極３７の材料はＩｎのみに限定されるもの
ではなく、素子電極３３及びバリア層３６よりも硬度が
低いものであればよく、また拡散防止層形成用膜３８は
Ａｕのみに限定されず、例えばＰｄやＩｎとＰｂの合金
等であってもよい。The diffusion prevention layer 36 is formed to prevent mutual diffusion of Ni and In and to secure the close contact state between the barrier layer 35 and the bump electrode 37. Further, the material of the bump electrode 37 is not limited to In only, and any material having a hardness lower than that of the device electrode 33 and the barrier layer 36 may be used, and the diffusion prevention layer forming film 38 is limited to Au only. Alternatively, for example, Pd or an alloy of In and Pb may be used.

【００４０】すなわち、本発明の好適な実施例による半
導体装置においては、バリア層３５及び拡散防止層３６
が保護層３４の開口部内にのみ形成されており、かつ突
起電極３７が拡散防止層３６を介した上でバリア層３５
に形成されている。このため、開口部の外側まで広がっ
たバリア層をエッチングによって形成する必要がなくな
り、突起電極３７のサイズ、並びに離間スペースを微細
化することが可能となる。本実施例の場合、開口部径は
１５μｍ、隣接する開口部同士の距離は３０μｍ程度と
することが可能である。また突起電極３７の硬度が素子
電極３３及びバリア層３５の硬度よりも低くなっている
ため、配線基板等に対する半導体装置の実装において、
突起電極３７を介した機械的ストレスが吸収され、能動
層３２まで伝達される可能性が減じられる。That is, in the semiconductor device according to the preferred embodiment of the present invention, the barrier layer 35 and the diffusion prevention layer 36.
Is formed only in the opening of the protective layer 34, and the bump electrode 37 is formed on the barrier layer 35 via the diffusion prevention layer 36.
Is formed in. Therefore, it is not necessary to form a barrier layer that spreads to the outside of the opening by etching, and the size of the protruding electrode 37 and the spacing space can be miniaturized. In the case of this embodiment, the diameter of the opening can be set to 15 μm, and the distance between the adjacent openings can be set to about 30 μm. Further, since the hardness of the protruding electrode 37 is lower than the hardness of the element electrode 33 and the barrier layer 35, when mounting the semiconductor device on a wiring board or the like,
The mechanical stress via the protruding electrode 37 is absorbed and the possibility of being transmitted to the active layer 32 is reduced.

【００４１】次にかかる半導体装置の製造方法は図２の
側面図を参照して下記のように説明される。まず、スパ
ッタ法を利用してＡｌ等からなる素子電極３３のそれぞ
れが半導体素子３１の能動面３２上に離間した状態で形
成される。またＣＶＤ法を用いて半導体素子３１の能動
面３２上にＳｉ窒化膜の保護層３４が形成される。この
後、保護層３４の所定位置毎に素子電極３３を露出させ
る開口部が形成される。続いてこの開口部から露出した
素子電極３３上にバリア層３５として機能するＮｉめっ
き膜が無電解めっき法によって形成される。さらに、拡
散防止層３６を形成するための拡散防止層形成用膜３８
となるＡｕのフラッシュめっき膜が無電解めっき法によ
りバリア層３５上に形成され、この拡散防止層形成用膜
３８上にＩｎからなる突起電極３７が形成される。この
Ｉｎからなる突起電極３７を半導体素子に転写する工程
が図３（ａ）〜（ｃ）を参照しながら以下に説明され
る。A method of manufacturing the semiconductor device will be described below with reference to the side view of FIG. First, the element electrodes 33 made of Al or the like are formed on the active surface 32 of the semiconductor element 31 in a separated state by using the sputtering method. Further, a protective layer 34 of Si nitride film is formed on the active surface 32 of the semiconductor element 31 by using the CVD method. After that, an opening for exposing the element electrode 33 is formed at each predetermined position of the protective layer 34. Then, a Ni plating film functioning as a barrier layer 35 is formed on the element electrode 33 exposed from the opening by electroless plating. Further, a diffusion prevention layer forming film 38 for forming the diffusion prevention layer 36.
A Au flash plating film to be formed is formed on the barrier layer 35 by the electroless plating method, and the projection electrode 37 made of In is formed on the diffusion preventing layer forming film 38. The process of transferring the protruding electrode 37 made of In to the semiconductor element will be described below with reference to FIGS.

【００４２】図３（ａ）に示されるように、加圧治具４
０は第一の半導体素子３１を把持する。半導体素子３１
にはバリア層３５として機能するＮｉめっき膜と、その
表面に加工された拡散防止層形成用膜３８として機能す
るＡｕのフラッシュめっき膜が形成されている。一方、
ＳｉＯ2基板５０上に形成されたＩＴＯ基板５１上に、
Ｉｎ塊５２が接着されている。さらにＩＴＯ基板５１上
には還元剤５３がＩｎ塊５２を被覆するように塗布され
る。As shown in FIG. 3A, the pressing jig 4
0 holds the first semiconductor element 31. Semiconductor element 31
A Ni plating film that functions as a barrier layer 35 and a flash plating film of Au that functions as a diffusion prevention layer forming film 38 that has been processed are formed on the surface. on the other hand,
On the ITO substrate 51 formed on the SiO 2 substrate 50,
The In lump 52 is adhered. Further, a reducing agent 53 is applied on the ITO substrate 51 so as to cover the In lump 52.

【００４３】Ｉｎ塊５３と拡散防止層形成用膜３８とが
位置あわせされたのち、半導体素子３１が加圧治具４０
によってＳｉＯ2基板５０に向けて押圧される。Ｉｎ塊
５２のＩＴＯ基板５１に対する密着性はあまり高くない
ので、Ｉｎ塊５２は容易に半導体素子３１に転写され
る。また、Ｉｎの硬度は低いので、図３（ｂ）に示すご
とく、その形状は歪んだものとなる。さらに還元剤５３
の一部も半導体素子３１に転写される。After the In lump 53 and the diffusion preventing layer forming film 38 are aligned with each other, the semiconductor element 31 is pressed against the pressing jig 40.
Is pressed toward the SiO 2 substrate 50. Since the adhesion of the In lump 52 to the ITO substrate 51 is not so high, the In lump 52 is easily transferred to the semiconductor element 31. Further, since the hardness of In is low, its shape is distorted as shown in FIG. Further reducing agent 53
Is also transferred to the semiconductor element 31.

【００４４】こうして転写されたＩｎ塊５２は、加圧治
具４０によって加熱され、図３（ｃ）に図示されるよう
に半球状の突起となり、これが突起電極３７となる。そ
して、拡散防止層形成用膜３８とＩｎ塊５２が相互拡散
して、拡散防止層３６が形成される。このとき拡散防止
層形成用膜３８はＩｎ塊５２の全体に拡散することはな
い。従って突起電極３７の硬度はＩｎの硬度とほぼ変わ
りないと考えて良い。このため、突起電極３７の高さが
低くとも、突起電極３７の変形性能は損なわれることは
ない。The In lump 52 thus transferred is heated by the pressing jig 40 and becomes a hemispherical projection as shown in FIG. 3C, which becomes the projection electrode 37. Then, the diffusion prevention layer forming film 38 and the In lump 52 mutually diffuse to form the diffusion prevention layer 36. At this time, the diffusion prevention layer forming film 38 does not diffuse to the entire In lump 52. Therefore, it can be considered that the hardness of the bump electrode 37 is almost the same as the hardness of In. Therefore, even if the height of the protruding electrode 37 is low, the deformability of the protruding electrode 37 is not deteriorated.

【００４５】このように還元剤５３を予め塗布した状態
でＩｎ塊５２を半導体装置３１に転写することにより、
Ｉｎ塊５２と拡散防止層形成用膜３８として作用するＡ
ｕフラッシュめっき層との間の酸化物が除去されて、Ｉ
ｎ塊５２とＡｕフラッシュめっき層との間の接続の信頼
性が向上する。また、成形された突起電極の表面を被膜
する酸化物が、還元剤を塗布しない場合に比べて、格段
に除去されているので、例えば突起電極と他の電極との
接続においても接続の信頼性が向上する。By transferring the In lump 52 to the semiconductor device 31 with the reducing agent 53 applied in advance in this manner,
A acting as In lump 52 and diffusion preventing layer forming film 38
The oxide between the u flash plating layer is removed, and I
The reliability of the connection between the n-lump 52 and the Au flash plating layer is improved. In addition, since the oxide coating the surface of the formed protruding electrode is significantly removed compared to the case where the reducing agent is not applied, the reliability of the connection can be improved even when connecting the protruding electrode and other electrodes. Is improved.

【００４６】次に図１に示す半導体装置を用いて、一対
の半導体装置を接合することも可能であり、この場合同
一機能を有する単体の半導体装置よりも小型化され、か
つ専有面積が小さい半導体装置の組み合わせを得ること
が可能である。一対の半導体装置を接合する場合には、
これらの半導体装置が外圧によって互いに押圧される。
この時の圧力が素子電極３３、バリア層３５等を介して
半導体素子３１の能動面３２に伝達されることになる。
ところが、本発明の半導体装置では開口部の径が直径１
５μｍ程度と非常に小さいため、従来の半導体装置に比
べて、能動面３２に単位面積当たりに加わる圧力が大き
くなり、その機械的ストレスによる影響が懸念される。Next, by using the semiconductor device shown in FIG. 1, it is possible to bond a pair of semiconductor devices. In this case, a semiconductor which is smaller and has a smaller occupied area than a single semiconductor device having the same function. It is possible to obtain a combination of devices. When joining a pair of semiconductor devices,
These semiconductor devices are pressed against each other by external pressure.
The pressure at this time is transmitted to the active surface 32 of the semiconductor element 31 via the element electrode 33, the barrier layer 35 and the like.
However, in the semiconductor device of the present invention, the diameter of the opening is 1
Since it is as small as about 5 μm, the pressure applied to the active surface 32 per unit area becomes large as compared with the conventional semiconductor device, and there is a concern that the mechanical stress may affect the active surface 32.

【００４７】図４にはかかる問題点をも克服した半導体
装置の組み合わせの構成が示されている。図４において
は、一対の半導体装置が図示されているが、各々の半導
体装置の構造は図１に示した半導体装置と同一の構造を
有するので、図１に示す実施例と同等の部分には同じ番
号を付与し、その説明は適宜省略する。図４に示す半導
体装置の組み合わせは、一対の半導体装置のそれぞれの
突起電極３７同士が互いに接続されている。一対の半導
体装置のそれぞれの保護層３７間には絶縁性樹脂３９が
充填される。FIG. 4 shows a configuration of a combination of semiconductor devices which overcomes such problems. Although a pair of semiconductor devices is shown in FIG. 4, the structure of each semiconductor device is the same as that of the semiconductor device shown in FIG. The same numbers are assigned and the description thereof is omitted as appropriate. In the combination of semiconductor devices shown in FIG. 4, the protruding electrodes 37 of the pair of semiconductor devices are connected to each other. An insulating resin 39 is filled between the protective layers 37 of the pair of semiconductor devices.

【００４８】すなわち、かかる半導体装置の組み合わせ
において、各々の半導体装置は保護層３４に形成された
開口部、及び開口部内に設けられたバリア層３５及び拡
散防止層３６を有している。そして各々の半導体装置は
素子電極３３及びバリア層３５よりも硬度が低い突起電
極３７を共有して、相互に接続されている。かかる半導
体装置の組み合わせは以下の示す製造方法に従って作製
される。That is, in such a combination of semiconductor devices, each semiconductor device has an opening formed in the protective layer 34, and a barrier layer 35 and a diffusion prevention layer 36 provided in the opening. The respective semiconductor devices share the protruding electrode 37 having a hardness lower than that of the element electrode 33 and the barrier layer 35 and are connected to each other. Such a combination of semiconductor devices is manufactured according to the following manufacturing method.

【００４９】まず、図１に示される半導体装置が１組準
備される。そして各々の半導体装置の突起電極３７同士
が互いに位置合わせされ、すくなくともいずれか一方の
半導体装置の保護層３４上にエポキシ樹脂などの絶縁性
樹脂３９が所要量塗布される。その後一方の半導体装置
が他方に対して押圧され、かつ加熱されることによって
突起電極３７同士が固着されるとともに、絶縁性樹脂３
９が硬化される。このプロセスにより主として突起電極
３７が塑性変形し、加えられる外圧がバリア層３５や素
子電極３３を介して能動層３２に伝わる影響が減じられ
る。またそれぞれの半導体装置の反りや、それぞれの突
起電極３７の高さのばらつきも吸収される。First, one set of semiconductor devices shown in FIG. 1 is prepared. Then, the protruding electrodes 37 of the respective semiconductor devices are aligned with each other, and a required amount of insulating resin 39 such as epoxy resin is applied onto the protective layer 34 of at least one of the semiconductor devices. Thereafter, one semiconductor device is pressed against the other and heated, so that the protruding electrodes 37 are fixed to each other and the insulating resin 3
9 is cured. By this process, the protruding electrode 37 is mainly plastically deformed, and the influence of the applied external pressure on the active layer 32 via the barrier layer 35 and the device electrode 33 is reduced. Further, the warp of each semiconductor device and the height variation of each protruding electrode 37 are also absorbed.

【００５０】この実施例においては、一対の半導体装置
の一方を配線基板に置き換えることも可能である。すな
わち、配線基板上の基板電極と半導体装置とが半導体装
置に形成された突起電極により接合される。図５は半導
体装置の組み合わせの他の製造方法を示す。図５の実施
例においては、図１の実施例に示す半導体装置（これを
ｘとする）と、図１の実施例に示す半導体装置のうち拡
散防止層３６及び突起電極３７を除いた構成を有するサ
ブ半導体装置（これをｙとする）が準備される。ただし
サブ半導体装置ｙのバリア層３５上には拡散防止層形成
用膜３８が形成されているものとする。このような半導
体装置ｘの突起電極３７とサブ半導体装置ｙの拡散防止
層形成用膜３８とが位置あわせされる。次いで半導体装
置ｘあるいはサブ半導体装置ｙの少なくともいずれか一
方の保護層３４上に絶縁性樹脂３９が塗布される。この
実施例においては、サブ半導体装置ｙの保護層３４上に
絶縁性樹脂３９が塗布される。In this embodiment, one of the pair of semiconductor devices can be replaced with a wiring board. That is, the substrate electrode on the wiring substrate and the semiconductor device are joined by the protruding electrode formed on the semiconductor device. FIG. 5 shows another manufacturing method of a combination of semiconductor devices. In the embodiment shown in FIG. 5, the semiconductor device shown in the embodiment shown in FIG. 1 (denoted by x) and the semiconductor device shown in the embodiment shown in FIG. A sub-semiconductor device having the same (this is y) is prepared. However, it is assumed that the diffusion prevention layer forming film 38 is formed on the barrier layer 35 of the sub semiconductor device y. The projection electrode 37 of the semiconductor device x and the diffusion prevention layer forming film 38 of the sub semiconductor device y are aligned with each other. Next, the insulating resin 39 is applied on the protective layer 34 of at least one of the semiconductor device x and the sub semiconductor device y. In this embodiment, the insulating resin 39 is applied on the protective layer 34 of the sub semiconductor device y.

【００５１】引き続いて半導体装置ｘあるいはサブ半導
体装置ｙの少なくともいずれか一方が他方に対して加圧
され、かつ加熱される。するとサブ半導体装置ｙの拡散
防止層形成用膜３８と半導体装置ｘの突起電極３７とが
相互拡散し、厚みの増加した拡散防止層３６がサブ半導
体装置ｙのバリア層３５上に形成される。そして半導体
装置ｘ及びサブ半導体装置ｙは突起電極３７によって互
いに固着され、さらに絶縁性樹脂３９が硬化されること
によって、半導体装置ｘおよびサブ半導体装置ｙが一体
化される。Subsequently, at least one of the semiconductor device x and the sub-semiconductor device y is pressed against the other and heated. Then, the diffusion prevention layer forming film 38 of the sub semiconductor device y and the bump electrode 37 of the semiconductor device x mutually diffuse, and the diffusion prevention layer 36 having an increased thickness is formed on the barrier layer 35 of the sub semiconductor device y. Then, the semiconductor device x and the sub semiconductor device y are fixed to each other by the protruding electrode 37, and the insulating resin 39 is further cured, so that the semiconductor device x and the sub semiconductor device y are integrated.

【００５２】なお、サブ半導体装置ｙに代えて、拡散防
止層形成用膜３８が施された電極を有する他の電気装
置、例えば配線基板なども上記実施例に適用され得る。
次に、半導体装置の組み合わせのさらに他の一実施例の
構造が以下に説明される。図６においては説明の簡略化
の都合上、使用される半導体装置の構成として、半導体
素子３１、素子電極３３及び突起電極３７のみが図示さ
れるが、図１に図示される半導体装置の構成を適用する
ことも可能である。Instead of the sub-semiconductor device y, another electric device having an electrode provided with the diffusion prevention layer forming film 38, such as a wiring board, can be applied to the above-described embodiment.
Next, the structure of still another embodiment of the combination of semiconductor devices will be described below. In FIG. 6, only the semiconductor element 31, the element electrode 33, and the protruding electrode 37 are shown as the configuration of the semiconductor device used for convenience of description, but the configuration of the semiconductor device shown in FIG. It is also possible to apply.

【００５３】まず、第一の半導体素子３１ａの表面には
第一の突起電極３７ａが形成され、一方第二の半導体素
子３１ｂの表面には第二の突起電極３７ｂが形成されて
いる。これら第一の突起電極３７ａ及び第二の突起電極
３７ｂはそれぞれ電気的に接続されている。さらに第一
の半導体素子３１ａと第二の半導体素子３１ｂとの間に
は絶縁性樹脂３９が充填されている。ここで第二の突起
電極３７ｂは第一の突起電極３７ａよりも硬度が低く、
さらに好ましくは面積が大きく形成されている。例えば
第一の突起電極３７ａはＮｉにＡｕ層を形成したものが
用いられ、第二の突起電極３７ｂはＮｉにＡｕ層を形成
した後、さらにＩｎを形成したものが用いられる。Ｉｎ
のビッカース硬度は１〜４Ｈｖ程度と非常に低いため、
第一の突起電極３７ａと第二の突起電極３７ｂを当接さ
せると、第一の突起電極３７ａの少なくとも一部、例え
ば先端部が第二の突起電極３７ｂに埋没する。このよう
に第一の突起電極３７ａが第二の突起電極３７ｂに埋没
するためには、第二の突起電極３７ｂのビッカース硬度
が１〜２０Ｈｖ程度であればよく、このためには第二の
突起電極３７ｂとしてＩｎのみならずＩｎを主成分とし
た合金や、Ｐｂ及びＰｂを主成分とする合金が適してい
る。また第一の突起電極３７ａの材料としてはＡｕ，Ｐ
ｄ，Ｐｔ，Ｃｕ及びこれらを主成分とする合金が適して
いる。First, the first protruding electrode 37a is formed on the surface of the first semiconductor element 31a, while the second protruding electrode 37b is formed on the surface of the second semiconductor element 31b. The first protruding electrode 37a and the second protruding electrode 37b are electrically connected to each other. Further, an insulating resin 39 is filled between the first semiconductor element 31a and the second semiconductor element 31b. Here, the second protruding electrode 37b has lower hardness than the first protruding electrode 37a,
More preferably, it has a large area. For example, the first protruding electrode 37a is formed by forming an Au layer on Ni, and the second protruding electrode 37b is formed by forming an Au layer on Ni and then forming In. In
Has a very low Vickers hardness of 1 to 4 Hv,
When the first projecting electrode 37a and the second projecting electrode 37b are brought into contact with each other, at least a part of the first projecting electrode 37a, for example, the tip portion is embedded in the second projecting electrode 37b. In order for the first protrusion electrode 37a to be buried in the second protrusion electrode 37b in this way, the Vickers hardness of the second protrusion electrode 37b may be about 1 to 20 Hv. Not only In but also an alloy containing In as a main component or Pb and an alloy containing Pb as a main component are suitable for the electrode 37b. The material of the first protruding electrode 37a is Au, P
D, Pt, Cu and alloys containing these as the main components are suitable.

【００５４】次に上記の半導体装置の組み合わせの製造
方法が以下に説明される。図７は第一及び第二の突起電
極３７ａ、３７ｂ同士の位置あわせ工程を示す側面図で
ある。この実施例においては第一の突起電極３７ａとし
て、寸法径が５〜２０μｍの電極上に無電解めっき法に
よりＮｉを３〜５μｍ、Ａｕを０．２〜２μｍ形成した
ものが用いられ、一方第二の突起電極３７ｂとして、寸
法径が２０〜１００μｍの電極上に無電解めっき法によ
りＮｉを２μｍ、Ａｕを０．２μｍ形成した後、Ｉｎを
転写やディッピングによって３〜５μｍ形成したものが
用いられる。加圧治具４０は第一の半導体素子３１ａを
吸着する吸着装置（図示せず）を有し、この吸着装置は
第一の半導体素子３１ａを吸着する。加圧治具４０はこ
うして第一の半導体素子３１ａを吸着したまま第一の半
導体素子３１ａを搬送し、第一の突起電極３７ａと第二
の突起電極３７ｂを位置あわせする。Next, a method of manufacturing the combination of the above semiconductor devices will be described below. FIG. 7 is a side view showing a step of aligning the first and second protruding electrodes 37a and 37b with each other. In this embodiment, as the first protruding electrode 37a, one having Ni of 3 to 5 μm and Au of 0.2 to 2 μm formed by an electroless plating method on an electrode having a dimension diameter of 5 to 20 μm is used. As the second bump electrode 37b, used is one in which Ni is formed to 2 μm and Au is formed to 0.2 μm by an electroless plating method, and In is formed to 3 to 5 μm by transfer or dipping on an electrode having a size diameter of 20 to 100 μm. . The pressure jig 40 has a suction device (not shown) that suctions the first semiconductor element 31a, and this suction device sucks the first semiconductor element 31a. The pressing jig 40 thus conveys the first semiconductor element 31a while adsorbing the first semiconductor element 31a, and aligns the first protruding electrode 37a and the second protruding electrode 37b.

【００５５】図８は第一及び第二の突起電極３７ａ、３
７ｂの接続工程を示す側面図である。加圧治具４０を用
いて、一つの突起電極あたり５ｇ以下の荷重で第一の突
起電極３７ａ及び／又は第二の突起電極３７ｂが加圧さ
れ、接続される。このとき第二の突起電極３７ｂの主た
る成分であるＩｎはビッカース硬度は１〜４Ｈｖ程度と
非常に柔らかく、一方第一の突起電極３７ａを構成する
Ｎｉのビッカース硬度は４５０〜５００Ｈｖ、Ａｕのビ
ッカース硬度は４０〜５０Ｈｖと硬いため、第一の突起
電極３７ａの少なくとも一部、例えば先端部は容易に第
二の突起電極３７ｂに埋没され、電気的な接続が得られ
る。このとき、好ましくは第一の突起電極３７ａは第二
の突起電極３７ｂに２〜４μｍ埋没する。FIG. 8 shows the first and second protruding electrodes 37a and 3a.
It is a side view which shows the connection process of 7b. Using the pressing jig 40, the first protruding electrode 37a and / or the second protruding electrode 37b are pressed and connected with a load of 5 g or less per protruding electrode. At this time, In, which is a main component of the second protruding electrode 37b, has a very soft Vickers hardness of about 1 to 4 Hv, while Ni constituting the first protruding electrode 37a has a Vickers hardness of 450 to 500 Hv and a Vickers hardness of Au. Is hard at 40 to 50 Hv, so that at least a part of the first protruding electrode 37a, for example, the tip portion is easily buried in the second protruding electrode 37b, and an electrical connection can be obtained. At this time, preferably, the first protruding electrode 37a is buried in the second protruding electrode 37b by 2 to 4 μm.

【００５６】図９は第一の半導体素子３１ａと第二の半
導体素子３１ｂとの間に絶縁性樹脂３９を充填する工程
を示す側面図である。この工程では第一の半導体素子３
１ａと第二の半導体素子３１ｂとの間に作用する毛細管
現象を利用して絶縁性樹脂３９が充填される。FIG. 9 is a side view showing a step of filling the insulating resin 39 between the first semiconductor element 31a and the second semiconductor element 31b. In this process, the first semiconductor element 3
The insulating resin 39 is filled by utilizing the capillarity that acts between 1a and the second semiconductor element 31b.

【００５７】図１０は絶縁性樹脂３９を硬化させる工程
を示す側面図である。接続した第一の半導体素子３１ａ
及び第二の半導体素子３１ｂの好ましくは斜め上方よ
り、紫外線ランプ４１により紫外線が照射される。図１
１は加圧治具４０による加圧、及び紫外線ランプ４１に
よる紫外線の照射を除去する工程を示す側面図である。
加圧及び紫外線の照射が除去されると、図６に示した一
対の半導体素子の組み合わせが形成される。FIG. 10 is a side view showing the step of curing the insulating resin 39. Connected first semiconductor element 31a
Further, ultraviolet rays are emitted from the ultraviolet lamp 41, preferably obliquely above the second semiconductor element 31b. Figure 1
FIG. 1 is a side view showing a step of removing the pressure applied by the pressure jig 40 and the irradiation of ultraviolet rays by the ultraviolet lamp 41.
When the pressure and the irradiation of ultraviolet rays are removed, the combination of the pair of semiconductor elements shown in FIG. 6 is formed.

【００５８】この好適な実施例によれば、第二の突起電
極３７ｂが第一の突起電極３７ａより面積が大きく、か
つ硬度が低いので、第一の突起電極３７ａの先端部が第
二の突起電極３７ｂに埋没され、低温、低荷重での接続
が可能となる。このため、従来行われていた高温、高荷
重による一対の半導体素子の接合方法を用いた場合に懸
念される、それぞれの半導体素子の特性劣化を招く恐れ
が少なくなり、信頼性の高い半導体素子の組み合わせを
提供することが可能となる。また第一の突起電極３７ａ
が第二の突起電極３７ｂに埋没されて接続されるので、
安定した接続が期待できる。According to this preferred embodiment, the second protrusion electrode 37b has a larger area and a lower hardness than the first protrusion electrode 37a, so that the tip of the first protrusion electrode 37a has the second protrusion. Since it is buried in the electrode 37b, connection at low temperature and low load becomes possible. For this reason, there is less concern about the deterioration of the characteristics of each semiconductor element, which is a concern when using the conventional method of joining a pair of semiconductor elements due to high temperature and high load, and a highly reliable semiconductor element It is possible to provide a combination. The first protruding electrode 37a
Is buried in and connected to the second protruding electrode 37b,
You can expect a stable connection.

【００５９】次にさらなる半導体装置の組み合わせの製
造方法が以下に記述される。この実施例における第一の
突起電極３７ａはＮｉを形成したものが使用され、第二
の突起電極３７ｂはＮｉおよびＡｕを形成したあと、Ｉ
ｎ−Ｓｎ合金を形成したものが使用される。より詳しく
は、第一の突起電極３７ａは無電解めっき法によりＮｉ
を３μｍ形成したものが、また第二の突起電極３７ｂは
無電解めっき法によりＮｉを１μｍ、Ａｕを０．２μｍ
形成した後、Ｉｎ−Ｓｎ合金を転写やディッピングによ
り３〜５μｍ形成したものが用いられる。また第一の突
起電極３７ａの寸法径は５〜２０μｍ、第二の突起電極
３７ｂの寸法径は２０〜１００μｍ程度である。その他
の構成については図６に示した半導体装置の組み合わせ
と同じ構成が用いられる。Next, a method of manufacturing a further combination of semiconductor devices will be described below. In this embodiment, the first protruding electrode 37a is formed of Ni, and the second protruding electrode 37b is formed of Ni and Au.
What formed the n-Sn alloy is used. More specifically, the first protruding electrode 37a is made of Ni by electroless plating.
With a thickness of 3 μm, and the second protruding electrode 37b has a Ni content of 1 μm and an Au content of 0.2 μm by electroless plating.
After being formed, an In—Sn alloy having a thickness of 3 to 5 μm formed by transfer or dipping is used. The dimensional diameter of the first protruding electrode 37a is 5 to 20 μm, and the dimensional diameter of the second protruding electrode 37b is about 20 to 100 μm. For other configurations, the same configurations as the combination of the semiconductor devices shown in FIG. 6 are used.

【００６０】図１２に示されるように、第一の半導体素
子３１ａと第二の半導体素子３１ｂのそれぞれの突起電
極３７ａ及び３７ｂは加圧治具４０によって接触され
る。図１３は第一及び第二の半導体素子の少なくともい
ずれか一方、例えば第二の半導体素子３１ａ上に紫外線
硬化型の絶縁性樹脂３９を塗布する工程を示す側面図で
ある。すなわちこの工程においては第一の半導体素子３
１ａおよび第二の半導体素子３１ｂを接続する前に絶縁
性樹脂３９が少なくとも一方の半導体素子上に塗布され
る。図１４は第一の突起電極３７ａ及び第二の突起電極
３７ｂの接続及び紫外線を照射する工程を示す側面図で
ある。すなわち加圧治具４０を用いて一つの突起電極あ
たり５ｇ以下の荷重で第一及び第二の突起電極が加圧さ
れることにより第一の突起電極３７ａの先端部は第二の
突起電極３７ｂに２μｍ程度埋没する。その後紫外線ラ
ンプ４１によって紫外線が照射され、絶縁性樹脂３９が
硬化される。図１５は加圧治具４０と紫外線ランプ４１
を除去する工程を説明するための側面図である。以上の
工程により第一の半導体素子３１ａと第二の半導体素子
３１ｂは相互に接続される。As shown in FIG. 12, the protruding electrodes 37a and 37b of the first semiconductor element 31a and the second semiconductor element 31b are brought into contact with each other by the pressing jig 40. FIG. 13 is a side view showing a step of applying the ultraviolet curable insulating resin 39 on at least one of the first and second semiconductor elements, for example, the second semiconductor element 31a. That is, in this step, the first semiconductor element 3
Insulating resin 39 is applied to at least one of the semiconductor elements before connecting 1a and the second semiconductor element 31b. FIG. 14 is a side view showing a step of connecting the first protruding electrode 37a and the second protruding electrode 37b and irradiating with ultraviolet rays. That is, the pressure jig 40 is used to pressurize the first and second projecting electrodes with a load of 5 g or less per one projecting electrode, so that the tip of the first projecting electrode 37a becomes the second projecting electrode 37b. Buried about 2 μm. Thereafter, the ultraviolet lamp 41 irradiates ultraviolet rays to cure the insulating resin 39. FIG. 15 shows a pressure jig 40 and an ultraviolet lamp 41.
It is a side view for explaining the process of removing. Through the above steps, the first semiconductor element 31a and the second semiconductor element 31b are connected to each other.

【００６１】この好適な実施例によれば、第一の突起電
極３７ａと第二の突起電極３７ｂとを接続するより前に
絶縁性樹脂３９が塗布され、接続後に紫外線によって絶
縁性樹脂３９が硬化される。従って、絶縁性樹脂３９を
第一の半導体素子３１ａと第二の半導体素子３１ｂとの
間に容易に介在させることが可能となる。以上の様に一
対の半導体素子を積層して得られる半導体素子の組み合
わせにおいては、突起電極の表面に付着した酸化物を除
去するため、還元剤としての還元剤、例えばアビエチン
酸を主成分とする還元剤を用いて、予め突起電極の表面
を被覆する酸化物を除去することが好ましい。According to this preferred embodiment, the insulating resin 39 is applied before connecting the first protruding electrode 37a and the second protruding electrode 37b, and after connecting, the insulating resin 39 is cured by ultraviolet rays. To be done. Therefore, the insulating resin 39 can be easily interposed between the first semiconductor element 31a and the second semiconductor element 31b. In the combination of semiconductor elements obtained by stacking a pair of semiconductor elements as described above, a reducing agent as a reducing agent, such as abietic acid, as a main component, is used to remove oxides adhering to the surface of the protruding electrode. It is preferable to remove the oxide coating the surface of the bump electrode in advance with a reducing agent.

【００６２】酸化物を除去するために使用される還元剤
は、半導体装置の組み合わせ工程を完了した後で洗浄さ
れるか、あるいは加熱によって揮発する還元剤を排出す
る必要がある。ところが本発明によって実装効率を高め
られた半導体装置においては、突起電極の高さやピッチ
が小さくなり、こうした還元剤の洗浄工程や排出工程を
十分に行うために、比較的長い時間を要していた。The reducing agent used for removing the oxide needs to be washed after completion of the combination process of the semiconductor device, or the reducing agent volatilized by heating should be discharged. However, in the semiconductor device in which the mounting efficiency is increased by the present invention, the height and pitch of the protruding electrodes are reduced, and it takes a relatively long time to sufficiently perform such a reducing agent cleaning step and discharging step. .

【００６３】このため本発明では、一対の半導体装置の
接続に当たって使用される絶縁性樹脂として、還元剤が
混入された絶縁性樹脂を用いることでこうした欠点を克
服することが可能となる。図１６は例えば図３で示した
本発明にかかる半導体装置を配線基板２５にフェイスダ
ウンボンディング法で実装した構成を示す側面図であ
る。なおここでの突起電極３７はＳｎ−Ｐｂ系半田など
の低融点金属からなるものとし、１０μｍ以下の高さを
有するものであり、素子電極３３上に電解メッキや蒸着
などの方法で形成されているものとする。Therefore, in the present invention, such a defect can be overcome by using an insulating resin mixed with a reducing agent as the insulating resin used for connecting a pair of semiconductor devices. FIG. 16 is a side view showing a configuration in which the semiconductor device according to the present invention shown in FIG. 3, for example, is mounted on the wiring board 25 by a face-down bonding method. The protruding electrode 37 here is made of a low melting point metal such as Sn-Pb-based solder and has a height of 10 μm or less, and is formed on the element electrode 33 by a method such as electrolytic plating or vapor deposition. Be present.

【００６４】一方配線基板２５はガラスセラミック基板
などであり、配線基板２５の表面には基板電極２７が形
成されている。ここでは基板電極２７はＣｕやＮｉから
なる金属膜の表面上を、数μｍ程度の膜厚のＳｎ−Ｐｂ
系半田で被覆したものが用いられる。半導体装置３１の
保護層３４と、配線基板２５との間には絶縁性樹脂３９
が充填されている。この絶縁性樹脂３９は１５００ｃ．
ｐ．ｓ．程度の粘度を有するエポキシ樹脂のような熱硬
化性樹脂であるとともに、その内部に酸化物を除去する
ための還元剤であるところの、例えばアビエチン酸を主
成分とする還元剤４２が混入されている。そして突起電
極３７と基板電極２７とが互いに導通接続されている。
この時、突起電極３７と基板電極２７によって還元剤４
２が破砕され、突起電極３７あるいは基板電極２７の表
面を被覆していた酸化物は、還元剤４２の破砕、分散に
伴って除去される。On the other hand, the wiring substrate 25 is a glass ceramic substrate or the like, and the substrate electrode 27 is formed on the surface of the wiring substrate 25. Here, the substrate electrode 27 is made of Sn—Pb having a film thickness of about several μm on the surface of a metal film made of Cu or Ni.
The one coated with a system solder is used. An insulating resin 39 is provided between the protective layer 34 of the semiconductor device 31 and the wiring board 25.
Is filled. This insulating resin 39 is 1500c.
p. s. A thermosetting resin such as an epoxy resin having a viscosity of a certain degree, and a reducing agent 42 containing abietic acid as a main component, which is a reducing agent for removing oxides, is mixed therein. There is. The protruding electrode 37 and the substrate electrode 27 are electrically connected to each other.
At this time, the reducing agent 4 is formed by the protruding electrode 37 and the substrate electrode 27.
2 is crushed, and the oxide that covers the surface of the protruding electrode 37 or the substrate electrode 27 is removed as the reducing agent 42 is crushed and dispersed.

【００６５】この還元剤４２は市販されている無洗浄タ
イプの還元剤を２００℃程度の温度に保たれた活性雰囲
気中に噴霧した上で急冷することによって少なくとも外
表面を硬化した塊状となったものでる。あるいは塊状と
なった還元剤４２の外表面をエポキシ樹脂などの絶縁樹
脂や、ポリイミドなどの熱可塑性樹脂で被覆したもの、
あるいは、粉末状や液体状とされた還元剤４２を絶縁樹
脂や熱可塑性樹脂からなるカプセル中に封入したものな
どが還元剤４２として適用できる。そして還元剤４２の
外表面を絶縁性樹脂３９と同質の絶縁性樹脂で被覆して
おいたり、絶縁性樹脂３９と同質のカプセル中に還元剤
４２を封入しておけば、還元剤４２と絶縁性樹脂３９と
の間の密着性が高まり、半導体装置を配線基板に実装す
る場合に加えられる加圧力が少なくてすむ。As the reducing agent 42, a commercially available non-cleaning type reducing agent was sprayed into an active atmosphere kept at a temperature of about 200 ° C. and then rapidly cooled to form a lump in which at least the outer surface was hardened. It comes. Alternatively, the outer surface of the reducing agent 42 in the form of a lump is coated with an insulating resin such as an epoxy resin or a thermoplastic resin such as polyimide,
Alternatively, the reducing agent 42 may be a powdery or liquid reducing agent 42 encapsulated in an insulating resin or thermoplastic resin capsule. If the outer surface of the reducing agent 42 is covered with an insulating resin of the same quality as the insulating resin 39, or if the reducing agent 42 is enclosed in a capsule of the same quality as the insulating resin 39, it is insulated from the reducing agent 42. The adhesiveness with the conductive resin 39 is enhanced, and the pressure applied when the semiconductor device is mounted on the wiring board is small.

【００６６】また絶縁性樹脂３９に混入される還元剤４
２の配合比率は４０〜８０体積％の範囲とされる。これ
はこの範囲内であれば、互いに当接しあう突起電極３７
と基板電極２７との間に還元剤４２が存在する確率が極
めて高くなるからである。一方、配合比率が４０体積％
未満である場合には還元剤４２が少量過ぎて酸化物の十
分な除去効果が期待できず、また配合比率が８０体積％
を越える場合には絶縁性樹脂３９による十分な保護効果
が得られないことが予測される。The reducing agent 4 mixed in the insulating resin 39
The compounding ratio of 2 is in the range of 40 to 80% by volume. If this is within this range, the protruding electrodes 37 that abut each other
This is because the probability that the reducing agent 42 exists between the substrate electrode 27 and the substrate electrode 27 becomes extremely high. On the other hand, the compounding ratio is 40% by volume
If the amount is less than the above, the amount of the reducing agent 42 is too small and a sufficient oxide removing effect cannot be expected, and the compounding ratio is 80% by volume.
If it exceeds, it is predicted that the insulating resin 39 cannot provide a sufficient protection effect.

【００６７】図１７（ａ）及び図１７（ｂ）はそれぞれ
半導体装置を配線基板に実装する工程を示すための側面
図である。図１７（ａ）に図示されるように、半導体素
子３１と配線基板２５とが互いに対向して配置され、さ
らに突起電極３７と基板電極２７とが位置あわせされ
る。そして塊状などの還元剤４２が混入された熱硬化性
の絶縁樹脂３９が滴下等の方法で配線基板２５上に塗布
される。引き続き図１７（ｂ）に示されるように、半導
体素子３１が加圧されて配線基板２５に押しつけられ、
突起電極３７と基板電極２７とが当接される。このとき
絶縁樹脂３９に混入された塊状の還元剤４２は突起電極
３７と基板電極２７によって挟み込まれ、破砕される。
破砕された還元剤４２は突起電極３７や基板電極２７の
表面上に分散し、酸化物を除去することが可能となる。17A and 17B are side views showing the steps of mounting the semiconductor device on the wiring board. As shown in FIG. 17A, the semiconductor element 31 and the wiring board 25 are arranged to face each other, and the protruding electrode 37 and the substrate electrode 27 are aligned with each other. Then, the thermosetting insulating resin 39 mixed with the reducing agent 42 such as lumps is applied onto the wiring substrate 25 by a method such as dropping. Subsequently, as shown in FIG. 17B, the semiconductor element 31 is pressed and pressed against the wiring board 25,
The protruding electrode 37 and the substrate electrode 27 are brought into contact with each other. At this time, the block-shaped reducing agent 42 mixed in the insulating resin 39 is sandwiched between the protruding electrode 37 and the substrate electrode 27 and crushed.
The crushed reducing agent 42 is dispersed on the surfaces of the protruding electrode 37 and the substrate electrode 27, and the oxide can be removed.

【００６８】さらに突起電極３７と基板電極２７とを互
いに当接させながら半導体素子３１を加熱すると、突起
電極３７と基板電極２７とは金属拡散によって物理的か
つ電気的に接続される。また突起電極３７と基板電極２
７との間に塗布された絶縁性樹脂３９も同時に硬化させ
られる。なお、この製造方法においては、半導体素子３
１に圧力が加えられた状態で加熱されるようにしている
が、予め絶縁性樹脂３９の粘度や粘着性を高めておけ
ば、半導体素子３１への加圧を続ける必要はなく、また
半導体素子３１のみならず配線基板２５を同時に加熱し
てもよい。また絶縁性樹脂３９に混入される還元剤とし
ての還元剤４２は塊状である必要はなく、絶縁性樹脂や
熱可塑性樹脂製のカプセル中に粉末状や液体状にされた
還元剤を混入したものであってもかまわない。Further, when the semiconductor element 31 is heated while bringing the protruding electrode 37 and the substrate electrode 27 into contact with each other, the protruding electrode 37 and the substrate electrode 27 are physically and electrically connected to each other by metal diffusion. In addition, the protruding electrode 37 and the substrate electrode 2
The insulative resin 39 applied between 7 and 7 is also cured at the same time. In this manufacturing method, the semiconductor element 3
1 is heated while pressure is applied, but if the viscosity and the adhesiveness of the insulating resin 39 are increased in advance, it is not necessary to continue to pressurize the semiconductor element 31, and Not only 31 but wiring board 25 may be heated at the same time. Further, the reducing agent 42 as a reducing agent mixed in the insulating resin 39 does not need to be in a lump form, and a powder or liquid reducing agent is mixed in a capsule made of an insulating resin or a thermoplastic resin. It doesn't matter.

【００６９】このようにすると、従来では配線基板の表
面上に塗布した還元剤を洗浄あるいは揮発させた後で絶
縁性樹脂が充填されていたのに対し、上記した好適な実
施例においては、還元剤の洗浄あるいは揮発作業工程が
不要になる。また、洗浄にともなう機械的ストレスが突
起電極に加わることもなく、さらに揮発成分を排出する
排出用の間隙を設ける必要もなくなり、小型化された半
導体装置にとって特に有益である。In this way, the insulating resin is filled after the reducing agent applied on the surface of the wiring board is washed or volatilized in the conventional case, whereas in the preferred embodiment described above, the reducing agent is reduced. There is no need to wash or volatilize the agent. In addition, mechanical stress due to cleaning is not applied to the protruding electrodes, and it is not necessary to provide a discharge gap for discharging volatile components, which is particularly useful for a miniaturized semiconductor device.

【００７０】尚、以上説明した各実施例においては、発
明の趣旨を逸脱しない範囲で種々の応用が可能である。It should be noted that each of the embodiments described above can be variously applied without departing from the spirit of the invention.

【００７１】[0071]

【発明の効果】以上説明したように、本発明にかかる半
導体装置は、保護層の開口部内のみにバリア層及び拡散
防止層が形成されているので、突起電極のサイズ及びピ
ッチを微細化することが可能となる。また好ましくは突
起電極は素子電極及びバリア層よりも硬度が低いので、
かかる半導体装置の実装にあたって加えられる圧力によ
る機械的ストレスが半導体素子の能動層に伝達される危
険性が少なくなる。As described above, in the semiconductor device according to the present invention, since the barrier layer and the diffusion prevention layer are formed only in the opening of the protective layer, the size and pitch of the protruding electrodes can be reduced. Is possible. Further, preferably, the bump electrode has a lower hardness than the device electrode and the barrier layer,
The risk that mechanical stress due to the pressure applied when mounting such a semiconductor device is transmitted to the active layer of the semiconductor element is reduced.

【００７２】また一対の半導体装置の組み合わせた構造
において、一方の突起電極が他方の突起電極に埋没され
得るよう硬度を異ならせているので、一対の半導体装置
の実装時の機械的ストレスが半導体素子の能動層に伝達
される危険性が少なくなる。さらに、半導体装置同士の
組み合わせ、あるいは半導体装置の配線基板への実装時
に用いられる絶縁性樹脂には、還元剤を混入させたの
で、還元剤の洗浄作業、あるいは揮発する還元剤の排出
過程を必要としないで半導体装置の組み合わせを提供す
ることが可能となる。Further, in the structure in which the pair of semiconductor devices are combined, the hardness is made different so that one protruding electrode can be buried in the other protruding electrode, so that the mechanical stress at the time of mounting the pair of semiconductor devices is a semiconductor element. Is less likely to be transmitted to the active layer of the. Furthermore, since a reducing agent is mixed in the insulating resin used when the semiconductor devices are combined with each other or mounted on the wiring board of the semiconductor device, it is necessary to wash the reducing agent or discharge the volatilized reducing agent. Therefore, it is possible to provide a combination of semiconductor devices.

【図面の簡単な説明】[Brief description of drawings]

【図１】本発明にかかる半導体装置の一実施例の構成を
示す断面図FIG. 1 is a sectional view showing a configuration of an embodiment of a semiconductor device according to the present invention.

【図２】本発明にかかる半導体装置の製造工程の一実施
例を示す工程図FIG. 2 is a process drawing showing an example of a manufacturing process of a semiconductor device according to the present invention.

【図３】本発明にかかる半導体装置に突起電極を転写す
る工程を示す工程図FIG. 3 is a process drawing showing a process of transferring a bump electrode to a semiconductor device according to the present invention.

【図４】本発明にかかる半導体装置を用いた半導体装置
の組み合わせの一実施例を示す断面図FIG. 4 is a sectional view showing an example of a combination of semiconductor devices using the semiconductor device according to the present invention.

【図５】本発明にかかる、一対の半導体装置を接続する
工程の一実施例を示す工程図FIG. 5 is a process chart showing an embodiment of a process of connecting a pair of semiconductor devices according to the present invention.

【図６】さらに本発明にかかる、一対の半導体装置の組
み合わせの一実施例を示す断面図FIG. 6 is a sectional view showing an embodiment of a combination of a pair of semiconductor devices according to the present invention.

【図７】本発明にかかる、一対の半導体装置の組み合わ
せを製造する工程の一実施例を示す工程図FIG. 7 is a process chart showing an embodiment of a process of manufacturing a combination of a pair of semiconductor devices according to the present invention.

【図８】本発明にかかる、一対の半導体装置の組み合わ
せを製造する工程の一実施例を示す工程図FIG. 8 is a process chart showing an example of a process of manufacturing a combination of a pair of semiconductor devices according to the present invention.

【図９】本発明にかかる、一対の半導体装置の組み合わ
せを製造する工程の一実施例を示す工程図FIG. 9 is a process drawing showing an embodiment of a process of manufacturing a combination of a pair of semiconductor devices according to the present invention.

【図１０】本発明にかかる、一対の半導体装置の組み合
わせを製造する工程の一実施例を示す工程図FIG. 10 is a process drawing showing an embodiment of a process of manufacturing a combination of a pair of semiconductor devices according to the present invention.

【図１１】本発明にかかる、一対の半導体装置の組み合
わせを製造する工程の一実施例を示す工程図FIG. 11 is a process chart showing an example of a process of manufacturing a combination of a pair of semiconductor devices according to the present invention.

【図１２】本発明にかかる、一対の半導体装置の組み合
わせを製造する工程の他の一実施例を示す工程図FIG. 12 is a process drawing showing another embodiment of the process of manufacturing a combination of a pair of semiconductor devices according to the present invention.

【図１３】本発明にかかる、一対の半導体装置の組み合
わせを製造する工程の他の一実施例を示す工程図FIG. 13 is a process chart showing another embodiment of the process of manufacturing a combination of a pair of semiconductor devices according to the present invention.

【図１４】本発明にかかる、一対の半導体装置の組み合
わせを製造する工程の他の一実施例を示す工程図FIG. 14 is a process chart showing another embodiment of the process of manufacturing a combination of a pair of semiconductor devices according to the present invention.

【図１５】本発明にかかる、一対の半導体装置の組み合
わせを製造する工程の他の一実施例を示す工程図FIG. 15 is a process drawing showing another embodiment of the process of manufacturing a combination of a pair of semiconductor devices according to the present invention.

【図１６】本発明にかかる半導体装置と配線基板との接
続の一実施例を示す断面図FIG. 16 is a cross-sectional view showing an example of connection between a semiconductor device and a wiring board according to the present invention.

【図１７】本発明にかかる半導体装置と配線基板との接
続工程の一実施例を示す工程図FIG. 17 is a process diagram showing an example of a process of connecting a semiconductor device and a wiring board according to the present invention.

【図１８】従来の半導体装置の一例を示す断面図FIG. 18 is a sectional view showing an example of a conventional semiconductor device.

【図１９】他の従来の半導体装置の一例を示す断面図FIG. 19 is a cross-sectional view showing an example of another conventional semiconductor device.

【符号の説明】[Explanation of symbols]

３１ 半導体素子 ３２ 能動層 ３３ 素子電極 ３４ 保護層 ３５ バリア層 ３６ 拡散防止層 ３７ 突起電極 ３８ 拡散防止層形成用膜 ３９ 絶縁性樹脂 ４２ 還元剤 31 Semiconductor element 32 Active layer 33 element electrode 34 Protective layer 35 Barrier layer 36 Diffusion prevention layer 37 Projection electrode 38 Diffusion prevention layer forming film 39 Insulating resin 42 reducing agent

フロントページの続き (72)発明者 河北 哲郎 大阪府門真市大字門真1006番地 松下電器 産業株式会社内 (72)発明者 藤本 博昭 大阪府門真市大字門真1006番地 松下電器 産業株式会社内 Ｆターム(参考） 5F044 KK02 KK05 KK13 KK18 LL11Continued front page    (72) Inventor Tetsuro Kawakita             1006 Kadoma, Kadoma-shi, Osaka Matsushita Electric             Sangyo Co., Ltd. (72) Inventor Hiroaki Fujimoto             1006 Kadoma, Kadoma-shi, Osaka Matsushita Electric             Sangyo Co., Ltd. F term (reference) 5F044 KK02 KK05 KK13 KK18 LL11

Claims (22)

【特許請求の範囲】[Claims] 【請求項１】 半導体素子の能動面を被覆して形成さ
れ、前記半導体素子の能動面に設けられた素子電極を臨
ませた開口部を有する保護層と、前記開口部の内部にお
いて前記素子電極を被覆するバリア層と、前記バリア層
を被覆した拡散防止層と、前記拡散防止層上に設けられ
た突起電極とを有することを特徴とする半導体装置。1. A protective layer formed to cover an active surface of a semiconductor element, the protective layer having an opening facing the element electrode provided on the active surface of the semiconductor element, and the element electrode inside the opening. A semiconductor device comprising: a barrier layer that covers the barrier layer; a diffusion prevention layer that covers the barrier layer; and a bump electrode that is provided on the diffusion prevention layer. 【請求項２】 前記突起電極は前記素子電極及び前記バ
リア層よりも硬度の低い材料で形成されていることを特
徴とする請求項１記載の半導体装置。2. The semiconductor device according to claim 1, wherein the protruding electrode is formed of a material having a hardness lower than that of the element electrode and the barrier layer. 【請求項３】 前記バリア層及び拡散防止層の厚みの合
計は、前記保護層の厚みとほぼ等しいことを特徴とする
請求項１記載の半導体装置。3. The semiconductor device according to claim 1, wherein the total thickness of the barrier layer and the diffusion prevention layer is substantially equal to the thickness of the protective layer. 【請求項４】 第一の突起電極を有する第一の半導体装
置と、前記第一の突起電極よりも硬度の低い第二の突起
電極を有する配線基板あるいは第二の半導体装置とを備
え、前記第一の突起電極の少なくとも一部が前記第二の
突起電極に埋没した構造を有することを特徴とする半導
体装置。4. A first semiconductor device having a first projecting electrode, and a wiring substrate or a second semiconductor device having a second projecting electrode having a hardness lower than that of the first projecting electrode. A semiconductor device having a structure in which at least a part of a first protruding electrode is buried in the second protruding electrode. 【請求項５】 前記第一の半導体装置と、前記第二の半
導体装置あるいは配線基板との間に介在する絶縁性樹脂
をさらに備えることを特徴とする請求項４記載の半導体
装置。5. The semiconductor device according to claim 4, further comprising an insulating resin interposed between the first semiconductor device and the second semiconductor device or the wiring board. 【請求項６】 前記第一及び／又は第二の半導体装置
は、半導体素子の能動面を被覆して形成され、前記半導
体素子の能動面に設けられた素子電極を臨ませた開口部
を有する保護層と、前記開口部の内部において前記素子
電極を被覆するバリア層と、前記バリア層を被覆した拡
散防止層とを備えることを特徴とする請求項４記載の半
導体装置。6. The first and / or second semiconductor device has an opening formed to cover an active surface of a semiconductor element and facing an element electrode provided on the active surface of the semiconductor element. The semiconductor device according to claim 4, further comprising: a protective layer, a barrier layer that covers the element electrode inside the opening, and a diffusion prevention layer that covers the barrier layer. 【請求項７】 前記第一の突起電極は金、パラジウム、
白金、銅及びこれらを主成分とする合金のうちのいずれ
かであることを特徴とする請求項４記載の半導体装置。7. The first bump electrode is gold, palladium,
The semiconductor device according to claim 4, wherein the semiconductor device is one of platinum, copper, and an alloy containing these as main components. 【請求項８】 前記第二の突起電極は、インジウム、イ
ンジウムを主成分とする合金、鉛、鉛を主成分とする合
金のうちのいずれかであること特徴とする請求項４記載
の半導体装置。8. The semiconductor device according to claim 4, wherein the second bump electrode is made of indium, an alloy containing indium as a main component, lead, or an alloy containing lead as a main component. . 【請求項９】 第一及び第二の半導体装置を備え、前記
第一及び第二の半導体装置のそれぞれは、半導体素子の
能動面を被覆して形成され、前記半導体素子の能動面に
設けられた素子電極を臨ませた開口部を有する保護層
と、前記開口部の内部において前記素子電極を被覆する
バリア層と、前記バリア層を被覆した拡散防止層とを備
えると共に、前記第一の半導体装置の拡散防止層と、前
記第二の半導体装置の拡散防止層との間を、突起電極に
て接合したことを特徴とする半導体装置。9. A semiconductor device comprising first and second semiconductor devices, wherein each of the first and second semiconductor devices is formed by covering an active surface of a semiconductor element, and is provided on the active surface of the semiconductor element. A semiconductor layer having an opening facing the device electrode, a barrier layer covering the device electrode inside the opening, and a diffusion prevention layer covering the barrier layer, and the first semiconductor A semiconductor device, wherein a diffusion prevention layer of the device and a diffusion prevention layer of the second semiconductor device are joined by a protruding electrode. 【請求項１０】 前記突起電極は前記素子電極及び前記
バリア層よりも硬度の低い材料で形成されていることを
特徴とする請求項９記載の半導体装置。10. The semiconductor device according to claim 9, wherein the protruding electrode is formed of a material having a hardness lower than that of the element electrode and the barrier layer. 【請求項１１】 前記第一及び第二の半導体装置との間
に介在する絶縁材をさらに備えることを特徴とする請求
項９記載の半導体装置。11. The semiconductor device according to claim 9, further comprising an insulating material interposed between the first and second semiconductor devices. 【請求項１２】 前記絶縁材は、還元剤が混入された熱
硬化性の絶縁性樹脂であることを特徴とする請求項１１
記載の半導体装置。12. The insulating material is a thermosetting insulating resin mixed with a reducing agent.
The semiconductor device described. 【請求項１３】 前記還元剤の前記絶縁性樹脂に対する
配合比率は４０〜８０体積％であることを特徴とする請
求項１２記載の半導体装置。13. The semiconductor device according to claim 12, wherein the compounding ratio of the reducing agent to the insulating resin is 40 to 80% by volume. 【請求項１４】 半導体素子の能動面を被覆して形成さ
れた保護層の開口部から露出した素子電極上にバリア層
及び拡散防止層形成用膜を無電解めっき法によって形成
する工程と、前記拡散防止層形成用膜上に突起電極を形
成すると共に、前記突起電極と前記拡散防止層形成用膜
との相互拡散によって拡散防止層を形成する工程と、を
含むことを特徴とする半導体装置の製造方法。14. A step of forming a barrier layer and a diffusion prevention layer forming film on an element electrode exposed from an opening of a protective layer formed by covering an active surface of a semiconductor element by an electroless plating method, Forming a projection electrode on the diffusion prevention layer forming film, and forming a diffusion prevention layer by mutual diffusion of the projection electrode and the diffusion preventing layer forming film. Production method. 【請求項１５】 突起電極の形成された第一の半導体装
置と、拡散防止層形成用膜を備えた第二の半導体装置ま
たは配線基板とを接合する方法であって、前記突起電極
及び前記拡散防止層形成用膜とを接触させる工程と、前
記突起電極と前記拡散防止層形成用膜との相互拡散によ
って拡散防止層を形成し、かつ前記第一の半導体装置
と、第二の半導体装置又は前記配線基板とを前記突起電
極により接合する工程とを含むことを特徴とする半導体
装置の製造方法。15. A method for joining a first semiconductor device having a bump electrode formed thereon and a second semiconductor device having a diffusion barrier layer forming film or a wiring substrate, comprising: A step of contacting with a prevention layer forming film, forming a diffusion prevention layer by mutual diffusion of the bump electrode and the diffusion preventing layer forming film, and the first semiconductor device, a second semiconductor device or And a step of bonding the wiring board to the wiring board by the projecting electrode. 【請求項１６】 第一の半導体素子及び第二の半導体素
子又は配線基板上に硬度が異なる第一と第二の突起電極
をそれぞれ形成する工程と、前記第一の突起電極と、前
記第二の突起電極とを位置あわせする工程と、前記第一
と第二の突起電極のうち硬度が高い突起電極の少なくと
も一部を他の突起電極に埋設するように接続する工程と
を含むことを特徴とする半導体装置の製造方法。16. A step of forming first and second projecting electrodes having different hardness on a first semiconductor element and a second semiconductor element or a wiring substrate, respectively, the first projecting electrode, and the second projecting electrode. And a step of connecting at least a part of the protrusion electrode having high hardness among the first and second protrusion electrodes so as to be embedded in another protrusion electrode. And a method for manufacturing a semiconductor device. 【請求項１７】 第一の半導体素子及び第二の半導体素
子又は配線基板上に硬度が異なる第一と第二の突起電極
をそれぞれ形成する工程と、前記第一の突起電極と、前
記第二の突起電極とを位置あわせする工程と、前記第一
と第二の突起電極のうち硬度が高い突起電極の少なくと
も一部を他の突起電極に埋設するように接続する工程と
前記第一及び第二の突起電極の周囲に絶縁材を充填する
工程を含むことを特徴とする半導体装置の製造方法。17. A step of forming first and second projecting electrodes having different hardness on a first semiconductor element and a second semiconductor element or a wiring substrate, respectively, the first projecting electrode, and the second projecting electrode. The step of aligning the protruding electrode with the other protruding electrode, and the step of connecting at least a part of the protruding electrode having high hardness among the first and second protruding electrodes so as to be embedded in another protruding electrode; A method of manufacturing a semiconductor device, comprising the step of filling an insulating material around the second bump electrodes. 【請求項１８】 第一の半導体素子と第二の半導体素子
又は配線基板上に、硬度が異なる第一と第二の突起電極
をそれぞれ形成する工程と、前記第一の突起電極と、前
記第二の突起電極とを位置あわせする工程と、前記第一
及び／又は第二の突起電極の周囲に絶縁性樹脂を塗布す
る工程と、前記第一と第二の突起電極のうち硬度が高い
突起電極の少なくとも一部を他の突起電極に埋設するよ
うに接続する工程と、前記絶縁性樹脂を硬化させる工程
とを含むことを特徴とする半導体装置の製造方法。18. A step of forming first and second projecting electrodes having different hardness on a first semiconductor element and a second semiconductor element or a wiring substrate, respectively, the first projecting electrode, and the second projecting electrode. A step of aligning the second protrusion electrode with each other; a step of applying an insulating resin around the first and / or the second protrusion electrode; and a protrusion having a higher hardness than the first and second protrusion electrodes. A method of manufacturing a semiconductor device, comprising: a step of connecting at least a part of an electrode so as to be embedded in another protruding electrode; and a step of curing the insulating resin. 【請求項１９】 第一の半導体素子と第二の半導体素子
又は配線基板上に、硬度が異なる第一と第二の突起電極
をそれぞれ形成する工程と、前記第一の突起電極と、前
記第二の突起電極とを位置あわせする工程と、前記第一
及び／又は第二の突起電極上に還元剤を含む絶縁性樹脂
を塗布する工程と、前記第一と第二の突起電極のうち硬
度が高い突起電極の少なくとも一部を他の突起電極に埋
設するように接続する工程と、前記絶縁性樹脂を硬化さ
せる工程とを含むことを特徴とする半導体装置の製造方
法。19. A step of forming first and second projecting electrodes having different hardness on a first semiconductor element and a second semiconductor element or a wiring board, respectively, and the first projecting electrode and the second projecting electrode. A step of aligning the second protruding electrode with each other, a step of applying an insulating resin containing a reducing agent on the first and / or the second protruding electrode, and a hardness of the first and second protruding electrodes. A method of manufacturing a semiconductor device, comprising: a step of connecting at least a part of a high protruding electrode so as to be embedded in another protruding electrode; and a step of curing the insulating resin. 【請求項２０】 第一の半導体装置の突起電極と、第二
の半導体装置又は配線基板上の基板電極を接触させる工
程と、還元剤が混入された絶縁性樹脂を第一の半導体装
置の突起電極及び／または第二の半導体装置または配線
基板の基板電極に塗布する工程と、絶縁性樹脂を硬化す
る工程を含むことを特徴とする半導体装置の製造方法。20. A step of bringing the protruding electrode of the first semiconductor device into contact with the substrate electrode of the second semiconductor device or the wiring substrate, and using an insulating resin mixed with a reducing agent, the protruding electrode of the first semiconductor device. A method of manufacturing a semiconductor device, comprising: a step of applying an electrode and / or a substrate electrode of a second semiconductor device or a wiring board; and a step of curing an insulating resin. 【請求項２１】 互いの素子電極が電気的に接合されて
なる第一及び第二の半導体装置又は配線基板と、前記第
一の半導体装置と、前記第二の半導体装置又は前記配線
基板の間に充填され、酸化物を除去する還元剤を含む絶
縁性樹脂層とを備えることを特徴とする半導体装置。21. Between a first and a second semiconductor device or a wiring board in which element electrodes of each are electrically joined, and between the first semiconductor device and the second semiconductor device or the wiring board. And an insulating resin layer containing a reducing agent that removes oxides. 【請求項２２】 半導体素子の能動面を被覆して形成さ
れ、前記半導体素子の能動面に設けられた素子電極を臨
ませた開口部を有する保護層と、前記開口部の内部にお
いて前記素子電極を被覆するバリア層と、前記バリア層
を被覆した拡散防止層と、前記拡散防止層上に設けら
れ、前記素子電極及び前記バリア層よりも硬度が低い突
起電極とを備えた第一の半導体装置と、前記突起電極と
結合された電極を備えた第二の半導体装置と、前記突起
電極と前記電極との近傍に充填され、還元剤が混入され
てなる絶縁性樹脂とを備えることを特徴とする半導体装
置。22. A protective layer formed to cover an active surface of a semiconductor element, the protective layer having an opening facing the element electrode provided on the active surface of the semiconductor element; and the element electrode inside the opening. A first semiconductor device including: a barrier layer that covers the barrier layer; a diffusion prevention layer that covers the barrier layer; and a protrusion electrode that is provided on the diffusion prevention layer and has a hardness lower than that of the element electrode and the barrier layer. And a second semiconductor device including an electrode coupled to the bump electrode, and an insulating resin filled in the vicinity of the bump electrode and the electrode and containing a reducing agent. Semiconductor device.
JP2002199714A 1996-02-23 2002-07-09 Manufacturing method of semiconductor device having protruding electrode Expired - Fee Related JP3931749B2 (en)

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