WO2003005441A1 - Coating material of semiconductor chip, coating method of semiconductor chip and semiconductor device - Google Patents

Coating material of semiconductor chip, coating method of semiconductor chip and semiconductor device Download PDF

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Publication number
WO2003005441A1
WO2003005441A1 PCT/JP2002/005404 JP0205404W WO03005441A1 WO 2003005441 A1 WO2003005441 A1 WO 2003005441A1 JP 0205404 W JP0205404 W JP 0205404W WO 03005441 A1 WO03005441 A1 WO 03005441A1
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WO
WIPO (PCT)
Prior art keywords
semiconductor chip
coating
coating layer
substrate
resin
Prior art date
Application number
PCT/JP2002/005404
Other languages
French (fr)
Japanese (ja)
Inventor
Kenji Kobae
Hidehiko Kira
Norio Kainuma
Hiroshi Kobayashi
Katsutoshi Hirasawa
Takatoyo Yamakami
Masumi Katayama
Original Assignee
Fujitsu Limited
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Application filed by Fujitsu Limited filed Critical Fujitsu Limited
Publication of WO2003005441A1 publication Critical patent/WO2003005441A1/en

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/83909Post-treatment of the layer connector or bonding area
    • H01L2224/83951Forming additional members, e.g. for reinforcing, fillet sealant
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01033Arsenic [As]

Definitions

  • the present invention relates to a semiconductor chip coating material, a semiconductor chip coating method, and a semiconductor device for enclosing dust from a semiconductor chip.
  • the information processing device is operated in an environment where temperature and humidity are controlled.
  • this environment has been increasingly managed including dust.
  • magnetic disk drives are strongly demanded to have large capacity and high storage density with the improvement of computer performance. For this reason, the flying height of the magnetic head from the medium is reduced, and the flying surface of the magnetic head is ultra-smoothed.
  • a semiconductor chip for driving and controlling a magnetic head has been arranged around a magnetic head.
  • the semiconductor chip is made of brittle silicon, dust is generated from the semiconductor chip for various reasons, and the dust enters between the magnetic head and the medium, causing wear of the magnetic recording medium. Various adverse effects occur, such as information rupture. For this reason, semiconductor chips are coated with a coating material in order to seal dust.
  • FIG. 22 shows a method of coating the semiconductor chip 10 with a potting resin.
  • FIG. 23 shows a method in which a coating resin is printed on a semiconductor chip 10 using a mask 11 and the coating resin is cured by heat or irradiated with ultraviolet rays. is there.
  • the resin 14 is supplied by the squeegee 13, so that the viscosity of the resin 14 needs to be increased.
  • the coating area becomes narrow, the resin becomes the semiconductor chip 10 and the mask. 1. There is a possibility that it will not be filled sufficiently during 1 Disclosure of the invention
  • an object of the present invention is to provide a semiconductor chip coating material capable of performing coating without exposing a corner of a semiconductor chip, and a method of coating a semiconductor chip. And a semiconductor device.
  • a coating material for a semiconductor chip according to the present invention includes: a base material; a first coating layer made of a thermosetting resin formed on one side of the base material; and a first coating layer formed on the first coating layer. And a second coating layer made of a resin having a higher flowability at the time of softening than the first coating layer.
  • the method for coating a semiconductor chip according to the present invention includes a step of flip-chip connecting the semiconductor chip to a substrate, and a step of coating a coating material having a coating layer made of a thermosetting resin on one side of a substrate.
  • the coating layer is placed on the semiconductor chip with the layer facing the semiconductor chip side, and the coating material is pressurized and heated to soften the coating layer and to hold the softened coating layer flowing out by surface tension.
  • the method includes a pressing step and a heating step for curing the semiconductor chip while covering the side surface of the semiconductor chip.
  • the softened coating layer is held by surface tension and is cured as it is while covering the side surfaces of the semiconductor chip, so that the corners of the semiconductor chip can be prevented from being exposed.
  • the coating material comprises: a base material; A coating layer made of a thermosetting resin formed, and the coating material is placed on the semiconductor chip with the coating layer facing the semiconductor chip side, and is pressurized and heated.
  • the coating layer that has flowed out is thermoset while being held at surface tension on the substrate surface, the semiconductor chip side surface, and the substrate surface, and covers the semiconductor chip with the substrate. I do. BRIEF DESCRIPTION OF THE FIGURES
  • FIG. 1 is an explanatory view of a coating material
  • FIG. 2 is an explanatory view of a state where a semiconductor chip is coated with the coating material of FIG. 1
  • FIG. 3 is a state where a semiconductor chip is chamfered.
  • Fig. 4 is an explanatory view of a state in which a step portion is formed at an edge of a semiconductor chip.
  • Figs. 5A and 5B show an example in which a bent piece is formed on an FPC sheet to form a base material.
  • FIG. 6 is an explanatory diagram of a coating material without a base material
  • FIG. 7 is an explanatory diagram of a state in which a semiconductor chip is coated with the coating material of FIG. 6,
  • FIG. 8 is a diagram using a mask.
  • FIG. 1 is an explanatory view of a coating material
  • FIG. 2 is an explanatory view of a state where a semiconductor chip is coated with the coating material of FIG. 1
  • FIG. 3 is a state where
  • FIG. 9 is an explanatory view of a state in which a coating resin is injected
  • FIG. 9 is an explanatory view of a state in which ultraviolet light is irradiated using a light diffusion plate in FIG. 8
  • FIG. 10 is a mask in FIG. A state in which light reflecting particles are applied to the inner wall of the hole and irradiated with ultraviolet light
  • FIG. 11 is an explanatory view showing an example of irradiating ultraviolet rays by an ultraviolet irradiator in FIG. 8, and FIGS. 12A and 12B show an ultraviolet irradiator around a coating area.
  • FIG. 13 is an explanatory view showing an example of arrangement, FIG.
  • FIG. 13 is an explanatory view showing an example in which a semiconductor chip is formed in a trapezoidal shape
  • FIG. 14 is a diagram in which air is blown between an underfill material and a lower surface of a mask.
  • FIG. 15 is an explanatory view showing an example in which an underfill material is ground and flattened
  • FIG. 16 is an explanatory view showing a state in which a mask is pressed against an underfill material.
  • FIG. 17 is an explanatory view showing a state in which a cap is attached to the ridge of the semiconductor chip.
  • FIGS. 18A and 18B are explanatory views showing a state in which the ridge of the semiconductor chip is chamfered.
  • 1 9 is semiconductor
  • FIG. 20 is an explanatory view of a state in which a step portion is formed at an edge portion, and FIG. 20 illustrates a fine powder layer.
  • Fig. 21 is an explanatory view of the state of irradiating the fine powder layer with infrared rays, and
  • Fig. 22 is a state of the semiconductor chip with corners exposed by the conventional coating method.
  • FIG. 23 is an explanatory view showing a method of filling a coating resin with a squeegee using a mask.
  • FIG. 1 is an explanatory diagram of a coating material.
  • the coating material 20 includes a substrate 21, a first coating layer 22 made of a thermosetting resin formed on one surface of the substrate 21, and a first coating layer 22 on the first coating layer 22.
  • the second coating layer 23 is formed of a thermosetting resin, and is made of a resin having a higher flowability at the time of softening than the first coating layer 22.
  • the base material 21 is made of, for example, a polyimide resin and preferably has a thickness of about 50 m.
  • the material of the substrate 21 is not necessarily limited to resin.
  • a mixed resin of a thermosetting epoxy resin and an acryl resin as a binder can be used.
  • An ultraviolet curing resin may be further mixed with this mixed resin. However, it is not limited to these.
  • thermosetting epoxy resin for example, a bisphenol A-type thermosetting epoxy resin and a resin such as dicyclopentene can be used.
  • the first coating layer 22 and the second coating layer 23 are formed by adjusting the compounding ratio of the compounded resin so that the flowability when softened once when the resin is thermally cured has the first coating layer. It is adjusted so that the second coating layer 23 is higher than 22.
  • the fluidity is measured in terms of the elastic modulus (Young's modulus)
  • the elasticity at 100 ° C. is about 600 to 900 Pa in the first coating layer 22, and the flow is hardened.
  • a material having low fluidity is preferable, and a material having a softness and good flowability of about 30 to 100 Pa for the second coating layer 23 is preferable.
  • the elastic modulus of the first coating layer 22 is about 8 OOPa, while that of the second coating layer 23 is about 40 Pa. Is preferred.
  • a semiconductor chip 24 is mounted on a substrate 25 by flip-chip connection.
  • the substrate 25 is a wiring substrate, package, FPC, or the like, and is not particularly limited.
  • a sealing resin (underfill material 26) having good flowability such as epoxy resin is filled between the semiconductor chip 24 and the substrate 25 and cured.
  • the above-mentioned coating material 20 and the second coating layer 23 are applied to a semiconductor chip.
  • the substrate is placed on the semiconductor chip 24 toward the 24 side, and is pressed from above the substrate 21 and heated to thermally cure the coating layer.
  • the curing conditions were as follows: curing at 110 ° C for about 30 seconds, and then 150 ° C in an oven.
  • the first coating layer 22 and the second coating layer 23 are both softened and pressurized from above the substrate 21, as shown in FIG. It is pushed out to the side of 4.
  • the second coating layer 23 with good flowability flows out between the lower portion of the side surface of the semiconductor chip 24 and the fillet surface 26 a (inclined surface) of the underfill material 26.
  • the c and both resins flowing between the first coatings layer 2 2 is a side top and base 2 first face of the semiconductor chip 2 4 not very flow resistance, the fillet surface 2 6 a, the semiconductor chip 24 is in contact with the lower surface of the substrate 21, and is held between the fillet surface 26 a and the substrate surface due to surface tension between these surfaces.
  • the highly viscous first coating material 22 does not flow down the side surface of the semiconductor chip 24, is held between the base material 21 and the upper side of the semiconductor chip 24, and is thermally cured.
  • the corners are not exposed, and the dust on the surface of the semiconductor chip 24 can be completely sealed.
  • the base material 21 is larger than the semiconductor chip 24, and it is preferable that the base material 21 be protruded outward from the edge of the semiconductor chip, because the surface tension can be more easily applied.
  • the thicknesses of the first coating layer 22 and the second coating layer 23 are as described above.
  • the ratio is preferably about 4: 1 to 3: 1. This is because if the amount of the second coating layer 23 having good flowability is too large, the second coating layer 23 may flow down and expose the side surface of the semiconductor chip 24.
  • the semiconductor chip 30 is directly coated with the coating material 20 as described above without previously filling the underfill material between the substrate 31 and the semiconductor chip 30.
  • the air between the substrate 31 and the semiconductor chip 30 is sucked and exhausted by a suction tool (not shown) or the like, and the second coating layer 23 with good flowability is filled with an underfill material. It can also be filled as. That is, it serves as both a coating material and an underfill material.
  • the coating layer has a two-layer configuration, but may have a single layer. In this case, as the material of the coating layer, a flowable resin intermediate between the first coating layer 22 and the second coating layer 23 is selected.
  • a UV-curable resin may be used for the coating layer, and a transparent material may be used for the base material 21 to be cured by irradiating UV rays while applying pressure.
  • FIG. 3 shows an example in which a chamfered portion 27 is formed on a ridge of a semiconductor chip 24.
  • FIG. 4 shows an example in which a step 28 is formed on the ridge of the semiconductor chip 24. Also in this case, the use of the above-mentioned coating material 20 (including one having a single coating layer) can further prevent the corners from being exposed.
  • the step portion may be formed on all the ridge portions, or may be formed only on some of the ridge portions.
  • FIG. 5 shows still another embodiment.
  • the semiconductor chip 24 is mounted on an FPC (flexible print circuit) sheet 30 made of a polyimide film or the like, and a bent piece 31 is formed on the FPC sheet near the semiconductor chip 24.
  • the above coating layer (including one and two layers, not shown) is formed on the bent piece 3 la, and the bent piece 31 a is bent on the semiconductor chip 24, pressurized and heated. Heat the coating layer Let it cure. This makes it possible to prevent the corners of the semiconductor chip 24 from being exposed in a very simple manner.
  • a two-layer coating material 20 having no base material 21 is used. That is, the coating material 20 is obtained by simply laminating the first coating layer 22 and the second coating layer 23 similar to the above.
  • the coating material 20 is placed on the semiconductor chip 30 mounted on the substrate 31 with the second coating layer 23 facing the semiconductor chip side, and then, as shown in FIG. As described above, by blowing hot air at a temperature of about 150 ° C. onto the coating material 20 without applying pressure, the coating material 20 is softened so that the sheet-like cheese melts. However, the side surfaces of the semiconductor chip 30 are also covered, and heat curing is performed in this state. Since the first coating layer 22 is made of a resin having low flowability at the time of softening, the corners of the semiconductor chip 30 are not exposed. In this case, the semiconductor chip 30 is directly coated with the coating material 20 as described above without pre-filling the underfill material between the substrate 31 and the semiconductor chip 30.
  • the air between the substrate 31 and the semiconductor chip 30 is suctioned and exhausted by a suction tool (not shown) or the like, and the second coating layer 23 having good flowability is under- laid. It can be filled as one fill material. That is, the coating step and the filling step of the underfill material are combined, and the coating step and the underfill material are combined.
  • FIG. 8 shows still another embodiment.
  • the side of the semiconductor chip 30 mounted on the substrate 31 is covered with the mask 35, and the inside of the hole 36 of the mask 35 rises by the surface tension on the inner wall of the mask hole 36 (
  • the semiconductor chip 30 is covered by injecting a coating resin 37 having a viscosity low enough to cause wet-up.
  • the injected coating resin 37 is cured by heat or ultraviolet light.
  • the coating resin with low viscosity is injected, even if the coating area is small, the coating resin can be filled reliably. Also, by curing as it is, the coating resin 37 is cured in a state where the peripheral part is higher than the central part. Therefore, it is possible to reliably prevent the corners of the semiconductor chip 30 from being exposed.
  • the underfill material may be separately filled in advance, or may be filled with the coating resin 37 and cured.
  • FIG. 9 shows an example in which the light diffusing plate 38 is disposed between the ultraviolet irradiation lamp 39 and the coating resin 37 when the coating resin 37 is cured by ultraviolet light in FIG. In this way, the ultraviolet light is diffused by the light diffusing plate 38 and is evenly applied to the coating resin 37, so that the narrow part of the mask hole 36 is also irradiated with the ultraviolet light. Can be prevented.
  • FIG. 10 shows light reflecting particles 40 such as glass fixed with a binder on the wall surface of the mask hole 36 or the side surface of the semiconductor chip 30 when the coating resin 37 is cured by ultraviolet light in FIG. An example in which is applied.
  • the ultraviolet rays are irregularly reflected by the light reflecting particles, and the ultraviolet rays are irradiated deep inside the mask hole 36, so that the generation of the uncured portion can be prevented.
  • Fig. 11 shows that, in Fig. 8, when the coating resin 3 is cured by ultraviolet light, the ultraviolet irradiator 41 is inserted so that its tip is located at the lower part of the mask hole 36, and the mask hole 36
  • An example is shown in which after curing the resin in the lower part, the irradiator 41 is pulled up, and the whole is irradiated with ultraviolet light to cure the coating resin 37. This can also prevent the generation of uncured portions.
  • Fig. 12 shows an ultraviolet curing unit 41 arranged in a strip around the coating area and supplying the coating resin while irradiating the ultraviolet rays to prevent the resin from protruding outside the area and to cure the uncured area. An example of preventing the occurrence of the error will be described.
  • Fig. 13 shows the case where the coating resin 37 in Fig. 8 is cured with ultraviolet light.
  • the ultraviolet light is irradiated to the bottom of the mask hole 36, and the coating is performed. An example of preventing the occurrence of an uncured portion of the resin 37 will be described.
  • FIG. 14 shows the case of FIG. 8 in which the resin flows from the nozzle 42 into the gap from the side to prevent resin from flowing out from the gap between the underfill material 26 and the bottom of the mask hole 36.
  • An example is shown in which the coating resin 37 is injected while blowing.
  • Fig. 15 shows the underfill material 26 beforehand so that the surface is flat. After grinding the fill material 26, the mask 35 is placed to make the underfill material
  • Figure 16 shows that when the underfill material 26 is thermally cured, the mask 35 is pressed against the still uncured underfill material 26, thereby forming the underfill material 26 and the bottom of the mask hole 36. An example in which a gap is prevented from occurring is shown. This can prevent the coating resin 37 from flowing out. At the same time as the underfill material 26 is hardened, the coating resin 37 is injected, and the underfill material 26 and the coating resin are cured.
  • FIG. 17 shows a state in which a cap 45 capable of covering the ridge of the upper surface of the semiconductor chip 30 is attached to the semiconductor chip 30 in advance, and then the semiconductor chip 30 is coated with the coating resin 43.
  • the coating resin 43 is an example. Since the corners of the semiconductor chip 30 are covered with the cap 45, they are not exposed. In this case, the coating resin
  • thermosetting resin or an ultraviolet curable resin a conventional material (a thermosetting resin or an ultraviolet curable resin) can be used. 4 6 are bumps.
  • FIG. 18 shows the chamfered portion of the semiconductor chip 30 as shown in FIG. 18 (b).
  • the 43 may be a normal resin (a thermosetting resin or an ultraviolet curable resin), but has an intermediate flowability between the first coating layer 22 and the second coating layer 23 It is preferable to use a resin.
  • FIG. 19 shows an example in which a step portion 48 is formed at a ridge portion on the upper surface of the semiconductor chip 30.
  • the coating resin 43 may be a normal resin (a thermosetting resin or a UV-curable resin), but may be an intermediate flow between the first coating layer 22 and the second coating layer 23. It is preferable to use a resin having properties.
  • Figure 20 shows the surface of the semiconductor chip 30, epoxy resin mixed with a binder, etc.
  • Resin fine powder is sprayed to form a fine powder layer 50 having a thickness of about 5 to 10 / im, and then a coating resin 43 is applied on the fine powder layer 50, and then thermosetting or ultraviolet curing An example is shown below.
  • the coating resin 43 may be a normal resin (a thermosetting resin or an ultraviolet curable resin), but a resin having an intermediate flowability between the first coating layer 22 and the second coating layer 23 may be used. It is preferred to use.
  • Fig. 21 shows a fine powder layer 50 with a thickness of about 10 to 15 m formed by spraying resin fine powder such as epoxy resin mixed with a binder on the surface of the semiconductor chip 30 and then using infrared rays.
  • resin fine powder such as epoxy resin mixed with a binder
  • irradiation lamp 51 An example in which the fine powder layer 50 is heated and cured by the irradiation lamp 51 will be described. The so-called baking is performed, and the flow of the resin hardly occurs, so that the corner of the semiconductor chip 30 can be prevented from being exposed.
  • the invention's effect is performed, and the flow of the resin hardly occurs, so that the corner of the semiconductor chip 30 can be prevented from being exposed.
  • the softened coating layer As described above, according to the present invention, a state in which the softened coating layer is held by the surface tension between the substrate surface or the fillet surface of the underfill material and the substrate surface, and covers the side surface of the semiconductor chip As a result, the corners of the semiconductor chip can be prevented from being exposed.
  • the softened coating material covers the top and side surfaces of the semiconductor chip so that the sheet-shaped cheese melts, and is cured as it is, so that the corners of the semiconductor chip are exposed. Can be prevented.

Abstract

A method for coating a semiconductor chip without exposing the corner parts thereof. The coating method characterized by comprising the steps of mounting a coating material having a coating layer of thermosetting resin formed on one side of a basic material on the semiconductor chip while directing the coating layer toward the semiconductor chip side, hot pressing the coating material to soften the coating layer, and then curing the fluidized coating layer while holding by surface tension and covering the side face of the semiconductor chip.

Description

明 細 書 半導体チップのコーティング材、 半導体チップのコーティング方法および半導  Description Semiconductor chip coating material, semiconductor chip coating method and semiconductor
技術分野 Technical field
本発明は、 半導体チップからの塵埃を封止込めるための、 半導体チップのコ' ティング材、 半導体チップのコーティング方法および半導体装置に関する。  The present invention relates to a semiconductor chip coating material, a semiconductor chip coating method, and a semiconductor device for enclosing dust from a semiconductor chip.
¾5 ¾5
冃景: 技術 Landscape: Technology
情報処理装置は温度、 湿度を管理した環境下で稼動される。 近年、 さらに、 こ の環境に塵埃を含めて管理されるようになっている。 例えば磁気ディスク装置は コンピュータの性能向上に伴い、 大容量化、 高記憶密度化が強く望まれている。 このため、 媒体からの磁気ヘッドの浮上量を小さくしたり、 磁気ヘッドの浮上面 を超平滑化することが行われている。 一方では、 高速化のために、 磁気ヘッドを 駆動制御する半導体チップを磁気へッドの周辺に配置することが行われている。 しかし、 半導体チップは、 脆いシリコンを素材としているために、 種々の原因で 半導体チップから塵埃が発生し、この塵埃が磁気へッドと媒体との間に入り込み、 磁気記録媒体の摩耗が起こり、情報の破壌が生じるなど、種々の弊害が発生する。 そのため、 塵埃を封止込めるために、 半導体チップをコーティング材で被覆す るようにしている。  The information processing device is operated in an environment where temperature and humidity are controlled. In recent years, this environment has been increasingly managed including dust. For example, magnetic disk drives are strongly demanded to have large capacity and high storage density with the improvement of computer performance. For this reason, the flying height of the magnetic head from the medium is reduced, and the flying surface of the magnetic head is ultra-smoothed. On the other hand, for speeding up, a semiconductor chip for driving and controlling a magnetic head has been arranged around a magnetic head. However, since the semiconductor chip is made of brittle silicon, dust is generated from the semiconductor chip for various reasons, and the dust enters between the magnetic head and the medium, causing wear of the magnetic recording medium. Various adverse effects occur, such as information rupture. For this reason, semiconductor chips are coated with a coating material in order to seal dust.
コーティング材で被覆するには種々の方法がある。  There are various methods for coating with a coating material.
図 2 2に示すのは、 半導体チップ 1 0をポッティング樹脂で被覆する方法であ る。  FIG. 22 shows a method of coating the semiconductor chip 10 with a potting resin.
また、 図 2 3に示すのは、 半導体チップ 1 0上に、 マスク 1 1を用いてコ一テ イング樹脂を印刷し、 このコーティング樹脂を熱硬化させたり、 紫外線を照射し て硬化させる方法である。  FIG. 23 shows a method in which a coating resin is printed on a semiconductor chip 10 using a mask 11 and the coating resin is cured by heat or irradiated with ultraviolet rays. is there.
しかし、 半導体チップ 1 0をポッティング樹脂で覆う方法は、 ポッティング樹 脂が液状であることから、 図 2 2に示すように、 ポッティング樹脂 1 2が表面張 力により基板側へ引っ張られ、 半導体チップ 1 0の角部が露出し、 十分な被覆効 果が得られないという課題がある。 もちろん、 十分な量のポッティング樹脂を用 レ ^れば、半導体チップ 1 0の角部を露出させることなく被覆することができるが、 コーティングエリアが増大し、 小型化の要請に反する。 要するに、 少ない量のコ 一ティング材で十分な被覆効果を得たいのである。 However, in the method of covering the semiconductor chip 10 with the potting resin, since the potting resin is in a liquid state, as shown in FIG. There is a problem that the semiconductor chip 10 is pulled to the substrate side by the force and the corners of the semiconductor chip 10 are exposed, so that a sufficient covering effect cannot be obtained. Of course, if a sufficient amount of potting resin is used, it is possible to coat the semiconductor chip 10 without exposing the corners thereof, but this increases the coating area and contradicts the demand for miniaturization. In short, we want to obtain a sufficient coating effect with a small amount of coating material.
また、 上記の印刷方法によるときは、 樹脂をスキージ 1 3で供給するため、 樹 脂 1 4の粘度を高くする必要があるが、 コ一ティングエリアが狭くなると、 樹脂 が半導体チップ 1 0とマスク 1. 1の間に十分充填されないおそれがある。 発明の開示  In addition, when the printing method described above is used, the resin 14 is supplied by the squeegee 13, so that the viscosity of the resin 14 needs to be increased. However, when the coating area becomes narrow, the resin becomes the semiconductor chip 10 and the mask. 1. There is a possibility that it will not be filled sufficiently during 1 Disclosure of the invention
そこで、 本発明は上記課題を解決すべくなされたものであり、 その目的とする ところは、 半導体チップの角部を露出させることなくコーティングが行える半導 体チップのコーティング材、 半導体チップのコーティング方法および半導体装置 を提供するにある。  Therefore, the present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide a semiconductor chip coating material capable of performing coating without exposing a corner of a semiconductor chip, and a method of coating a semiconductor chip. And a semiconductor device.
本発明に係る半導体チップのコ一ティング材は、 基材と、 この基材の片面側に 形成された熱硬化性樹脂からなる第 1のコーティング層と、 該第 1のコーティン グ層上に形成され、 熱硬化性樹脂樹脂であって、 前記第 1のコーティング廇より も、 軟化時の流れ性の高い樹脂からなる第 2のコ一ティング層とからなることを 特徴とする。  A coating material for a semiconductor chip according to the present invention includes: a base material; a first coating layer made of a thermosetting resin formed on one side of the base material; and a first coating layer formed on the first coating layer. And a second coating layer made of a resin having a higher flowability at the time of softening than the first coating layer.
また本発明に係る半導体チップのコーティング方法は、 半導体チップを基板に フリップチップ接続する工程と、 基材の片面側に熱硬化性樹脂からなるコ一ティ ング層が形成されたコーティング材を、 コーティング層を半導体チップ側に向け て半導体チップ上に載せ、 コーティング材を加圧、 加熱して、 前記コ一ティング 層を軟化せしめると共に、 該軟化して流れ出したコ一ティング層を表面張力で保 持し、 半導体チップの側面を覆った状態で硬化させる加圧、 加熱工程とを含むこ とを特徴としている。  The method for coating a semiconductor chip according to the present invention includes a step of flip-chip connecting the semiconductor chip to a substrate, and a step of coating a coating material having a coating layer made of a thermosetting resin on one side of a substrate. The coating layer is placed on the semiconductor chip with the layer facing the semiconductor chip side, and the coating material is pressurized and heated to soften the coating layer and to hold the softened coating layer flowing out by surface tension. In addition, the method includes a pressing step and a heating step for curing the semiconductor chip while covering the side surface of the semiconductor chip.
これによれば、 軟化したコーティング層が、 表面張力で保持され、 半導体チッ プの側面を覆った状態でそのまま硬化されるので、 半導体チップの角部が露出す るのを防止できる。 また、 本発明に係る半導体装置は、 基板に半導体チップがフリップチップ接続 され、 該半導体チップがコーティング材で被覆された半導体装置において、 前記 コーティング材は、 基材と、 この基材の片面側に形成された熱硬化性樹脂からな るコーティング層とからなり、 該コーティング材が、 前記コーティング層を前記 半導体チップ側に向けて半導体チップ上に載せられ、 加圧、 加熱されることによ り、 流れ出した前記コーティング層が、 前記基材面、 前記半導体チップ側面およ び前記基板面に表面張力で保持された状態で熱硬化されて、 前記基材とで半導体 チップを被覆することを特徴とする。 図面の簡単な説明 According to this, the softened coating layer is held by surface tension and is cured as it is while covering the side surfaces of the semiconductor chip, so that the corners of the semiconductor chip can be prevented from being exposed. Further, in the semiconductor device according to the present invention, in a semiconductor device in which a semiconductor chip is flip-chip connected to a substrate, and the semiconductor chip is coated with a coating material, the coating material comprises: a base material; A coating layer made of a thermosetting resin formed, and the coating material is placed on the semiconductor chip with the coating layer facing the semiconductor chip side, and is pressurized and heated. The coating layer that has flowed out is thermoset while being held at surface tension on the substrate surface, the semiconductor chip side surface, and the substrate surface, and covers the semiconductor chip with the substrate. I do. BRIEF DESCRIPTION OF THE FIGURES
図 1はコーティング材の説明図であり、 図 2は図 1のコ一ティング材により半 導体チップをコ一ティングした状態の説明図であり、 図 3は半導体チップに面取 りをした状態の説明図であり、 図 4は半導体チップの端縁に段差部を形成した状 態の説明図であり、 図 5 Aおよび図 5 Bは F P Cシートに折り曲げ片を形成して 基材とした例を示す説明図であり、 図 6は基材の無いコーティング材の説明図で あり、 図 7は図 6のコ一ティング材により半導体チップをコーティングした状態 の説明図であり、 図 8はマスクを用いてコ一ティング樹脂を注入する状態の説明 図であり、 図 9は図 8のものにおいて光拡散板を用いて紫外線を照射する状態の 説明図であり、 図 1 0は図 8のものにおいてマスク孔内壁に光反射粒子を塗布し て紫外線を照射する状態の説明図であり、 図 1 1は図 8のものにおいて紫外線照 射器により紫外線を照射する例を示す説明図であり、 図 1 2 Aおよび 1 2 Bはコ 一ティングエリア外周に紫外線照射器を配置した例を示す説明図であり、 図 1 3 は半導体チップを台形状に形成した例を示す説明図であり、 図 1 4はアンダーフ ィル材とマスク下面との間にエアーをプロ一する状態の説明図であり、 図 1 5は アンダーフィル材を研削して平坦にした例を示す説明図であり、 図 1 6はアンダ —フィル材にマスクを押し当てた状態を示す説明図であり、 図 1 7は半導体チッ プの稜線部にキヤップを装着した状態の説明図であり、 図 1 8 Aおよび図 1 8 B は半導体チップの稜線部を面取りした状態を示す説明図であり、 図 1 9は半導体  FIG. 1 is an explanatory view of a coating material, FIG. 2 is an explanatory view of a state where a semiconductor chip is coated with the coating material of FIG. 1, and FIG. 3 is a state where a semiconductor chip is chamfered. Fig. 4 is an explanatory view of a state in which a step portion is formed at an edge of a semiconductor chip. Figs. 5A and 5B show an example in which a bent piece is formed on an FPC sheet to form a base material. FIG. 6 is an explanatory diagram of a coating material without a base material, FIG. 7 is an explanatory diagram of a state in which a semiconductor chip is coated with the coating material of FIG. 6, and FIG. 8 is a diagram using a mask. FIG. 9 is an explanatory view of a state in which a coating resin is injected, FIG. 9 is an explanatory view of a state in which ultraviolet light is irradiated using a light diffusion plate in FIG. 8, and FIG. 10 is a mask in FIG. A state in which light reflecting particles are applied to the inner wall of the hole and irradiated with ultraviolet light FIG. 11 is an explanatory view showing an example of irradiating ultraviolet rays by an ultraviolet irradiator in FIG. 8, and FIGS. 12A and 12B show an ultraviolet irradiator around a coating area. FIG. 13 is an explanatory view showing an example of arrangement, FIG. 13 is an explanatory view showing an example in which a semiconductor chip is formed in a trapezoidal shape, and FIG. 14 is a diagram in which air is blown between an underfill material and a lower surface of a mask. FIG. 15 is an explanatory view showing an example in which an underfill material is ground and flattened, and FIG. 16 is an explanatory view showing a state in which a mask is pressed against an underfill material. FIG. 17 is an explanatory view showing a state in which a cap is attached to the ridge of the semiconductor chip. FIGS. 18A and 18B are explanatory views showing a state in which the ridge of the semiconductor chip is chamfered. 1 9 is semiconductor
)端縁部に段差部を形成した状態の説明図であり、 図 2 0は微粉末層を形 成した状態の説明図であり、 図 2 1は微粉末層に赤外線を照射する状態の説明図 であり.、 図 2 2は従来のコーティング方法によって半導体チップの角部が露出し た状態を示す説明図であり、 図 2 3はマスクを用いてコーティング樹脂をスキー ジにより充填する方法を示す説明図である。 発明を実施するための最良の形態 FIG. 20 is an explanatory view of a state in which a step portion is formed at an edge portion, and FIG. 20 illustrates a fine powder layer. Fig. 21 is an explanatory view of the state of irradiating the fine powder layer with infrared rays, and Fig. 22 is a state of the semiconductor chip with corners exposed by the conventional coating method. FIG. 23 is an explanatory view showing a method of filling a coating resin with a squeegee using a mask. BEST MODE FOR CARRYING OUT THE INVENTION
以下本発明の好適な実施例を添付図面に基づいて詳細に説明する。  Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.
(第 1実施例)  (First embodiment)
図 1は、 コーティング材の説明図である。  FIG. 1 is an explanatory diagram of a coating material.
コーティング材 2 0は、 基材 2 1と、 この基材 2 1の片面側に形成された熱硬 化性樹脂からなる第 1のコーティング層 2 2と、 該第 1のコーティング層 2 2上 に形成され、 熱硬化性樹脂であって、 第 1のコーティング層 2 2よりも、 軟化時 の流れ性の高い樹脂からなる第 2のコーティング層 2 3とからなる。  The coating material 20 includes a substrate 21, a first coating layer 22 made of a thermosetting resin formed on one surface of the substrate 21, and a first coating layer 22 on the first coating layer 22. The second coating layer 23 is formed of a thermosetting resin, and is made of a resin having a higher flowability at the time of softening than the first coating layer 22.
基材 2 1は、 例えばポリイミド樹脂からなり、 厚さは 5 0 m程度が好適であ る。 基材 2 1の材質は必ずしも樹脂に限定されない。  The base material 21 is made of, for example, a polyimide resin and preferably has a thickness of about 50 m. The material of the substrate 21 is not necessarily limited to resin.
第 1のコーティング層 2 2は、 熱硬化型のエポキシ樹脂、 バインダーとしての ァクリル樹脂の混合樹脂を用いることができる。 この混合樹脂にさらに紫外線硬 化型樹脂を混合してもよい。 しかし、 これらに限定されることはない。  For the first coating layer 22, a mixed resin of a thermosetting epoxy resin and an acryl resin as a binder can be used. An ultraviolet curing resin may be further mixed with this mixed resin. However, it is not limited to these.
第 2のコーティング層 2 3は、 熱硬化型のエポキシ樹脂、 例えばビスフエノー ル A型の熱硬化性のエポキシ樹脂と、 ジシクロペン夕ジェン等の樹脂の混合体を 用いることができる。  For the second coating layer 23, a mixture of a thermosetting epoxy resin, for example, a bisphenol A-type thermosetting epoxy resin and a resin such as dicyclopentene can be used.
第 1のコーティング層 2 2と第 2のコーティング層 2 3とは、 配合樹脂の配合 率を調整して、 熱硬化させる際、 一旦軟化するときの流れ性が、 第 1のコ一ティ ング層 2 2よりも第 2のコーティング層 2 3の方が高くなるように調整する。 流れ性を例えば弾性率(ヤング率) でみれば、 1 0 0 °Cでの弾性率が、 第 1のコ —ティング層 2 2では 6 0 0〜9 0 0 P a程度の、 固めで流れ性の低いものが好 適であり、 また第 2のコーティング層 2 3では 3 0〜 1 0 0 P a程度の、 柔らか く流れ性のよいものが好適であった。 特に弾性率が、 第 1のコーティング層 2 2 では 8 O O P a前後のものが、 第 2のコ一ティング層 2 3では 4 0 P a前後のも のが好適である。 The first coating layer 22 and the second coating layer 23 are formed by adjusting the compounding ratio of the compounded resin so that the flowability when softened once when the resin is thermally cured has the first coating layer. It is adjusted so that the second coating layer 23 is higher than 22. For example, if the fluidity is measured in terms of the elastic modulus (Young's modulus), the elasticity at 100 ° C. is about 600 to 900 Pa in the first coating layer 22, and the flow is hardened. A material having low fluidity is preferable, and a material having a softness and good flowability of about 30 to 100 Pa for the second coating layer 23 is preferable. In particular, the elastic modulus of the first coating layer 22 is about 8 OOPa, while that of the second coating layer 23 is about 40 Pa. Is preferred.
次に半導体チップを上記コ一ティング材 2 0でコーティングする方法について 説明する。  Next, a method of coating a semiconductor chip with the coating material 20 will be described.
図 2に示すように、 まず半導体チップ 2 4を基板 2 5にフリツプチップ接続し て搭載する。 基板 2 5は、 配線基板、 パッケージ、 F P C等で、 特に限定はない。 次に、 半導体チップ 2 4と基板 2 5との間にエポキシ榭脂等の流れ性のよい封 止樹脂 (アンダーフィル材 2 6 ) を充填し、 硬化させる。  As shown in FIG. 2, first, a semiconductor chip 24 is mounted on a substrate 25 by flip-chip connection. The substrate 25 is a wiring substrate, package, FPC, or the like, and is not particularly limited. Next, a sealing resin (underfill material 26) having good flowability such as epoxy resin is filled between the semiconductor chip 24 and the substrate 25 and cured.
次に、 上記コーティング材 2 0を、 第 2のコーティング層 2 3を半導体チップ Next, the above-mentioned coating material 20 and the second coating layer 23 are applied to a semiconductor chip.
2 4側に向けて半導体チップ 2 4上に載せ、 基材 2 1の上から加圧すると共に、 加熱してコーティング層を熱硬化させる。 The substrate is placed on the semiconductor chip 24 toward the 24 side, and is pressed from above the substrate 21 and heated to thermally cure the coating layer.
硬化条件は、 1 1 0 °Cで 3 0秒程度で硬化させた後、 オーブン中で 1 5 0 °C、 The curing conditions were as follows: curing at 110 ° C for about 30 seconds, and then 150 ° C in an oven.
3 0分程度アフターキュアする。 After-cure for about 30 minutes.
上記加熱工程の初期段階で、 第 1のコ一ティング層 2 2、 第 2のコーティング 層 2 3は共に軟化し、 基板 2 1上からの加圧により、 図 2に示すように、 半導体 チップ 2 4の側方に押し出される。 そのとき、 流れ性のよい第 2のコーティング 層 2 3は、 半導体チップ 2 4の側面下部とアンダーフィル材 2 6のフィレット面 2 6 a (傾斜面) との間に流れ出す。 一方、 流れ性のあまり高くない第 1のコー ティング層 2 2は半導体チップ 2 4の側面上部と基材 2 1の面との間に流れ出す c そして両樹脂は、 フィレット面 2 6 a、 半導体チップ 2 4の側面、 基材 2 1の 下面に接触していて、 これら面との間の表面張力により、 フィレット面 2 6 aと 基材面との間に保持される。 In the initial stage of the heating step, the first coating layer 22 and the second coating layer 23 are both softened and pressurized from above the substrate 21, as shown in FIG. It is pushed out to the side of 4. At this time, the second coating layer 23 with good flowability flows out between the lower portion of the side surface of the semiconductor chip 24 and the fillet surface 26 a (inclined surface) of the underfill material 26. Meanwhile, the c and both resins flowing between the first coatings layer 2 2 is a side top and base 2 first face of the semiconductor chip 2 4 not very flow resistance, the fillet surface 2 6 a, the semiconductor chip 24 is in contact with the lower surface of the substrate 21, and is held between the fillet surface 26 a and the substrate surface due to surface tension between these surfaces.
そしてこの状態で熱硬化されるのである。 とりわけ、 粘性の高い第 1のコーテ イング材 2 2は、 半導体チップ 2 4の側面を流れ落ちず、 基材 2 1と半導体チッ プ 2 4の側面上部との間に保持され、 熱硬化されるから、 従来のように角部が露 出されるようなことはなく、 半導体チップ 2 4表面の塵埃を完全に封止込める。 図 2からわかるように、 基材 2 1は半導体チップ 2 4よりも大きく、 半導体チ ップの端縁から外方に突出させるようにすると、 より表面張力を作用させやすい ので好適である。  And it is thermoset in this state. In particular, the highly viscous first coating material 22 does not flow down the side surface of the semiconductor chip 24, is held between the base material 21 and the upper side of the semiconductor chip 24, and is thermally cured. However, unlike the conventional case, the corners are not exposed, and the dust on the surface of the semiconductor chip 24 can be completely sealed. As can be seen from FIG. 2, the base material 21 is larger than the semiconductor chip 24, and it is preferable that the base material 21 be protruded outward from the edge of the semiconductor chip, because the surface tension can be more easily applied.
第 1のコ一ティング層 2 2と第 2のコーティング層 2 3の厚さは、 前記のよう に 4 : 1〜3 : 1程度とするのが好適である。 これは流れ性の良い第 2のコーテ イング層 2 3の量をあまり多くすると、 流れ落ちてしまい、 半導体チップ 2 4の 側面が露出するおそれがあるからである。 The thicknesses of the first coating layer 22 and the second coating layer 23 are as described above. The ratio is preferably about 4: 1 to 3: 1. This is because if the amount of the second coating layer 23 having good flowability is too large, the second coating layer 23 may flow down and expose the side surface of the semiconductor chip 24.
なお、 この場合、 基板 3 1と半導体チップ 3 0との間にアンダーフィル材をぁ らかじめ充填することなく、 半導体チップ 3 0に直接上記のようにしてコーティ ング材 2 0をコーティングし、 このコーティングの際、 基板 3 1と半導体チップ 3 0との間の空気を吸引具 (図示せず) 等により吸引、 排気しつつ、 流れ性のよ い第 2のコーティング層 2 3をアンダーフィル材として充填するようにすること もできる。 すなわち、 コーティング材とアンダーフィル材とを兼ねるのである。 また、 上記では、 コーティング層を 2層構成としたが、 1層であってもよい。 この場合は、 コーティング層の材質として、 上記第 1のコーティング層 2 2と第 2のコーティング層 2 3との中間の流れ性の樹脂を選択することになる。  In this case, the semiconductor chip 30 is directly coated with the coating material 20 as described above without previously filling the underfill material between the substrate 31 and the semiconductor chip 30. During this coating, the air between the substrate 31 and the semiconductor chip 30 is sucked and exhausted by a suction tool (not shown) or the like, and the second coating layer 23 with good flowability is filled with an underfill material. It can also be filled as. That is, it serves as both a coating material and an underfill material. In the above description, the coating layer has a two-layer configuration, but may have a single layer. In this case, as the material of the coating layer, a flowable resin intermediate between the first coating layer 22 and the second coating layer 23 is selected.
また、 コーティング層に紫外線硬化型の樹脂を用い、 基材 2 1に透明材料を用 いて、 加圧しつつ紫外線を照射して硬化させるようにしてもよい。  Alternatively, a UV-curable resin may be used for the coating layer, and a transparent material may be used for the base material 21 to be cured by irradiating UV rays while applying pressure.
図 3は、 半導体チップ 2 4の稜線部に面取り部 2 7を形成した例を示す。 この ように稜線部を面取りすることによって、 コーナ一部の角度が大きくなるから、 上記のコーティング材 2 0 (コーティング層が 1層のものも含む) を用いること により、 より一層角部の露出を防止することができる。 面取りは全ての稜線部に 行ってもよいし、 一部の稜線部だけであってもよい。  FIG. 3 shows an example in which a chamfered portion 27 is formed on a ridge of a semiconductor chip 24. By chamfering the ridge line in this way, the angle of a part of the corner becomes large. Therefore, by using the above-mentioned coating material 20 (including one having a single coating layer), the corner portion can be further exposed. Can be prevented. Chamfering may be performed on all ridges or only some ridges.
図 4は、 半導体チップ 2 4の稜線部に段差部 2 8を形成した例を示す。 これに よっても、 上記のコ一ティング材 2 0 (コーティング層が 1層のものも含む) を 用いることによって、 より一層角部の露出を防止することができる。 段差部は全 ての稜線部に形成してもよいし、 一部の稜線部だけに形成してもよい。  FIG. 4 shows an example in which a step 28 is formed on the ridge of the semiconductor chip 24. Also in this case, the use of the above-mentioned coating material 20 (including one having a single coating layer) can further prevent the corners from being exposed. The step portion may be formed on all the ridge portions, or may be formed only on some of the ridge portions.
図 5はさらに他の実施例を示す。  FIG. 5 shows still another embodiment.
本実施例では、 半導体チップ 2 4をポリイミドフィルム等からなる F P C (フ レキシブルプリントサ一キット) シート 3 0上に搭載し、 この半導体チップ 2 4 の近傍の F P Cシートに折り曲げ片 3 1を形成し、 この折り曲げ片 3 l aに上記 のコーティング層 (1層、 2層を含む。 図示せず) を形成しておいて、 折り曲げ 片 3 1 aを半導体チップ 2 4上に折り曲げ、 加圧、 加熱してコーティング層を熱 硬化させるのである。 このようにすれば、 非常に簡単な方法で、 半導体チップ 2 4の角部の露出を防止することができる。 In this embodiment, the semiconductor chip 24 is mounted on an FPC (flexible print circuit) sheet 30 made of a polyimide film or the like, and a bent piece 31 is formed on the FPC sheet near the semiconductor chip 24. The above coating layer (including one and two layers, not shown) is formed on the bent piece 3 la, and the bent piece 31 a is bent on the semiconductor chip 24, pressurized and heated. Heat the coating layer Let it cure. This makes it possible to prevent the corners of the semiconductor chip 24 from being exposed in a very simple manner.
図 6、 図 7は他の実施例を示す。  6 and 7 show another embodiment.
本実施例では、 基材 2 1を有しない、 2層のコーティング材 2 0を用いる。 すなわち、 コーティング材 2 0は、 上記と同様の第 1のコーティング層 2 2と 第 2のコーティング層 2 3とを単に積層したものである。  In this embodiment, a two-layer coating material 20 having no base material 21 is used. That is, the coating material 20 is obtained by simply laminating the first coating layer 22 and the second coating layer 23 similar to the above.
このコーティング材 2 0を、 図 6に示すように、 基板 3 1上に実装した半導体 チップ 3 0上に第 2のコーティング層 2 3を半導体チップ側に向けて載せ、次に、 図 7に示すように、 加圧することなく、 1 5 0 °C程度の温度の熱風をコーティン グ材 2 0にブローすることにより、あたかもシ一ト状のチーズがとろけるように、 コーティング材 2 0を軟化させて、 半導体チップ 3 0の側面も覆わせ、 この状態 で熱硬化させるのである。 第 1のコーティング層 2 2に、 軟化時の流れ性の低い 樹脂を用いているので、 半導体チップ 3 0の角部が露出するということはない。 なお、 この場合、 基板 3 1と半導体チップ 3 0との間にアンダーフィル材をぁ らかじめ充填することなく、 半導体チップ 3 0に直接上記のようにしてコ一ティ ング材 2 0をコーティングし、 このコーティングの際、 基板 3 1と半導体チップ 3 0との間の空気を吸引具 (図示せず) 等により吸引、 排気しつつ、 流れ性のよ い第 2のコーティング層 2 3をアンダ一フィル材として充填するようにすること もできる。すなわち、コーティング工程とアンダーフィル材の充填工程とを兼ね、 またコーティング材とアンダーフィル材とを兼ねるのである。  As shown in FIG. 6, the coating material 20 is placed on the semiconductor chip 30 mounted on the substrate 31 with the second coating layer 23 facing the semiconductor chip side, and then, as shown in FIG. As described above, by blowing hot air at a temperature of about 150 ° C. onto the coating material 20 without applying pressure, the coating material 20 is softened so that the sheet-like cheese melts. However, the side surfaces of the semiconductor chip 30 are also covered, and heat curing is performed in this state. Since the first coating layer 22 is made of a resin having low flowability at the time of softening, the corners of the semiconductor chip 30 are not exposed. In this case, the semiconductor chip 30 is directly coated with the coating material 20 as described above without pre-filling the underfill material between the substrate 31 and the semiconductor chip 30. At the time of this coating, the air between the substrate 31 and the semiconductor chip 30 is suctioned and exhausted by a suction tool (not shown) or the like, and the second coating layer 23 having good flowability is under- laid. It can be filled as one fill material. That is, the coating step and the filling step of the underfill material are combined, and the coating step and the underfill material are combined.
図 8はさらに他の実施例を示す。  FIG. 8 shows still another embodiment.
本実施例では、 まず、 基板 3 1に実装された半導体チップ 3 0の側方をマスク 3 5で覆い、 マスク 3 5の孔 3 6内に、 マスク孔 3 6内壁に表面張力により這い 上がり (濡れ上がり) を生じるだけの粘度の低いコーティング樹脂 3 7を注入し て半導体チップ 3 0を覆う。 次いで、 注入したコーティング樹脂 3 7を熱硬化も しくは紫外線硬化させるのである。  In this embodiment, first, the side of the semiconductor chip 30 mounted on the substrate 31 is covered with the mask 35, and the inside of the hole 36 of the mask 35 rises by the surface tension on the inner wall of the mask hole 36 ( The semiconductor chip 30 is covered by injecting a coating resin 37 having a viscosity low enough to cause wet-up. Next, the injected coating resin 37 is cured by heat or ultraviolet light.
粘度の低いコーティング樹脂を注入するので、 コーティングエリアが狭い場合 であっても、 コーティング樹脂を確実に充填できる。 また、 そのまま硬化させる ことにより、 コーティング樹脂 3 7が中央部より周辺部が高くなる状態で硬化さ れるので、 半導体チップ 3 0の角部が露出するのを確実に防止できる。 アンダー フィル材はあらかじめ別途充填しておいてもよいし、 コーティング樹脂 3 7を充 填して硬化させるようにすることもできる。 Since the coating resin with low viscosity is injected, even if the coating area is small, the coating resin can be filled reliably. Also, by curing as it is, the coating resin 37 is cured in a state where the peripheral part is higher than the central part. Therefore, it is possible to reliably prevent the corners of the semiconductor chip 30 from being exposed. The underfill material may be separately filled in advance, or may be filled with the coating resin 37 and cured.
図 9は、 図 8において、 コーティング樹脂 3 7を紫外線硬化させる場合におい て、 紫外線照射ランプ 3 9とコーティング樹脂 3 7との間に光拡散板 3 8を配置 させた例を示す。 このようにすると、 紫外線が光拡散板 3 8により拡散されて、 コーティング樹脂 3 7に均等に照射され、 マスク孔 3 6の狭い個所にも紫外線が 照射されることとなり、 未硬化部分の発生を防ぐことができる。  FIG. 9 shows an example in which the light diffusing plate 38 is disposed between the ultraviolet irradiation lamp 39 and the coating resin 37 when the coating resin 37 is cured by ultraviolet light in FIG. In this way, the ultraviolet light is diffused by the light diffusing plate 38 and is evenly applied to the coating resin 37, so that the narrow part of the mask hole 36 is also irradiated with the ultraviolet light. Can be prevented.
図 1 0は、 図 8において、 コーティング樹脂 3 7を紫外線硬化させる場合にお いて、 マスク孔 3 6の壁面や半導体チップ 3 0の側面に、 バインダーで固めたガ ラス等の光反射粒子 4 0を塗布した例を示す。 このようにすると、 紫外線が光反 射粒子により乱反射されて、 紫外線がマスク孔 3 6内深くまで照射され、 未硬化 部分の発生を防止することができる。  FIG. 10 shows light reflecting particles 40 such as glass fixed with a binder on the wall surface of the mask hole 36 or the side surface of the semiconductor chip 30 when the coating resin 37 is cured by ultraviolet light in FIG. An example in which is applied. In this case, the ultraviolet rays are irregularly reflected by the light reflecting particles, and the ultraviolet rays are irradiated deep inside the mask hole 36, so that the generation of the uncured portion can be prevented.
図 1 1は、 図 8において、 コーティング樹脂 3マを紫外線硬化させる場合にお いて、 紫外線照射器 4 1をその先端がマスク孔 3 6の低部に位置するように挿入 し、 マスク孔 3 6低部の樹脂を硬化させた後、 照射器 4 1を引き上げ、 全体に紫 外線を照射してコーティング樹脂 3 7を硬化される例を示す。 これによつても未 硬化部分の発生を防止できる。  Fig. 11 shows that, in Fig. 8, when the coating resin 3 is cured by ultraviolet light, the ultraviolet irradiator 41 is inserted so that its tip is located at the lower part of the mask hole 36, and the mask hole 36 An example is shown in which after curing the resin in the lower part, the irradiator 41 is pulled up, and the whole is irradiated with ultraviolet light to cure the coating resin 37. This can also prevent the generation of uncured portions.
図 1 2は、 紫外線照射器 4 1をコーティングエリァ外周に帯状に複数配置し、 紫外線を照射しながら、 コーティング樹脂を供給することにより、 エリア外への 樹脂のはみ出しを防止しつつ未硬化部分の発生を防止する例を示す。  Fig. 12 shows an ultraviolet curing unit 41 arranged in a strip around the coating area and supplying the coating resin while irradiating the ultraviolet rays to prevent the resin from protruding outside the area and to cure the uncured area. An example of preventing the occurrence of the error will be described.
図 1 3は、 図 8において、 コーティング樹脂 3 7を紫外線硬化させる場合にお いて、 半導体チップ 3 0の形状を台形に形成することにより、 紫外線がマスク孔 3 6の底部にまで照射され、 コーティング樹脂 3 7の未硬化部分の発生を防止す る例を示す。  Fig. 13 shows the case where the coating resin 37 in Fig. 8 is cured with ultraviolet light. By forming the shape of the semiconductor chip 30 into a trapezoid, the ultraviolet light is irradiated to the bottom of the mask hole 36, and the coating is performed. An example of preventing the occurrence of an uncured portion of the resin 37 will be described.
図 1 4は、 図 8の場合において、 アンダーフィル材 2 6とマスク孔 3 6の底部 との隙間から樹脂が流出するのを防止するため、 側方から該隙間内にノズル 4 2 からエア一を吹き込みつつコ一ティング樹脂 3 7を注入する例を示す。  FIG. 14 shows the case of FIG. 8 in which the resin flows from the nozzle 42 into the gap from the side to prevent resin from flowing out from the gap between the underfill material 26 and the bottom of the mask hole 36. An example is shown in which the coating resin 37 is injected while blowing.
図 1 5は、 アンダーフィル材 2 6の表面が平らになるようにあらかじめアンダ 一フィル材 2 6を研削した後、 マスク 3 5を配置することで、 アンダーフィル材Fig. 15 shows the underfill material 26 beforehand so that the surface is flat. After grinding the fill material 26, the mask 35 is placed to make the underfill material
2 6とマスク孔 3 6底部との間に隙間が生じるのを防止した例を示す。 これによ り、 コーティング樹脂 3 7が流出するのを防止できる。 An example in which a gap is prevented from occurring between 26 and the bottom of the mask hole 36 will be described. This can prevent the coating resin 37 from flowing out.
図 1 6は、 アンダーフィル材 2 6の熱硬化時に、 まだ未硬化状態のアンダーフ ィル材 2 6にマスク 3 5を押し当て、 これにより、 アンダーフィル材 2 6とマス ク孔 3 6底部との間に隙間が生じるのを防止する例を示す。 これにより、 コーテ イング樹脂 3 7の流出を防止できる。 なお、 アンダーフィル材 2 6の硬化時に同 時にコ一ティング樹脂 3 7を注入し、 アンダーフィル材 2 6とコーティング樹脂 Figure 16 shows that when the underfill material 26 is thermally cured, the mask 35 is pressed against the still uncured underfill material 26, thereby forming the underfill material 26 and the bottom of the mask hole 36. An example in which a gap is prevented from occurring is shown. This can prevent the coating resin 37 from flowing out. At the same time as the underfill material 26 is hardened, the coating resin 37 is injected, and the underfill material 26 and the coating resin are cured.
3 7とを同時に硬化させるようにしてもよい。 3 and 7 may be cured at the same time.
図 1 7は、 半導体チップ 3 0の上面の稜線部を覆うことのできるキャップ 4 5 をあらかじめ半導体チップ 3 0に装着した後、 コーティング榭脂 4 3により、 半 導体チップ 3 0をコ一ティングする例を示す。 半導体チップ 3 0の角部はキヤッ プ 4 5に覆われるので露出することはない。 なお、 この場合のコーティング樹脂 FIG. 17 shows a state in which a cap 45 capable of covering the ridge of the upper surface of the semiconductor chip 30 is attached to the semiconductor chip 30 in advance, and then the semiconductor chip 30 is coated with the coating resin 43. Here is an example. Since the corners of the semiconductor chip 30 are covered with the cap 45, they are not exposed. In this case, the coating resin
3 7は、 従前の材料 (熱硬化性樹脂あるいは紫外線硬化性樹脂) を用いることが できる。 4 6はバンプである。 For 37, a conventional material (a thermosetting resin or an ultraviolet curable resin) can be used. 4 6 are bumps.
図 1 8は、 半導体チップ 3 0の稜線部に、 図 1 8 ( b ) に示すように面取り部 FIG. 18 shows the chamfered portion of the semiconductor chip 30 as shown in FIG. 18 (b).
4 7を形成した例を示す。 このように面取り部 4 7を形成することで、 半導体チ ップ 3 0の角部の角度が鈍角になるので、 コーティング樹脂 4 3で半導体チップAn example in which 47 is formed is shown. By forming the chamfered portion 47 in this manner, the angle of the corner of the semiconductor chip 30 becomes obtuse, so that the semiconductor chip is coated with the coating resin 43.
3 0をコーティングした際、 角部が露出するのを防止できる。 コーティング樹脂Exposed corners can be prevented when 30 is coated. Coating resin
4 3は、 通常の樹脂 (熱硬化性樹脂あるいは紫外線硬化性樹脂) でもよいが、 前 記第 1のコ一ティング層 2 2と第 2のコーティング層 2 3との中間の流れ性を有 する樹脂を用いると好適である。 43 may be a normal resin (a thermosetting resin or an ultraviolet curable resin), but has an intermediate flowability between the first coating layer 22 and the second coating layer 23 It is preferable to use a resin.
図 1 9は、 半導体チップ 3 0の上面の稜線部に、 段差部 4 8を形成した例を示 す。 このように段差部 4 8を形成することで、 段差部 4 8が樹脂溜まりとなるの で、 コーティング樹脂 4 3で半導体チップ 3 0をコーティングした際、 角部が露 出するのを防止できる。 コ一ティング樹脂 4 3は、 通常の樹脂 (熱硬化性樹脂あ るいは紫外線硬化性榭脂) でもよいが、 前記第 1のコーティング層 2 2と第 2の コーティング層 2 3との中間の流れ性を有する樹脂を用いると好適である。 図 2 0は、 半導体チップ 3 0の表面に、 バインダーに混合したエポキシ樹脂等 の樹脂微粉末を散布して 5〜1 0 /i m程度の厚さの微粉末層 5 0を形成した後、 この微粉末層 5 0上にコーティング樹脂 4 3を塗布し、 熱硬化もしくは紫外線硬 化させた例を示す。 微粉末層 5 0を形成することで、 表面張力の低下、 あるいは 表面抵抗の増大により、コーティング樹脂 4 3の流れ性を低下させることができ、 半導体チップ 3 0の角部の露出を防止することができる。 コーティング樹脂 4 3 は、 通常の樹脂 (熱硬化性樹脂あるいは紫外線硬化性樹脂) でもよいが、 前記第 1のコーティング層 2 2と第 2のコーティング層 2 3との中間の流れ性を有する 樹脂を用いると好適である。 FIG. 19 shows an example in which a step portion 48 is formed at a ridge portion on the upper surface of the semiconductor chip 30. By forming the step portion 48 in this way, the step portion 48 becomes a pool of resin, so that when the semiconductor chip 30 is coated with the coating resin 43, the corner portion can be prevented from being exposed. The coating resin 43 may be a normal resin (a thermosetting resin or a UV-curable resin), but may be an intermediate flow between the first coating layer 22 and the second coating layer 23. It is preferable to use a resin having properties. Figure 20 shows the surface of the semiconductor chip 30, epoxy resin mixed with a binder, etc. Resin fine powder is sprayed to form a fine powder layer 50 having a thickness of about 5 to 10 / im, and then a coating resin 43 is applied on the fine powder layer 50, and then thermosetting or ultraviolet curing An example is shown below. By forming the fine powder layer 50, the flowability of the coating resin 43 can be reduced due to a decrease in surface tension or an increase in surface resistance, thereby preventing the corners of the semiconductor chip 30 from being exposed. Can be. The coating resin 43 may be a normal resin (a thermosetting resin or an ultraviolet curable resin), but a resin having an intermediate flowability between the first coating layer 22 and the second coating layer 23 may be used. It is preferred to use.
図 2 1は、 半導体チップ 3 0の表面に、 バインダーに混合したエポキシ樹脂等 の樹脂微粉末を散布して 1 0〜1 5 m程度の厚さの微粉末層 5 0を形成した後、 赤外線照射ランプ 5 1により微粉末層 5 0を加熱し、 硬化させる例を示す。 いわ ゆる、 焼きつけを行うものであり、 樹脂の流れは生じがたく、 半導体チップ 3 0 の角部の露出を防止できる。 発明の効果  Fig. 21 shows a fine powder layer 50 with a thickness of about 10 to 15 m formed by spraying resin fine powder such as epoxy resin mixed with a binder on the surface of the semiconductor chip 30 and then using infrared rays. An example in which the fine powder layer 50 is heated and cured by the irradiation lamp 51 will be described. The so-called baking is performed, and the flow of the resin hardly occurs, so that the corner of the semiconductor chip 30 can be prevented from being exposed. The invention's effect
以上のように、 本発明によれば、 軟化したコーティング層が、 基板面もしくは アンダーフィル材のフィレツト面と基材面等との間で表面張力で保持され、 この 半導体チップの側面を覆った状態で硬化されるので、 半導体チップの角部が露出 するのを防止できる。 あるいは、 本発明によれば、 軟化したコーティング材が、 シート状のチーズがとろけるように、 半導体チップの上面と側面を覆い、 そのま まの状態で硬化されるので、 半導体チップの角部が露出するのを防止できる。  As described above, according to the present invention, a state in which the softened coating layer is held by the surface tension between the substrate surface or the fillet surface of the underfill material and the substrate surface, and covers the side surface of the semiconductor chip As a result, the corners of the semiconductor chip can be prevented from being exposed. Alternatively, according to the present invention, the softened coating material covers the top and side surfaces of the semiconductor chip so that the sheet-shaped cheese melts, and is cured as it is, so that the corners of the semiconductor chip are exposed. Can be prevented.

Claims

請求の範囲 The scope of the claims
1 . 半導体チップのコーティング材において、 1. In coating materials for semiconductor chips,
基材と、  A substrate,
この基材の片面側に形成された熱硬化性樹脂からなる第 1のコーティング層と、 該第 1のコーティング層上に形成され、 熱硬化性樹脂であって、 前記第 1のコ 一ティング層よりも、 軟化時の流れ性の高い樹脂からなる第 2のコーティング層 とからなることを特徴とする半導体チップのコーティング材。  A first coating layer made of a thermosetting resin formed on one side of the substrate; and a thermosetting resin formed on the first coating layer, wherein the first coating layer And a second coating layer made of a resin having a high flowability at the time of softening.
2 . 前記第 1のコ一ティング層と前記第 2のコーティング層との厚さの比率が、 4 : 1〜3 : 1であることを特徴とする請求項 1記載の半導体チップのコーティ ング材。 2. The coating material for a semiconductor chip according to claim 1, wherein the ratio of the thickness of the first coating layer to the thickness of the second coating layer is 4: 1 to 3: 1. .
3 . 基板に半導体チップがフリップチップ接続され、 該半導体チップがコ一ティ ング材で被覆された半導体装置において、 3. In a semiconductor device in which a semiconductor chip is flip-chip connected to a substrate, and the semiconductor chip is coated with a coating material,
前記コーティング材は、 基材と、 この基材の片面側に形成された熱硬化性樹脂 からなるコーティング層とからなり、  The coating material is composed of a base material, and a coating layer made of a thermosetting resin formed on one side of the base material,
該コーティング材が、 前記コーティング層を前記半導体チップ側に向けて半導 体チップ上に載せられ、 加圧、 加熱されることにより、 流れ出した前記コ一ティ ング層が、 前記基材面、 前記半導体チップ側面および前記基板面に表面張力で保 持された状態で熱硬化されて、 前記基材とで半導体チップを被覆することを特徴 とする半導体装置。  The coating material is placed on the semiconductor chip with the coating layer facing the semiconductor chip, and the coating layer that has flowed out by being pressed and heated is applied to the base material surface, A semiconductor device, wherein the semiconductor chip is thermally cured while being held at a surface tension on a side surface of the semiconductor chip and the substrate surface, and covers the semiconductor chip with the base material.
4 . 前記基材が前記半導体チップの端縁から外方に突出していることを特徴とす る請求項 3記載の半導体装置。 4. The semiconductor device according to claim 3, wherein the base material protrudes outward from an edge of the semiconductor chip.
5 . 前記コ一ティング層が、 前記半導体チップと前記基板との間に充填されてい ることを特徴とする請求項 3記載の半導体装置。 5. The semiconductor device according to claim 3, wherein the coating layer is filled between the semiconductor chip and the substrate.
6 . 前記半導体チップと前記基板との間にアンダーフィル材が充填されているこ とを特徴とする請求項 3記載の半導体装置。 6. The semiconductor device according to claim 3, wherein an underfill material is filled between the semiconductor chip and the substrate.
7.基板に半導体チップがフリップチップ接続され、該半導体チップがコーティン グ材で被覆された半導体装置において、 7. In a semiconductor device in which a semiconductor chip is flip-chip connected to a substrate and the semiconductor chip is coated with a coating material,
前記コーティング材は、 基材と、 この基材の片面側に形成された熱硬化性樹脂 からなる第 1のコーティング層と、 該第 1のコーティング層上に形成され、 熱硬 化性樹脂であって、 前記第 1のコーティング層よりも、 軟化時の流れ性の高い樹 脂からなる第 2のコーティング層とからなり、  The coating material is a base material, a first coating layer made of a thermosetting resin formed on one side of the base material, and a thermosetting resin formed on the first coating layer. And a second coating layer made of a resin having a high flowability during softening than the first coating layer,
該コ一ティング材が、 前記第 2のコーティング層を前記半導体チップ側に向け て半導体チップ上に載せられ、 加圧、 加熱されることにより、 流れ出した前記第 2のコーティング層が前記半導体チップの側面下部側を覆って硬化されると共に、 流れ出した前記第 1のコーティング層が前記半導体チップの側面上部側と前記基 材面とを覆つて硬化されていることを特徴とする半導体装置。  The coating material is placed on the semiconductor chip with the second coating layer facing the semiconductor chip, and is pressed and heated so that the second coating layer that has flowed out of the semiconductor chip A semiconductor device, wherein the semiconductor device is cured so as to cover a lower portion of a side surface, and the first coating layer which has flowed out is cured so as to cover an upper portion of a side surface of the semiconductor chip and the substrate surface.
8 . 塵埃を封止込めるべく半導体チップをコーティング材で被覆する半導体チッ プのコ一ティング方法において、 8. In a semiconductor chip coating method in which a semiconductor chip is coated with a coating material to seal dust,
半導体チップを基板にフリップチップ接続する工程と、  A step of flip-chip connecting the semiconductor chip to the substrate,
基材の片面側に熱硬化性樹脂からなるコーティング層が形成されたコーティン グ材を、 コーティング層を半導体チップ側に向けて半導体チップ上に載せ、 コー ティング材を加圧、 加熱して、 前記コーティング層を軟化せしめると共に、 該軟 化して流れ出したコーティング層を表面張力で保持し、 半導体チップの側面を覆 つた状態で硬化させる加圧、 加熱工程とを含むことを特徴とする半導体チップの コーティング方法。  A coating material in which a coating layer made of a thermosetting resin is formed on one side of the base material is placed on a semiconductor chip with the coating layer facing the semiconductor chip side, and the coating material is pressed and heated, and A coating and / or heating step of softening the coating layer, holding the softened and flowed coating layer at surface tension, and curing the semiconductor chip while covering the side surfaces of the semiconductor chip. Method.
9 . 前記基板と半導体チップとの間にアンダーフィル材を充填する工程を含むこ とを特徴とする請求項 8記載の半導体チップのコーティング方法。 9. The method for coating a semiconductor chip according to claim 8, comprising a step of filling an underfill material between the substrate and the semiconductor chip.
1 0 . 前記コーティング層が、 基材の片面側に形成された熱硬化性樹脂からなる 第 1のコーティング層と、 該第 1のコーティング層上に形成され、 熱硬化性樹脂 であって、 前記第 1のコーティング層よりも、 軟化時の流れ性の高い樹脂からな る第 2のコーティング層とからなる前記コーティング材を用いることを特徴とす る請求項 8記載の半導体チップのコ一ティング方法。 10. The coating layer is composed of a thermosetting resin formed on one side of the substrate. A first coating layer; and a second coating formed on the first coating layer, the second coating being a thermosetting resin and having a higher flowability at the time of softening than the first coating layer. 9. The method for coating a semiconductor chip according to claim 8, wherein the coating material comprising a layer is used.
1 1 . 前記コーティング材の基材に、 半導体チップの端縁から外方に突出する基 材を用いることを特徴とする請求項 8記載の半導体チップのコーティング方法。 11. The method for coating a semiconductor chip according to claim 8, wherein a base material protruding outward from an edge of the semiconductor chip is used as a base material of the coating material.
1 2 . 前記コーティング材の基材に、 半導体チップの端縁から外方に突出する基 材を用いることを特徴とする請求項 1 0記載の半導体チップのコーティング方法。 12. The method for coating a semiconductor chip according to claim 10, wherein a substrate protruding outward from an edge of the semiconductor chip is used as a base material of the coating material.
1 3 .前記第 1のコーティング層と前記第 2のコーティング層との厚さの比率が、 4 : ;!〜 3 : 1であるコーティング材を用いることを特徴とする請求項 1 0記載 の半導体チップのコーティング方法。 13. The thickness ratio of the first coating layer to the second coating layer is 4: The method for coating a semiconductor chip according to claim 10, wherein a coating material that satisfies 〜3: 1 is used.
1 4 . 前記基材に透明材料を用い、 前記第 1のコーティング層に紫外線硬化型樹 脂を用いたコーティング材を使用することを特徴とする請求項 1 .0記載の半導体 チップのコーティング方法。 14. The method for coating a semiconductor chip according to claim 1.0, wherein a transparent material is used for the base material, and a coating material using an ultraviolet curable resin is used for the first coating layer.
1 5 . 前記基材に、 半導体装置を搭載する F P Cシートを折り曲げたものを使用 することを特徴とする請求項 8記載の半導体チップのコーティング方法。 15. The method of coating a semiconductor chip according to claim 8, wherein the base material is obtained by bending an FPC sheet on which a semiconductor device is mounted.
1 6 . 前記基材に、 半導体装置を搭載する F P Cシートを折り曲げたものを使用 することを特徴とする請求項 1 0記載の半導体チップのコーティング方法。 16. The method for coating a semiconductor chip according to claim 10, wherein the base material is obtained by bending an FPC sheet on which a semiconductor device is mounted.
1 7 . 前記加圧、 加熱工程が、 前記第 2のコ一ティング層を軟化させると共に、 該軟化した第 2のコーティング層を前記アンダーフィル材として基板と半導体チ ップとの間に充填させる前記充填工程を兼ねることを特徴とする請求項 1 0記載 の半導体チップのコーティング方法。 17. The pressurizing and heating steps soften the second coating layer and fill the softened second coating layer between the substrate and the semiconductor chip as the underfill material. The method for coating a semiconductor chip according to claim 10, wherein the method also serves as the filling step.
1 8 . 稜線部を面取りした半導体チップをコ一ティングすることを特徴とする請 求項 8記載の半導体チップのコーティング ^法。 18. The method for coating a semiconductor chip according to claim 8, wherein a semiconductor chip having a chamfered ridge is coated.
1 9 . 稜線部を面取りした半導体チップをコーティングすることを特徴とする請 求項 1 0記載の半導体チップのコーティング方法。 19. The method for coating a semiconductor chip according to claim 10, wherein the semiconductor chip is coated with a chamfered ridge.
2 0 . 稜線部に段差部を形成した半導体チップをコーティングすることを特徴と する請求項 8記載の半導体チップのコーティング方法。 20. The method for coating a semiconductor chip according to claim 8, wherein a semiconductor chip having a step portion formed on a ridge portion is coated.
2 1 . 稜線部に段差部を形成した半導体チップをコーティングすることを特徴と する請求項 1 0記載の半導体チップのコーティング方法。 21. The method for coating a semiconductor chip according to claim 10, wherein a semiconductor chip having a step portion formed on a ridge portion is coated.
2 2 . 塵埃を封止込めるべく半導体チップをコーティング材で被覆する半導体チ ップのコーティング方法において、 2 2. In a semiconductor chip coating method in which a semiconductor chip is coated with a coating material so as to encapsulate dust,
半導体チップを基板にフリップチップ接続する工程と、  A step of flip-chip connecting the semiconductor chip to the substrate,
基板と半導体チップとの間にアンダーフィル材を充填する工程と、  A step of filling an underfill material between the substrate and the semiconductor chip,
熱硬化性樹脂からなる第 1のコーティング層上に、熱硬化性樹脂樹脂であって、 前記第 1のコーティング層よりも、 軟化時の流れ性の高い樹脂からなる第 2のコ 一ティング層が積層されたコーティング材を、 第 2のコーティング層を半導体チ ップ側に向けて半導体チップ上に載せ、 コーティング材を加熱して、 前記第 1お よび第 2のコーティング層を軟化せしめて半導体チップの側面をも覆った状態で 硬化させる加熱工程とを含むことを特徴とする半導体チップのコーティング方法 c On a first coating layer made of a thermosetting resin, a second coating layer made of a resin that is a thermosetting resin and has a higher flowability at the time of softening than the first coating layer is provided. The laminated coating material is placed on the semiconductor chip with the second coating layer facing the semiconductor chip side, and the coating material is heated to soften the first and second coating layers to form the semiconductor chip. coating methods c of the semiconductor chip, characterized in that it comprises a heating step to cure in a state in which side was also covering the
2 3 . 塵埃を封止込めるべく半導体チップをコーティング材で被覆する半導体チ ップのコーティング方法において、 23. In a semiconductor chip coating method of coating a semiconductor chip with a coating material in order to encapsulate dust,
基板に半導体チップを実装する工程と、  Mounting a semiconductor chip on a substrate;
該実装した基板の側方をマスクで覆う工程と、  A step of covering the sides of the mounted substrate with a mask,
該マスクの孔内に、 マスク孔内壁に表面張力により這い上がりを生じるだけの 粘度の低いコーティング樹脂を注入して半導体チップを覆う注入工程と、 注入したコ一ティング樹脂を熱硬化もしくは紫外線硬化させる硬化工程とを含 むことを特徴とする半導体チップのコ一ティング方法。 In the hole of the mask, the inner wall of the mask only creeps up due to surface tension. A method for coating a semiconductor chip, comprising: an injection step of injecting a coating resin having a low viscosity to cover a semiconductor chip; and a curing step of thermally or ultraviolet curing the injected coating resin.
PCT/JP2002/005404 2001-07-03 2002-05-31 Coating material of semiconductor chip, coating method of semiconductor chip and semiconductor device WO2003005441A1 (en)

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