WO2003005441A1 - Materiau de revetement de puce semi-conductrice, procede de revetement de puce semi-conductrice et dispositif semi-conducteur - Google Patents

Materiau de revetement de puce semi-conductrice, procede de revetement de puce semi-conductrice et dispositif semi-conducteur Download PDF

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Publication number
WO2003005441A1
WO2003005441A1 PCT/JP2002/005404 JP0205404W WO03005441A1 WO 2003005441 A1 WO2003005441 A1 WO 2003005441A1 JP 0205404 W JP0205404 W JP 0205404W WO 03005441 A1 WO03005441 A1 WO 03005441A1
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WO
WIPO (PCT)
Prior art keywords
semiconductor chip
coating
coating layer
substrate
resin
Prior art date
Application number
PCT/JP2002/005404
Other languages
English (en)
Japanese (ja)
Inventor
Kenji Kobae
Hidehiko Kira
Norio Kainuma
Hiroshi Kobayashi
Katsutoshi Hirasawa
Takatoyo Yamakami
Masumi Katayama
Original Assignee
Fujitsu Limited
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Limited filed Critical Fujitsu Limited
Publication of WO2003005441A1 publication Critical patent/WO2003005441A1/fr

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/83909—Post-treatment of the layer connector or bonding area
    • H01L2224/83951—Forming additional members, e.g. for reinforcing, fillet sealant
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]

Definitions

  • the present invention relates to a semiconductor chip coating material, a semiconductor chip coating method, and a semiconductor device for enclosing dust from a semiconductor chip.
  • the information processing device is operated in an environment where temperature and humidity are controlled.
  • this environment has been increasingly managed including dust.
  • magnetic disk drives are strongly demanded to have large capacity and high storage density with the improvement of computer performance. For this reason, the flying height of the magnetic head from the medium is reduced, and the flying surface of the magnetic head is ultra-smoothed.
  • a semiconductor chip for driving and controlling a magnetic head has been arranged around a magnetic head.
  • the semiconductor chip is made of brittle silicon, dust is generated from the semiconductor chip for various reasons, and the dust enters between the magnetic head and the medium, causing wear of the magnetic recording medium. Various adverse effects occur, such as information rupture. For this reason, semiconductor chips are coated with a coating material in order to seal dust.
  • FIG. 22 shows a method of coating the semiconductor chip 10 with a potting resin.
  • FIG. 23 shows a method in which a coating resin is printed on a semiconductor chip 10 using a mask 11 and the coating resin is cured by heat or irradiated with ultraviolet rays. is there.
  • the resin 14 is supplied by the squeegee 13, so that the viscosity of the resin 14 needs to be increased.
  • the coating area becomes narrow, the resin becomes the semiconductor chip 10 and the mask. 1. There is a possibility that it will not be filled sufficiently during 1 Disclosure of the invention
  • an object of the present invention is to provide a semiconductor chip coating material capable of performing coating without exposing a corner of a semiconductor chip, and a method of coating a semiconductor chip. And a semiconductor device.
  • a coating material for a semiconductor chip according to the present invention includes: a base material; a first coating layer made of a thermosetting resin formed on one side of the base material; and a first coating layer formed on the first coating layer. And a second coating layer made of a resin having a higher flowability at the time of softening than the first coating layer.
  • the method for coating a semiconductor chip according to the present invention includes a step of flip-chip connecting the semiconductor chip to a substrate, and a step of coating a coating material having a coating layer made of a thermosetting resin on one side of a substrate.
  • the coating layer is placed on the semiconductor chip with the layer facing the semiconductor chip side, and the coating material is pressurized and heated to soften the coating layer and to hold the softened coating layer flowing out by surface tension.
  • the method includes a pressing step and a heating step for curing the semiconductor chip while covering the side surface of the semiconductor chip.
  • the softened coating layer is held by surface tension and is cured as it is while covering the side surfaces of the semiconductor chip, so that the corners of the semiconductor chip can be prevented from being exposed.
  • the coating material comprises: a base material; A coating layer made of a thermosetting resin formed, and the coating material is placed on the semiconductor chip with the coating layer facing the semiconductor chip side, and is pressurized and heated.
  • the coating layer that has flowed out is thermoset while being held at surface tension on the substrate surface, the semiconductor chip side surface, and the substrate surface, and covers the semiconductor chip with the substrate. I do. BRIEF DESCRIPTION OF THE FIGURES
  • FIG. 1 is an explanatory view of a coating material
  • FIG. 2 is an explanatory view of a state where a semiconductor chip is coated with the coating material of FIG. 1
  • FIG. 3 is a state where a semiconductor chip is chamfered.
  • Fig. 4 is an explanatory view of a state in which a step portion is formed at an edge of a semiconductor chip.
  • Figs. 5A and 5B show an example in which a bent piece is formed on an FPC sheet to form a base material.
  • FIG. 6 is an explanatory diagram of a coating material without a base material
  • FIG. 7 is an explanatory diagram of a state in which a semiconductor chip is coated with the coating material of FIG. 6,
  • FIG. 8 is a diagram using a mask.
  • FIG. 1 is an explanatory view of a coating material
  • FIG. 2 is an explanatory view of a state where a semiconductor chip is coated with the coating material of FIG. 1
  • FIG. 3 is a state where
  • FIG. 9 is an explanatory view of a state in which a coating resin is injected
  • FIG. 9 is an explanatory view of a state in which ultraviolet light is irradiated using a light diffusion plate in FIG. 8
  • FIG. 10 is a mask in FIG. A state in which light reflecting particles are applied to the inner wall of the hole and irradiated with ultraviolet light
  • FIG. 11 is an explanatory view showing an example of irradiating ultraviolet rays by an ultraviolet irradiator in FIG. 8, and FIGS. 12A and 12B show an ultraviolet irradiator around a coating area.
  • FIG. 13 is an explanatory view showing an example of arrangement, FIG.
  • FIG. 13 is an explanatory view showing an example in which a semiconductor chip is formed in a trapezoidal shape
  • FIG. 14 is a diagram in which air is blown between an underfill material and a lower surface of a mask.
  • FIG. 15 is an explanatory view showing an example in which an underfill material is ground and flattened
  • FIG. 16 is an explanatory view showing a state in which a mask is pressed against an underfill material.
  • FIG. 17 is an explanatory view showing a state in which a cap is attached to the ridge of the semiconductor chip.
  • FIGS. 18A and 18B are explanatory views showing a state in which the ridge of the semiconductor chip is chamfered.
  • 1 9 is semiconductor
  • FIG. 20 is an explanatory view of a state in which a step portion is formed at an edge portion, and FIG. 20 illustrates a fine powder layer.
  • Fig. 21 is an explanatory view of the state of irradiating the fine powder layer with infrared rays, and
  • Fig. 22 is a state of the semiconductor chip with corners exposed by the conventional coating method.
  • FIG. 23 is an explanatory view showing a method of filling a coating resin with a squeegee using a mask.
  • FIG. 1 is an explanatory diagram of a coating material.
  • the coating material 20 includes a substrate 21, a first coating layer 22 made of a thermosetting resin formed on one surface of the substrate 21, and a first coating layer 22 on the first coating layer 22.
  • the second coating layer 23 is formed of a thermosetting resin, and is made of a resin having a higher flowability at the time of softening than the first coating layer 22.
  • the base material 21 is made of, for example, a polyimide resin and preferably has a thickness of about 50 m.
  • the material of the substrate 21 is not necessarily limited to resin.
  • a mixed resin of a thermosetting epoxy resin and an acryl resin as a binder can be used.
  • An ultraviolet curing resin may be further mixed with this mixed resin. However, it is not limited to these.
  • thermosetting epoxy resin for example, a bisphenol A-type thermosetting epoxy resin and a resin such as dicyclopentene can be used.
  • the first coating layer 22 and the second coating layer 23 are formed by adjusting the compounding ratio of the compounded resin so that the flowability when softened once when the resin is thermally cured has the first coating layer. It is adjusted so that the second coating layer 23 is higher than 22.
  • the fluidity is measured in terms of the elastic modulus (Young's modulus)
  • the elasticity at 100 ° C. is about 600 to 900 Pa in the first coating layer 22, and the flow is hardened.
  • a material having low fluidity is preferable, and a material having a softness and good flowability of about 30 to 100 Pa for the second coating layer 23 is preferable.
  • the elastic modulus of the first coating layer 22 is about 8 OOPa, while that of the second coating layer 23 is about 40 Pa. Is preferred.
  • a semiconductor chip 24 is mounted on a substrate 25 by flip-chip connection.
  • the substrate 25 is a wiring substrate, package, FPC, or the like, and is not particularly limited.
  • a sealing resin (underfill material 26) having good flowability such as epoxy resin is filled between the semiconductor chip 24 and the substrate 25 and cured.
  • the above-mentioned coating material 20 and the second coating layer 23 are applied to a semiconductor chip.
  • the substrate is placed on the semiconductor chip 24 toward the 24 side, and is pressed from above the substrate 21 and heated to thermally cure the coating layer.
  • the curing conditions were as follows: curing at 110 ° C for about 30 seconds, and then 150 ° C in an oven.
  • the first coating layer 22 and the second coating layer 23 are both softened and pressurized from above the substrate 21, as shown in FIG. It is pushed out to the side of 4.
  • the second coating layer 23 with good flowability flows out between the lower portion of the side surface of the semiconductor chip 24 and the fillet surface 26 a (inclined surface) of the underfill material 26.
  • the c and both resins flowing between the first coatings layer 2 2 is a side top and base 2 first face of the semiconductor chip 2 4 not very flow resistance, the fillet surface 2 6 a, the semiconductor chip 24 is in contact with the lower surface of the substrate 21, and is held between the fillet surface 26 a and the substrate surface due to surface tension between these surfaces.
  • the highly viscous first coating material 22 does not flow down the side surface of the semiconductor chip 24, is held between the base material 21 and the upper side of the semiconductor chip 24, and is thermally cured.
  • the corners are not exposed, and the dust on the surface of the semiconductor chip 24 can be completely sealed.
  • the base material 21 is larger than the semiconductor chip 24, and it is preferable that the base material 21 be protruded outward from the edge of the semiconductor chip, because the surface tension can be more easily applied.
  • the thicknesses of the first coating layer 22 and the second coating layer 23 are as described above.
  • the ratio is preferably about 4: 1 to 3: 1. This is because if the amount of the second coating layer 23 having good flowability is too large, the second coating layer 23 may flow down and expose the side surface of the semiconductor chip 24.
  • the semiconductor chip 30 is directly coated with the coating material 20 as described above without previously filling the underfill material between the substrate 31 and the semiconductor chip 30.
  • the air between the substrate 31 and the semiconductor chip 30 is sucked and exhausted by a suction tool (not shown) or the like, and the second coating layer 23 with good flowability is filled with an underfill material. It can also be filled as. That is, it serves as both a coating material and an underfill material.
  • the coating layer has a two-layer configuration, but may have a single layer. In this case, as the material of the coating layer, a flowable resin intermediate between the first coating layer 22 and the second coating layer 23 is selected.
  • a UV-curable resin may be used for the coating layer, and a transparent material may be used for the base material 21 to be cured by irradiating UV rays while applying pressure.
  • FIG. 3 shows an example in which a chamfered portion 27 is formed on a ridge of a semiconductor chip 24.
  • FIG. 4 shows an example in which a step 28 is formed on the ridge of the semiconductor chip 24. Also in this case, the use of the above-mentioned coating material 20 (including one having a single coating layer) can further prevent the corners from being exposed.
  • the step portion may be formed on all the ridge portions, or may be formed only on some of the ridge portions.
  • FIG. 5 shows still another embodiment.
  • the semiconductor chip 24 is mounted on an FPC (flexible print circuit) sheet 30 made of a polyimide film or the like, and a bent piece 31 is formed on the FPC sheet near the semiconductor chip 24.
  • the above coating layer (including one and two layers, not shown) is formed on the bent piece 3 la, and the bent piece 31 a is bent on the semiconductor chip 24, pressurized and heated. Heat the coating layer Let it cure. This makes it possible to prevent the corners of the semiconductor chip 24 from being exposed in a very simple manner.
  • a two-layer coating material 20 having no base material 21 is used. That is, the coating material 20 is obtained by simply laminating the first coating layer 22 and the second coating layer 23 similar to the above.
  • the coating material 20 is placed on the semiconductor chip 30 mounted on the substrate 31 with the second coating layer 23 facing the semiconductor chip side, and then, as shown in FIG. As described above, by blowing hot air at a temperature of about 150 ° C. onto the coating material 20 without applying pressure, the coating material 20 is softened so that the sheet-like cheese melts. However, the side surfaces of the semiconductor chip 30 are also covered, and heat curing is performed in this state. Since the first coating layer 22 is made of a resin having low flowability at the time of softening, the corners of the semiconductor chip 30 are not exposed. In this case, the semiconductor chip 30 is directly coated with the coating material 20 as described above without pre-filling the underfill material between the substrate 31 and the semiconductor chip 30.
  • the air between the substrate 31 and the semiconductor chip 30 is suctioned and exhausted by a suction tool (not shown) or the like, and the second coating layer 23 having good flowability is under- laid. It can be filled as one fill material. That is, the coating step and the filling step of the underfill material are combined, and the coating step and the underfill material are combined.
  • FIG. 8 shows still another embodiment.
  • the side of the semiconductor chip 30 mounted on the substrate 31 is covered with the mask 35, and the inside of the hole 36 of the mask 35 rises by the surface tension on the inner wall of the mask hole 36 (
  • the semiconductor chip 30 is covered by injecting a coating resin 37 having a viscosity low enough to cause wet-up.
  • the injected coating resin 37 is cured by heat or ultraviolet light.
  • the coating resin with low viscosity is injected, even if the coating area is small, the coating resin can be filled reliably. Also, by curing as it is, the coating resin 37 is cured in a state where the peripheral part is higher than the central part. Therefore, it is possible to reliably prevent the corners of the semiconductor chip 30 from being exposed.
  • the underfill material may be separately filled in advance, or may be filled with the coating resin 37 and cured.
  • FIG. 9 shows an example in which the light diffusing plate 38 is disposed between the ultraviolet irradiation lamp 39 and the coating resin 37 when the coating resin 37 is cured by ultraviolet light in FIG. In this way, the ultraviolet light is diffused by the light diffusing plate 38 and is evenly applied to the coating resin 37, so that the narrow part of the mask hole 36 is also irradiated with the ultraviolet light. Can be prevented.
  • FIG. 10 shows light reflecting particles 40 such as glass fixed with a binder on the wall surface of the mask hole 36 or the side surface of the semiconductor chip 30 when the coating resin 37 is cured by ultraviolet light in FIG. An example in which is applied.
  • the ultraviolet rays are irregularly reflected by the light reflecting particles, and the ultraviolet rays are irradiated deep inside the mask hole 36, so that the generation of the uncured portion can be prevented.
  • Fig. 11 shows that, in Fig. 8, when the coating resin 3 is cured by ultraviolet light, the ultraviolet irradiator 41 is inserted so that its tip is located at the lower part of the mask hole 36, and the mask hole 36
  • An example is shown in which after curing the resin in the lower part, the irradiator 41 is pulled up, and the whole is irradiated with ultraviolet light to cure the coating resin 37. This can also prevent the generation of uncured portions.
  • Fig. 12 shows an ultraviolet curing unit 41 arranged in a strip around the coating area and supplying the coating resin while irradiating the ultraviolet rays to prevent the resin from protruding outside the area and to cure the uncured area. An example of preventing the occurrence of the error will be described.
  • Fig. 13 shows the case where the coating resin 37 in Fig. 8 is cured with ultraviolet light.
  • the ultraviolet light is irradiated to the bottom of the mask hole 36, and the coating is performed. An example of preventing the occurrence of an uncured portion of the resin 37 will be described.
  • FIG. 14 shows the case of FIG. 8 in which the resin flows from the nozzle 42 into the gap from the side to prevent resin from flowing out from the gap between the underfill material 26 and the bottom of the mask hole 36.
  • An example is shown in which the coating resin 37 is injected while blowing.
  • Fig. 15 shows the underfill material 26 beforehand so that the surface is flat. After grinding the fill material 26, the mask 35 is placed to make the underfill material
  • Figure 16 shows that when the underfill material 26 is thermally cured, the mask 35 is pressed against the still uncured underfill material 26, thereby forming the underfill material 26 and the bottom of the mask hole 36. An example in which a gap is prevented from occurring is shown. This can prevent the coating resin 37 from flowing out. At the same time as the underfill material 26 is hardened, the coating resin 37 is injected, and the underfill material 26 and the coating resin are cured.
  • FIG. 17 shows a state in which a cap 45 capable of covering the ridge of the upper surface of the semiconductor chip 30 is attached to the semiconductor chip 30 in advance, and then the semiconductor chip 30 is coated with the coating resin 43.
  • the coating resin 43 is an example. Since the corners of the semiconductor chip 30 are covered with the cap 45, they are not exposed. In this case, the coating resin
  • thermosetting resin or an ultraviolet curable resin a conventional material (a thermosetting resin or an ultraviolet curable resin) can be used. 4 6 are bumps.
  • FIG. 18 shows the chamfered portion of the semiconductor chip 30 as shown in FIG. 18 (b).
  • the 43 may be a normal resin (a thermosetting resin or an ultraviolet curable resin), but has an intermediate flowability between the first coating layer 22 and the second coating layer 23 It is preferable to use a resin.
  • FIG. 19 shows an example in which a step portion 48 is formed at a ridge portion on the upper surface of the semiconductor chip 30.
  • the coating resin 43 may be a normal resin (a thermosetting resin or a UV-curable resin), but may be an intermediate flow between the first coating layer 22 and the second coating layer 23. It is preferable to use a resin having properties.
  • Figure 20 shows the surface of the semiconductor chip 30, epoxy resin mixed with a binder, etc.
  • Resin fine powder is sprayed to form a fine powder layer 50 having a thickness of about 5 to 10 / im, and then a coating resin 43 is applied on the fine powder layer 50, and then thermosetting or ultraviolet curing An example is shown below.
  • the coating resin 43 may be a normal resin (a thermosetting resin or an ultraviolet curable resin), but a resin having an intermediate flowability between the first coating layer 22 and the second coating layer 23 may be used. It is preferred to use.
  • Fig. 21 shows a fine powder layer 50 with a thickness of about 10 to 15 m formed by spraying resin fine powder such as epoxy resin mixed with a binder on the surface of the semiconductor chip 30 and then using infrared rays.
  • resin fine powder such as epoxy resin mixed with a binder
  • irradiation lamp 51 An example in which the fine powder layer 50 is heated and cured by the irradiation lamp 51 will be described. The so-called baking is performed, and the flow of the resin hardly occurs, so that the corner of the semiconductor chip 30 can be prevented from being exposed.
  • the invention's effect is performed, and the flow of the resin hardly occurs, so that the corner of the semiconductor chip 30 can be prevented from being exposed.
  • the softened coating layer As described above, according to the present invention, a state in which the softened coating layer is held by the surface tension between the substrate surface or the fillet surface of the underfill material and the substrate surface, and covers the side surface of the semiconductor chip As a result, the corners of the semiconductor chip can be prevented from being exposed.
  • the softened coating material covers the top and side surfaces of the semiconductor chip so that the sheet-shaped cheese melts, and is cured as it is, so that the corners of the semiconductor chip are exposed. Can be prevented.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

L'invention concerne un procédé permettant de revêtir une puce semi-conductrice sans exposer les parties de coin de celle-ci. Le procédé de revêtement est caractérisé en ce qu'il comprend les étapes consistant à monter, sur la puce semi-conductrice, un matériau de revêtement possédant une couche de revêtement de résine thermodurcissable formée sur un côté d'un matériau de base, tout en dirigeant la couche de revêtement en direction du côté de la puce semi-conductrice, à presser à chaud le matériau de revêtement, de manière à adoucir la couche de revêtement, et ensuite à sécher la couche de revêtement fludisée, tout en maintenant par tension interfaciale et couvrant la surface latérale de la puce semi-conductrice.
PCT/JP2002/005404 2001-07-03 2002-05-31 Materiau de revetement de puce semi-conductrice, procede de revetement de puce semi-conductrice et dispositif semi-conducteur WO2003005441A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JPPCT/JP01/05776 2001-07-03
PCT/JP2001/005776 WO2003005436A1 (fr) 2001-07-03 2001-07-03 Materiau d'enrobage de puce semi-conductrice permettant de reguler un lecteur de disque et procede d'enrobage d'une puce semi-conductrice permettant de reguler un lecteur de disque

Publications (1)

Publication Number Publication Date
WO2003005441A1 true WO2003005441A1 (fr) 2003-01-16

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Family Applications (2)

Application Number Title Priority Date Filing Date
PCT/JP2001/005776 WO2003005436A1 (fr) 2001-07-03 2001-07-03 Materiau d'enrobage de puce semi-conductrice permettant de reguler un lecteur de disque et procede d'enrobage d'une puce semi-conductrice permettant de reguler un lecteur de disque
PCT/JP2002/005404 WO2003005441A1 (fr) 2001-07-03 2002-05-31 Materiau de revetement de puce semi-conductrice, procede de revetement de puce semi-conductrice et dispositif semi-conducteur

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JPH04340258A (ja) * 1990-10-08 1992-11-26 Toshiba Corp 半導体装置の製造方法
JPH05152373A (ja) * 1991-11-26 1993-06-18 Sharp Corp 半導体素子の実装構造
JPH06204292A (ja) * 1992-12-28 1994-07-22 Rohm Co Ltd 半導体装置
JPH09167780A (ja) * 1995-12-14 1997-06-24 Denso Corp ベアチップ封止方法およびベアチップ封止基板
JPH10199936A (ja) * 1997-01-14 1998-07-31 Olympus Optical Co Ltd フレキシブル配線板へのフリップチップ実装構造
DE10002039A1 (de) * 2000-01-19 2001-08-09 Horst Gentsch Apparatur zur Verbesserung der Fusionsausbeute bei Wasserstoffisotopen

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