TW444364B - Manufacturing method for stacked chip package - Google Patents

Manufacturing method for stacked chip package Download PDF

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Publication number
TW444364B
TW444364B TW89105412A TW89105412A TW444364B TW 444364 B TW444364 B TW 444364B TW 89105412 A TW89105412 A TW 89105412A TW 89105412 A TW89105412 A TW 89105412A TW 444364 B TW444364 B TW 444364B
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Taiwan
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wafer
substrate
manufacturing
patent application
package structure
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TW89105412A
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Chinese (zh)
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Hsueh-Te Wang
Su Tao
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Advanced Semiconductor Eng
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector

Abstract

A manufacturing method for stacked chip package includes the following steps: (a) configuring a first chip on a substrate so that the solder bump of the first chip is aligned with the corresponding flip-chip bonding pad on the substrate; (b) re-flowing the solder bump; (c) using an adhesive layer to attach the back of a second chip on the first chip; (d) curing the adhesive layer; (e) forming an encapsulation between the first chip and the substrate; (f) curing the encapsulation; (g) electrically connecting the chip pad of the second chip to the corresponding plurality of wire-bonding pads; and, (h) forming an encapsulation to enclose the first chip, the second chip and a part of the upper surface of the substrate. The adhesive layer was firstly cured in the step (d) to form a passivation on the back of the first chip. Therefore, during the encapsulation curing process, the cured adhesive layer can help the first chip to resist the stress generated in the encapsulation curing process so as to avoid the die crack problem.

Description

4443 64 五、發明說明（1) 發明領域： 本發明係有關於一種製造堆疊晶片封裝構造（stacked-chip package) 之方法 ，其特 別有關 於將晶 片以堆 叠的方 式安裝到一基板。 先前技術： 美國專利第59 7340 3號揭示一堆疊晶片封裝構造 (stacked chip package)l〇〇 ，其包含一第一半導體晶片 110以覆晶接合的方式設於一基板120以及一第二半導體晶 片130堆*於該第一半導體晶片110上並且電性連接至該基 板120。該基板120上表面設有複數個線接合墊 (wire-bonding pad )122 以及複數個復晶接合塾 (flip-chip bonding pad)124，該基板 120 下表面設有複 數個錫球銲墊1 26 »該第一半導«晶片1 1 0係利用錫鉛連接 (solder joint)112接合至基板120上的復晶接合墊124。 該第二半導體晶片130則是利用複數條銲線132連接至基板 120上的線接合墊122。該第一丰導體晶片11〇與基板120間 一般係具有一填膠（under f i 1 1) 11 4用以密封該錫鉛連接 11 2間之空隙該第二半導體晶片1 30則是利用一膠層1 34 固設於該第一半導體晶片110之背面。該膠層134 —般係以 熱固性環氟材料（thermosetting epoxy material)製成》4443 64 V. Description of the invention (1) Field of the invention: The present invention relates to a method for manufacturing a stacked-chip package, which is particularly related to mounting a wafer on a substrate in a stacked manner. Prior art: US Patent No. 59 7340 3 discloses a stacked chip package 100, which includes a first semiconductor wafer 110 provided on a substrate 120 and a second semiconductor wafer in a flip-chip bonding manner. 130 stacks * are on the first semiconductor wafer 110 and are electrically connected to the substrate 120. A plurality of wire-bonding pads 122 and a plurality of flip-chip bonding pads 124 are provided on the upper surface of the substrate 120. A plurality of solder ball pads 1 26 are provided on the lower surface of the substrate 120. »The first semiconductor« wafer 1 1 0 »is bonded to a polycrystalline bonding pad 124 on a substrate 120 by a solder joint 112. The second semiconductor wafer 130 is connected to a wire bonding pad 122 on the substrate 120 by a plurality of bonding wires 132. An adhesive (under fi 1 1) 11 4 is generally used between the first abundant conductor wafer 110 and the substrate 120 to seal the gap between the tin-lead connection 11 2 and the second semiconductor wafer 1 30 is made of an adhesive. The layer 1 34 is fixed on the back surface of the first semiconductor wafer 110. The adhesive layer 134 is generally made of thermosetting epoxy material.

請參照第二圖，該堆4晶片封裝構造100大量生產時， 一般係將複數個基板整合在一基板片（strip)上，該基板 條上具有對正孔（alignment hole)(未示於圈_)，用以 使製程自動化β該半導II晶片110 —般係以微晶妙Please refer to the second figure. When the stack of 4-chip package structures 100 is mass-produced, a plurality of substrates are generally integrated on a substrate strip, and the substrate strip has alignment holes (not shown in the circle). _) Is used to automate the process. The semiconductor II chip 110 is generally microcrystalline.

4443 64 五、發明稅明（2) (microcrystalline silicon)形成，其熱膨脹係數 (coefficient of thermal expansion, CTE)約為 3-5 ppm °C-1。該基板片一般係以聚合物含浸玻磷纖維4443 64 V. The invention tax (2) (microcrystalline silicon) is formed, and its coefficient of thermal expansion (CTE) is about 3-5 ppm ° C-1. The substrate is generally impregnated with polymer glass fiber

(polymer impregnated fiberg lass)形成，其厚度一般不 大於0· 3 6mm且熱膨脹係數（CTE)約為25-40 ppm t-1。由於 該半導體晶片110與基板片熱膨脹係數差異相當大且基板 片厚度甚薄，因此在填膠114的硬化（curing)製程（一般 包含預硬化120 °C 30分鐘，以及後硬化150 小時）中， 該半導體晶片110與基板片會隨溫度變化而產生不同的膨 脹或收縮量而導致該半導艟晶月110與基板片的結構弩翹 (warpage);並且硬化所需要的溫度越高或時間越長，所 產生的結構穹翹就越大，而由於該晶片110係結合在基板 片上’因此會產生一彎曲力矩施加在晶片110上。假如該 弩曲力矩太大甚至有可能使晶片110破裂。 如第二圖所示，該因應力而弩翹之半導體晶片110與基 板片，對晶片本身及後續製程會造成不利影響。例如該彎 勉之基板片及晶片110會使後續點應·製程（epoxy dispensing)產生定位誤差而使環氧膠134無法正確地點在 晶片110上之預定位置並影響膠量控制，同時，該環氧膠 在晶片110上所形成之黏合層亦可能產生不完全填滿 (incomplete f i 1 1 ing)之問題而影響該晶片1 30之黏合品 質。 該填膠114及膠層134之硬化（curing)製程所使用之温 度視其材質特性而定，一般需大於其最大放熱溫度(polymer impregnated fiberg lass), the thickness of which is generally not greater than 0.36 mm and the coefficient of thermal expansion (CTE) is about 25-40 ppm t-1. Because the thermal expansion coefficient of the semiconductor wafer 110 and the substrate wafer are quite different and the thickness of the substrate wafer is very thin, during the curing process of the filler 114 (generally including pre-hardening at 120 ° C for 30 minutes and post-hardening for 150 hours), The semiconductor wafer 110 and the substrate sheet will have different expansion or contraction amounts with temperature changes, which will cause the structure of the semiconductor wafer 110 and the substrate sheet to warp; and the higher the temperature or time required for hardening, As the length increases, the resulting structural dome is larger, and since the wafer 110 is bonded to the substrate sheet, a bending moment is generated on the wafer 110. If the cross-bending moment is too large, the wafer 110 may even break. As shown in the second figure, the semiconductor wafer 110 and the substrate which are warped due to stress will adversely affect the wafer itself and subsequent processes. For example, the warped substrate sheet and wafer 110 may cause positioning errors in subsequent dot dispensing processes, making the epoxy glue 134 unable to be correctly positioned at a predetermined position on the wafer 110 and affecting the amount of glue. At the same time, the ring The adhesive layer formed by the oxygen glue on the wafer 110 may also cause incomplete fi 1 1 ing problems and affect the adhesion quality of the wafer 1 30. The temperature used in the curing process of the filler 114 and the adhesive layer 134 depends on the material characteristics, and generally needs to be greater than its maximum exothermic temperature.

4 443 6 4 五、發明說明（3) (Maxifflum Exothermic Temp.)。該最大放熱溫度可由示差 掃描熱卡計（Differential Scanning Calorimeter, DSO )所測得之放熱硬化曲線（heat of cure curve)決定。 美國專利第5973403號亦揭示一方法以製造該堆φ晶片 封裝構造（stacked chip package)100。然而該方法並未 揭示如何解決前述之彎翹問題。因此有必要尋求一方法其 可克服或至少改善前述之先前技術的問題。 、 發明概要：4 443 6 4 V. Description of the Invention (3) (Maxifflum Exothermic Temp.). The maximum exothermic temperature can be determined by a heat of cure curve measured by a differential scanning calorimeter (DSO). U.S. Patent No. 5,973,403 also discloses a method to fabricate the stacked φ chip package structure 100. However, this method does not reveal how to solve the aforementioned warpage problem. It is therefore necessary to find a way to overcome or at least improve the aforementioned problems of the prior art. , Summary of invention:

本發明之主要目的係提供一種製造堆疊晶片封裝構造 之方法，其利用對膠層材料的選擇以及硬化製程最適化， 使得基板以及晶片之聲組最小化。 根據本發明一較佳實施例之製造堆疊晶片封裴構造之 方法’其包含下列步驟：（a)將一第一晶片置放在一基板 上’使得該第一晶片之錫錯凸塊（s〇lder bump)對齊該基 板上相對應的覆晶接合整《(flip-chip bonding pad) ;(b) 回焊該錫鉛凸塊，藉此將該第一晶片固定於基板並且電性 速接該第一晶片至基板；（c)將—第二晶片之背面利用一 膠層貼在該第一晶片上，該第二晶片具有複數個晶片銲墊 (bonding pad)設於其正面：（d)硬化（curing)該膠層； (e)形成一填膠於第一晶片與基板間；（f)硬化（curing) 該填膠：（g)電性連接該第二晶片之晶片銲墊至基板上相 對應的複數個線接合墊；及（h)形成一封膠體包覆該第一 晶片、第一晶片以及該基板上表面之一部分》由於該膝層 係先在步驟（d)中被硬化而形成一保護層於第一晶片之背The main object of the present invention is to provide a method for manufacturing a stacked chip package structure, which utilizes the selection of the adhesive layer material and the optimization of the hardening process to minimize the sound set of the substrate and the wafer. A method of manufacturing a stacked wafer package structure according to a preferred embodiment of the present invention 'includes the following steps: (a) placing a first wafer on a substrate' so that the tin bumps of the first wafer (s 〇lder bump) align the corresponding flip-chip bonding pad on the substrate; (b) re-solder the tin-lead bump, thereby fixing the first chip to the substrate and electrically connecting it quickly The first wafer to the substrate; (c) the back of the second wafer is attached to the first wafer with an adhesive layer, and the second wafer has a plurality of wafer bonding pads provided on the front thereof: (d ) Curing the adhesive layer; (e) forming a filler between the first wafer and the substrate; (f) curing the filler: (g) electrically connecting the wafer pads of the second wafer to A plurality of corresponding wire bonding pads on the substrate; and (h) forming a colloid to cover the first wafer, the first wafer, and a portion of the upper surface of the substrate. "Because the knee layer was first used in step (d), Hardened to form a protective layer on the back of the first wafer

4443 644443 64

五、發明說明（4) 面。因而，在該填膠硬化的過程中，該已硬化的膠層可以 幫助該第一晶片抵抗填膠硬化製程產生之應力，藉此改 晶片破裂（die crack)之問題。5. Description of the invention (4). Therefore, during the filling and hardening process, the hardened adhesive layer can help the first wafer resist the stress generated by the filling and hardening process, thereby resolving the problem of die crack.

根據本發明另一較佳實施例之製造堆疊晶片封裝構造 之方法，其包含下列步驟：（a，）將一第一晶片置放在一 基板上，使得該第一晶另之錫鉛凸塊對齊該基板上相對應 的覆晶接合墊；（b’）回焊該錫鉛凸塊，藉此將該第一晶 片固定於基板並且電性連接該第一晶片至基板；（c,)形 成一填膠於第一晶片與基板間；（d，）部份硬t(partial curing)該填應使得其固化（geiati〇n)但不變硬（cured); (e )將一第二晶片之背面利用一膠層貼在該第一晶片 上；（f，）硬化（curing)該膠層以及在第一晶片與基板間 的填膠；Cg’）電性連接該第二晶片至該複數個線接合 墊；及（h’）形成一封膠體包復核第—晶片、第二晶片以 及該基板上表面之一部分。在步称（d’）中，由於該部份硬 化製程係加熱該填膠使得其固化但不變硬（該固化之溫度 以及時間視材質而定），因此該第一晶片以及基板在步驟 (d’）的加熱溫度得以降低並且加熱時間也蠻減小 該第-晶片以及基板在步驟(d，）所受之熱工 一晶片以及基板在步驟U’）較不易彎翹’因此可確保後續 製程例如步称（e)中點應"（dispensing)之進行。A method for manufacturing a stacked chip package structure according to another preferred embodiment of the present invention includes the following steps: (a,) placing a first chip on a substrate so that the first crystal is another tin-lead bump Align the corresponding flip-chip bonding pads on the substrate; (b ') resolder the tin-lead bumps, thereby fixing the first wafer to the substrate and electrically connecting the first wafer to the substrate; (c,) forming A filler is filled between the first wafer and the substrate; (d,) partial hardening t (partial curing) The filling should make it solid (geiatiOn) but not hardened (e) a second wafer The back surface is adhered to the first wafer by an adhesive layer; (f,) curing the adhesive layer and the filling between the first wafer and the substrate; Cg ') electrically connecting the second wafer to the plurality A wire bonding pad; and (h ') forming a colloid envelope to review the first wafer, the second wafer, and a portion of the upper surface of the substrate. In step (d '), because the partial hardening process is heating the filler to make it solidify but not harden (the temperature and time of curing depend on the material), the first wafer and substrate are in step ( d ') The heating temperature is reduced and the heating time is also greatly reduced. The thermal processing of the first wafer and the substrate in step (d,), and the wafer in step U') are less prone to warping. Processes such as step (e) midpoint should be carried out.

圈示說明： ° 為了讓本發明之上述和其他目的、特微、 更 明顯特徵’下文特舉本發明較佳實施例，並配合#所附圖Illustrative description: ° In order to make the above and other objects, special features, and more obvious features of the present invention ’, the preferred embodiments of the present invention are enumerated below, and #

第7頁 4 443 64 五、發明說明（5) ' 示，作詳細說明如下。 _ 第1圓：根據美國專利第5973403號一較佳實施例之堆-疊晶片封裝構造之刮面阅； 第2囷：其係用以說明在填膠硬化（curing)製程後基 板片以及晶片彎麵之剖面圈； 第3至5圔：其係用以說明根據本發明一 之製造堆疊晶片封裝構造之方法；及 , 第^6至8® :其係用以說明根據本發 例之數造堆4晶片封裝構造之^ T 圖號說明： 100 堆疊晶片封裝構造 踢銘連接 基板 覆晶接合墊 晶片 膠層 110 晶片 | j 2 1Μ 填膠 m 122 線接合墊 124 126 錄球鋒整· 130 132 銲線 134 140 封膠《 發明說明： 第二圖至笫五圖係用以說明根據本發明第一較佳實施 例之製造埃疊晶片封裝構造之方法。 第三圓揭示一晶片110利用複數個錫鉛連接（s〇lder joint)112接合至一基板120 »該基板120較佳係以聚酿亞 胺薄片（polyimide film)或玻璃纖維強化 BT(bismaleimide-triazine)樹脂製成。該基板12〇上表面Page 7 4 443 64 V. Description of the invention (5) ', detailed description is as follows. _ Round 1: Scrap surface reading of a stack-stacked wafer package structure according to a preferred embodiment of US Patent No. 5,973,403; Section 2: It is used to explain the substrate sheet and the wafer after the curing process Sectional circle of curved surface; Sections 3 to 5: It is used to explain the method for manufacturing a stacked chip package structure according to the first aspect of the invention; and, Sections 6 to 8®: It is used to explain the number according to the present example Stacking 4 chip package structure ^ T Description of the drawing number: 100 stacked chip package structure Ki-Ming connection substrate flip-chip bonding pad wafer adhesive layer 110 chip | j 2 1M filling m 122 wire bonding pad 124 126 recording ball sharpening · 130 132 bonding wires 134 140 encapsulant "Description of the invention: The second to the fifth figures are used to explain the method for manufacturing the package structure of the Angstrom chip according to the first preferred embodiment of the present invention. The third circle reveals that a wafer 110 is bonded to a substrate 120 using a plurality of solder joints 112. The substrate 120 is preferably made of polyimide film or glass fiber reinforced BT (bismaleimide- triazine) resin. The upper surface of the substrate 12

BHHBHH

4443 64 五、發明說明（6) . 設有複數個覆晶接合墊124以及複數個線接合墊122設於該 復晶接合墊124之周圍。該覆晶接合墊124以及線接合墊-122係利用導電線路（conductive traces)以及通孔（vias) (未示於圖中）電性連接至該基板120之下表面之複數個 錫球鲜塾126。 該晶片110係先被一自動化選取及安放的機器移至一浸 潰器（dip fluxer)，浸入助銲劑。當助銲劑施加完成後， 該晶片110會先被提高移出該層助銲剤，然後精確置放在 該基板120上，使得晶片上之錫鉛凸塊精確地對齊基板120 上相對應的復晶接合墊124。該浸潰器一般係設計在晶片 安放機器内，其包含一平坦的旋轉平台以預備一層助銲 劑。該晶片110上之錫鉛凸塊可利用習知的C4 (Controlled Collapse Chip Connection)製程形成，其 包含步驟（A)在晶片之晶片銲墊（bonding pad)上形成一錫 球突起下冶金（under bump metallurgy, UBM);以及步称 (B)在UB Μ上形成鍚球突起》 然後，該晶片110以及基板120係被移至一回焊爐 (reflow oven)内，並且經由該回焊製程形成錫鉛連接 (solder joint) 112。該錫鉛連接112係用以將該晶片110 固定於基板120並且電性連接該晶片110至基板120。4443 64 V. Description of the invention (6). A plurality of flip-chip bonding pads 124 and a plurality of wire bonding pads 122 are provided around the compound bonding pads 124. The flip-chip bonding pad 124 and the wire bonding pad-122 are a plurality of solder balls electrically connected to the lower surface of the substrate 120 by using conductive traces and vias (not shown). 126. The wafer 110 is first moved to a dip fluxer by an automated selection and placement machine, and immersed in a flux. After the application of the flux is completed, the wafer 110 is first lifted out of the layer of flux, and then accurately placed on the substrate 120, so that the tin-lead bumps on the wafer are precisely aligned with the corresponding polycrystals on the substrate 120.垫 垫 124。 The bonding pad 124. The impregnator is generally designed in a wafer mounting machine and includes a flat rotating platform to prepare a layer of flux. The tin-lead bumps on the wafer 110 can be formed using a conventional C4 (Controlled Collapse Chip Connection) process, which includes step (A) forming a solder ball under metallurgy (under) on a bonding pad of the wafer. (bump metallurgy, UBM); and step (B) forming ball bumps on the UB M. Then, the wafer 110 and the substrate 120 are moved to a reflow oven and formed through the reflow process. Solder joint 112. The tin-lead connection 112 is used for fixing the chip 110 to the substrate 120 and electrically connecting the chip 110 to the substrate 120.

第四圓揭示一晶片130利用一縢層134貼在該晶片110之 背面。該膠層134係先以點膠的方式塗伟在該晶片110之背 面’然後該晶片130再以貼晶片製程（chip attachment ) 貼上·The fourth circle reveals that a wafer 130 is attached to the back of the wafer 110 with a stack of layers 134. The adhesive layer 134 is firstly applied on the back surface of the wafer 110 by a dispensing method, and then the wafer 130 is attached by a chip attachment process.

4 443 8 A____ 五、發明說明（7) 請參照第五囷，該填膠11 4.係利用一自動化點膠系統 (automated underfill dispense system)將填膠材料點-在晶片110之邊緣。然後該填膠材料經由毛細作用吸到晶 片110之下而完成填膠製程。然後將完成填膠之產物移至 一填膠硬.化爐（underfill curing oven)内，硬化該填膠 114 ° 根據本發明第一較佳實施例之方法，其係在膠層134之 點膠步驟完成後，再進行填膠硬化製程。所以該第一晶片 以及基板在點膠步驟前不會因硬化製程而產生弩翹，藉此 可確保後續製程例如點膠之進行。此外，由於該膠層134 係先被瑷化而形成一保護層於晶片110之背面》因而，在 該填膠114硬化的過程中，該已硬化的膠層134可以幫助該 第一晶片抵抗填膠硬化製程產生之應力，藉此改善晶片破 裂（die crack)之問題。 然後，將銲線132係利用習知的線銲（wire bonding)技 術分別連接該晶片130之晶片銲墊132至該基板120上表面 之線接合墊122 ;並且利用習知的塑膠模塑法（例如轉注 成形法（t r a n s f e r m 〇〖d i n g ))形成一封膝體1 4 0復蓋於該 晶片110、130以及基板120上表面之一部分。最後，以習 用之方法將錫球裝設於該基板120下表面之複數個錫球銲 墊12 6，即可製得如第一圖所示之堆4晶片封裝構造1〇〇。4 443 8 A____ V. Description of the invention (7) Please refer to the fifth step, the glue filling 4. 4. Use an automated underfill dispense system to place the glue filling material on the edge of the wafer 110. The glue-filling material is then sucked under the wafer 110 by capillary action to complete the glue-filling process. The finished product is then moved to an underfill curing oven, which cures the underfill 114 ° According to the method of the first preferred embodiment of the present invention, it is dispensed on the glue layer 134 After the steps are completed, the glue filling and hardening process is performed. Therefore, the first wafer and the substrate will not be warped by the hardening process before the dispensing step, thereby ensuring that subsequent processes such as dispensing are performed. In addition, since the adhesive layer 134 is first agitated to form a protective layer on the back surface of the wafer 110, the hardened adhesive layer 134 can help the first wafer resist filling during the hardening process of the filler 114. The stress generated by the glue hardening process, thereby improving the problem of die crack. Then, the bonding wires 132 are respectively connected to the wafer bonding pads 132 of the wafer 130 to the wire bonding pads 122 on the upper surface of the substrate 120 using a conventional wire bonding technology; and a conventional plastic molding method ( For example, a transfer molding method is used to form a knee body 140 covering a portion of the upper surfaces of the wafers 110 and 130 and the substrate 120. Finally, a plurality of solder ball pads 12 6 are mounted on the lower surface of the substrate 120 by a conventional method to obtain a stack of 4 chip packages 100 as shown in the first figure.

第六圖至第八圖係用以說明根據本發明第二較佳實施 例之製造堆疊晶片封裝構造之方法。 第六圊揭示一晶片110利用複數個踢船連接（solder6 to 8 are diagrams for explaining a method of manufacturing a stacked chip package structure according to a second preferred embodiment of the present invention. The sixth 圊 reveals that a chip 110 is connected by a plurality of kickers (solder

4443 64 五、發明說明（8) j〇int)112接合至—基板120，其中技術細節係同前所述/ 請參煦第七®’當填膠114形成於晶片110與基板120之-間後，該填膠11 4係被部份硬化使得其固化但不變硬。該 部份硬化製程可以是在烤箱中烘烤或是對該填膠114吹熱 空氣。該固化的時間以及溫度係選擇使得該晶片1 1 0及基 板120維持最小之鸞翹程度，同時又足以固化該填膠114以 進行後續製程。在本發明中’ 「固化（g e 1 )」係指液態填 膠變成_固體。 第八圖揭示一晶片130利用一膠層134貼在該晶片110之 背面。由於該填膠114係僅被加熱使得其固化但不變硬， 因此該晶片110以及基板120維持最小之脊翹程度，而可確 保膠層134精確地點在晶片110背面之預定點膠的位置。 然後，完全硬化該膠層134以及填膠114使得其硬化 (cured)。當該膠層1 34以及填膠1 14選擇使其最大放熱溫 度相近時，則該膠層134以及填膠114可同時進行該硬化 (curing)製程 。 可以理解的是，該膠層134較佳係選擇使其最大放熱溫 度小於填膠114之最大放熱溫度。例如一適當之具低最大 放熱溫度之膠層為購自QUANTUM MATERIALS, INC.之 QMI536。藉此該具低最大放熱溫度之膠層134可在較低之 溫度即完全硬化（例如1 0 0 °C 1小時），待其冷卻而形成一 保護層於晶片110之背面後，再完全硬化該填膠114»因 而’在該填膠114完全硬化的過程中，晶片130以及該已完 全硬化的膠層134可以幫助該晶片110抵抗在完全硬化製程4443 64 V. Description of the invention (8) jint) 112 is bonded to the substrate 120, of which the technical details are the same as described above / please refer to the seventh ® when the glue 114 is formed between the wafer 110 and the substrate 120 After that, the filler 11 4 series was partially hardened so that it was cured but not hardened. The partial hardening process may be baking in an oven or blowing hot air to the filler 114. The curing time and temperature are selected so that the wafer 110 and the substrate 120 maintain a minimum warpage degree, and at the same time, it is sufficient to cure the filler 114 for subsequent processes. In the present invention, "" curing (g e 1) "means that the liquid filler becomes solid. The eighth figure shows that a wafer 130 is attached to the back of the wafer 110 with an adhesive layer 134. Since the filler 114 is only heated to make it solidify but not hard, the wafer 110 and the substrate 120 maintain a minimum degree of ridges, and the adhesive layer 134 can be accurately positioned at a predetermined dispensing position on the back of the wafer 110. Then, the glue layer 134 and the filler 114 are completely hardened so that they are cured. When the adhesive layer 1 34 and the filler 114 are selected so that their maximum exothermic temperatures are similar, the adhesive layer 134 and the filler 114 can simultaneously perform the curing process. It can be understood that the adhesive layer 134 is preferably selected so that its maximum exothermic temperature is lower than the maximum exothermic temperature of the filler 114. For example, a suitable adhesive layer with a low maximum exothermic temperature is QMI536 available from QUANTUM MATERIALS, INC. As a result, the adhesive layer 134 with a low maximum exothermic temperature can be completely hardened at a lower temperature (for example, 100 ° C for 1 hour). After it is cooled to form a protective layer on the back surface of the wafer 110, it is completely cured. The filler 114 »Thus, during the hardening of the filler 114, the wafer 130 and the fully cured adhesive layer 134 can help the wafer 110 resist the hardening process.

4 443 6 4 五、發明說明（9) 卡所承受之應力，藉此改善晶片破裂（die crack)之問 題。 其餘之打線製程、封膠製程以及錫球裝設製程之細節 係同前所述》 根據本發明第二較佳實施例之方法，由於該填膠114係 僅被加熱至使其固化但不變硬，因此基板所受之加熱溫度 係遠低於習用製程。所以該晶片11()以及基板12〇不會在部 份硬化製程（partial curing process)中受到太大之應 力’藉此可使得該晶片110以及基板12〇之弩翹最小化以確 保後續製程之進行。此外，由於該膠層134以及填膠114可 以選擇使其同時進行硬化（curing)製程’藉此可以縮短生 產時間（cycle time)因而降低製造成本》 雖然本發明已以前述較佳實施例揭示，然其並非用以 限定本發明’任何熟習此技藝者，在不脫離本發明之精神 和範圍内’當可作各種之更動與修改，因此本發明之保護 範团當視後附之申請專利範圍所界定者為準。4 443 6 4 V. Description of the invention (9) The stress on the card to improve the problem of die crack. Details of the rest of the wire bonding process, the sealing process and the solder ball mounting process are the same as described above. According to the method of the second preferred embodiment of the present invention, since the filler 114 is only heated to make it solidify but not change. Hard, so the heating temperature of the substrate is much lower than the conventional process. Therefore, the wafer 11 () and the substrate 12 will not be subjected to too much stress in the partial curing process. This can minimize the warpage of the wafer 110 and the substrate 12 to ensure the subsequent process. get on. In addition, since the adhesive layer 134 and the filler 114 can be selected to undergo a curing process at the same time, thereby reducing cycle time and thereby reducing manufacturing costs. "Although the present invention has been disclosed in the foregoing preferred embodiments, However, it is not intended to limit the present invention. 'Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention'. Therefore, the protection scope of the present invention should be regarded as the scope of the attached patent The ones defined shall prevail.

Claims (1)

4443 64 六、申請專利範团 1 、一種製造堆疊晶片封裝構造之方法，其包含下列步 期ί : 提供一基板具有一上表面及一下表面，該基板上表面 設有複數個復晶接合墊（flip-chip bonding pad)以及複 數個線接合墊（wire-bonding pad)設於該覆晶接合塾之周 圍； 提供第一晶片具有複數個錫鉛凸塊（solder bump)設 於其正面： 將該第一晶片置放在基板上’使得該第一晶片之錫鉛 凸塊對齊該基板上相對應的復晶接舍墊； 回焊該錫鉛凸塊，藉此將該第一晶片固定於基板並且 電性連接該第一晶片至基板； 提供第二晶片具有複數個晶片鲜塾（b〇nding pad)設 於其正面； 將第二晶片之背面利用一鏐層貼在該第一晶片上； 硬化（curing)該膠層； 形成一填膠於第一晶片與基板間； 硬化（cur ing)該填膠； 電性連接該第二晶片至該複數個線接合墊；及 形成一封膠髏包覆該第一晶片第二晶片以及該基板 上表面之一部分β f : 請專利範園第1項之製造堆4晶片封裝構造之方 ，中該基板另包含複數個錫球銲墊設於該基板下表4443 64 VI. Patent application group 1. A method for manufacturing a stacked wafer package structure, including the following steps: Provide a substrate with an upper surface and a lower surface, and the upper surface of the substrate is provided with a plurality of polycrystalline bonding pads ( A flip-chip bonding pad) and a plurality of wire-bonding pads are provided around the flip-chip bonding pad; a first chip is provided with a plurality of tin-lead bumps provided on a front surface thereof: The first wafer is placed on the substrate, so that the tin-lead bumps of the first wafer are aligned with the corresponding polycrystalline pads on the substrate; the tin-lead bumps are re-soldered, thereby fixing the first wafer to the substrate. And electrically connecting the first wafer to the substrate; providing a second wafer having a plurality of wafer pads provided on the front surface thereof; and attaching a back surface of the second wafer to the first wafer using a wafer layer; Curing the glue layer; forming a glue between the first wafer and the substrate; curing the glue; electrically connecting the second wafer to the plurality of wire bonding pads; and forming a glue skull Wrap the first Wafer and the second wafer substrate on a surface of a portion β f: Please manufacturing Patent Fan Garden Party stack 1, Paragraph 4 of the chip package structure, in which the substrate further comprises a plurality of solder ball pads disposed on the lower substrate table 4 443 6 4 六、申請專利範園 面’該複數個錫球銲墊係分別電性連接至該複數個覆晶接 合墊以及線接合墊。 3 、依申請專利範圍第2項之製造堆疊晶片封裝構造之方 法，其另包含將錫球襞設於該錫球銲墊之步驟。 4、 依申請專利範圍第1項之製造堆疊晶片封裝構造之方 法，其中該膠層大致可在125-150 °C下10分鐘内完全硬 化。 5、 依申請專利範圍第1項之製造堆疊晶片封裝構造之方 法，其中該基板係以聚醯亞胺薄片（polyimide film)或玻 璃織維強化BT(bismaleimide-triazine)樹脂製成。 6 、依申請專利範圍第5項之製造堆疊晶片封裝構造之方 法，其中該基板之厚度不大於0.36mm。 7、一種製造堆疊晶片封裝構造之方法，其包含下列步 驊： 提供一基板具有一上表面及一下表面，該基板上表面 設有複數個復晶接合墊以及複數個線接合墊設於該復晶接 合墊之周園； 提供第一晶片具有複數個錫鉛凸塊設於其正面； 將該第一晶片里放在基板上，使得該第一晶片之錫鉛4 443 6 4 VI. Patent Application Fanyuan Surface ’The plurality of solder ball pads are electrically connected to the flip-chip bonding pads and wire bonding pads, respectively. 3. The method for manufacturing a stacked chip package structure according to item 2 of the scope of patent application, which further includes the step of placing a solder ball on the solder ball pad. 4. The method for manufacturing a stacked chip package structure according to item 1 of the scope of patent application, wherein the adhesive layer can be completely hardened in about 10 minutes at 125-150 ° C. 5. The method for manufacturing a stacked chip package structure according to item 1 of the scope of patent application, wherein the substrate is made of polyimide film or glass-woven BT resin (bismaleimide-triazine). 6. The method for manufacturing a stacked chip package structure according to item 5 of the scope of patent application, wherein the thickness of the substrate is not greater than 0.36 mm. 7. A method for manufacturing a stacked chip package structure, comprising the following steps: providing a substrate having an upper surface and a lower surface, the upper surface of the substrate being provided with a plurality of polycrystalline bonding pads and a plurality of wire bonding pads provided in the complex; A circle of crystal bonding pads; providing a first wafer with a plurality of tin-lead bumps provided on its front surface; placing the first wafer inside a substrate so that the tin-lead of the first wafer 方 接 之表晶 造下復 構板個 裝基數 封該複 片於該 晶設至 疊墊接 堆銲連 造球性 製錫電 之個別 項數分 7複係 第含墊 圍包銲。 範另球塾 利板錫合 專基個接 請該數線 申中複及 依其該以 、，，整 8法面合 4 443 6 4 六、申請專利範团 凸塊對齊該基板上相對應的覆晶接合墊； 回焊該錫鉛凸塊，藉此將該第一晶片固定於基板並且‘ 電性連接該第一晶片至基板； 、 形成一填膠於第一晶片與基板間； 部份硬化（partial curing)該填膠使得其固化 〔gelation)但不變硬（cured); 提供第一晶片具有複數個晶片鲜塾設於其正面； 將第二晶片之背面利用一膠層貼在該第一晶片上； 硬化（curing)該膠層以及在第一晶片與基板間的填 膠； 電性連接該第二晶片至該複數個線接合墊；及 形成一封膠艘包覆該第一晶片、第二晶片以及該基板 上表面之部分β 9 、依申請專利範園第8項之製造堆疊晶片封裝構造之方 法，其另包含將錫球裝設於該錫球銲墊之步騨。 1 0、依申請專利範圍第7項之製造堆*晶片封裝構造之 方法，其中該膠層大致可在125-150 eC下10分鐘内完全硬The surface of the crystal is connected to the base plate of the composite board. The package is sealed in the crystal to the laminated pad. The number of individual items of the tin making system is 7. The system consists of the pad-packed welding. Fan Qiuqiu and the board of patents and tins are invited to apply for the number of lines and apply them in accordance with the law, and the whole 8 law face 4 443 6 4 Six, the patent application Fan group bumps aligned on the substrate corresponding Flip-chip bonding pad; resoldering the tin-lead bump, thereby fixing the first wafer to the substrate and 'electrically connecting the first wafer to the substrate; forming a glue between the first wafer and the substrate; Partial curing The filler makes the gelation but does not harden. The first wafer is provided with a plurality of wafers arranged on its front surface. The back of the second wafer is affixed with an adhesive layer. On the first wafer; curing the adhesive layer and filling between the first wafer and the substrate; electrically connecting the second wafer to the plurality of wire bonding pads; and forming a glue boat to cover the first wafer A wafer, a second wafer, and a portion of the upper surface of the substrate β 9. The method for manufacturing a stacked wafer package structure according to item 8 of the patent application patent garden, further comprising the step of mounting a solder ball on the solder ball pad. . 10. According to the method for manufacturing a stack * chip package structure according to item 7 of the patent application scope, the adhesive layer can be completely hardened within 10 minutes at 125-150 eC. Λ ： φ 第15頁 4443S04 六、申請專利範困 化0 11、依申請專利範圍第7項之製造堆疊晶片封裝構造之 方法，其中該基板係以聚醯亞胺薄片或玻璃纖維強化 BT(bismaleimide-triazine)樹脂製成。 1 2、依申請專利範園第7項，其中該基板之厚度不大於 0.36mm。 1 3 、依申請專利範圍第7項之製造堆叠晶片封裝構造之 方法，其中該膠層以及填膠之最大放熱溫度大致相同。 1 4、依申請專利範圍第1 3項之製造堆疊晶片封裝構造 之方法，其中硬化該膠層以及在第一晶片與基板間的填膠 之步驟係包含同時硬化該膠層以及填膠。 1 5 、依申請專利範圍第7項之製造堆疊晶片封裝構造之 方法，其中該膠層之最大放熱溫度係小於填膠之最大放熱 溫度。 1 6 、依申請專利範圍第1 5項之製造堆4晶片封裝構造 之方法，其中硬化該膠層以及在第一晶片與基板間的填膠 W 之步驟係先硬化該膠眉…再峡化玆填膠。Λ: φ Page 15 4443S04 VI. Application for patent application 0 11. Method for manufacturing a stacked chip package structure according to item 7 of the patent application scope, wherein the substrate is reinforced with polyimide sheet or glass fiber reinforced BT (bismaleimide -triazine) resin. 1 2. According to item 7 of the patent application park, the thickness of the substrate is not more than 0.36mm. 13. The method for manufacturing a stacked chip package structure according to item 7 of the scope of patent application, wherein the maximum exothermic temperature of the adhesive layer and the filler is approximately the same. 14. The method for manufacturing a stacked chip package structure according to item 13 of the scope of patent application, wherein the steps of hardening the adhesive layer and filling the adhesive between the first wafer and the substrate include simultaneously curing the adhesive layer and the adhesive filling. 15. The method for manufacturing a stacked chip package structure according to item 7 of the scope of patent application, wherein the maximum exothermic temperature of the adhesive layer is less than the maximum exothermic temperature of the filling. 16. The method for manufacturing a stack 4 chip package structure according to item 15 of the scope of patent application, wherein the steps of hardening the adhesive layer and filling W between the first wafer and the substrate are first hardening the eyebrows ... Hereby fill. CM fcCM fc
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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7416919B2 (en) 2004-11-03 2008-08-26 Advanced Semiconductor Engineering, Inc. Method for wafer level stack die placement
US7902679B2 (en) 2001-03-05 2011-03-08 Megica Corporation Structure and manufacturing method of a chip scale package with low fabrication cost, fine pitch and high reliability solder bump
TWI398942B (en) * 2007-05-22 2013-06-11 United Test & Assembly Ct Lt Method of assembling a silicon stacked semiconductor package

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7902679B2 (en) 2001-03-05 2011-03-08 Megica Corporation Structure and manufacturing method of a chip scale package with low fabrication cost, fine pitch and high reliability solder bump
US8158508B2 (en) 2001-03-05 2012-04-17 Megica Corporation Structure and manufacturing method of a chip scale package
US7416919B2 (en) 2004-11-03 2008-08-26 Advanced Semiconductor Engineering, Inc. Method for wafer level stack die placement
TWI398942B (en) * 2007-05-22 2013-06-11 United Test & Assembly Ct Lt Method of assembling a silicon stacked semiconductor package

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