JPH05152373A - Semiconductor element mounting structure - Google Patents
Semiconductor element mounting structureInfo
- Publication number
- JPH05152373A JPH05152373A JP33765091A JP33765091A JPH05152373A JP H05152373 A JPH05152373 A JP H05152373A JP 33765091 A JP33765091 A JP 33765091A JP 33765091 A JP33765091 A JP 33765091A JP H05152373 A JPH05152373 A JP H05152373A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor element
- circuit board
- semiconductor chip
- resin
- periphery
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 67
- 229920005989 resin Polymers 0.000 claims abstract description 20
- 239000011347 resin Substances 0.000 claims abstract description 20
- 230000002093 peripheral effect Effects 0.000 claims description 8
- 238000007789 sealing Methods 0.000 abstract description 9
- 238000000034 method Methods 0.000 description 8
- 238000010586 diagram Methods 0.000 description 3
- 239000004840 adhesive resin Substances 0.000 description 2
- 229920006223 adhesive resin Polymers 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000010410 layer Substances 0.000 description 2
- 239000007788 liquid Substances 0.000 description 2
- 239000012790 adhesive layer Substances 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/1015—Shape
- H01L2924/10155—Shape being other than a cuboid
- H01L2924/10157—Shape being other than a cuboid at the active surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、半導体素子を回路基板
に直接接続するフリップチップボンディングの実装構造
に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a flip chip bonding mounting structure for directly connecting a semiconductor element to a circuit board.
【０００２】[0002]
【従来の技術】近年、半導体素子の微細化に伴ない、半
導体素子の多端子化の傾向は顕著である。そのため、半
導体チップの実装工程においては、従来のワイヤーボン
ディングによる端子接続方式では対処しきれなくなって
きており、新たにフリップチップボンディング方式が脚
光を浴びるようになった。フリップチップボンディング
方式は、電極パッド上に半田や金などから成るバンプ
（突起電極）が形成された半導体チップをフェイスダウ
ン方式で、回路基板に接続する方法である。2. Description of the Related Art In recent years, along with the miniaturization of semiconductor elements, the tendency of multi-terminals of semiconductor elements has become remarkable. Therefore, in the mounting process of the semiconductor chip, the conventional terminal connection method by wire bonding cannot be dealt with enough, and the flip chip bonding method has come into the spotlight. The flip chip bonding method is a method of connecting a semiconductor chip in which bumps (projection electrodes) made of solder, gold or the like are formed on electrode pads to a circuit board by a face down method.
【０００３】図４に、従来の半導体素子の実装構造の側
面図を示す。同図において、半導体チップ10は、回路基
板11上にフリップチップボンディングされ、さらに半導
体チップ10の素子面と回路基板11の間及びその周縁を樹
脂12で封止されている。樹脂12による封止の目的は、接
続部の機械的強度を高め、半導体チップ10の素子面への
水等の侵入を防止して実装の安定した信頼性を得ること
である。封止樹脂12は、ディスペンサー（不図示）等に
より液体の状態で供給され、その後、加熱や光照射等の
手段によって硬化される。ここで、半導体チップ10の周
縁部を覆う領域の樹脂12は、半導体チップ10の周囲から
素子面への水分侵入に対して、その経路を長くすること
により、高信頼性を確保する点で効果のあるものであ
る。FIG. 4 shows a side view of a conventional semiconductor element mounting structure. In the figure, the semiconductor chip 10 is flip-chip bonded onto the circuit board 11, and the space between the element surface of the semiconductor chip 10 and the circuit board 11 and its periphery is sealed with resin 12. The purpose of the sealing with the resin 12 is to increase the mechanical strength of the connection portion, prevent water and the like from entering the element surface of the semiconductor chip 10, and obtain stable mounting reliability. The sealing resin 12 is supplied in a liquid state by a dispenser (not shown) or the like, and then cured by means such as heating or light irradiation. Here, the resin 12 in the region covering the peripheral portion of the semiconductor chip 10 is effective in ensuring high reliability by lengthening the path for moisture intrusion from the periphery of the semiconductor chip 10 to the element surface. There is something.
【０００４】[0004]
【発明が解決しようとする課題】しかしながら、上述の
ような構造においては、半導体チップ10周辺のコーナー
部に供給された液状樹脂12は、その表面張力により流動
し、半導体チップ10のコーナー部が露出したり、露出し
ないまでも樹脂層が薄くなり、信頼性に悪影響を及ばす
という問題があった。本発明は、このような問題を解決
し、半導体素子がその周縁を封止するための樹脂から露
出するようなことのない、半導体素子の実装構造を提供
することを目的とする。However, in the structure as described above, the liquid resin 12 supplied to the corner portion around the semiconductor chip 10 flows due to the surface tension, and the corner portion of the semiconductor chip 10 is exposed. However, there is a problem that the resin layer becomes thin even if it is not exposed, and the reliability is adversely affected. SUMMARY OF THE INVENTION It is an object of the present invention to solve such a problem and provide a semiconductor element mounting structure in which the semiconductor element is not exposed from the resin for sealing the peripheral edge thereof.
【０００５】[0005]
【課題を解決するための手段】上記目的を達成するた
め、本発明の半導体素子の実装構造は、半導体素子の電
極と回路基板の電極とが対向した状態で電気的導通を成
し、樹脂により前記半導体素子と前記回路基板間、及び
その周縁を封止して成る半導体素子の実装構造におい
て、前記半導体素子の外周角部が、２つ以上の鈍角で形
成されているか、または円弧状になっているか、または
前記回路基板に向けて漸次多く切り欠かれている。In order to achieve the above object, the semiconductor element mounting structure of the present invention has a structure in which the electrodes of the semiconductor element and the electrodes of the circuit board face each other and are electrically connected to each other. In a mounting structure of a semiconductor element formed by sealing the semiconductor element and the circuit board and a peripheral edge thereof, an outer peripheral corner portion of the semiconductor element is formed with two or more obtuse angles or has an arc shape. Or is progressively cut out toward the circuit board.
【０００６】[0006]
【作用】このようにすると、樹脂が流動して半導体素子
の一部が露出してしまうようなことがなく、封止樹脂層
が半導体素子の外周に対して均一な幅で形成されるた
め、実装の信頼性の向上が図れる。With this configuration, the resin does not flow and the semiconductor element is not partially exposed, and the sealing resin layer is formed with a uniform width with respect to the outer periphery of the semiconductor element. The reliability of mounting can be improved.
【０００７】[0007]
【実施例】以下、本発明の実施例を図面を参照しつつ、
説明する。ここでは、例えば、特開平2-159090号の実施
例に記載の方法で、回路基板に半導体チップを接続して
いる。即ち、半導体チップの素子面に接着剤層を形成
後、電極以外の領域を硬化させ、それにより電極上のみ
に導電媒体を配設する。その後、半導体チップと回路基
板の間に別の接着樹脂を介在させ、半導体チップと回路
基板の電極同志を位置合わせし、半導体チップの電極に
配設された導電媒体と回路基板の電極間の導通が得られ
るように、半導体チップの背面から加圧して、接触させ
た状態で接着樹脂を硬化させるという方法である。Embodiments of the present invention will now be described with reference to the drawings.
explain. Here, for example, the semiconductor chip is connected to the circuit board by the method described in the example of Japanese Patent Laid-Open No. 2-159090. That is, after forming the adhesive layer on the element surface of the semiconductor chip, the area other than the electrodes is cured, whereby the conductive medium is arranged only on the electrodes. After that, another adhesive resin is interposed between the semiconductor chip and the circuit board, the electrodes of the semiconductor chip and the circuit board are aligned, and conduction between the conductive medium arranged on the electrode of the semiconductor chip and the electrode of the circuit board is established. Is obtained by applying pressure from the back surface of the semiconductor chip to cure the adhesive resin in a state of contacting.
【０００８】図１に、本発明を実施した半導体チップの
実装構造を示す。（ａ）は平面図であり、（ｂ）は側面
図である。半導体チップ20の電極と回路基板11の電極
は、導電媒体13を介して電気的導通を得ており、半導体
チップ20と回路基板11の間及びその周辺は樹脂12によっ
て封止されている。半導体チップ20の形状は、そのコー
ナー部20ａが直角ではなく、２つの鈍角で形成されてい
る。このような形状により、実装時に封止樹脂12が半導
体チップの周縁に均等に流れだし、その周囲を均一な厚
さで被覆することができる。FIG. 1 shows a semiconductor chip mounting structure embodying the present invention. (A) is a plan view and (b) is a side view. The electrodes of the semiconductor chip 20 and the electrodes of the circuit board 11 are electrically connected through the conductive medium 13, and the space between the semiconductor chip 20 and the circuit board 11 and its periphery is sealed with the resin 12. The shape of the semiconductor chip 20 is such that the corner portion 20a is not a right angle but two obtuse angles. With such a shape, the sealing resin 12 evenly flows out to the periphery of the semiconductor chip during mounting, and the periphery thereof can be covered with a uniform thickness.
【０００９】図２に、別の実施例の平面図を示す。本実
施例においては、半導体チップ21のコーナー部21ａは円
弧上に形成されており、図１の形状のものと同様の効果
が得られる。FIG. 2 shows a plan view of another embodiment. In this embodiment, the corner portion 21a of the semiconductor chip 21 is formed in a circular arc, and the same effect as that of the shape of FIG. 1 can be obtained.
【００１０】図３に、別の実施例を示す。（ａ）は斜視
図であり、（ｂ）は側面図である。本実施例において
は、半導体チップ22は、コーナー部において素子面側か
ら背面側にかけて傾斜を持った形状になっている。この
ようにすることにより、封止樹脂12が素子面のコーナー
部にも流れ込み易くなり、図１及び図２と同様の効果が
得られる。FIG. 3 shows another embodiment. (A) is a perspective view and (b) is a side view. In the present embodiment, the semiconductor chip 22 has a shape having an inclination from the element surface side to the back surface side at the corner portion. By doing so, the sealing resin 12 easily flows into the corner portion of the element surface, and the same effect as in FIGS. 1 and 2 is obtained.
【００１１】上述の３例の形状は、半導体チップのコー
ナー部を機械的に切断したり切削したりして得られる。
また、図１及び図２で示すような形状の場合は、例え
ば、ウェハー状態で、取り除くべきコーナー部以外をフ
ォトレジストでマスキングし、コーナーの不要部分をエ
ッチングで取り除くことによって、工程の簡略化を図る
こともできる。尚、本発明の実施例は、上述の３例に限
定されるものではなく、本発明に係る特徴を有していれ
ば、いかなる形態においても応用できるものである。The shapes of the above-mentioned three examples are obtained by mechanically cutting or cutting the corner portion of the semiconductor chip.
Further, in the case of the shape as shown in FIGS. 1 and 2, for example, in the wafer state, by masking the portions other than the corner portions to be removed with photoresist and removing unnecessary portions of the corners by etching, the process is simplified. It can also be planned. The embodiments of the present invention are not limited to the above-mentioned three examples, and can be applied in any form as long as they have the characteristics according to the present invention.
【００１２】[0012]
【発明の効果】以上説明したように、本発明によれば、
半導体素子の周縁を封止するための樹脂が流動して半導
体素子の一部が露出することによる水分の侵入等のトラ
ブルによって、半導体素子の不良を生じるようなことが
ないので、その信頼性は大幅に向上する。As described above, according to the present invention,
Since the resin for sealing the peripheral edge of the semiconductor element flows and a part of the semiconductor element is exposed to cause a trouble such as intrusion of moisture, a defect of the semiconductor element does not occur, so that reliability is high. Greatly improved.
【図１】 本発明を実施した半導体素子の実装構造を示
す図。FIG. 1 is a diagram showing a mounting structure of a semiconductor element embodying the present invention.
【図２】 本発明の別の実施例を示す図。FIG. 2 is a diagram showing another embodiment of the present invention.
【図３】 本発明の別の実施例を示す図。FIG. 3 is a diagram showing another embodiment of the present invention.
【図４】 従来の半導体素子の実装構造を示す図。FIG. 4 is a view showing a conventional semiconductor element mounting structure.
10 半導体チップ 11 回路基板 12 樹脂 13 導電媒体 20 半導体チップ 20ａ コーナー部 21 半導体チップ 21ａ コーナー部 22 半導体チップ 10 semiconductor chip 11 circuit board 12 resin 13 conductive medium 20 semiconductor chip 20a corner 21 semiconductor chip 21a corner 22 semiconductor chip
Claims (3)
対向した状態で電気的導通を成し、樹脂により前記半導
体素子と前記回路基板間及びその周縁を封止して成る半
導体素子の実装構造において、 前記半導体素子の外周角部が、２つ以上の鈍角で形成さ
れていることを特徴とする半導体素子の実装構造。1. Mounting of a semiconductor element in which the electrodes of the semiconductor element and the electrodes of the circuit board face each other and are electrically connected to each other, and the gap between the semiconductor element and the circuit board and its periphery are sealed with a resin. In the structure, a mounting structure of a semiconductor element, wherein an outer peripheral corner portion of the semiconductor element is formed with two or more obtuse angles.
対向した状態で電気的導通を成し、樹脂により前記半導
体素子と前記回路基板間及びその周縁を封止して成る半
導体素子の実装構造において、 前記半導体素子の外周角部が、円弧状になっていること
を特徴とする半導体素子の実装構造。2. A semiconductor element mounting in which the electrodes of the semiconductor element and the electrodes of the circuit board face each other to establish electrical conduction, and the resin seals the semiconductor element and the circuit board and the periphery thereof. In the structure, the semiconductor element mounting structure is characterized in that an outer peripheral corner portion of the semiconductor element has an arc shape.
対向した状態で電気的導通を成し、樹脂により前記半導
体素子と前記回路基板間及びその周縁を封止して成る半
導体素子の実装構造において、 前記半導体素子の外周角部が、前記回路基板に向けて漸
次多く切り欠かれていることを特徴とする半導体素子の
実装構造。3. A mounting of a semiconductor element in which the electrodes of the semiconductor element and the electrodes of the circuit board face each other to establish electrical conduction, and the resin seals the semiconductor element and the circuit board and the periphery thereof. In the structure, the outer peripheral corner of the semiconductor element is gradually cut away toward the circuit board, and a mounting structure of the semiconductor element.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP33765091A JPH05152373A (en) | 1991-11-26 | 1991-11-26 | Semiconductor element mounting structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP33765091A JPH05152373A (en) | 1991-11-26 | 1991-11-26 | Semiconductor element mounting structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH05152373A true JPH05152373A (en) | 1993-06-18 |
Family
ID=18310652
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP33765091A Pending JPH05152373A (en) | 1991-11-26 | 1991-11-26 | Semiconductor element mounting structure |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH05152373A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2003005441A1 (en) * | 2001-07-03 | 2003-01-16 | Fujitsu Limited | Coating material of semiconductor chip, coating method of semiconductor chip and semiconductor device |
-
1991
- 1991-11-26 JP JP33765091A patent/JPH05152373A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2003005441A1 (en) * | 2001-07-03 | 2003-01-16 | Fujitsu Limited | Coating material of semiconductor chip, coating method of semiconductor chip and semiconductor device |
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