JPH0846121A - Resin sealed semiconductor device - Google Patents
Resin sealed semiconductor deviceInfo
- Publication number
- JPH0846121A JPH0846121A JP20317095A JP20317095A JPH0846121A JP H0846121 A JPH0846121 A JP H0846121A JP 20317095 A JP20317095 A JP 20317095A JP 20317095 A JP20317095 A JP 20317095A JP H0846121 A JPH0846121 A JP H0846121A
- Authority
- JP
- Japan
- Prior art keywords
- resin
- electrode
- film
- semiconductor chip
- solder
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、樹脂封止型半導体装置
に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a resin-sealed semiconductor device.
【０００２】[0002]
【従来の技術】半導体装置の小型化、高集積化が進む中
で、樹脂封止した半導体装置のサイズを半導体チップの
サイズに近付ける工夫がなされている。このような半導
体装置として、特開昭６２−１４７７３５号公報、実開
昭６３−１３４１号公報および特開昭６２−２３００２
７号公報に記載されたものが知られている。2. Description of the Related Art With the progress of miniaturization and high integration of semiconductor devices, some efforts have been made to bring the size of a resin-sealed semiconductor device closer to the size of a semiconductor chip. As such semiconductor devices, Japanese Patent Laid-Open No. 62-147735, Japanese Utility Model Laid-Open No. 63-1341 and Japanese Patent Laid-Open No. 62-23002 are available.
The one described in Japanese Patent Publication No. 7 is known.
【０００３】特開昭６２−１４７７３５号公報又は特開
昭６２−２３００２７号公報に記載のものは、半導体チ
ップ上の電極部に相当する個所に半田などによりバンプ
を形成した後、このバンプを含めて全体を樹脂で被覆
し、その後樹脂の一部を研磨などにより除去してバンプ
を樹脂表面と面一に露出させた構造のものである。ま
た、特開昭６２−２３００２７号公報には、バンプが露
出した樹脂表面に、そのバンプと接続される回路導体層
を形成することも提案されている。The device disclosed in Japanese Patent Laid-Open No. 62-147735 or Japanese Patent Laid-Open No. 62-230027 includes bumps formed by solder or the like on the portions corresponding to the electrode portions on a semiconductor chip, and then the bumps are included. The entire structure is covered with a resin, and then a part of the resin is removed by polishing or the like to expose the bumps flush with the resin surface. Further, JP-A-62-230027 proposes that a circuit conductor layer connected to the bump is formed on the resin surface where the bump is exposed.
【０００４】一方、実開昭６３−１３４１号公報に記載
されたものは、半導体チップの電極面にバンプを形成
し、そのバンプの一部が突き出るように半導体チップの
周囲を樹脂で封止した構造のものである。On the other hand, in the one disclosed in Japanese Utility Model Laid-Open No. 63-1341, bumps are formed on the electrode surface of a semiconductor chip, and the periphery of the semiconductor chip is sealed with a resin so that a part of the bump protrudes. It is of structure.
【０００５】このように構成された樹脂封止型の半導体
装置は、回路基板上にフェースダウンさせ、バンプに対
応して形成された配線等に、半田などにより接合して実
装される。The resin-encapsulated semiconductor device thus constructed is mounted face down on the circuit board and joined to the wiring or the like formed corresponding to the bumps by soldering or the like.
【０００６】[0006]
【発明が解決しようとする課題】上記従来技術のうち、
特開昭６２−１４７７３５号公報又は特開昭６２−２３
００２７号公報に記載された半導体装置では、バンプの
露出面が封止樹脂の表面と面一であることから、これを
回路基板に実装するにあたり、バンプと基板配線等とを
接続する半田接合部の高さを十分に確保できない。その
ため、実装後の温度変化によって半導体装置と回路基板
との間に生ずる熱歪を、バンプや半田接合部自体の変形
により緩和する作用が小さいから、多大な熱歪により半
田接合部が損傷するおそれがある。Of the above-mentioned conventional techniques,
JP 62-147735 A or JP 62-23
In the semiconductor device described in Japanese Patent Laid-Open No. 0027, since the exposed surface of the bump is flush with the surface of the sealing resin, when mounting this on a circuit board, a solder joint portion for connecting the bump and board wiring or the like. Cannot secure enough height. Therefore, the effect of mitigating the thermal strain generated between the semiconductor device and the circuit board due to the temperature change after mounting by the deformation of the bumps or the solder joint itself is small, and the solder joint may be damaged by the great thermal strain. There is.
【０００７】この点、実開昭６３−１３４１号公報に記
載されたものは、バンプが封止樹脂から突出しているの
で、実装後の温度変化によって生ずる熱歪を、バンプや
半田接合部自体の変形により緩和する作用があるから、
上記のような問題が生ずるおそれは少ない。In this regard, in the one disclosed in Japanese Utility Model Laid-Open No. 63-1341, since the bumps protrude from the sealing resin, thermal strain caused by a temperature change after mounting is generated in the bumps or the solder joints themselves. Because it has a relaxing effect by deformation,
It is unlikely that the above problems will occur.
【０００８】しかし、実開昭６３−１３４１号公報に記
載のものは、半導体チップの電極表面の形状が、バンプ
の接合面の形状と同一に形成されているから、電極又は
バンプと樹脂封止体の接触面を、外部から半導体チップ
の電極に至る方向に沿って見ると、それらの接触面が一
直線状になっている。そのため、その接触面部を介して
外部から水分が容易に浸入するおそれがあり、これによ
り電気特性上好ましくない現象が発生する。つまり、半
導体チップの電極及びこれに接続されている微細な配線
をも腐食させるなど、耐湿性の点で問題がある。この点
は、他の従来技術も同様である。However, in the one disclosed in Japanese Utility Model Laid-Open No. 63-1341, since the shape of the electrode surface of the semiconductor chip is formed to be the same as the shape of the bonding surface of the bump, the electrode or the bump and the resin are sealed. When the contact surfaces of the body are viewed along the direction from the outside to the electrodes of the semiconductor chip, the contact surfaces are straight. Therefore, moisture may easily enter from the outside through the contact surface portion, which causes a phenomenon that is not preferable in terms of electrical characteristics. That is, there is a problem in terms of moisture resistance, such as corroding the electrodes of the semiconductor chip and the fine wiring connected thereto. In this respect, the other conventional techniques are similar.
【０００９】本発明は、上記の問題点等を解決すること
を課題とするものであり、言い換えれば、樹脂封止型半
導体装置において、耐湿性を向上させることを課題とす
る。An object of the present invention is to solve the above problems and the like. In other words, an object of the present invention is to improve the moisture resistance of a resin-sealed semiconductor device.
【００１０】[0010]
【課題を解決するための手段】上記課題は、次の手段に
より解決できる。まず、半導体チップと、この半導体チ
ップの表面に形成された電極と、この電極の表面の一部
を露出して半導体チップの表面に形成された樹脂膜と、
電極と外部との電気的接続をとる導電性部材と、この導
電性部材の一部を露呈させて半導体チップを覆って形成
された樹脂封止体とを備えてなるものとする。さらに、
電極と導電性部材との間に半田を介在させる。The above-mentioned problems can be solved by the following means. First, a semiconductor chip, an electrode formed on the surface of the semiconductor chip, a resin film formed on the surface of the semiconductor chip by exposing a part of the surface of the electrode,
A conductive member for electrically connecting the electrodes to the outside and a resin sealing body formed by exposing a part of the conductive member to cover the semiconductor chip are provided. further,
Solder is interposed between the electrode and the conductive member.
【００１１】[0011]
【作用】上記手段によれば、次の作用により、課題を解
決することができる。まず、電極表面の一部を露出して
半導体チップの表面に形成された樹脂膜（パッシベーシ
ョン膜に相当する。）を備えたことから、言い換えれ
ば、電極表面のうち少なくとも導電性部材が接合される
露出面を除く部分がパッシベーション膜により被覆され
ていることから、外部からの水分浸入を抑制することが
できる。すなわち、電極又は導電性部材（バンプに相当
する。）と樹脂封止体の接触面を、外部から半導体チッ
プの電極に至る方向に沿って見ると、それらの接触面は
一直線状ではなく、少なくとも導電性部材から電極の表
面に移る部分で屈曲し、さらに電極の表面から側面に移
る部分で屈曲した形状になる。そのため、樹脂封止体の
厚みが同じであっても、水分の浸入経路が実質的に長く
なるから、その分だけ水分が浸入し難くなる。しかも、
電極表面の周縁部に樹脂膜を形成しているから、その樹
脂膜の硬化時の収縮によって電極と樹脂膜との密着力が
大きくなり、耐湿性を一層向上できる。According to the above means, the following problems can be solved. First, since a resin film (corresponding to a passivation film) formed on the surface of the semiconductor chip by exposing a part of the electrode surface is provided, in other words, at least a conductive member on the electrode surface is bonded. Since the portion excluding the exposed surface is covered with the passivation film, it is possible to suppress intrusion of water from the outside. That is, when the contact surface between the electrode or the conductive member (corresponding to a bump) and the resin encapsulant is viewed along the direction from the outside to the electrode of the semiconductor chip, the contact surfaces are not straight, and The shape is such that the conductive member bends at the portion moving to the surface of the electrode, and further bends at the portion moving from the surface of the electrode to the side surface. Therefore, even if the resin encapsulant has the same thickness, the water infiltration path becomes substantially long, and accordingly, it becomes more difficult for water to intrude. Moreover,
Since the resin film is formed on the peripheral portion of the electrode surface, the contraction of the resin film during curing increases the adhesion between the electrode and the resin film, and the moisture resistance can be further improved.
【００１２】また、導電性部材と電極と間に半田を介在
させていることから、フリップチップ法により半田を形
成でき、これにより電極表面を樹脂膜と半田によって覆
うことができる。その結果、半田が電極の露出部及びそ
の露出部に隣接する樹脂膜の外表面を覆うことができる
から、樹脂膜よりも耐水性が劣る樹脂封止体に電極が直
接接しない構造にできるので、この点でも耐水性が向上
する。Further, since the solder is interposed between the conductive member and the electrode, the solder can be formed by the flip chip method, and the electrode surface can be covered with the resin film and the solder. As a result, since the solder can cover the exposed portion of the electrode and the outer surface of the resin film adjacent to the exposed portion, it is possible to form a structure in which the electrode does not come into direct contact with the resin encapsulant having poorer water resistance than the resin film. In this respect also, the water resistance is improved.
【００１３】また、フリップチップ実装技術では、半田
バンプを蒸着又はメッキなどの薄膜製造法により形成す
るので、半田層を電極と導電性部材との電気的導通を確
保できる厚みにすることにより、電極への半田接合作業
の時間とコストを低減できることになる。Further, in the flip-chip mounting technique, the solder bumps are formed by a thin film manufacturing method such as vapor deposition or plating. Therefore, the thickness of the solder layer can ensure electrical continuity between the electrodes and the conductive member. It is possible to reduce the time and cost of the solder joining work to.
【００１４】[0014]
【実施例】本発明による半導体装置の一実施例を図１お
よび図２を用いて説明する。図１は断面図、図２は斜視
図である。同図において半導体チップ２があり、この半
導体チップ２の素子が組込まれた主表面にはパッシベー
ション膜（樹脂膜）３が形成されている。このパッシベ
ーション膜３には前記素子と電気的に接続されているパ
ッド（電極）５が形成され、さらにこのパッド５面には
導電性部材としての導電性膜４が半田バンプ６を介して
形成されている。この半田バンプ６は、パッド５と導電
性膜４との電気的接続を良好に保つ。DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the semiconductor device according to the present invention will be described with reference to FIGS. 1 is a sectional view and FIG. 2 is a perspective view. In the figure, there is a semiconductor chip 2, and a passivation film (resin film) 3 is formed on the main surface in which the elements of this semiconductor chip 2 are incorporated. A pad (electrode) 5 electrically connected to the element is formed on the passivation film 3, and a conductive film 4 as a conductive member is formed on the surface of the pad 5 via a solder bump 6. ing. The solder bumps 6 maintain good electrical connection between the pads 5 and the conductive film 4.
【００１５】この導電性膜４は、たとえば周知の厚膜印
刷法により形成される導電性膜と同様の材料で形成され
るものである。さらに、導電性膜４のみを露呈させた状
態で、半導体チップ２の周辺を被覆して封止樹脂１が設
けられている。The conductive film 4 is formed of the same material as the conductive film formed by the well-known thick film printing method, for example. Furthermore, the sealing resin 1 is provided by covering the periphery of the semiconductor chip 2 with only the conductive film 4 exposed.
【００１６】すなわち、図１と図２に示したように、半
導体チップ２の表面に独立して形成された複数個のパッ
ド５の表面の一部を露出して、半導体チップ２の表面に
パッシベーション膜３が形成されいる。つまり、パッド
５の表面の縁部はパッシベーション膜３により覆われ、
各パッド５の露出部に外部との電気的接続をとる導電性
膜４が半田バンプ６を介して接合されている。したがっ
て、半田バンプ６は、パッド５と接する接合面と、封止
樹脂１と接する接着面と、パッシベーション膜３と接す
る接着面とを有している。導電性膜４は封止樹脂１の表
面よりも外方に突出した突出部を有している。このよう
な導電性膜４の配置は、図２に示すように、半導体装置
の長辺に沿った方向の少なくとも２列の縦列配置とされ
ている。That is, as shown in FIGS. 1 and 2, a part of the surface of the plurality of pads 5 formed independently on the surface of the semiconductor chip 2 is exposed and the surface of the semiconductor chip 2 is passivated. The film 3 is formed. That is, the edge portion of the surface of the pad 5 is covered with the passivation film 3,
A conductive film 4 for electrically connecting to the outside is bonded to the exposed portion of each pad 5 via a solder bump 6. Therefore, the solder bump 6 has a bonding surface that contacts the pad 5, an adhesive surface that contacts the sealing resin 1, and an adhesive surface that contacts the passivation film 3. The conductive film 4 has a protruding portion that protrudes outward from the surface of the sealing resin 1. As shown in FIG. 2, the conductive films 4 are arranged in at least two columns in the direction along the long side of the semiconductor device.
【００１７】このように構成される実施例によれば、パ
ッド５の表面のうち少なくとも半田バンプ６が接合され
る露出面を除く部分が、パッシベーション膜３により被
覆されていることから、外部から半導体チップ２に至る
方向に沿って、封止樹脂１と半田バンプ６及びパッシベ
ーション膜３との接触面を見ると、それらの接触面は一
直線状ではなく、少なくとも半田バンプ６からパッド５
の表面に移る部分で屈曲し、さらにパッド５の表面から
側面に移る部分で屈曲した形状になっている。そのた
め、封止樹脂１の厚みが同じであっても、水分の浸入経
路が実質的に長くなるから、その分だけ水分が浸入し難
くなる。また、パッド５の表面の外縁がパッシベーショ
ン膜３により被覆されていることから、パッシベーショ
ン膜３の硬化時の収縮によって、パッド５とパッシベー
ション膜３との密着力が大きくなるので、耐湿性を一層
向上できる。しかも、パッシベーション膜３よりも一般
に耐水性が劣るとされている封止樹脂１にパッド５が直
接接しない構造にしているので、一層、耐水性が向上す
る。According to the embodiment configured as described above, since at least a portion of the surface of the pad 5 excluding the exposed surface to which the solder bump 6 is bonded is covered with the passivation film 3, the semiconductor is externally applied. Looking at the contact surfaces of the sealing resin 1, the solder bumps 6 and the passivation film 3 along the direction reaching the chip 2, these contact surfaces are not in a straight line form, and at least the solder bumps 6 to the pads 5 are formed.
Has a shape that is bent at a portion that moves to the surface of, and further bent at a portion that moves from the surface of the pad 5 to the side surface. Therefore, even if the sealing resin 1 has the same thickness, the moisture infiltration path is substantially lengthened, and accordingly, it becomes more difficult for moisture to intrude. Further, since the outer edge of the surface of the pad 5 is covered with the passivation film 3, the adhesion between the pad 5 and the passivation film 3 increases due to the contraction of the passivation film 3 during curing, so that the moisture resistance is further improved. it can. Moreover, since the pad 5 does not come into direct contact with the sealing resin 1 which is generally inferior in water resistance to the passivation film 3, the water resistance is further improved.
【００１８】ここで、導電性膜４の形成方法としては、
たとえば周知の厚膜印刷法によって、封止樹脂１の形成
前後を問わず形成する。これにより、容易に厚い導電性
膜４を形成できる。また、封止樹脂１はたとえばポッテ
ング法あるいはトランスモールド法等によって形成す
る。Here, as a method of forming the conductive film 4,
For example, the well-known thick film printing method is used before and after the formation of the sealing resin 1. Thereby, the thick conductive film 4 can be easily formed. The sealing resin 1 is formed by, for example, the potting method or the transmolding method.
【００１９】このように形成した導電性膜４は、上述の
ように周知の厚膜印刷法により形成される導電性膜と同
様の材料からなり、この材料は封止樹脂１と強固な接着
が図れるものとして確認されている。このため、従来見
られたような電極部における水分浸入は、上述した構成
により解消でき、高耐湿性の半導体装置を得ることがで
きる。つまり、従来技術によれば、半田と樹脂との間の
いわゆる濡れ性が悪いために、電極部における水分浸入
があったのである。The conductive film 4 thus formed is made of the same material as the conductive film formed by the well-known thick film printing method as described above, and this material is firmly bonded to the sealing resin 1. It has been confirmed that it can be achieved. Therefore, the infiltration of water into the electrode portion, which has been conventionally seen, can be eliminated by the above-described configuration, and a semiconductor device having high humidity resistance can be obtained. That is, according to the conventional technology, the so-called wettability between the solder and the resin is poor, so that water has entered the electrode portion.
【００２０】なお、上述した実施例では、周知の厚膜印
刷法により形成される導電性膜と同様の材料を用いたも
のであるが、これに封止樹脂１と同様の樹脂を若干混合
させたものを使用することによって、封止樹脂１とのよ
り強固な接着が図れる。In the above-described embodiment, the same material as the conductive film formed by the well-known thick film printing method is used, but a resin similar to the sealing resin 1 is slightly mixed with this. By using such a resin, stronger adhesion with the sealing resin 1 can be achieved.
【００２１】なお、半田バンプ６の替りに、金等の貴金
属性バンプ、他の材料であってもよいことはいうまでも
ない。It goes without saying that the solder bumps 6 may be replaced by noble metal bumps such as gold or other materials.
【００２２】上述した実施例では、いずれも封止樹脂１
との接着性の良好な導電材として、周知の厚膜印刷法に
よる導電材を用いて説明したものであるが、必ずしも、
この材料に限られないことはいうまでもない。In each of the above-mentioned embodiments, the sealing resin 1 is used.
As a conductive material having good adhesiveness with, it is explained using a conductive material by a known thick film printing method, but not necessarily,
It goes without saying that the material is not limited to this.
【００２３】[0023]
【発明の効果】以上説明したことから明らかなように、
本発明による半導体装置によれば、耐湿性を向上させる
ことができる。As is apparent from the above description,
According to the semiconductor device of the present invention, moisture resistance can be improved.
【図１】本発明による樹脂封止型半導体装置の一実施例
を示す断面構成図である。FIG. 1 is a cross-sectional configuration diagram showing an embodiment of a resin-sealed semiconductor device according to the present invention.
【図２】図１実施例の外観を示す斜視図である。FIG. 2 is a perspective view showing the external appearance of the embodiment shown in FIG.
【符号の説明】 １ 封止樹脂 ２ 半導体チップ ３ パッシベーション膜 ４ 導電性部材 ５ パッド ６ 半田バンプ[Explanation of reference numerals] 1 sealing resin 2 semiconductor chip 3 passivation film 4 conductive member 5 pad 6 solder bump
───────────────────────────────────────────────────── フロントページの続き (72)発明者 矢口 昭弘 茨城県土浦市神立町502番地 株式会社日 立製作所機械研究所内 (72)発明者 河合 末男 茨城県土浦市神立町502番地 株式会社日 立製作所機械研究所内 ─────────────────────────────────────────────────── ─── Continued Front Page (72) Inventor Akihiro Yaguchi 502 Jinritsu-cho, Tsuchiura-shi, Ibaraki Hiritsu Seisakusho Co., Ltd.Mechanical Research Institute (72) Sueo Kawai 502 Jinritsu-cho, Tsuchiura-shi, Ibaraki Nitate Seisakusho Co., Ltd. Inside the mechanical laboratory
Claims (3)
面に形成された電極と、この電極の表面の一部を露出し
て前記半導体チップの表面に形成された樹脂膜と、前記
電極と外部との電気的接続をとる導電性部材と、この導
電性部材の一部を露呈させて前記半導体チップを覆って
形成された樹脂封止体とを備えてなり、前記電極と前記
導電性部材との間に半田を介在させてなる樹脂封止型半
導体装置。1. A semiconductor chip, an electrode formed on the surface of the semiconductor chip, a resin film formed on the surface of the semiconductor chip by exposing a part of the surface of the electrode, the electrode and the outside. Of a conductive member for electrical connection, and a resin encapsulant formed by exposing a part of the conductive member to cover the semiconductor chip, the electrode and the conductive member A resin-encapsulated semiconductor device having solder interposed therebetween.
との接触面とを有する請求項１に記載の樹脂封止型半導
体装置。2. The resin-encapsulated semiconductor device according to claim 1, wherein the electrode has a joint surface with solder and a contact surface with a resin film.
も薄くした請求項１又は２に記載の樹脂封止型半導体装
置。3. The resin-encapsulated semiconductor device according to claim 1, wherein the solder has a thickness smaller than that of the conductive member.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7203170A JP2743157B2 (en) | 1995-08-09 | 1995-08-09 | Resin-sealed semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7203170A JP2743157B2 (en) | 1995-08-09 | 1995-08-09 | Resin-sealed semiconductor device |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63200620A Division JP2756791B2 (en) | 1988-08-11 | 1988-08-11 | Resin-sealed semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0846121A true JPH0846121A (en) | 1996-02-16 |
| JP2743157B2 JP2743157B2 (en) | 1998-04-22 |
Family
ID=16469620
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7203170A Expired - Lifetime JP2743157B2 (en) | 1995-08-09 | 1995-08-09 | Resin-sealed semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2743157B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6597070B2 (en) | 2000-02-01 | 2003-07-22 | Nec Electronics Corporation | Semiconductor device and method of manufacturing the same |
| CN107946260A (en) * | 2017-12-28 | 2018-04-20 | 江阴长电先进封装有限公司 | A kind of wafer level cladded type chip-packaging structure and its method for packing |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57152301A (en) * | 1981-03-17 | 1982-09-20 | Nippon Kokan Kk <Nkk> | Production of ribbed irregular shaped steel |
| JPS5892242A (en) * | 1981-11-27 | 1983-06-01 | Mitsubishi Electric Corp | Ceramic multi-layer substrate |
-
1995
- 1995-08-09 JP JP7203170A patent/JP2743157B2/en not_active Expired - Lifetime
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57152301A (en) * | 1981-03-17 | 1982-09-20 | Nippon Kokan Kk <Nkk> | Production of ribbed irregular shaped steel |
| JPS5892242A (en) * | 1981-11-27 | 1983-06-01 | Mitsubishi Electric Corp | Ceramic multi-layer substrate |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6597070B2 (en) | 2000-02-01 | 2003-07-22 | Nec Electronics Corporation | Semiconductor device and method of manufacturing the same |
| CN107946260A (en) * | 2017-12-28 | 2018-04-20 | 江阴长电先进封装有限公司 | A kind of wafer level cladded type chip-packaging structure and its method for packing |
| CN107946260B (en) * | 2017-12-28 | 2023-12-05 | 江阴长电先进封装有限公司 | Wafer-level cladding type chip packaging structure and packaging method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2743157B2 (en) | 1998-04-22 |
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