JP2000164761A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device, which is capable of relaxing the stress that concentrates on a joint between a chip and a wiring layer and on another joint between a package and a mounting board and improving the package in mounting reliability, and a manufacturing method thereof. SOLUTION: A low-elasticity resin layer 3 is provided at a joint between a chip 1 and a wiring layer 4 connected to an outer connection terminal, and the wiring layer 4 formed on the low-elasticity resin layer 3 and an electrode 2 formed on the chip 1 are connected together with a bonding wire 6, so as to relax stresses from concentrating at joints.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device called a chip size package or a chip scale package and a method of manufacturing a semiconductor device, and more particularly, to a connection between a chip and a wiring layer and a connection between a package and a mounting board. The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device, which can reduce stress concentration and improve mounting reliability.

[0002]

2. Description of the Related Art In recent years, in a semiconductor device called a chip size package or a chip scale package (hereinafter, referred to as a CSP), it is one of important factors to relieve stress at a connection portion. For this purpose, usually a CSP
The thickness of the interposer is relatively thick, the external terminals are composed of solder balls, and the stress concentrated on the solder connection due to the difference in thermal expansion between the semiconductor device and the mounting board when mounted and connected to the mounting board is reduced. The occurrence of cracks and the like is suppressed, and connection reliability is improved. Further, the chip and the interposer that constitute the CSP are connected by wire bonding or TAB.
They are connected by a connection means having a spring property like a bonding lead. For this reason, even if the chip and the interposer constituting the CSP are sealed with a resin having a relatively high elastic modulus, stress concentration due to a difference in thermal expansion between the chip and the interposer is alleviated and reliability is maintained.

Further, in order to satisfy market demands for further reduction in size, thickness, and cost of the CSP, the interposer is further reduced in size and thickness, and a manufacturing method called a wafer-level CSP is required along with a reduction in assembly cost. As a result, there has been an increasing demand for a technique for forming a wiring layer without using a conventional interposer.

[0004]

However, the CSP manufactured by such a conventional technique has a reduced effect of the conventional stress relaxation. In the August 1998 issue of Nikkei Electronics, various structures for realizing a semiconductor device closer to the chip size are listed, but all of them relate to the concentration of stress applied to the connection between the chip and the interposer or the wiring layer. There was a problem that it was not enough.

The present invention has been made in view of such a problem, and an object of the present invention is to reduce a stress concentrated on a connection portion between a chip and an interposer or a wiring layer accompanying a reduction in size and thickness of a semiconductor device. An object of the present invention is to provide a semiconductor device having a connection structure that can be relaxed and a method for manufacturing the semiconductor device.

Another object of the present invention is to provide a chip size package (CSP: Chip Scale Pack).
It is an object of the present invention to provide a semiconductor device structure and a manufacturing method which have a connection structure capable of relaxing stress concentrated on a connection portion between the a.

[0007]

The gist of the present invention is to provide a semiconductor device of a chip size package type having a solder ball for obtaining electrical conduction with an external terminal, wherein the semiconductor element is The chip electrode for wire bond connection formed on the formed chip and the concentration of stress applied to the connection portion on the chip at least near the lower portion of the connection portion between the wiring layer and the solder ball are reduced. A low-elastic resin layer formed of a resin having a low elastic modulus as low as possible and having a perforated via hole for obtaining a connection between the semiconductor element and a wiring; Formed on the wiring layer for obtaining electrical conduction with the solder ball, formed on the low elastic resin layer,
There is provided a semiconductor device having a land to which the solder ball is connected, and a bonding wire for wire-bonding the wiring layer and the chip electrode with a spring. The gist of claim 2 of the present invention is characterized in that the solder ball has a thickness enough to fill the vicinity of the bottom of the surface of the solder ball, and has a cover resin layer formed including at least the periphery of the solder ball. The semiconductor device according to claim 1. According to another aspect of the present invention, there is provided a semiconductor device of a chip size package type including a solder ball for connecting to an external terminal, wherein a wire formed on a chip on which a semiconductor element is formed. Use of a chip electrode for bond connection, and a resin having a low elastic modulus on the chip at least near a lower portion of a connection portion between the wiring layer and the solder ball and having an elastic modulus low enough to reduce stress concentration applied to the connection portion. A low-elastic resin layer formed on the low-elastic resin layer to have a predetermined thickness and a via hole for obtaining a connection between the semiconductor element and the wiring; A wiring layer for obtaining, formed on the low elastic resin layer,
In order to obtain a land to which the solder ball is connected, a bonding wire for connecting the wiring layer and the chip electrode with a wire bond having a spring property, and electrical connection between the wiring layer and the solder ball. And a via post formed to include a columnar conductive material that penetrates the lower portion of the solder ball and reaches the wiring layer. The gist of claim 4 of the present invention is that the side surface of the via post has a thickness enough to fill the side surface of the via post, and is at least a bottom portion of the solder ball electrically connected to the via post. 4. The semiconductor device according to claim 3, further comprising a cover resin layer formed including the periphery.
The gist of claim 5 of the present invention is characterized in that the solder ball has a layer thickness such that the vicinity of the bottom surface of the solder ball is buried, and has a cover resin layer formed including at least the periphery of the solder ball. The semiconductor device according to claim 3. The gist of claim 6 of the present invention is that the side surface of the via post has a thickness enough to fill the side surface of the via post, and is at least a bottom portion of the solder ball electrically connected to the via post. A first cover resin layer formed so as to cover the periphery of the solder ball, and having a thickness such that the vicinity of the bottom of the surface of the solder ball is buried, and contacting the first cover resin layer including at least the periphery of the solder ball; The semiconductor device according to claim 3, further comprising a second cover resin layer formed by forming. According to a seventh aspect of the present invention, there is provided a method of manufacturing a chip-size package type semiconductor device including solder balls for obtaining electrical continuity with external terminals, wherein the semiconductor element is formed. Forming a chip electrode for wire bond connection thereon, and at least near a lower portion of a connection portion between the wiring layer and the solder ball, on the chip, so that stress concentration applied to the connection portion can be reduced. Forming a low-elastic resin layer having a predetermined thickness using a resin having a low elastic modulus, and forming a via hole in the low-elastic resin layer to obtain a connection between the semiconductor element and a wiring; Forming a wiring layer for obtaining electrical conduction with the solder balls on the low elastic resin layer, and forming lands to which the solder balls are connected on the low elastic resin layer; A step, and the wiring layer and the tip electrode, consists in a method of manufacturing a semiconductor device characterized by having a step of connecting wire bonding by a bonding wire with a spring property. The gist of claim 8 of the present invention has a step of forming a cover resin layer having a thickness enough to fill the vicinity of the bottom of the surface of the solder ball and including at least the periphery of the solder ball. A method for manufacturing a semiconductor device according to claim 7 is provided. The gist of claim 9 of the present invention is a method of manufacturing a chip-size package type semiconductor device provided with solder balls for connecting to external terminals, wherein a semiconductor element is formed on a chip. Forming a chip electrode for wire bond connection; and an elastic modulus low enough to reduce stress concentration applied to the connection portion on the chip at least near a lower portion of a connection portion between the wiring layer and the solder ball. Forming a low-elastic resin layer having a predetermined thickness using a resin having a low elasticity, and forming a via hole in the low-elasticity resin layer to obtain a connection between the semiconductor element and a wiring; A step of forming a wiring layer for obtaining electrical conduction with the solder balls on the layer, and a step of forming lands to which the solder balls are connected on the low elastic resin layer, A step of wire-bonding the wiring layer and the chip electrode with a bonding wire having a spring property, and penetrating near a lower portion of the solder ball in order to obtain electrical conduction between the wiring layer and the solder ball. Forming a via post including a columnar conductive material reaching the wiring layer. The gist of claim 10 of the present invention is that a cover resin layer having a thickness enough to bury the side surface of the via post is provided at least at the bottom of the solder ball electrically connected to the via post. The method of manufacturing a semiconductor device according to claim 9, further comprising a step of forming the periphery of the via post. The gist of claim 11 of the present invention is characterized by comprising a step of forming a cover resin layer having a thickness such that the vicinity of the bottom surface of the solder ball is buried near at least the periphery of the solder ball. According to a ninth aspect of the present invention, there is provided a method of manufacturing a semiconductor device. The gist of the twelfth aspect of the present invention is that the first cover resin layer having a thickness enough to bury the side surface of the via post is provided at least at the bottom of the solder ball electrically connected to the via post. And forming a second cover resin layer having a thickness such that the vicinity of the bottom of the surface of the solder ball is buried in the first cover including at least the periphery of the solder ball. Forming the semiconductor device in contact with the cover resin layer.

[0008]

Embodiments of the present invention will be described below in detail with reference to the drawings.

(First Embodiment) FIG. 1 is a sectional view of an element for explaining a connection structure of a semiconductor device according to a first embodiment of the present invention. The semiconductor device of the present embodiment includes a chip 1, a chip electrode 2, a low elastic resin layer 3, a wiring layer 4, a cover resin layer 5, a bonding wire 6, a land 7, a solder ball (B
Flip chip BGA (Bal (Bal) with GA ball) 8
l Grid Array (ball grid array) type semiconductor device, in which a low elastic resin layer 3 having a low elastic modulus is used in a connection portion between a chip 1 and a wiring layer 4 for connecting to an external connection terminal, and has a low elasticity. A wiring structure is formed in which the wiring layer 4 formed on the resin layer 3 and the chip electrode 2 on the chip 1 are wire-bonded using a bonding wire 6 having a spring property to reduce the concentration of stress applied to the connection part. It is characterized by points.

In this embodiment, a low elastic resin layer 3 having an elastic modulus of 1 kgf / mm 2 is formed on a semiconductor element, and a wiring layer 4 is provided on the low elastic resin layer 3. In addition, as a connection structure for connecting the chip 1 to the external terminals, a resin having a low elastic modulus is adopted for the low elastic resin layer 3 forming the wiring layer 4, and wire bonding is performed for the connection between the wiring layer 4 and the chip 1. I'm using Specifically, the chip electrode 2 of the semiconductor element (denoted as chip 1 in the figure) and the wiring layer 4 are wire-bonded using the bonding wires 6. Wiring layer 4
Use a Cu wiring, a Cu wiring plated with partial plating of Ag in consideration of bonding properties, or a wiring having a Cu / Ni / Au configuration. In this wiring layer 4, the external terminals B
A land 7 for mounting the GA ball 8 (the mounting land 7 for the BGA ball 8) and a wire bonding portion are formed, and the wire bonding portion is protected by the cover resin layer 5 to form the land 7.

As described above, according to the connection structure of the first embodiment of the semiconductor device of the present invention, the stress is reduced by the combination of the low elastic resin and the wire bonding, or the combination of the low elastic resin hierarchical structure and the wire bonding. A structure that can reduce concentration can be obtained. In addition, the low elastic resin layer 3
By using a semiconductor device, when a semiconductor device is mounted and used, the deterioration caused at the material interface due to expansion and contraction due to the difference in thermal expansion coefficient between the mounting substrate and the chip 1 is flexibly alleviated, and is caused by cracks and cracks. This can prevent breakage and the like. As a result, long-term reliability when using semiconductor devices,
In particular, an effect of improving the temperature cycle reliability is obtained.

FIG. 4 is a sectional view showing a first embodiment of the semiconductor device manufacturing method of the present invention, in which a connection structure of the semiconductor device of FIG. 1 is formed. 4A shows a semiconductor element (chip 1 or wafer) which has not been cut into individual pieces. As shown in FIG. 4B, the low-elastic resin layer 3 and the copper The connection structure is formed by forming the layers in the order of the foil layers. As a method for forming a laminated film of the low elastic resin layer 3 and the copper foil layer, a low elastic resin
Processed into a sheet with a thickness of μm to 80 μm,
A method of bonding with a copper foil of about m by hot pressing, applying a liquid low-elastic resin to a required thickness by a method such as spin coater, curtain coater or printing, curing and then forming a copper wiring layer by a plating method Can be used.

Here, 1 kgf / mm 2 is selected as the elastic modulus E of the low elastic resin layer 3, but 10 kgf / m 2 depending on the material and thickness of the semiconductor element or wiring to be combined.
It can be selected and adjusted up to the order of m2 to 100 kgf / mm2. In the next step shown in FIG. 4C, the wiring layer 4 is processed into a predetermined pattern by using an exposure and development technique. FIG.
In the step (d), in order to establish an electrical connection between the chip electrode 2 of the semiconductor element and the wiring layer 4, a hole is formed in the low-elastic resin layer 3 by a laser to perform a surface treatment.

In the step of FIG. 4E, the electrical connection between the patterned wiring layer 4 and the chip electrode 2 of the semiconductor element is made by wire bonding using bonding wires 6. 4 (f) and 4 (g), a solder resist is formed. In the step of FIG.
After attaching the GA ball 8, the wafer is cut and the process is completed.

As described above, according to the first embodiment of the method of manufacturing a semiconductor device of the present invention, the steps in the state of a wafer are carried out, so that the method of forming the low-elastic resin layer 3 and the wiring layer 4 has The resin layer or the application of the liquid resin and the wiring layer 4 are characterized in that a method such as metal foil sticking or plating can be freely selected, and an effect utilizing the characteristics of the material can be expected. Further, performing wafer batch processing and using wire bonding for interlayer connection between the semiconductor element and the wiring layer 4 lead to cost reduction. Except for the step of performing wire bonding (the step of FIG. 4 (e)), a batch process such as hot pressing, printing, exposure and development is used, so that the interposer is more precise and more precise than the method of attaching the interposer to the wafer. It has the advantage that it can be manufactured at low cost. Further, a structure that can reduce stress concentration can be obtained by a combination of a low elastic resin and wire bonding, or a combination of a low elastic resin hierarchical structure and wire bonding.
Further, the use of the low elastic resin layer 3 flexibly mitigates deterioration occurring at the material interface due to expansion and contraction due to a difference in thermal expansion coefficient between the mounting substrate and the chip 1 when the semiconductor device is mounted and used. (Cracks) and breaks caused by cracks can be prevented. As a result, there is obtained an effect that the long-term reliability when the semiconductor device is used, particularly, the temperature cycle reliability is improved.

(Second Embodiment) FIG. 2 is a sectional view of an element for explaining a connection structure of a semiconductor device according to a second embodiment of the present invention. The semiconductor device of the present embodiment shown in FIG. 2 has a flip chip including a via post 9 in addition to a chip 1, a chip electrode 2, a low elastic resin layer 3, a wiring layer 4, a bonding wire 6, a land 7, and a BGA ball 8. In a BGA (ball grid array) type semiconductor device, as a structure for connecting the chip 1 to an external terminal, a resin having a low elastic modulus is used for a low elastic resin layer 3 forming a wiring layer 4 and a wiring is formed. It is characterized in that wire bonding is used for connection between the layer 4 and the chip 1, and a connection structure is provided in which via posts 9 made of a highly stacked columnar conductive material are provided in order to obtain connection between the wiring layer 4 and external terminals. are doing.

In this embodiment, a low elastic resin layer 3 having an elastic modulus of 1 kgf / mm 2 is formed on a semiconductor element, and a wiring layer 4 is provided on the low elastic resin layer 3 to form a chip electrode 2 of the semiconductor element. And the wiring layer 4 are wire-bonded using the bonding wires 6. The wiring layer 4 is made of Cu partially plated with Ag in consideration of Cu wiring and bonding properties.
Or a wiring having a Cu / Ni / Au configuration. Cu is added on the wiring to further improve the connection reliability.
A via post 9 is provided by plating, and a connection structure is formed on the via post 9 to form a land 7 for mounting a BGA ball 8 as an external terminal and a wire bonding portion.

As described above, the connection structure of the second embodiment of the semiconductor device can be summarized as follows. By using the low-elastic resin layer 3 and the via posts 9 made of a columnar conductive material, the semiconductor device can be mounted and used. It flexibly alleviates the deterioration that occurs at the material interface due to expansion and contraction due to the difference in thermal expansion coefficient between the substrate and the chip 1, and plays a role in preventing cracks and breaks caused by the cracks. Therefore, an effect is obtained that the long-term reliability when using the semiconductor device, particularly the temperature cycle reliability is improved.

FIG. 5 shows a second embodiment of the method of manufacturing a semiconductor device according to the present invention, and is a cross-sectional view showing steps in the case of forming a connection structure of the semiconductor device of FIG. Referring to FIG. 5, there is shown a process sectional view of a semiconductor device and a semiconductor device manufacturing method according to an embodiment of the present invention. The step of FIG. 5A shows a semiconductor element (wafer) that has not been cut into pieces. In the step of FIG. 5B, a copper foil layer is formed after the low elastic resin layer 3 is formed. As a method of forming the low elastic resin layer 3 and the copper foil layer, a low elastic resin
m, and then apply a hot-press method together with a copper foil of about 20 μm or apply a liquid low-elastic resin to the required thickness using a spin coater, curtain coater, printing, etc., and cure. After that, a method of forming a copper wiring layer using a plating method can be used.

In the next step shown in FIG. 5C, the wiring layer 4 is processed into a predetermined pattern by using an exposure and development technique. FIG.
In the step (d), in order to establish an electrical connection between the chip electrode 2 of the semiconductor element and the wiring layer 4, a hole is formed in the low-elasticity resin layer 3 by a laser to perform a surface treatment. FIG. 5 (e)
In the step (3), the electrical connection between the patterned wiring layer 4 and the chip electrode 2 of the semiconductor element is established by bonding wires 6.
This is performed using In the step of FIG. 5F, a liquid low elastic resin is coated to form the low elastic resin layer 3 again. In the step of FIG. 5G, an opening is provided at a predetermined pattern position.

In the step shown in FIG. 5H, a via post 9 is formed by filling the hole with a conductive material. The low elastic resin used here may be the same resin as the previously formed low elastic resin layer 3 or a second low elastic resin whose elastic modulus is particularly adjusted. When a metal material is used as a hole filling material for forming the via post 9, it is preferable to use an electroplating method. When a conductive resin is used, it is desirable to use a printing method.

Next, in the step of FIG. 5 (i), a BG as an external terminal is placed on the top of the filled conductive material (via post 9).
The lands 7 for attaching the A balls 8 are formed by plating, and the solder resist is patterned. FIG.
In the step (j), after attaching the BGA balls 8 as external terminals, the wafer is cut and the process is completed.

As described above, according to the second embodiment of the method of manufacturing a semiconductor device of the present invention, the steps in the state of a wafer are carried out, so that the method of forming the low elastic resin layer 3 and the wiring layer 4 can be formed into a sheet. The resin layer or the application of the liquid resin and the wiring layer 4 are characterized in that a method such as metal foil sticking or plating can be freely selected, and an effect utilizing the characteristics of the material can be expected. Further, performing wafer batch processing and using wire bonding for interlayer connection between the semiconductor element and the wiring layer 4 lead to cost reduction. Except for the step of performing wire bonding (the step of FIG. 5E), a batch process such as hot pressing, printing, exposure and development is used, so that the interposer is more precise and more precise than the method of attaching the interposer to the wafer. It has the advantage that it can be manufactured at low cost. Further, a structure that can reduce stress concentration can be obtained by a combination of a low elastic resin and wire bonding, or a combination of a low elastic resin hierarchical structure and wire bonding.
Further, the use of the low elastic resin layer 3 flexibly mitigates deterioration occurring at the material interface due to expansion and contraction due to a difference in thermal expansion coefficient between the mounting substrate and the chip 1 when the semiconductor device is mounted and used. (Cracks) and breaks caused by cracks can be prevented. As a result, there is obtained an effect that the long-term reliability when the semiconductor device is used, particularly, the temperature cycle reliability is improved.

(Third Embodiment) FIG. 3 is a sectional view of an element for explaining a connection structure of a semiconductor device according to a third embodiment of the present invention. The semiconductor device of the present embodiment shown in FIG. 3 has a chip 1, a chip electrode 2, a low elastic resin layer 3, a wiring layer 4, a bonding wire 6, A flip chip BGA type semiconductor device in which a cover resin layer 5 (hereinafter, referred to as a cover resin layer 5a and a cover resin layer 5b) is added in addition to the lands 7, the BGA balls 8, and the via posts 9, As a structure for connecting to an external terminal, a wiring layer 4
A low-elasticity resin is used for the low-elasticity resin layer 3 forming the wiring layer, and wire bonding is used for connection between the wiring layer 4 and the chip 1. It is characterized in that the connection structure has a via post 9 in which a conductive material is piled high.

In this embodiment, a low elastic resin layer 3 having an elastic modulus of 1 kgf / mm 2 is formed on a semiconductor element, and a wiring layer 4 is provided on the low elastic resin layer 3 to form a chip electrode 2 of the semiconductor element. And the wiring layer 4 are wire-bonded using the bonding wires 6. The wiring layer 4 is made of Cu partially plated with Ag in consideration of Cu wiring and bonding properties.
Or a wiring having a Cu / Ni / Au configuration. Cu is added on the wiring to further improve the connection reliability.
A via post 9 is provided by plating, a land 7 for mounting a BGA ball 8 as an external terminal and a wire bonding portion are formed on the via post 9, and the wire bonding portion is protected by a cover resin layer 5a, and further becomes an external terminal. A cover resin layer 5b is provided for the purpose of reinforcing the land 7 of the BGA ball 8 and improving the connection reliability.

Here, the cover resin layer 5a and the cover resin layer 5b may be made of the same material as the low elastic resin layer 3, and the elastic modulus is selected in consideration of the material and structure used for the semiconductor element and the via post 9. . Further, plated metal is selected for the via post 9 as a conductive material, but a resin paste mixed with conductive particles may be used. In this case, by reducing the elastic modulus of the via post 9 as much as possible and setting the elastic modulus of the cover resin layer 5a high, the concentration of the stress applied to the land 7 during connection can be reduced.

As described above, the connection structure of the third embodiment of the conductor device can be summarized as follows. By using the low elastic resin layer 3 and the via post 9 made of a columnar conductive material, the semiconductor device can be mounted and used. It flexibly alleviates the deterioration that occurs at the material interface due to expansion and contraction due to the difference in thermal expansion coefficient between the substrate and the chip 1, and plays a role in preventing cracks and breaks caused by the cracks. Therefore, an effect is obtained that the long-term reliability when using the semiconductor device, particularly the temperature cycle reliability is improved.

FIG. 5 is a sectional view showing a third embodiment of the method of manufacturing a semiconductor device according to the present invention, in which a connection structure of the semiconductor device of FIG. 3 is formed. A method for manufacturing the connection structure of the third embodiment of the semiconductor device shown in FIG. 3 will be described with reference to FIG. 1 is a cross-sectional view illustrating a process of a semiconductor device and a semiconductor device manufacturing method according to an embodiment of the present invention. FIG.
The step (a) shows a semiconductor element (wafer) that has not been cut into pieces. In the step of FIG. 5B, a copper foil layer is formed after the low elastic resin layer 3 is formed. Low elastic resin layer 3
And a method for forming a copper foil layer, a low-elastic resin
Process into a sheet of μm to 80 μm and apply a method of bonding by hot pressing with a copper foil of about 20 μm or a liquid low elastic resin to a required thickness using a method such as spin coater, curtain coater or printing. After curing, a method of forming a copper wiring layer using a plating method can be used.

In the next step shown in FIG. 5C, the wiring layer 4 is processed into a predetermined pattern by using an exposure and development technique. FIG.
In the step (d), in order to establish an electrical connection between the chip electrode 2 of the semiconductor element and the wiring layer 4, a hole is formed in the low-elasticity resin layer 3 by a laser to perform a surface treatment. FIG. 5 (e)
In the step (3), the electrical connection between the patterned wiring layer 4 and the chip electrode 2 of the semiconductor element is established by bonding wires 6.
This is performed using In the step of FIG. 5F, a liquid low-elastic resin is coated to form the low-elastic resin layer 3 again. In the step of FIG. 5G, an opening is provided at a predetermined pattern position.

In the step of FIG. 5H, a via post 9 is formed by filling the hole with a conductive material. The low elastic resin used here may be the same resin as the previously formed low elastic resin layer 3 or a second low elastic resin whose elastic modulus is particularly adjusted. When a metal material is used as a hole filling material for forming the via post 9, it is preferable to use an electroplating method. When a conductive resin is used, it is desirable to use a printing method.

Next, in the step of FIG. 5 (i), a BG as an external terminal is placed on the top of the filled conductive material (via post 9).
The lands 7 for attaching the A balls 8 are formed by plating, and the solder resist is patterned. FIG.
In the step (j), after attaching the BGA ball 8 as the external terminal, a cover resin layer 5a for protecting the wire bonding portion is formed, and then the land 7 of the BGA ball 8 as the external terminal is reinforced. After forming the cover resin layer 5b for improving the connection reliability, the wafer is cut and the process is completed.

As described above, according to the method of manufacturing the connection structure of the third embodiment of the semiconductor device of the present invention, the steps are performed in a wafer state to form the low-elastic resin layer 3 and the wiring layer 4. The method is characterized in that a method such as affixing a sheet-like resin or applying a liquid resin and applying a metal foil on the wiring layer 4 can be freely selected, and an effect of utilizing the characteristics of the material can be expected. Further, performing wafer batch processing and using wire bonding for interlayer connection between the semiconductor element and the wiring layer 4 lead to cost reduction. Except for the step of performing wire bonding (the step of FIG. 5E), a batch process such as hot pressing, printing, exposure and development is used, so that the interposer is more precise and more precise than the method of attaching the interposer to the wafer. It has the advantage that it can be manufactured at low cost. Further, a structure that can reduce stress concentration can be obtained by a combination of a low elastic resin and wire bonding, or a combination of a low elastic resin hierarchical structure and wire bonding. Further, the use of the low elastic resin layer 3 flexibly mitigates deterioration occurring at the material interface due to expansion and contraction due to a difference in thermal expansion coefficient between the mounting substrate and the chip 1 when the semiconductor device is mounted and used. (Cracks) and breaks caused by cracks can be prevented. As a result, there is obtained an effect that the long-term reliability when the semiconductor device is used, particularly, the temperature cycle reliability is improved.

In the present embodiment, the present invention is not limited to a flip-chip ball grid array type semiconductor device and a manufacturing method, but is a flip-chip / chip size package type suitable for applying the present invention. The present invention can be applied to a semiconductor device and a manufacturing method. Further, the number, position, shape, and the like of the constituent members are not limited to the above-described embodiments,
Position, shape, etc. In each drawing, the same components are denoted by the same reference numerals.

[0034]

Since the present invention is configured as described above, it is possible to realize a connection structure capable of reducing stress concentrated on a connection portion between a chip and an interposer or a wiring layer accompanying a reduction in size and thickness of a semiconductor device. Can be.

Further, it is possible to alleviate the stress concentrated on the connection portion between the package and the mounting board and to improve the mounting reliability.

[Brief description of the drawings]

FIG. 1 is an element cross-sectional view for explaining a connection structure of a first embodiment of a semiconductor device of the present invention.

FIG. 2 is an element cross-sectional view for explaining a connection structure of a semiconductor device according to a second embodiment of the present invention.

FIG. 3 is an element cross-sectional view for explaining a connection structure of a semiconductor device according to a third embodiment of the present invention.

FIG. 4 is a cross-sectional view illustrating a first embodiment of a method of manufacturing a semiconductor device according to the present invention, in which a connection structure of the semiconductor device of FIG. 1 is formed.

FIG. 5 is a sectional view of a process in the second and third embodiments of the method of manufacturing a semiconductor device according to the present invention, in which a connection structure between the semiconductor devices of FIGS. 2 and 3 is formed.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Chip 2 ... Electrode 3 ... Low elastic resin layer 4 ... Wiring layer 5 ... Cover resin layer 6 ... Bonding wire 7 ... Land 8 ... BGA ball 9 ... Via post

Claims (12)

[Claims] 1. A chip size package type semiconductor device provided with solder balls for obtaining electrical conduction with external terminals, wherein a chip for wire bond connection is formed on a chip on which a semiconductor element is formed. An electrode, at least in the vicinity of a lower portion of a connection portion between the wiring layer and the solder ball, and on the chip, using a resin having a low elastic modulus enough to reduce stress concentration applied to the connection portion, and having a predetermined thickness. A low-elastic resin layer formed with a via hole for obtaining a connection between the semiconductor element and the wiring; and a wiring formed on the low-elastic resin layer for obtaining electrical continuity with the solder ball. A land formed on the low-elasticity resin layer, to which the solder ball is connected, and a button for wire-bonding the wiring layer and the chip electrode to each other. Wherein a and a loading wire. 2. The solder ball according to claim 1, wherein the solder ball has a thickness enough to fill the vicinity of the bottom of the surface of the solder ball, and has a cover resin layer formed including at least the periphery of the solder ball. Semiconductor device. 3. A semiconductor device of a chip size package type having a solder ball for connecting to an external terminal, comprising: a chip electrode for wire bond connection formed on a chip on which a semiconductor element is formed; A predetermined thickness is formed on the chip at least near the lower part of the connection part between the wiring layer and the solder ball, using a resin having a low elastic modulus enough to reduce stress concentration applied to the connection part. A low-elastic resin layer in which a via hole for obtaining a connection between the semiconductor element and the wiring is perforated; and a wiring layer formed on the low-elastic resin layer for obtaining electrical continuity with the solder ball; A land formed on the low-elasticity resin layer and connected to the solder ball; and a bond for connecting the wiring layer and the chip electrode with a wire bond having a spring property. A wire and a via post formed to include a columnar conductive material that penetrates near the lower part of the solder ball and reaches the wiring layer in order to obtain electrical conduction between the wiring layer and the solder ball. A semiconductor device comprising: 4. A cover having a thickness enough to fill the side surface of the via post, and including at least a bottom portion of the solder ball electrically connected to the via post and including a periphery of the side surface of the via post. The semiconductor device according to claim 3, further comprising a resin layer. 5. The solder ball according to claim 3, wherein the solder ball has a thickness enough to fill the vicinity of the bottom of the surface of the solder ball, and has a cover resin layer formed including at least the periphery of the solder ball. Semiconductor device. 6. A bottom portion of the solder ball which is electrically connected to the via post and has a thickness enough to fill the side surface of the via post, and is formed including the periphery of the side surface of the via post. And a cover resin layer having a thickness such that the vicinity of the bottom of the surface of the solder ball is buried, and the first resin layer including at least the periphery of the solder ball.
4. The semiconductor device according to claim 3, further comprising a second cover resin layer formed in contact with said cover resin layer. 7. A method of manufacturing a semiconductor device of a chip size package type having a solder ball for obtaining electrical conduction with an external terminal, the method comprising the steps of: A step of forming a chip electrode, and using a resin having a low elastic modulus on the chip at least near a lower portion of a connection portion between the wiring layer and the solder ball and having an elastic modulus low enough to reduce stress concentration applied to the connection portion. To form a low elastic resin layer having a predetermined thickness,
Drilling a via hole in the low-elastic resin layer to obtain a connection between the semiconductor element and a wiring; and forming a wiring layer on the low-elastic resin layer to obtain electrical conduction with the solder ball. Forming a land on the low-elastic resin layer to which the solder ball is connected; and wire-bonding the wiring layer and the chip electrode with a bonding wire having a spring property. A method for manufacturing a semiconductor device, comprising: 8. The method according to claim 7, further comprising a step of forming a cover resin layer having a thickness such that a portion near the bottom of the surface of the solder ball is buried, and including at least the periphery of the solder ball. Of manufacturing a semiconductor device. 9. A method of manufacturing a semiconductor device of a chip size package type having a solder ball for connecting to an external terminal, wherein a chip electrode for wire bond connection is formed on a chip on which a semiconductor element is formed. Forming, using a resin having a modulus of elasticity low enough to reduce stress concentration applied to the connection portion at least near the lower portion of the connection portion between the wiring layer and the solder ball and on the chip. Forming a low-elastic resin layer having a thickness of, and drilling a via hole in the low-elastic resin layer to obtain a connection between the semiconductor element and the wiring; and forming the solder ball on the low-elastic resin layer. A step of forming a wiring layer for obtaining electrical continuity; a step of forming a land on the low elastic resin layer to which the solder ball is connected; and a step of forming the wiring layer and the chip. A step of wire-bonding the electrodes with a bonding wire having a spring property; and, in order to obtain electrical conduction between the wiring layer and the solder ball, the electrode penetrates a lower portion of the solder ball and reaches the wiring layer. Forming a via post including a pillar-shaped conductive material. 10. A cover resin layer having a thickness enough to fill the side surface of the via post is formed including at least a bottom portion of the solder ball electrically connected to the via post and including a periphery of the side surface of the via post. The method of manufacturing a semiconductor device according to claim 9, further comprising: 11. The method according to claim 9, further comprising the step of forming a cover resin layer having a thickness such that the vicinity of the bottom of the surface of the solder ball is buried near at least the periphery of the solder ball. A method for manufacturing a semiconductor device. 12. A first cover resin layer having a thickness such that a side surface of the via post is buried is formed on at least a bottom portion of the solder ball electrically connected to the via post and around a side surface of the via post. And forming a second cover resin layer having a thickness such that a portion near the bottom of the surface of the solder ball is filled in contact with the first cover resin layer including at least the periphery of the solder ball. The method of manufacturing a semiconductor device according to claim 9, further comprising: