JPH1197584A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH1197584A
JPH1197584A JP25083097A JP25083097A JPH1197584A JP H1197584 A JPH1197584 A JP H1197584A JP 25083097 A JP25083097 A JP 25083097A JP 25083097 A JP25083097 A JP 25083097A JP H1197584 A JPH1197584 A JP H1197584A
Authority
JP
Japan
Prior art keywords
semiconductor element
ground electrode
insulating substrate
semiconductor device
solder
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP25083097A
Other languages
Japanese (ja)
Inventor
Toru Hosokawa
徹 細川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera Corp
Original Assignee
Kyocera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyocera Corp filed Critical Kyocera Corp
Priority to JP25083097A priority Critical patent/JPH1197584A/en
Publication of JPH1197584A publication Critical patent/JPH1197584A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16237Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area disposed in a recess of the surface of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/095Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701Low temperature co-fired ceramic [LTCC]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/1515Shape
    • H01L2924/15153Shape the die mounting substrate comprising a recess for hosting the device
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/15165Monolayer substrate

Abstract

PROBLEM TO BE SOLVED: To ensure the excellent state of ground of a semiconductor element in a semiconductor device on which a semiconductor element having a ground electrode on the back is flip-chip-mounted. SOLUTION: In a semiconductor device, a semiconductor element 2 where a ground electrode 3 is formed on the upper surface is mounted on a semiconductor element mounting portion of the upper surface of an insulating substrate 1, and wiring electrode pads 5 formed in the semiconductor element mounting portion and wiring electrodes 4 formed on the lower surface of the semiconductor element are electrically connected by using conductive interconnection members 8. The ground electrode 3 of the semiconductor element 2 and ground electrode pads 6 formed in the vicinity of the semiconductor element mounting portion are connected by using solder or conductive paste 9, and the semiconductor element 2, the ground electrode pads 6 and the solder or the conductive paste 9 are sealed with sealing resin 10. Hence the excellent state of ground of the semiconductor element 2 can be ensured, and miniaturization of the semiconductor device can be realized.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【産業上の利用分野】本発明はマイクロ波帯やミリ波帯
等の高周波用の半導体装置に関し、特に半導体素子がフ
ェースダウンでフリップチップ実装された半導体装置に
関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device for high frequencies such as a microwave band and a millimeter wave band, and more particularly to a semiconductor device in which a semiconductor element is mounted face-down and flip-chip.

【0002】[0002]

【従来の技術】マイクロ波帯やミリ波帯等の高周波用の
半導体装置における半導体素子の実装の形態としては、
大きく分けて(1)キャリア実装:半導体素子をキャリ
ア基板に実装し、複数のキャリア基板をつなぎ合わせて
1つの回路とする方法、(2)パッケージ実装:半導体
素子1つを半導体素子収納用パッケージに実装する方
法、(3)マルチチップモジュール:複数の半導体素子
を1つのキャリア基板または半導体素子収納用パッケー
ジに実装する方法、の3つがある。これら3つの実装方
法においては、半導体素子の配線電極と外部電気回路と
の電気的接続はキャリア基板やパッケージ・マルチチッ
プモジュール内ではワイヤボンディング法を用いるため
に、半導体素子の配線電極が形成された表面を上にして
基板等の上に固着するのが一般的である。
2. Description of the Related Art As a mode of mounting a semiconductor element in a semiconductor device for a high frequency such as a microwave band or a millimeter wave band,
(1) Carrier mounting: A method in which a semiconductor element is mounted on a carrier substrate and a plurality of carrier substrates are connected to form a single circuit. (2) Package mounting: One semiconductor element is mounted in a semiconductor element storage package. (3) Multi-chip module: There are three methods: a method of mounting a plurality of semiconductor elements on one carrier substrate or a package for housing semiconductor elements. In these three mounting methods, the wiring electrodes of the semiconductor element were formed because the wiring electrodes of the semiconductor element and the external electric circuit used the wire bonding method in the carrier substrate or the package / multi-chip module. It is common to fix it on a substrate or the like with its surface facing up.

【0003】すなわち、半導体集積回路素子等の半導体
素子として片面(表面)に配線電極が形成され他面(裏
面)にも接地電極が形成されているような両面電極構造
のものを用いて絶縁基板上に実装して半導体装置を構成
する場合には、接地面が形成された絶縁基板の半導体素
子搭載部に半導体素子を裏面側を下にしていわゆるフェ
ースアップで固定し、半導体素子の上面(表面)側の配
線電極と絶縁基板の半導体素子搭載部の周囲に形成され
た配線電極パッドとをボンディングワイヤによって電気
的に接続して、その後、必要に応じて封止用樹脂を半導
体素子及びボンディングワイヤを覆うようにして塗布
し、あるいは蓋体を用いて封止が行なわれることにより
半導体装置が構成されていた。
That is, a semiconductor element such as a semiconductor integrated circuit element having a double-sided electrode structure in which a wiring electrode is formed on one surface (front surface) and a ground electrode is also formed on the other surface (back surface) is used. When the semiconductor device is mounted on the semiconductor device, the semiconductor device is fixed to the semiconductor device mounting portion of the insulating substrate on which the ground plane is formed with the back surface side down, so-called face-up, and the upper surface (front surface) of the semiconductor device is mounted. ) Side and the wiring electrode pad formed around the semiconductor element mounting portion of the insulating substrate are electrically connected by a bonding wire, and then, if necessary, a sealing resin is applied to the semiconductor element and the bonding wire. Is applied so as to cover the semiconductor device, or the semiconductor device is sealed by using a lid.

【0004】しかし、このような半導体装置では、半導
体素子搭載部の周囲に多数の配線電極パッドを形成する
必要があることから、半導体素子の高密度化に伴って配
線電極パッドの配置やボンディングワイヤとの接続が困
難となり、また半導体装置の小型化の要求に十分に応え
ることが難しいという問題点があった。また、GHz帯
のような高周波用の半導体素子に対しては、配線電極と
配線電極パッドとの電気的接続にボンディングワイヤを
用いることから接続長が長くなるため、その影響で高周
波特性が悪化してしまうという問題点もあった。
However, in such a semiconductor device, it is necessary to form a large number of wiring electrode pads around the semiconductor element mounting portion. Connection with the semiconductor device, and it is difficult to sufficiently meet the demand for miniaturization of the semiconductor device. Further, for semiconductor devices for high frequencies such as the GHz band, since a bonding wire is used for electrical connection between the wiring electrode and the wiring electrode pad, the connection length becomes long, and the high frequency characteristics deteriorate due to the influence. There was also a problem that it would.

【0005】そのため最近は、半導体素子の高密度化や
半導体装置の小型化の要求に応えることができ、しかも
電気的接続の接続長を短くして良好な高周波特性を得る
ことができる実装方法として、半導体素子として片面
(表面)側のみに配線電極を形成した片面電極構造のも
のを用いてその表面を下にして実装する、いわゆるフェ
ースダウン方式のフリップチップ実装が実用化されはじ
めている。
[0005] For this reason, recently, as a mounting method capable of responding to demands for higher density of semiconductor elements and miniaturization of semiconductor devices, it is possible to obtain good high frequency characteristics by shortening the connection length of electrical connection. A so-called face-down type flip chip mounting, in which a semiconductor element having a single-sided electrode structure in which a wiring electrode is formed only on one side (front side) and mounted with the surface down, has begun to be put into practical use.

【0006】このような半導体素子をフリップチップ実
装した半導体装置においては、絶縁基板上面の配線電極
パッドが形成された半導体素子搭載部に半導体素子を表
面側を下にしてベアチップ状態でフェースダウンで搭載
し、絶縁基板の配線電極パッドと半導体素子の配線電極
とをそれらの少なくとも一方に形成した半田や金などの
金属バンプにより電気的に接続して半導体素子を絶縁基
板上に実装する。その後、半導体素子の4辺に封止樹脂
を塗布して封止を行なうか、またはワイヤボンディング
法のときと同様に半導体素子の上面(裏面)を覆うよう
に封止樹脂を塗布して封止が行なわれることにより半導
体装置が構成されている。
In a semiconductor device in which such a semiconductor element is flip-chip mounted, the semiconductor element is mounted face down in a bare chip state with the surface side down on the semiconductor element mounting portion on the upper surface of the insulating substrate where the wiring electrode pads are formed. Then, the semiconductor device is mounted on the insulating substrate by electrically connecting the wiring electrode pad of the insulating substrate and the wiring electrode of the semiconductor device by a metal bump such as solder or gold formed on at least one of them. After that, sealing is performed by applying a sealing resin to four sides of the semiconductor element, or by applying a sealing resin so as to cover the upper surface (back surface) of the semiconductor element as in the case of the wire bonding method. The semiconductor device is configured by performing the above.

【0007】[0007]

【発明が解決しようとする問題点】しかしながら、上記
の従来のフリップチップ実装による半導体装置では、半
導体素子として片面電極構造のものしか用いることがで
きず、裏面に接地電極が形成されたような両面電極構造
の半導体素子を用いようとしても、接地電極が形成され
た裏面すなわち絶縁基板に実装した場合の上面を接地す
ることは困難であった。
However, in the above-mentioned conventional flip-chip-mounted semiconductor device, only a single-sided electrode structure can be used as a semiconductor element, and both sides of the semiconductor device have a ground electrode formed on the back surface. Even when a semiconductor element having an electrode structure is used, it is difficult to ground the back surface on which the ground electrode is formed, that is, the upper surface when mounted on an insulating substrate.

【0008】これに対し、絶縁基板の上面の半導体素子
の近傍に接地電極パッドを形成し、その接地電極パッド
に半導体素子の上面の接地電極をボンディングワイヤに
より電気的に接続して接地をとる方法も考えられる。
On the other hand, a method of forming a ground electrode pad near the semiconductor element on the upper surface of the insulating substrate, and electrically connecting the ground electrode on the upper surface of the semiconductor element to the ground electrode pad with a bonding wire to establish grounding. Is also conceivable.

【0009】しかし、この場合は、接地手段であるボン
ディングワイヤが細いために良好な接地状態を確保する
ことができず、半導体素子の動作が不安定になるという
問題点があった。また,GHz帯のような高周波用の半
導体素子に対しては、接地のための接続長が長くなるた
めに高周波特性を悪化させてしまうという問題点があっ
た。
However, in this case, since the bonding wire as the grounding means is thin, a good grounding state cannot be secured, and there is a problem that the operation of the semiconductor element becomes unstable. In addition, a high-frequency semiconductor element such as a GHz band has a problem in that high-frequency characteristics are deteriorated due to a long connection length for grounding.

【0010】また、封止樹脂を半導体素子およびボンデ
ィングワイヤを覆うように塗布して封止が行なわれるこ
とから、封止樹脂の粘度制御も非常に重要であり、粘度
が高くなりすぎるとボンディングワイヤを倒してしまい
断線させてしまうという問題点があった。また一方、粘
度が低くなりすぎると封止樹脂が広がってしまい、封止
面積が大きくなってワイヤの最も高い部分が封止されず
に露出することがあるという問題点もあった。
In addition, since sealing is performed by applying a sealing resin so as to cover the semiconductor element and the bonding wire, viscosity control of the sealing resin is also very important. There is a problem that it is knocked down and the wire is broken. On the other hand, if the viscosity is too low, the sealing resin spreads, and the sealing area becomes large, so that the highest portion of the wire may be exposed without being sealed.

【0011】その他にも、ボンディングワイヤを覆うよ
うに封止樹脂を塗布することから半導体装置の高さが高
くなってしまい、半導体装置の小型化、特に低背化が困
難であるという問題点もあった。
Another problem is that the height of the semiconductor device is increased because the sealing resin is applied so as to cover the bonding wires, and it is difficult to reduce the size of the semiconductor device, especially to reduce the height. there were.

【0012】本発明は上記事情に鑑みて案出されたもの
であり、その目的は、裏面に接地電極が形成された半導
体装置をフェースダウンでフリップチップ実装し封止材
で封止して成る半導体装置について、半導体素子を封止
しつつ良好な接地状態を確保し、半導体素子の安定した
動作が確保できるとともに所望の高周波特性を発揮させ
ることができ、かつ半導体素子を気密封止することによ
り信頼性が高く、しかも小型化にも対応できる半導体装
置を提供することにある。
SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and has as its object to flip-chip mount a semiconductor device having a ground electrode on the back surface face-down and seal it with a sealing material. For a semiconductor device, by securing a good grounding state while sealing the semiconductor element, it is possible to secure a stable operation of the semiconductor element and exhibit desired high-frequency characteristics, and to hermetically seal the semiconductor element. It is an object of the present invention to provide a semiconductor device which has high reliability and can cope with miniaturization.

【0013】[0013]

【問題点を解決するための手段】本発明の半導体装置
は、絶縁基板の上面に形成された半導体素子搭載部に、
上面に接地電極が形成された半導体素子を搭載させると
ともに、前記半導体素子搭載部内に形成された配線電極
パッドと前記半導体素子の下面に形成された配線電極と
を導電性相互接続部材により電気的に接続させて成り、
かつ、前記半導体素子の接地電極と前記半導体素子搭載
部の近傍に形成された接地電極パッドとが半田もしくは
導電性ペーストで接続され、さらに前記半導体素子と前
記接地電極パッドと前記半田もしくは導電性ペーストと
が封止樹脂で封止されていることを特徴とするものであ
る。
A semiconductor device according to the present invention comprises a semiconductor element mounting portion formed on an upper surface of an insulating substrate.
A semiconductor element having a ground electrode formed on the upper surface is mounted, and a wiring electrode pad formed in the semiconductor element mounting portion and a wiring electrode formed on the lower surface of the semiconductor element are electrically connected by a conductive interconnect member. Made by connecting
A ground electrode of the semiconductor element and a ground electrode pad formed near the semiconductor element mounting portion are connected by solder or conductive paste; and the semiconductor element, the ground electrode pad, and the solder or conductive paste are connected to each other. Are sealed with a sealing resin.

【0014】本発明の半導体装置によれば、表面側に配
線電極が形成され裏面側に接地電極が形成された半導体
素子が絶縁基板上の半導体素子搭載部に表面側を下面と
してフェースダウンでフリップチップ実装され、その半
導体素子の裏面すなわち実装後の上面の接地電極と絶縁
基板上の半導体素子搭載部の近傍に形成された接地電極
パッドとがこれらを共に覆うように付与される半田もし
くは導電性ペーストによって電気的に接続され、さらに
前記半導体素子と前記半導体素子搭載部の近傍に形成さ
れた接地電極パッドと前記半田もしくは導電性ペースト
とが封止樹脂によりそれら全面を覆って封止されている
ことから、導電性部材である半田もしくは導電性ペース
トによって半導体素子の接地電極と絶縁基板の接地電極
パッドとの導通を広い面積でとって良好な接地状態を確
保することができるとともに、封止樹脂による高信頼性
の気密封止が可能となる。その結果、裏面に接地電極が
形成された両面電極構造の半導体素子を用いて良好な接
地をとりつつフェースダウンでフリップチップ実装する
ことができ、半導体素子の安定した動作を確保しつつ良
好な高周波特性を発揮させることができ、しかも小型
化、特に低背化にも対応できる半導体装置となる。
According to the semiconductor device of the present invention, the semiconductor element having the wiring electrode formed on the front side and the ground electrode formed on the back side is flipped face-down on the semiconductor element mounting portion on the insulating substrate with the front side as the lower side. Solder or conductive material that is mounted on a chip, and the ground electrode on the back surface of the semiconductor element, that is, the mounted upper surface, and the ground electrode pad formed near the semiconductor element mounting portion on the insulating substrate are provided so as to cover them together. The semiconductor element, the ground electrode pad formed near the semiconductor element mounting portion, and the solder or conductive paste are electrically connected by a paste, and the entire surface thereof is sealed with a sealing resin to be sealed. Therefore, the conduction between the ground electrode of the semiconductor element and the ground electrode pad of the insulating substrate is achieved by the conductive member solder or conductive paste. It is possible to take in the stomach area to ensure good grounding condition, it is possible to hermetically seal the high reliability by the sealing resin. As a result, the semiconductor device having a double-sided electrode structure with a ground electrode formed on the back surface can be flip-chip mounted face down while maintaining good grounding, and a good high frequency while ensuring stable operation of the semiconductor device. A semiconductor device that can exhibit characteristics and that can be reduced in size, particularly, can be reduced in height.

【0015】また、本発明の半導体装置によれば、半導
体素子の上面の接地電極と絶縁基板上の接地電極パッド
との電気的接続のための導電性部材として半田もしくは
導電性ペーストを用いることにより、半導体素子の接地
電極に対して広い接地面積でかつ低い電気抵抗でもって
良好な接地状態を確保することができ、ボンディングワ
イヤによる接続のように細い導電体によって接地のため
の接続長が長くなることもないため、GHz帯のような
高周波用の半導体素子に対しても高周波特性を悪化させ
ることがなく、所望の高周波特性を発揮させることがで
きる。しかも、その上から封止樹脂を用いて半導体素子
・接地電極パッド・半田もしくは導電性ペーストの全体
を封止樹脂で封止することにより、良好に気密封止され
た信頼性の高い半導体装置となる。
Further, according to the semiconductor device of the present invention, by using a solder or a conductive paste as a conductive member for electrically connecting the ground electrode on the upper surface of the semiconductor element to the ground electrode pad on the insulating substrate. A good grounding state can be ensured with a wide grounding area and a low electric resistance with respect to the grounding electrode of the semiconductor element, and the connection length for grounding is lengthened by a thin conductor like a connection by a bonding wire. Therefore, desired high-frequency characteristics can be exhibited without deteriorating high-frequency characteristics even for a high-frequency semiconductor element such as a GHz band. Moreover, by sealing the entire semiconductor element, ground electrode pad, solder or conductive paste with the sealing resin from above using the sealing resin, a highly reliable and highly airtight semiconductor device can be obtained. Become.

【0016】[0016]

【発明の実施の形態】以下、本発明の半導体装置を添付
の図面に基づき詳細に説明する。図1は本発明の半導体
装置の実施の形態の一例を示す断面図であり、実装方法
としてキャリア実装またはマルチチップモジュールとし
たものについての一例である。図1において、1は絶縁
基板であり、例えばセラミック基板や多層セラミック基
板・ガラス基板・樹脂基板等の絶縁性材料から成る。ま
た、2は絶縁基板1の半導体素子搭載部に搭載された両
面電極構造の半導体集積回路素子等の半導体素子であ
る。なお、絶縁基板1の半導体素子搭載部は、この例の
ように絶縁基板1上の一部に平坦面として設定される場
合の他に、絶縁基板1上に形成された凹部内に設定され
る場合もある。
DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings. FIG. 1 is a cross-sectional view illustrating an example of an embodiment of a semiconductor device of the present invention, which is an example of a carrier mounting method or a multi-chip module as a mounting method. In FIG. 1, reference numeral 1 denotes an insulating substrate, which is made of an insulating material such as a ceramic substrate, a multilayer ceramic substrate, a glass substrate, and a resin substrate. Reference numeral 2 denotes a semiconductor element such as a semiconductor integrated circuit element having a double-sided electrode structure mounted on the semiconductor element mounting portion of the insulating substrate 1. The semiconductor element mounting portion of the insulating substrate 1 is set in a recess formed on the insulating substrate 1 in addition to the case where the semiconductor element mounting portion is set as a flat surface on a part of the insulating substrate 1 as in this example. In some cases.

【0017】3は半導体素子2の上面(裏面)のほぼ全
面に形成された接地電極、4は半導体素子の下面(表
面)に形成された配線電極である。このうち接地電極3
は、半導体素子2の上面の一部に1個あるいは複数個形
成されたものであってもよい。
Reference numeral 3 denotes a ground electrode formed on almost the entire upper surface (back surface) of the semiconductor element 2, and reference numeral 4 denotes a wiring electrode formed on the lower surface (front surface) of the semiconductor element. Of these, ground electrode 3
May be formed on a part of the upper surface of the semiconductor element 2 by one or more.

【0018】一方、5は絶縁基板1の上面の半導体素子
搭載部内に半導体素子2の配線電極4に対応して形成さ
れた配線電極パッド、6は絶縁基板1の上面の半導体素
子搭載部の近傍に形成された接地電極パッドである。
On the other hand, 5 is a wiring electrode pad formed in the semiconductor element mounting portion on the upper surface of the insulating substrate 1 so as to correspond to the wiring electrode 4 of the semiconductor element 2, and 6 is near the semiconductor element mounting portion on the upper surface of the insulating substrate 1. Is a ground electrode pad formed on the substrate.

【0019】なお、この例においては、絶縁基板1上に
形成された配線導体(図示せず)を覆って絶縁層7を形
成し、その絶縁層7に窓を開けて配線導体の一部を露出
させることにより配線電極パッド5および接地電極パッ
ド6を形成しているが、各パッド間の絶縁が確保できれ
ば、この絶縁層7は必ずしも設けなくともよい。
In this example, an insulating layer 7 is formed so as to cover a wiring conductor (not shown) formed on the insulating substrate 1, and a window is opened in the insulating layer 7 so that a part of the wiring conductor is formed. Although the wiring electrode pad 5 and the ground electrode pad 6 are formed by exposing the insulating layer, if the insulation between the pads can be ensured, the insulating layer 7 is not necessarily provided.

【0020】8は導電性相互接続部材であり、半田や金
・銅等の金属バンプ、もしくは銀ペーストや半田ペース
ト・異方性導電ペーストなどの導電性ペースト、または
異方性導電シート等により、絶縁基板1の配線電極パッ
ド5と半導体素子2の配線電極4とを電気的に接続する
ものである。また、このようなフリップチップ実装にお
いては、半導体素子2を絶縁基板1の半導体素子搭載部
に搭載するための機械的接続手段としても利用すること
ができる。
Reference numeral 8 denotes a conductive interconnection member, which is formed by a metal bump such as solder, gold, or copper, a conductive paste such as a silver paste, a solder paste, or an anisotropic conductive paste, or an anisotropic conductive sheet. The wiring electrode pad 5 of the insulating substrate 1 is electrically connected to the wiring electrode 4 of the semiconductor element 2. In addition, in such flip chip mounting, it can be used as a mechanical connection means for mounting the semiconductor element 2 on the semiconductor element mounting portion of the insulating substrate 1.

【0021】そして、9は半田もしくは導電性ペースト
であり、絶縁基板1上に搭載された半導体素子2の上面
(裏面)の接地電極3と絶縁基板1上の接地電極パッド
6とを共に覆うように塗布等されて付与された導電性部
材として、半導体素子2の上面の接地電極3と絶縁基板
1の上面の接地電極パッド6とを電気的に接続して半導
体素子2の接地を良好に確保するためのものである。こ
のような半田もしくは導電性ペースト9としては、半導
体素子2の接地電極3と絶縁基板1の接地電極パッド6
の良好な接地導通を確保するための導電性材料として低
抵抗であるもので、かつ半導体装置の動作環境で耐えう
る耐熱温度を有する材料が用いられる。
Reference numeral 9 denotes a solder or a conductive paste which covers both the ground electrode 3 on the upper surface (back surface) of the semiconductor element 2 mounted on the insulating substrate 1 and the ground electrode pad 6 on the insulating substrate 1. The grounding electrode 3 on the upper surface of the semiconductor element 2 and the grounding electrode pad 6 on the upper surface of the insulating substrate 1 are electrically connected as a conductive member applied to the semiconductor element 2 so that the semiconductor element 2 is properly grounded. It is for doing. Such a solder or conductive paste 9 includes a ground electrode 3 of the semiconductor element 2 and a ground electrode pad 6 of the insulating substrate 1.
As a conductive material for ensuring good ground conduction, a material having a low resistance and a heat resistant temperature that can withstand the operating environment of the semiconductor device is used.

【0022】例えば、半田すなわち低融点のろう付け用
合金としてはスズ/鉛・スズ/鉛/銀・スズ/ビスマス
・スズ/鉛/ビスマス・スズ/インジウム・インジウム
/鉛・スズ/鉛/インジウム・鉛/インジウム/銀・鉛
/銀などが、また導電性ペーストとしては銀ペースト等
の一般的な導電性のペースト、あるいはエポキシ樹脂や
ポリイミド樹脂等に銀等の金属粉末を混入した導電性樹
脂等が用いられる。
For example, as a solder, ie, a low melting point brazing alloy, tin / lead / tin / lead / silver / tin / bismuth / tin / lead / bismuth / tin / indium / indium / lead / tin / lead / indium. Lead / Indium / Silver / Lead / Silver, etc. The conductive paste is a general conductive paste such as silver paste, or a conductive resin such as epoxy resin or polyimide resin mixed with metal powder such as silver. Is used.

【0023】このように半田もしくは導電性ペースト9
により接地電極3と接地電極パッド6とを電気的に接続
する場合、例えば半田であれば、半田ボールや半田ペー
ストを半導体素子2の接地電極3上から絶縁基板1の接
地電極パッド6上にわたるように設置し、基板全体を加
熱する工程を通すことにより、電気的に良好に接続して
良好な接地導通を確保することができる。また、導電性
ペーストであれば、銀ペースト等を半導体素子2の接地
電極3の上面と絶縁基板1の接地電極パッド6の上面と
をともに覆うように塗布し、熱処理してペーストを硬化
させることにより、同様に電気的に良好に接続して良好
な接地導通を確保することができる。
As described above, the solder or conductive paste 9
When the ground electrode 3 and the ground electrode pad 6 are electrically connected by soldering, for example, in the case of solder, a solder ball or a solder paste is applied from the ground electrode 3 of the semiconductor element 2 to the ground electrode pad 6 of the insulating substrate 1. And through the step of heating the entire substrate, it is possible to establish a good electrical connection and secure a good ground conduction. In the case of a conductive paste, silver paste or the like is applied so as to cover both the upper surface of the ground electrode 3 of the semiconductor element 2 and the upper surface of the ground electrode pad 6 of the insulating substrate 1, and the paste is cured by heat treatment. Accordingly, it is also possible to electrically connect well and secure good ground conduction.

【0024】本発明の半導体装置によれば、このように
半田もしくは導電性ペースト9を用い、半導体素子2上
面の接地電極3と絶縁基板1上の接地電極パッド6との
電気的接続を、それら半導体素子2・接地電極3と接地
電極パッド6とを覆うように付与した導電性部材により
行なったことから、接地電極3に対して広い接地面積で
かつ低い電気抵抗でもって良好な接地状態を確保するこ
とができ、接地のための接続長が長くなることもないた
め、GHz帯のような高周波用の半導体素子に対しても
高周波特性を悪化させることがなく、所望の高周波特性
を発揮させることができるものとなる。
According to the semiconductor device of the present invention, the electrical connection between the ground electrode 3 on the upper surface of the semiconductor element 2 and the ground electrode pad 6 on the insulating substrate 1 is established by using the solder or the conductive paste 9 as described above. Since a conductive member provided so as to cover the semiconductor element 2 / the ground electrode 3 and the ground electrode pad 6 is used, a good ground state is secured with a wide ground area and a low electric resistance with respect to the ground electrode 3. The connection length for grounding does not become long, so that high-frequency characteristics can be exhibited without deteriorating high-frequency characteristics even for a high-frequency semiconductor element such as a GHz band. Can be done.

【0025】10は半導体素子2と絶縁基板1上面の半導
体素子搭載部の近傍に形成された接地電極パッド6とそ
れらを接続する半田もしくは導電性ペースト9との全面
を覆って気密封止するための封止樹脂である。このよう
な封止樹脂10としては半導体素子2の封止材として耐湿
度性にすぐれ気密封止可能であるとともに、半導体装置
の動作環境で耐えうる耐熱温度を有する材料が用いられ
る。この封止樹脂10には従来周知の封止用樹脂材料を用
いることができ、例えばエポキシ系樹脂やポリイミド系
樹脂等が用いられ、いわゆるポッティング等の塗布方法
により付与され所定の熱処理等を行なうことにより半導
体素子2等を気密封止する。
Numeral 10 is for air-tightly sealing the whole surface of the semiconductor element 2 and the ground electrode pad 6 formed near the semiconductor element mounting portion on the upper surface of the insulating substrate 1 and the solder or conductive paste 9 connecting them. Sealing resin. As such a sealing resin 10, a material that has excellent heat resistance, can be hermetically sealed, and has a heat resistant temperature that can withstand the operating environment of the semiconductor device is used as a sealing material for the semiconductor element 2. A conventionally well-known sealing resin material can be used for the sealing resin 10. For example, an epoxy-based resin or a polyimide-based resin is used. To hermetically seal the semiconductor element 2 and the like.

【0026】11は半導体素子2の周囲の絶縁基板1の上
面との隙間を充填するように塗布された絶縁性樹脂であ
る。この絶縁性樹脂11は、半田もしくは導電性ペースト
9と導電性相互接続部材8あるいは配線電極4・配線電
極パッド5とのショートを防止するため、半導体素子2
の下面への半田もしくは導電性ペースト9の浸入を防止
するために付与されるものであるが、半田もしくは導電
性ペースト9が適度な粘性や凝固性を有しているためこ
れを接地電極3と接地電極パッド6とを接続するように
塗布し固化させた場合にも半導体素子2の下面に浸入せ
ずショートを発生させない時などには、特に必要とはさ
れない。
Reference numeral 11 denotes an insulating resin applied so as to fill a gap between the semiconductor element 2 and the upper surface of the insulating substrate 1. The insulating resin 11 is used to prevent a short circuit between the solder or the conductive paste 9 and the conductive interconnecting member 8 or the wiring electrode 4 and the wiring electrode pad 5.
Is applied in order to prevent the solder or conductive paste 9 from entering the lower surface of the solder. However, since the solder or conductive paste 9 has an appropriate viscosity or solidification property, the solder or conductive paste 9 is formed with the ground electrode 3. This is not particularly necessary even when the coating is applied and solidified so as to connect to the ground electrode pad 6 and does not penetrate into the lower surface of the semiconductor element 2 and does not cause a short circuit.

【0027】なお、半田もしくは導電性ペースト9とし
て、例えば半田のように、付与後に一旦流動性をもたせ
て良好な導通を持たせるために比較的高温での処理を必
要とするものを用いる場合には、半田9として半導体素
子2の特性に悪影響を与えない程度の温度で処理できる
ものを選定するとともに、絶縁層7や封止樹脂10・絶縁
性樹脂11にはその温度に耐え得るものを選定する。
When the solder or the conductive paste 9 is used, such as solder, which needs to be treated at a relatively high temperature in order to give fluidity once and give good conduction after application. Is selected as a solder 9 that can be processed at a temperature that does not adversely affect the characteristics of the semiconductor element 2, and a material that can withstand the temperature is selected as the insulating layer 7, the sealing resin 10, and the insulating resin 11. I do.

【0028】また、半導体素子2の下面と絶縁基板1の
上面との隙間には、半導体素子2を半導体素子搭載部へ
強固に固着し、あるいは熱応力等に対する導電性相互接
続部材8の破壊等を防止し、あるいは半導体素子2の発
熱を絶縁基板1に良好に伝導するなどのために、いわゆ
るアンダーフィル樹脂を付与してもよい。
Further, in the gap between the lower surface of the semiconductor element 2 and the upper surface of the insulating substrate 1, the semiconductor element 2 is firmly fixed to the semiconductor element mounting portion, or the conductive interconnect member 8 is destroyed by thermal stress or the like. A so-called underfill resin may be provided to prevent the occurrence of heat, or to conduct heat generated by the semiconductor element 2 to the insulating substrate 1 satisfactorily.

【0029】このような本発明の半導体装置によれば、
半田もしくは導電性ペースト9によって半導体素子2の
接地電極3と絶縁基板1の接地電極パッド6とを電気的
に接続し、十分な接地導通をとって良好な接地状態を確
保することができるとともに、さらに半導体素子2と絶
縁基板1上面の半導体素子搭載部の近傍に形成された接
地電極パッド6との全面に封止樹脂10を塗布することに
よって気密封止したことから、裏面に接地電極3が形成
された両面電極構造の半導体素子2を用いて良好な接地
をとりつつフェースダウンでフリップチップ実装するこ
とができ、半導体素子2の安定した動作を確保しつつ小
型化にも対応できる高信頼性の半導体装置となる。
According to such a semiconductor device of the present invention,
The ground electrode 3 of the semiconductor element 2 and the ground electrode pad 6 of the insulating substrate 1 are electrically connected by solder or conductive paste 9 and sufficient ground conduction can be ensured to secure a good ground state. Furthermore, since the sealing resin 10 is applied to the entire surface of the semiconductor element 2 and the ground electrode pad 6 formed near the semiconductor element mounting portion on the upper surface of the insulating substrate 1, the sealing electrode 10 is hermetically sealed. The semiconductor element 2 having the double-sided electrode structure formed can be flip-chip mounted face down while maintaining good grounding, and the semiconductor element 2 can operate stably and can be miniaturized. Semiconductor device.

【0030】また、半田もしくは導電性ペースト9によ
り半導体素子2の接地電極3に対して良好な接地状態を
確保することができ、GHz帯のような高周波用の半導
体素子2に対しても高周波特性を悪化させることがな
く、所望の高周波特性を発揮させることができる。
Further, a good grounding state can be ensured with respect to the ground electrode 3 of the semiconductor element 2 by the solder or the conductive paste 9, and the high-frequency characteristic can be applied to the high-frequency semiconductor element 2 such as a GHz band. , And desired high-frequency characteristics can be exhibited.

【0031】次に、本発明の半導体装置の実施の形態の
他の例を図2に図1と同様の断面図で示す。図2におい
て、21は絶縁基板、22は絶縁基板21の半導体素子搭載部
に搭載された両面電極構造の半導体素子であり、23は半
導体素子の上面(表面)に形成された接地電極、24は半
導体素子の下面(表面)に形成された配線電極である。
また、25は絶縁基板21の上面の半導体素子搭載部内に半
導体素子22の配線電極24に対応して形成された配線電極
パッド、26は絶縁基板21の上面の半導体素子搭載部の近
傍に形成された接地電極パッド、27は絶縁基板21上に形
成された配線導体(図示せず)を覆い、その一部に窓を
開けて配線導体の一部を露出させることにより配線電極
パッド25および接地電極パッド26を形成している絶縁
層、28は導電性接続部材である。
Next, another example of the embodiment of the semiconductor device of the present invention is shown in FIG. 2 in a sectional view similar to FIG. 2, reference numeral 21 denotes an insulating substrate, 22 denotes a semiconductor element having a double-sided electrode structure mounted on a semiconductor element mounting portion of the insulating substrate 21, 23 denotes a ground electrode formed on the upper surface (front surface) of the semiconductor element, and 24 denotes a ground electrode. This is a wiring electrode formed on the lower surface (front surface) of the semiconductor element.
Reference numeral 25 denotes a wiring electrode pad formed in the semiconductor element mounting portion on the upper surface of the insulating substrate 21 so as to correspond to the wiring electrode 24 of the semiconductor element 22, and 26 is formed near the semiconductor element mounting portion on the upper surface of the insulating substrate 21. The ground electrode pad 27 covers the wiring conductor (not shown) formed on the insulating substrate 21, and a window is opened in a part thereof to expose a part of the wiring conductor, thereby forming the wiring electrode pad 25 and the ground electrode. An insulating layer forming the pad 26 and a conductive connecting member 28 are provided.

【0032】また、29は絶縁基板21の上面の半導体素子
搭載部近傍の接地電極パッド26の外側にこれらの領域を
囲うように形成されたダム部材であり、30は搭載された
半導体素子22の上面(裏面)の接地電極23を絶縁基板21
上の接地電極パッド26とを共に覆うように付与され、両
者を電気的に接続して半導体素子2の接地を良好に確保
するための半田もしくは導電性ペースト、31は半導体素
子22と絶縁基板21上面の半導体素子搭載部の近傍に形成
された接地電極パッド26との全面を覆って気密封止する
ための封止樹脂である。また、32は半導体素子22の周囲
の絶縁基板21の上面との隙間を充填するように塗布され
た絶縁性樹脂である。
Numeral 29 denotes a dam member formed outside the ground electrode pad 26 near the semiconductor element mounting portion on the upper surface of the insulating substrate 21 so as to surround these areas. Numeral 30 denotes a dam member of the mounted semiconductor element 22. The ground electrode 23 on the upper surface (back surface) is
Solder or conductive paste 31 is provided so as to cover both the upper ground electrode pads 26 and electrically connects the two to ensure good grounding of the semiconductor element 2. This is a sealing resin for covering the entire surface of the ground electrode pad 26 formed in the vicinity of the semiconductor element mounting portion on the upper surface and hermetically sealing the resin. Reference numeral 32 denotes an insulating resin applied so as to fill a gap between the semiconductor element 22 and the upper surface of the insulating substrate 21.

【0033】この例においては、絶縁基板21上面の接地
電極パッド26の外側領域を囲うようにダム部材29を設け
たことから、このダム部材29により半田もしくは導電性
ペースト30および封止樹脂31の絶縁基板21の上面の他の
領域への流れ出しを防止することができ、例えば半田も
しくは導電性ペースト30が絶縁基板21上面の他の領域に
形成された配線導体上に拡がってショートを発生させる
こと等を防止することができる。
In this example, since the dam member 29 is provided so as to surround the area outside the ground electrode pad 26 on the upper surface of the insulating substrate 21, the dam member 29 allows the solder or the conductive paste 30 and the sealing resin 31 to be formed. It is possible to prevent the outflow to the other area of the upper surface of the insulating substrate 21, and for example, the solder or the conductive paste 30 spreads on the wiring conductor formed in the other area of the upper surface of the insulating substrate 21 to cause a short circuit. Etc. can be prevented.

【0034】このようなダム部材29は、例えば熱硬化性
のやや粘度の高い樹脂を用いて半導体素子22を適当なス
ペースをあけて取り囲むように塗布し、その囲まれたス
ペースに半導体素子22に覆いかぶせるように半田もしく
は導電性ペースト30を付与し、その後さらにそれらに覆
いかぶせるように封止樹脂31を塗布し、熱を加えて硬化
させることにより構成すればよい。このとき、硬化のた
めの熱が半導体素子22等の部材に悪影響を及ぼすような
場合には、光硬化性の樹脂を用いて光を当てることによ
り構成してもよい。
The dam member 29 is formed by coating the semiconductor element 22 so as to surround the semiconductor element 22 with a suitable space, for example, using a thermosetting resin having a relatively high viscosity. It may be configured by applying a solder or a conductive paste 30 so as to cover, and then applying a sealing resin 31 so as to cover them, and then curing by applying heat. At this time, if heat for curing adversely affects members such as the semiconductor element 22, the light may be irradiated by using a photocurable resin.

【0035】なお、この例においても、半導体素子搭載
部は絶縁基板21の上面に形成した凹部内に形成してもよ
く、絶縁性樹脂32は必ずしも必要とされるものではな
く、半導体素子22の下面と絶縁基板21の上面との隙間に
アンダーフィル樹脂を付与してもよい。
Also in this example, the semiconductor element mounting portion may be formed in a recess formed on the upper surface of the insulating substrate 21, and the insulating resin 32 is not always required. An underfill resin may be provided in a gap between the lower surface and the upper surface of the insulating substrate 21.

【0036】次に本発明の半導体装置の実施の形態のさ
らに他の例を図3に図1・図2と同様の断面図で示す。
図3において、41は絶縁基板としての半導体素子収納用
パッケージである。42は両面電極構造の半導体素子であ
り、半導体素子収納用パッケージ41の上面に形成され
た、半導体素子42を収容するための空間を形成するため
の凹部41a内に形成された半導体素子搭載部に搭載され
ている。なお、このような半導体素子搭載部は、凹部41
a内にさらに階段状に形成された凹部の内部に形成され
たものであってもよい。
Next, still another embodiment of the semiconductor device according to the present invention is shown in FIG. 3 in a sectional view similar to FIGS.
In FIG. 3, reference numeral 41 denotes a semiconductor element housing package as an insulating substrate. Reference numeral 42 denotes a semiconductor element having a double-sided electrode structure, which is provided on a semiconductor element mounting portion formed in a concave portion 41a for forming a space for accommodating the semiconductor element 42 formed on the upper surface of the semiconductor element housing package 41. It is installed. Incidentally, such a semiconductor element mounting portion is provided in the concave portion 41.
a may be formed inside a concave portion formed in a step-like shape in a.

【0037】43は半導体素子42の上面(裏面)に形成さ
れた接地電極、44は半導体素子の下面(表面)に形成さ
れた配線電極である。また、45は半導体素子収納用パッ
ケージ41の上面の半導体素子搭載部内に半導体素子42の
配線電極44に対応して形成された配線電極パッド、46は
半導体素子収納用パッケージ41の上面の半導体素子搭載
部の近傍に形成された接地電極パッド、47は半導体素子
収納用パッケージ41の上面に形成された配線導体(図示
せず)を覆い、その一部に窓を開けて配線導体の一部を
露出させることにより配線電極パッド45および接地電極
パッド46を形成している絶縁層、48は導電性相互接続部
材である。
Reference numeral 43 denotes a ground electrode formed on the upper surface (back surface) of the semiconductor element 42, and reference numeral 44 denotes a wiring electrode formed on the lower surface (front surface) of the semiconductor element. Reference numeral 45 denotes a wiring electrode pad formed in the semiconductor element mounting portion on the upper surface of the semiconductor element housing package 41 so as to correspond to the wiring electrode 44 of the semiconductor element 42. Reference numeral 46 denotes a semiconductor element mounting on the upper surface of the semiconductor element housing package 41. A ground electrode pad 47 formed in the vicinity of the portion covers a wiring conductor (not shown) formed on the upper surface of the semiconductor element housing package 41, and a window is opened in a part thereof to expose a part of the wiring conductor. By doing so, the insulating layer 48 forming the wiring electrode pad 45 and the ground electrode pad 46 is a conductive interconnection member.

【0038】49は搭載された半導体素子42の接地電極43
を半導体素子収納用パッケージ41の上面の接地電極パッ
ド46とを共に覆うように付与され、両者を電気的に接続
して半導体素子42の接地を良好に確保するための半田も
しくは導電性ペースト、50は半導体素子42と半導体素子
収納用パッケージ41上面の半導体素子搭載部の近傍に形
成された接地電極パッド46との全面を覆って気密封止す
るための封止樹脂である。また、51は半導体素子42の周
囲の半導体素子収納用パッケージ41の上面との隙間を充
填するように塗布された絶縁性樹脂である。
Reference numeral 49 denotes a ground electrode 43 of the mounted semiconductor element 42.
Is applied so as to cover both the ground electrode pad 46 on the upper surface of the semiconductor element housing package 41 and solder or conductive paste 50 for electrically connecting the both to ensure good grounding of the semiconductor element 42. Is a sealing resin for hermetically sealing the whole surface of the semiconductor element 42 and the ground electrode pad 46 formed near the semiconductor element mounting portion on the upper surface of the semiconductor element housing package 41. Reference numeral 51 denotes an insulating resin applied so as to fill a gap between the semiconductor element 42 and the upper surface of the semiconductor element housing package 41.

【0039】この例においては、絶縁基板として半導体
素子収納用パッケージ41を用いて、その上面の凹部41a
内の半導体素子搭載部近傍に形成された接地電極パッド
46の外側領域を囲うように凹部41aの側壁が形成されて
おり、この凹部41aからはみ出さないように半田もしく
は導電性ペースト49と封止樹脂50を塗布・付与し、半導
体素子42の上面の接地電極43と接地電極パッド46とを接
続するとともに半導体素子42と接地電極パッド46全体を
封止する。そして必要に応じて蓋体(図示せず)により
凹部41aを封止することにより半導体装置となる。
In this example, a package 41 for accommodating a semiconductor element is used as an insulating substrate, and a concave portion 41a on the upper surface thereof is used.
Electrode pad formed near the semiconductor element mounting part in the
The side wall of the concave portion 41a is formed so as to surround the outer region of 46, and solder or conductive paste 49 and a sealing resin 50 are applied and applied so as not to protrude from the concave portion 41a, and the upper surface of the semiconductor element 42 is formed. The ground electrode 43 and the ground electrode pad 46 are connected, and the semiconductor element 42 and the entire ground electrode pad 46 are sealed. The semiconductor device is obtained by sealing the recess 41a with a lid (not shown) as necessary.

【0040】なお、この例のように蓋体によっても半導
体素子42を封止する場合は、封止樹脂50は封止の信頼性
が高くなくてもよいものとできる。逆に、封止樹脂50の
封止の信頼性が高ければ、蓋体による封止は封止の信頼
性が低くても特に問題ないものとなる。
When the semiconductor element 42 is sealed with a lid as in this example, the sealing resin 50 does not need to have high sealing reliability. Conversely, if the sealing resin 50 has high sealing reliability, the sealing with the lid does not cause any problem even if the sealing reliability is low.

【0041】このような半導体素子収納用パッケージ41
としては、例えば絶縁基板としてセラミック材料を用い
たものやガラスセラミックスを用いたもの、有機絶縁性
樹脂を用いたものや無機絶縁物粉末と有機絶縁性樹脂を
用いたもの等、種々のパッケージを用いることができ
る。
Such a semiconductor device storage package 41
As, for example, various packages such as those using a ceramic material or glass ceramic as an insulating substrate, those using an organic insulating resin, those using an inorganic insulating powder and an organic insulating resin are used. be able to.

【0042】なお、この例においても、絶縁性樹脂51は
必ずしも必要とされるものではなく、半導体素子42の下
面と半導体素子収納用パッケージ41の上面との隙間にア
ンダーフィル樹脂を付与してもよい。
Also in this example, the insulating resin 51 is not always required, and the underfill resin may be applied to the gap between the lower surface of the semiconductor element 42 and the upper surface of the semiconductor element housing package 41. Good.

【0043】なお、本発明は以上の例に限定されるもの
ではなく、本発明の要旨を逸脱しない範囲で種々の変更
・改良を施すことは何ら差し支えない。
It should be noted that the present invention is not limited to the above examples, and various changes and improvements can be made without departing from the scope of the present invention.

【0044】[0044]

【発明の効果】以上のように、本発明の半導体装置によ
れば、表面側に配線電極が形成され裏面側に接地電極が
形成された半導体素子が絶縁基板上の半導体素子搭載部
に表面側を下面としてフェースダウンでフリップチップ
実装され、その半導体素子の実装後の上面の接地電極と
絶縁基板上の半導体素子搭載部の近傍に形成された接地
電極パッドとが半田もしくは導電性ペーストによって接
続されていることから、この半田もしくは導電性ペース
トによって広い接地面積での半導体素子の良好な接地状
態を確保することができる。
As described above, according to the semiconductor device of the present invention, the semiconductor element having the wiring electrode formed on the front side and the ground electrode formed on the rear side is provided on the front side of the semiconductor element mounting portion on the insulating substrate. And the ground electrode on the upper surface after mounting the semiconductor element and the ground electrode pad formed near the semiconductor element mounting portion on the insulating substrate are connected by solder or conductive paste. Therefore, a good grounding state of the semiconductor element in a wide grounding area can be ensured by the solder or the conductive paste.

【0045】また、その上から半導体素子と絶縁基板上
面の半導体素子搭載部の近傍に形成された接地電極パッ
ドとの全面を覆うように封止樹脂を塗布することによ
り、半導体素子の高信頼性の気密封止を行なうことがで
きる。
Further, by applying a sealing resin so as to cover the entire surface of the semiconductor element and the ground electrode pad formed near the semiconductor element mounting portion on the upper surface of the insulating substrate from above, the high reliability of the semiconductor element is achieved. Can be hermetically sealed.

【0046】また、本発明の半導体装置によれば、半田
もしくは導電性ペーストにより半導体素子の接地電極に
対して良好な接地状態を確保することができ、ボンディ
ングワイヤによる接続のように細い導体によって接地の
ための接続長が長くなることもないため、GHz帯のよ
うな高周波用の半導体素子に対しても高周波特性を悪化
させることなく、所望の周波数特性を発揮させることが
できる。
Further, according to the semiconductor device of the present invention, a good grounding state can be ensured with respect to the ground electrode of the semiconductor element by the solder or the conductive paste, and the ground is formed by a thin conductor like a connection by a bonding wire. Therefore, a desired frequency characteristic can be exhibited without deteriorating the high-frequency characteristics even for a high-frequency semiconductor element such as a GHz band.

【0047】以上により、本発明によれば、裏面に接地
電極が形成された両面電極構造の半導体素子をフェース
ダウンでフリップチップ実装し封止材で封止してなる半
導体装置について、半導体素子を封止しつつ良好な接地
状態を確保し、半導体素子の安定した動作が確保できる
とともに所望の高周波特性を発揮させることができ、か
つ半導体素子を気密封止することにより信頼性が高く、
しかも小型化にも対応できる半導体装置を提供すること
ができた。
As described above, according to the present invention, a semiconductor device having a double-sided electrode structure in which a ground electrode is formed on the back surface is flip-chip mounted face down and sealed with a sealing material. A good grounding state is ensured while sealing, stable operation of the semiconductor element can be ensured and desired high-frequency characteristics can be exhibited, and high reliability is obtained by hermetically sealing the semiconductor element.
In addition, a semiconductor device which can be reduced in size can be provided.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の半導体装置の実施の形態の一例を示す
断面図である。
FIG. 1 is a cross-sectional view illustrating an example of an embodiment of a semiconductor device of the present invention.

【図2】本発明の半導体装置の実施の形態の他の例を示
す断面図である。
FIG. 2 is a sectional view showing another example of the embodiment of the semiconductor device of the present invention.

【図3】本発明の半導体装置の実施の形態のさらに他の
例を示す断面図である。
FIG. 3 is a sectional view showing still another example of the embodiment of the semiconductor device of the present invention.

【符号の説明】[Explanation of symbols]

1、21・・・・・絶縁基板 41・・・・・・・半導体素子収納用パッケージ(絶縁基
板) 2、22、42・・・半導体素子 3、23、43・・・接地電極 4、24、44・・・配線電極 5、25、45・・・配線電極パッド 6、26、46・・・接地電極パッド 8、28、48・・・導電性相互接続部材 9、30、49・・・半田もしくは導電性ペースト 10、31、50・・・封止樹脂
1, 21,... Insulating substrate 41, package for semiconductor element storage (insulating substrate) 2, 22, 42, semiconductor element 3, 23, 43, ground electrode 4, 24 , 44 ... wiring electrode 5, 25, 45 ... wiring electrode pad 6, 26, 46 ... ground electrode pad 8, 28, 48 ... conductive interconnection member 9, 30, 49 ... Solder or conductive paste 10, 31, 50 ... sealing resin

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 絶縁基板の上面に形成された半導体素子
搭載部に、上面に接地電極が形成された半導体素子を搭
載させるとともに、前記半導体素子搭載部内に形成され
た配線電極パッドと前記半導体素子の下面に形成された
配線電極とを導電性相互接続部材により電気的に接続さ
せて成り、かつ、前記半導体素子の接地電極と前記半導
体素子搭載部の近傍に形成された接地電極パッドとが半
田もしくは導電性ペーストで接続され、さらに前記半導
体素子と前記接地電極パッドと前記半田もしくは導電性
ペーストとが封止樹脂で封止されていることを特徴とす
る半導体装置。
A semiconductor element having a ground electrode formed on an upper surface thereof mounted on a semiconductor element mounting portion formed on an upper surface of an insulating substrate; and a wiring electrode pad formed in the semiconductor element mounting portion and the semiconductor element. And a wiring electrode formed on the lower surface of the semiconductor element is electrically connected by a conductive interconnection member, and a ground electrode of the semiconductor element and a ground electrode pad formed near the semiconductor element mounting portion are soldered. Alternatively, the semiconductor device is connected with a conductive paste, and the semiconductor element, the ground electrode pad, and the solder or the conductive paste are sealed with a sealing resin.
JP25083097A 1997-09-16 1997-09-16 Semiconductor device Pending JPH1197584A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP25083097A JPH1197584A (en) 1997-09-16 1997-09-16 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP25083097A JPH1197584A (en) 1997-09-16 1997-09-16 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH1197584A true JPH1197584A (en) 1999-04-09

Family

ID=17213666

Family Applications (1)

Application Number Title Priority Date Filing Date
JP25083097A Pending JPH1197584A (en) 1997-09-16 1997-09-16 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH1197584A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7348263B2 (en) 2005-03-01 2008-03-25 Seiko Epson Corporation Manufacturing method for electronic component, electronic component, and electronic equipment
US7863529B2 (en) 2007-11-05 2011-01-04 Seiko Epson Corporation Electronic component
WO2011043281A1 (en) * 2009-10-09 2011-04-14 シャープ株式会社 Wiring sheet, solar battery cell with wiring sheet, solar battery module, and wiring sheet roll

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7348263B2 (en) 2005-03-01 2008-03-25 Seiko Epson Corporation Manufacturing method for electronic component, electronic component, and electronic equipment
US7867830B2 (en) 2005-03-01 2011-01-11 Seiko Epson Corporation Manufacturing method for electronic component with sealing film
US8664730B2 (en) 2005-03-01 2014-03-04 Seiko Epson Corporation Manufacturing method for electronic component, electronic component, and electronic equipment
US7863529B2 (en) 2007-11-05 2011-01-04 Seiko Epson Corporation Electronic component
US8097817B2 (en) 2007-11-05 2012-01-17 Seiko Epson Corporation Electronic component
US8342859B2 (en) 2007-11-05 2013-01-01 Seiko Epson Corporation Electronic component
WO2011043281A1 (en) * 2009-10-09 2011-04-14 シャープ株式会社 Wiring sheet, solar battery cell with wiring sheet, solar battery module, and wiring sheet roll
JP2011082431A (en) * 2009-10-09 2011-04-21 Sharp Corp Wiring sheet, solar battery cell with the same, solar battery module, and wiring sheet roll
CN102687281A (en) * 2009-10-09 2012-09-19 夏普株式会社 Wiring sheet, solar battery cell with wiring sheet, solar battery module, and wiring sheet roll

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