CN108461405B - Circuit carrier plate and manufacturing method thereof - Google Patents

Circuit carrier plate and manufacturing method thereof Download PDF

Info

Publication number
CN108461405B
CN108461405B CN201710093630.1A CN201710093630A CN108461405B CN 108461405 B CN108461405 B CN 108461405B CN 201710093630 A CN201710093630 A CN 201710093630A CN 108461405 B CN108461405 B CN 108461405B
Authority
CN
China
Prior art keywords
layer
circuit
circuit layer
solder mask
insulating layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201710093630.1A
Other languages
Chinese (zh)
Other versions
CN108461405A (en
Inventor
黄昱程
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Liding Semiconductor Technology Qinhuangdao Co ltd
Liding Semiconductor Technology Shenzhen Co ltd
Original Assignee
Qi Ding Technology Qinhuangdao Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qi Ding Technology Qinhuangdao Co Ltd filed Critical Qi Ding Technology Qinhuangdao Co Ltd
Priority to CN201710093630.1A priority Critical patent/CN108461405B/en
Priority to TW106114228A priority patent/TWI658557B/en
Publication of CN108461405A publication Critical patent/CN108461405A/en
Application granted granted Critical
Publication of CN108461405B publication Critical patent/CN108461405B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4857—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4867—Applying pastes or inks, e.g. screen printing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/4985—Flexible insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
    • H01L23/49894—Materials of the insulating layers or coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Wire Bonding (AREA)
  • Structure Of Printed Boards (AREA)
  • Non-Metallic Protective Coatings For Printed Circuits (AREA)

Abstract

The utility model provides a circuit support plate, includes an insulating layer, is located respectively first circuit layer, the second circuit layer on insulating layer both sides surface and be located first circuit layer side surface cladding first circuit layer prevent the solder layer, be located second circuit layer side surface cladding the solder layer is prevented to the second on second circuit layer, the insulating layer middle part is interrupted and is formed a first interval portion, the second prevents that the solder layer corresponds first interval portion forms a second interval portion, first interval portion and second interval portion link up each other and form a holding district jointly, a chip set up in the holding district with first circuit layer electricity is connected.

Description

Circuit carrier plate and manufacturing method thereof
Technical Field
The present invention relates to a circuit carrier, and more particularly, to a thin bendable circuit carrier and a method for manufacturing the same.
Background
Nowadays, in order to meet the diversified development of various electronic devices, the circuit carrier is widely applied due to its advantages of thinness, high circuit density, etc.
Generally, the thin circuit carrier is easy to bend or warp during the manufacturing process due to its thin thickness, and this problem is also easy to occur in the subsequent packaging process. Therefore, it is important to avoid the bending or warping of the thin circuit carrier during the manufacturing process.
Disclosure of Invention
Accordingly, the present invention provides a circuit carrier with a thin thickness and a high yield and a method for manufacturing the same.
The utility model provides a circuit support plate, includes an insulating layer, is located respectively first circuit layer, the second circuit layer on insulating layer both sides surface and be located first circuit layer side surface cladding first circuit layer prevent the solder layer, be located second circuit layer side surface cladding the solder layer is prevented to the second on second circuit layer, the insulating layer middle part is interrupted and is formed a first interval portion, the second prevents that the solder layer corresponds first interval portion forms a second interval portion, first interval portion and second interval portion link up each other and form a holding district jointly, a chip set up in the holding district with first circuit layer electricity is connected.
Drawings
Fig. 1 is a schematic diagram of a circuit carrier according to an embodiment of the invention.
Fig. 2 to 19 are schematic diagrams illustrating a method for manufacturing a circuit carrier according to the present invention.
Description of the main elements
Figure BDA0001229695110000011
Figure BDA0001229695110000021
The following detailed description further illustrates the invention with reference to the above figures.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is apparent that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be obtained by a person skilled in the art without any inventive step based on the embodiments of the present invention, are within the scope of the present invention.
The terms "first" and "second" as used herein are defined with respect to the position of the first substrate when in use, and are not limiting.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention.
As shown in fig. 1, the circuit carrier 100 of the present invention includes an insulating layer 10, a first circuit layer 20, a second circuit layer 30 respectively disposed on two side surfaces of the insulating layer 10, a first solder mask layer 40 disposed on one side surface of the first circuit layer 20 and covering the first circuit layer 20, and a second solder mask layer 50 disposed on one side surface of the second circuit layer 30 and covering the second circuit layer 30.
The insulating layer 10 is made of bendable thermosetting solder resist ink, and has a small thickness and good flexibility. In the embodiment of the present invention, the thickness of the insulating layer 10 is between 15 and 50 micrometers. The insulating layer 10 has a first surface 101 and a second surface 102 opposite to the first surface 101. The insulating layer 10 is provided with a plurality of conductive holes 103 penetrating through the first surface 101 and the second surface 102. In the embodiment of the present invention, the cross section of the conductive hole 103 is trapezoidal, and the aperture of the conductive hole gradually increases from the first surface 101 to the second surface 102. The insulating layer 10 is interrupted at the middle to form a first spacer 104.
The first circuit layer 20 is disposed on the first surface 101 of the insulating layer 10. The first circuit layer 20 has a plurality of pads 21. The solder pads 21 are correspondingly located at the first spacer 104 and not within the first spacer 104.
The second circuit layer 30 is disposed on the second surface 102 of the insulating layer 10. The second circuit layer 30 is electrically connected to the first circuit layer 20 through the conductive via 103.
The first solder mask layer 40 is made of an insulating material, and covers the first circuit layer 20.
The second solder mask layer 50 is also an insulating material, which can be the same as the first solder mask layer 40. The second solder mask layer 50 is filled in the second circuit layer 30, and a plurality of solder holes 501 are formed in the second solder mask layer 50 for filling solder to form solder balls 80.
The second solder mask layer 50 is broken corresponding to the first spacing portions 104 of the insulating layer 10 to form a second spacing portion 501, and the first spacing portion 104 and the second spacing portion 501 together form a receiving area 150.
Further, a chip 60 disposed in the receiving area is also included. The electrodes of the chip 60 are electrically connected to the pads 21 of the first circuit layer 20.
Further, the accommodating area 150 is further filled with an encapsulant 70. The encapsulant 70 encapsulates the chip 60.
In the circuit carrier 100 of the present invention, the insulating layer 10 is made of bendable thermosetting solder mask ink, and has a relatively thin thickness and relatively good flexibility, so that the thickness of the insulating layer 10 itself can be reduced, the flexibility of the circuit carrier 100 is increased, and the first circuit layer 20 and the second circuit layer 30 are prevented from being warped or bent. Further, the circuit carrier 100 of the present invention is formed with a receiving area, so that the chip 60 is disposed in the receiving area and electrically connected to the first circuit layer 20, thereby further reducing the thickness of the circuit carrier 100.
As shown in fig. 2 to 19, the method for manufacturing a circuit carrier 100 according to the present invention includes the following steps:
the method comprises the following steps: as shown in fig. 2, a first carrier 200 is provided.
The first carrier plate 200 includes a first substrate 210 and a first copper-clad layer 220 disposed on a surface of one side of the first substrate 210. The thickness of the first carrier plate 200 is between 150-300 μm. The thickness of the first copper-clad layer 220 is smaller than that of the first substrate 210.
Step two: as shown in fig. 3, a first photosensitive layer 300 is formed on the first copper-clad layer 220 of the first carrier board 200, and a plurality of first gaps 310 are formed on the first photosensitive layer 300 by an exposure and development technique.
Step three: as shown in fig. 4, a first metal layer 20a with a uniform thickness is plated in the first notch 310.
Step four: as shown in fig. 5, the first photosensitive layer 300 is removed, so that the first metal layer 20a is completely exposed to form a first wiring layer 20.
The first circuit layer 20 has a plurality of pads 21.
Step five: as shown in fig. 6, a first solder mask layer 40 is formed on the first circuit layer 20.
The first solder mask layer 40 is an insulating material, and covers the first circuit layer 20.
Step six: as shown in fig. 7, a thermal isolation film 400 and a second carrier plate 500 are sequentially laminated outside the first solder mask layer 40.
The thermal isolation film 400 is located between the first solder mask layer 40 and the second carrier plate 500. The second carrier board 500 includes a second substrate 510 and second copper-clad layers 520 formed on two side surfaces of the second substrate 510. The material of the second carrier plate 500 is the same as that of the first carrier plate 200. The thickness of the second copper-clad layer 520 is smaller than that of the second substrate 510.
Step seven: as shown in fig. 8, the first carrier plate 200 is separated from the first circuit layer 20 and the first solder mask layer 40.
Step eight: as shown in fig. 9, the first circuit layer 20 is further etched so that the outer surface of the first circuit layer 20 is lower than the outer surface of the first solder mask layer 40.
Step nine: as shown in fig. 10, an insulating layer 10 is formed outside the first wiring layer 20.
The insulating layer 10 is made of bendable thermosetting solder resist ink, and has a small thickness and good flexibility. In the embodiment of the present invention, the thickness of the insulating layer 10 is between 15 and 50 micrometers. The insulating layer 10 has a first surface 101 and a second surface 102 opposite to the first surface 101. The insulating layer 10 is interrupted at the middle to form a first spacing portion 104.
Step ten: as shown in fig. 11, a plurality of conductive holes 103 are formed in the insulating layer 10 by laser drilling.
The cross section of the conductive hole 103 is trapezoidal, and the aperture of the conductive hole gradually increases from the first surface 101 to the second surface 102.
In this step, before forming the conductive via 103, a conductive bonding layer may be further formed on the second surface 102 of the insulating layer 10 according to the process requirement.
Step eleven: as shown in fig. 12, a second photosensitive layer 600 is formed on the second surface of the insulating layer 10.
The second photosensitive layer 600 covers the second surface 102 of the insulating layer 10 and the spacer 104.
Step twelve: as shown in fig. 13, a plurality of second gaps 601 are formed on the second photosensitive layer 600 by exposure and development.
Step thirteen: as shown in fig. 14, a second metal layer 30a is formed in the second notch 601 by plating.
Fourteen steps: as shown in fig. 15, the second photosensitive layer 600 is removed to completely expose the second metal layer 30a to form a second wiring layer 30.
Step fifteen: as shown in fig. 16, a second solder mask layer 50 is formed on the outside of the second circuit layer 30, and a second spacer 501 is formed at a position of the second solder mask layer 50 corresponding to the first spacer 104.
The second solder mask layer 50 is filled on the second circuit layer 30, and the second solder mask layer 50 includes a plurality of solder holes 501. The second spacer 501 and the first spacer 104 are mutually connected to form a receiving area 150.
Sixthly, the steps are as follows: as shown in fig. 17, a chip 60 is disposed in the receiving area 150, and the chip 60 is electrically connected to the pad 21 of the first circuit layer 20.
Seventeen steps: as shown in fig. 18, the accommodating area is filled with a molding compound 70 to encapsulate the chip 60, and the solder balls 80 are formed in the solder holes 501 of the second solder mask layer 50 by plating.
Eighteen steps: as shown in fig. 19, the second carrier board 500 is separated from the first solder mask layer 40, so as to obtain the circuit carrier board 100 of the invention.
In the method for manufacturing the circuit carrier 100 according to the present invention, the first circuit layer 20 and the second circuit layer 30 are formed by plating on the first carrier 200 and the second carrier 500, so that the first circuit layer 20 and the second circuit layer 30 can be made more detailed. In addition, the insulating layer 10 is made of bendable thermosetting solder mask ink, and has a small thickness and good flexibility, so that the thickness of the insulating layer 10 itself can be reduced, and the phenomena of warping, bending and the like of the first circuit layer 20 and the second circuit layer 30 caused by stress concentration when the first carrier board 200 and the second carrier board 500 are removed or separated are avoided.
Further, the circuit carrier 100 of the present invention is formed with a receiving area, so that the chip 60 is disposed in the receiving area and electrically connected to the first circuit layer 20, thereby further reducing the thickness of the circuit carrier 100.
It is understood that various other changes and modifications may be made by those skilled in the art based on the technical idea of the present invention, and all such changes and modifications should fall within the protective scope of the claims of the present invention.

Claims (10)

1. The utility model provides a circuit support plate, includes an insulating layer, is located respectively the first circuit layer, the second circuit layer on insulating layer both sides surface and being located first circuit layer side surface cladding the first weld layer of preventing on first circuit layer, being located second circuit layer side surface cladding the second on second circuit layer prevents the weld layer, its characterized in that: the middle of the insulating layer is interrupted to form a first spacing part, the second solder mask layer corresponds to the first spacing part to form a second spacing part, the first spacing part and the second spacing part are mutually communicated and jointly form an accommodating area, a chip is arranged in the accommodating area and electrically connected with the first circuit layer, the surface of the first circuit layer faces the second circuit layer is lower than the surface of the first solder mask layer faces the second circuit layer, so that the first circuit layer is completely embedded into the first solder mask layer, and the insulating layer corresponds to the area of the first circuit layer and faces away from the direction of the second circuit layer, so that the insulating layer is convex.
2. The circuit carrier of claim 1, wherein: the first circuit layer is provided with a plurality of welding pads, and the chip is electrically connected with the first circuit layer through the welding pads.
3. The circuit carrier of claim 1, wherein: the insulating layer is composed of bendable thermosetting anti-welding ink, and the thickness of the insulating layer is 15-50 mu m.
4. The circuit carrier of claim 1, wherein: the insulating layer is provided with a first surface and a second surface opposite to the first surface, the first circuit layer is arranged on the first surface of the insulating layer, the second circuit layer is arranged on the second surface of the insulating layer, and the insulating layer is provided with a plurality of conductive holes penetrating through the first surface and the second surface.
5. The circuit carrier of claim 4, wherein: the second circuit layer is electrically connected with the first circuit layer through the conductive hole.
6. The circuit carrier of claim 1, wherein: the second solder mask is filled in the second circuit layer, and a plurality of welding holes are formed in the second solder mask and used for filling welding flux to form welding balls.
7. The circuit carrier of claim 1, wherein: and the accommodating area is further filled with a packaging colloid, and the packaging colloid wraps the chip.
8. A method for manufacturing a circuit carrier comprises the following steps:
providing a first bearing plate, wherein the first bearing plate comprises a first substrate and a first copper-clad layer arranged on one side surface of the first substrate;
forming a first photosensitive layer on the first copper-clad layer of the first bearing plate, and forming a plurality of first gaps on the first photosensitive layer by using an exposure and development technology;
plating a first metal layer with uniform thickness in the first notch;
removing the first photosensitive layer, thereby completely exposing the first metal layer to form a first circuit layer;
forming a first solder mask layer on the first circuit layer;
sequentially pressing and forming a layer of thermal isolation film and a second bearing plate outside the first welding-proof layer, wherein the second bearing plate comprises a second substrate and second copper-clad layers formed on the surfaces of two sides of the second substrate;
separating the first bearing plate from the first circuit layer and the first solder mask layer;
further etching the first circuit layer so that the outer surface of the first circuit layer is lower than the outer surface of the first solder mask layer;
forming an insulating layer outside the first circuit layer, wherein the middle part of the insulating layer is partitioned to form a first partition part;
forming a plurality of conductive holes on the insulating layer by laser;
pressing the second surface of the insulating layer to form a second photosensitive layer;
forming a plurality of second gaps on the second photosensitive layer by using an exposure and development technology;
plating a second metal layer in the second notch;
removing the second photosensitive layer to completely expose the second metal layer to form a second circuit layer;
forming a second solder mask layer outside the second circuit layer, so that a second spacing part is formed on the second solder mask layer corresponding to the first spacing part, the second spacing part and the first spacing part are mutually communicated and form an accommodating area together, and the second solder mask layer comprises a plurality of welding holes;
arranging a chip in the accommodating area, so that the chip is electrically connected with the first circuit layer;
filling a packaging colloid in the accommodating area to coat the chip, and plating a welding hole of the second solder mask layer to form a welding ball;
and separating the second bearing plate from the first solder mask layer.
9. The method of claim 8, wherein: the thickness of the first carrier plate is between 150 and 300 μm, and the thickness of the first copper-clad layer is smaller than that of the first substrate.
10. The method of claim 8, wherein: the insulating layer is composed of bendable thermosetting anti-welding ink, and the thickness of the insulating layer is 15-50 mu m.
CN201710093630.1A 2017-02-21 2017-02-21 Circuit carrier plate and manufacturing method thereof Active CN108461405B (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CN201710093630.1A CN108461405B (en) 2017-02-21 2017-02-21 Circuit carrier plate and manufacturing method thereof
TW106114228A TWI658557B (en) 2017-02-21 2017-04-28 Load circuit board and methord for manufacturing the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201710093630.1A CN108461405B (en) 2017-02-21 2017-02-21 Circuit carrier plate and manufacturing method thereof

Publications (2)

Publication Number Publication Date
CN108461405A CN108461405A (en) 2018-08-28
CN108461405B true CN108461405B (en) 2020-04-10

Family

ID=63228847

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201710093630.1A Active CN108461405B (en) 2017-02-21 2017-02-21 Circuit carrier plate and manufacturing method thereof

Country Status (2)

Country Link
CN (1) CN108461405B (en)
TW (1) TWI658557B (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110265365A (en) * 2019-06-12 2019-09-20 江门建滔电子发展有限公司 A kind of high heat resistance encapsulating carrier plate

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101789383A (en) * 2009-01-23 2010-07-28 欣兴电子股份有限公司 Method for making packaging substrate with recess structure
TW201113312A (en) * 2009-07-06 2011-04-16 Showa Denko Kk Thermosetting composition for protective film for wiring board
CN103687344A (en) * 2012-09-26 2014-03-26 宏启胜精密电子(秦皇岛)有限公司 Circuit board manufacturing method
CN104241219A (en) * 2014-08-26 2014-12-24 日月光半导体制造股份有限公司 Embedded component packaging structure and manufacturing method thereof
CN104244582A (en) * 2013-06-13 2014-12-24 宏启胜精密电子(秦皇岛)有限公司 Embedded type high-density interconnection printed circuit board and manufacturing method of embedded type high-density interconnection printed circuit board
CN104332412A (en) * 2013-07-22 2015-02-04 宏启胜精密电子(秦皇岛)有限公司 Package substrate, package structure, and manufacturing method for the package substrate
CN106298692A (en) * 2015-04-24 2017-01-04 碁鼎科技秦皇岛有限公司 Chip package base plate, chip-packaging structure and preparation method thereof

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100557540B1 (en) * 2004-07-26 2006-03-03 삼성전기주식회사 BGA package board and method for manufacturing the same

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101789383A (en) * 2009-01-23 2010-07-28 欣兴电子股份有限公司 Method for making packaging substrate with recess structure
TW201113312A (en) * 2009-07-06 2011-04-16 Showa Denko Kk Thermosetting composition for protective film for wiring board
CN103687344A (en) * 2012-09-26 2014-03-26 宏启胜精密电子(秦皇岛)有限公司 Circuit board manufacturing method
CN104244582A (en) * 2013-06-13 2014-12-24 宏启胜精密电子(秦皇岛)有限公司 Embedded type high-density interconnection printed circuit board and manufacturing method of embedded type high-density interconnection printed circuit board
CN104332412A (en) * 2013-07-22 2015-02-04 宏启胜精密电子(秦皇岛)有限公司 Package substrate, package structure, and manufacturing method for the package substrate
CN104241219A (en) * 2014-08-26 2014-12-24 日月光半导体制造股份有限公司 Embedded component packaging structure and manufacturing method thereof
CN106298692A (en) * 2015-04-24 2017-01-04 碁鼎科技秦皇岛有限公司 Chip package base plate, chip-packaging structure and preparation method thereof

Also Published As

Publication number Publication date
TW201832337A (en) 2018-09-01
CN108461405A (en) 2018-08-28
TWI658557B (en) 2019-05-01

Similar Documents

Publication Publication Date Title
US8823187B2 (en) Semiconductor package, semiconductor package manufacturing method and semiconductor device
US7719104B2 (en) Circuit board structure with embedded semiconductor chip and method for fabricating the same
US9258899B2 (en) Method of fabricating a wiring board
KR101168263B1 (en) Semiconductor package and fabrication method thereof
KR20070078711A (en) Wiring board and semiconductor apparatus
KR101070098B1 (en) Printed circuit board and fabricating method of the same
JP2008085089A (en) Resin wiring board and semiconductor device
KR20140021910A (en) Core substrate and printed circuit board using the same
US20130170148A1 (en) Package carrier and manufacturing method thereof
JP2005150718A (en) Superthin semiconductor package and manufacturing method of the same
JPWO2010052942A1 (en) Electronic component built-in wiring board and manufacturing method thereof
JP5117270B2 (en) WIRING BOARD, SEMICONDUCTOR DEVICE, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
US10062623B2 (en) Semiconductor package substrate, package system using the same and method for manufacturing thereof
JP2010093292A (en) Circuit device
WO2017006391A1 (en) Semiconductor device
US7714417B2 (en) Substrate for mounting semiconductor element and method of manufacturing the same
CN108461405B (en) Circuit carrier plate and manufacturing method thereof
US20080000874A1 (en) Printed wiring board and method of manufacturing the same
JP2010135347A (en) Wiring substrate, and method for manufacturing the same
JP2007214568A (en) Circuit board structure
JP4467540B2 (en) Circuit equipment
JP2007081150A (en) Semiconductor device and substrate
JPS58134450A (en) Semiconductor device and manufacture thereof
JP2016225398A (en) Semiconductor device
KR101617023B1 (en) Method of manufacturing PCB substrate having metal post

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant
TR01 Transfer of patent right

Effective date of registration: 20210707

Address after: 518105 area B, Room 403, block B, Rongchao Binhai building, No. 2021, haixiu Road, n26 District, Haiwang community, Xin'an street, Bao'an District, Shenzhen City, Guangdong Province

Patentee after: Liding semiconductor technology (Shenzhen) Co.,Ltd.

Patentee after: Qi Ding Technology Qinhuangdao Co.,Ltd.

Address before: No.18, Tengfei Road, Qinhuangdao Economic and Technological Development Zone, Hebei Province 066004

Patentee before: Qi Ding Technology Qinhuangdao Co.,Ltd.

TR01 Transfer of patent right
TR01 Transfer of patent right

Effective date of registration: 20240206

Address after: SL11, No. 8 Langdong Road, Yanchuan Community, Yanluo Street, Bao'an District, Shenzhen City, Guangdong Province, 518105

Patentee after: Liding semiconductor technology (Shenzhen) Co.,Ltd.

Country or region after: China

Patentee after: Liding semiconductor technology Qinhuangdao Co.,Ltd.

Address before: 518105 area B, Room 403, block B, Rongchao Binhai building, No. 2021, haixiu Road, n26 District, Haiwang community, Xin'an street, Bao'an District, Shenzhen City, Guangdong Province

Patentee before: Liding semiconductor technology (Shenzhen) Co.,Ltd.

Country or region before: China

Patentee before: Qi Ding Technology Qinhuangdao Co.,Ltd.

TR01 Transfer of patent right