KR100694668B1 - Manufacturing method of package substrate without lead line for plating - Google Patents

Abstract

A method for manufacturing a package substrate without a plating inlet line is provided to improve bonding reliability between a solder ball pad and a solder ball by adjusting spreading of plating resist. A method for manufacturing a package substrate without a plating inlet line includes the steps of: forming an inner layer circuit on a surface of an insulation layer, and forming an IVH(Interstitial Via Hole) which penetrates the insulation layer(90); laminating a buried pattern substrate having a circuit pattern on a surface of a seed layer so that the circuit pattern is opposite to a core substrate by installing an insulation material on the core substrate where the inner circuit having a bonding pad on the surface of the insulation layer is formed(100); forming a via-hole by perforating the insulation material, and electrically conducting the inner circuit and the seed layer by plating the via-hole(110); exposing the bonding pad by removing a part of the insulation material and the buried pattern substrate(120); and spreading a plating layer on the bonding pad by applying power to the seed layer(140).

Description

Manufacturing method of package substrate without lead line for plating}

1 is a plan view showing a printed circuit board using a plating lead wire according to the prior art.

2 is a flow chart showing a method for manufacturing a package substrate according to an embodiment of the present invention.

3 is a flow chart showing a package substrate manufacturing process according to an embodiment of the present invention.

Figure 4 is a cross-sectional view showing a package substrate immediately after the gold plating process of the package substrate manufacturing method according to an embodiment of the present invention.

5 is a cross-sectional view showing a package substrate manufactured by a package substrate manufacturing method according to an embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

10: insulating layer 11: core substrate

12: inner layer circuit 14: bonding pad

15: gold plated layer 16: IVH

18: protective resist 20: seed layer

21: buried pattern substrate 22: circuit pattern

24: carrier film 30: insulating material

32: via hole 34: electroless plating layer

36: paint plating layer 40, 42: plating resist

50: solder resist

The present invention relates to a method for manufacturing a package substrate without plating lead wire.

Despite the recent miniaturization of integrated circuits, the number of leads from integrated circuit packages is increasing. Recently, the use of package substrates such as ball grid array (BGA) and chip scale package (CSP) has become common. Since the package substrate is easy to increase the density of the substrate by using a solder ball (solder ball), the package substrate for mounting the semiconductor chip is actively applied.

In a package substrate, a so-called 'bond pad' such as a bonding pad connected to a semiconductor chip or a ball pad connected to a solder ball is often applied with gold plating to improve its electrical connection state. When the plating lead wire is formed, the densification of the circuit is limited, an additional process of removing the plating lead wire after plating is required, and there is a problem of causing signal noise due to remaining of the plating lead wire.

1 is a plan view showing a printed circuit board using a plating lead wire according to the prior art. As shown in Fig. 1, the portion of the printed circuit board 1 actually used as a product is the product portion 1 'indicated by a dotted line. The chip mounting portion 2 is provided at the center of the printed circuit board, and the wire bonding pad 3 is formed around the edge of the chip mounting portion. On the other hand, a plurality of ball pads 4 are formed on the surface of the printed circuit board. The ball pad 4 is a portion to which a solder ball for attaching a printed circuit board and an external substrate is attached. The ball pad 4 is also plated with gold to increase adhesion.

The ball pad 4 is electrically connected to the circuit pattern formed on the printed circuit board and is also substantially connected to the wire bonding pad 3. On the other hand, the wire bonding pad and the ball pad, respectively, the non-linear line 5 for plating is connected. The female wire 5 supplies power for gold plating the respective wire bonding pads 3 and the ball pads 4. The non-winning line 5 is electrically connected to the main line 6, which is formed around the outer portion of the product part 1 ′ in the printed circuit board 1.

However, the above-described prior art has the following problems.

The inlet line is formed to pass between the wire bonding pad 3 and the ball pad 4, and when the gold plating is completed, only the product portion 1 'is used by cutting along the dotted line. Therefore, in the product part 1 'which is actually used, the non-repudiation line 5 which has no function other than what is used at the time of gold plating remains. As the chips become denser and used in high-frequency environments, the signals from the chips also flow in these residual non-entrances, causing interference with adjacent non-entrances, resulting in degradation of product performance.

In order to solve this problem, after gold plating is applied while the gold plating resist is applied to the plating lead wire, the gold plating resist is removed to expose the lead wire 5, and the product is passed through an alkaline etching solution to remove the exposed lead wire. Etch-back technology has been proposed, but this method may remove the circuit pattern of the product by the etching solution when the printed circuit board passes through the etching solution to remove the lead line. It is necessary to leave the incoming line of degree. In addition, since the photosensitive resist is used as the gold-plated resist, there is a limit in that it is not possible to completely remove the nonlinearity in consideration of the positional deviation in applying the resist and the decrease in adhesion to the solder resist.

The present invention provides a package substrate manufacturing method capable of gold plating a bonding pad without using a plating lead wire in a substrate used in a high density integrated circuit package.

According to an aspect of the present invention, in the method of manufacturing a package substrate on which the electronic device is mounted by connecting the electrode of the electronic device to the bonding pad, (a) a core having an inner layer circuit including a bonding pad on the surface of the insulating layer Stacking a buried pattern substrate having a circuit pattern formed on a surface of a seed layer on a surface of a seed layer with an insulating material on the substrate, and (b) perforating the insulating material. Forming via holes, plating the via holes to electrically conduct the inner circuit and the seed layer, (c) removing a portion of the buried pattern substrate and the insulating material to expose the bonding pads, and (d) supplying power to the seed layer. Provided is a package substrate manufacturing method comprising applying a coating layer to a bonding pad by applying a coating.

Prior to step (a), the method may further include (e) forming an inner circuit on the surface of the insulating layer and forming an interstitial via hole (IVH) penetrating through the insulating layer.

Between step (e) and step (a), the method further includes a step of covering the area where the bonding pad is formed in the inner layer circuit with a protective resist, wherein step (c) corresponds to the buried pattern substrate corresponding to the area covered with the protective resist. And removing the insulating material and peeling off the protective resist.

The method may further include forming a circuit pattern by applying a modified semi additive process (MSAP) method on a carrier film on which a seed layer is stacked before step (a). Laminating to the core substrate and removing the carrier film.

Step (b) comprises: (b1) electroless copper plating on the surface of the via hole, (b2) applying a first plating resist to the surface of the seed layer except for the portion where the via hole is formed, and (b3) applying the via hole. Fill plating and peeling the first plating resist may be included.

Between step (c) and step (d), further comprising applying a second plating resist to the surface of the seed layer except for the region where the bonding pad is formed, and after step (d), the second plating resist is applied. Peeling may further comprise a step. Meanwhile, after step (d), the method may further include removing the seed layer by etching.

Other aspects, features, and advantages other than those described above will become apparent from the following detailed description of the invention, including the drawings and the claims.

Hereinafter, a preferred embodiment of a method for manufacturing a package substrate without a plating lead wire according to the present invention will be described in detail with reference to the accompanying drawings, and in describing with reference to the accompanying drawings, the same or corresponding components are given the same reference numerals. And duplicate description thereof will be omitted.

2 is a flowchart illustrating a method of manufacturing a package substrate according to an exemplary embodiment of the present invention.

In this embodiment, a buried pattern is formed by stacking a buried pattern substrate through an insulating material on a core substrate, and a via hole is formed to implement interlayer conduction of a multilayer circuit pattern, and then, a seed layer. By removing the bonding layer by using the seed layer as a plating lead wire gold plating before removing, characterized in that the gold plating on the bonding pad without a separate plating lead wire in the package substrate.

To this end, first, a core substrate and a buried pattern substrate are prepared (90). The core substrate is a substrate having an inner layer circuit formed on the surface of the insulating layer. The core substrate may be manufactured by applying a subtractive method to a copper clad laminate (CCL), or by applying an additive method to an insulating substrate.

IVH may be formed through the insulating layer of the core substrate for electrical connection between inner layer circuits formed on both sides of the core substrate. When a bonding pad for electrical connection with an electronic device mounted on a package substrate is formed in an inner layer circuit, that is, when a bonding pad is included in the inner layer circuit, a cavity is processed after laminating a circuit pattern layer as described below. A process of exposing the bonding pad is performed, and for this purpose, the peripheral area of the bonding pad is previously covered with a protective resist (92).

As the protective resist, a dry film may be used, and in the cavity forming process for exposing the bonding pad, the dry film may be processed only until the protective resist is exposed, and then the protective resist may be peeled off to perform the cavity forming process without damaging the bonding pad. have.

In addition, a buried pattern substrate is formed to stack a circuit pattern layer through an insulating material on an outer layer of the core substrate. The buried pattern substrate is a substrate on which a circuit pattern is formed on the surface of the seed copper foil layer, and may be manufactured by applying a MSAP method to a carrier film on which the seed layer is stacked (94).

Packages such as BGA and CSP are manufactured by mounting an electronic device on the surface of a substrate and then injecting an underfill resin between the electronic device and the substrate, thereby forming a buried circuit pattern to form a flat surface of the substrate. In order to use the seed layer as a plating lead wire, in this embodiment, a buried pattern substrate is used to form a conductive layer that electrically connects the entire circuit pattern to the outer layer of the circuit pattern. A buried circuit pattern is formed.

The carrier film may use a resin or a metal film as a part to be peeled off and removed after forming the buried circuit pattern.

After the core substrate and the buried pattern substrate are prepared, the buried pattern substrate is laminated (100) with an insulating material on the core substrate. In order to form the buried circuit pattern, it is preferable to stack the buried pattern substrate so that the circuit pattern faces the core substrate. As described above, after laminating the buried pattern substrate, the carrier film is removed by peeling or the like.

In this way, a buried circuit pattern is laminated on the core substrate to form a multilayer package substrate having four circuit pattern layers. Next, via holes are formed to electrically connect the multilayer circuit pattern layers. In other words, the insulating material stacked on the core substrate is drilled to form via holes such as blind via holes (BVHs), and the surface of the buried circuit pattern and the inner layer circuit are electrically connected (110). As a result, the seed layer of the buried pattern substrate and the inner layer circuit of the core substrate including the bonding pads are electrically connected to each other.

Since the surface of the via hole corresponds to an insulating material, the plating on the surface of the via hole is applied to the electroless copper plating process (112), and fills the inside of the via hole based on the electroless plating layer to realize an electrical passage between the circuit pattern layers. . That is, the plating resist is applied to the surface of the seed layer except for the portion where the via hole is formed (114), the via hole is peeled off, and the plating resist is peeled off to remove it (116).

Next, the cavity is processed so that the bonding pads in the inner layer circuit are exposed. That is, as described above, the buried pattern substrate and the insulating material corresponding to the position of the protective resist coated on the region where the bonding pad is formed are removed to expose the protective resist, and then the protective resist is peeled off to expose the bonding pad (120). ).

Since the present embodiment has been described by taking a case where a bonding pad for mounting an electronic device is formed in an inner layer circuit as an example, the above-described cavity processing process may be omitted when the bonding pad is formed on the surface of the package substrate.

Next, a plating resist is applied to the surface of the seed layer except for the region where the bonding pad is formed so that the gold plating process is applied only to the bonding pad (130). On the other hand, by applying a surface treatment process other than plating resist coating in this process, it is possible to separate the surface treatment to the portion other than the portion to which gold plating is applied, such as a bonding pad.

In this way, when the buried circuit pattern is formed on the surface and the multilayer circuit pattern layers are electrically connected by the via holes, when the portions other than the bonding pads are covered with the plating resist, the seed layer of the buried circuit pattern is supplied with a power source for plating. By applying the above, electrolytic plating is possible on the portion where the plating resist is not coated, that is, the bonding pad. That is, the seed layer of the buried circuit pattern serves as a plating lead wire. As such, in the present embodiment, the bonding pads can be gold plated without a separate plating lead wire, and a separate surface treatment is possible at portions other than the gold plated portions.

After the plating pad is gold-plated, the plating resist is peeled off and removed (140), and the surface of the substrate is etched to remove the seed layer (150), thereby completing the manufacture of the package substrate having the multilayer circuit pattern layer.

3 is a flowchart showing a package substrate manufacturing process according to an embodiment of the present invention, Figure 4 is a cross-sectional view showing a package substrate immediately after the gold plating process of the package substrate manufacturing method according to an embodiment of the present invention. 5 is a cross-sectional view showing a package substrate manufactured by a package substrate manufacturing method according to an embodiment of the present invention. 3 to 5, the insulating layer 10, the core substrate 11, the inner circuit 12, the bonding pad 14, the gold plating layer 15, the IVH 16, the protective resist 18, Seed layer 20, buried pattern substrate 21, circuit pattern 22, carrier film 24, insulating material 30, via hole 32, electroless plating layer 34, fill plating layer 36, plating resist 40 and 42, solder resist 50 is shown.

The present embodiment forms a circuit pattern 22 by applying an improved semi additive method when fabricating a package substrate for mounting an electronic device by processing a cavity, thereby using a wire bonding pad without using a plating lead wire. 14) characterized in that the gold plating.

To this end, as illustrated in FIG. 3A, a core substrate 11 having an inner layer circuit 12 formed on the surface of the insulating layer 10 is manufactured. The core substrate 11 is processed with IVH 16 for electrical conduction between circuit pattern layers, and an inner layer circuit 12 including a bonding pad 14 is formed on a surface by a circuit pattern forming process such as plating, exposure, or etching. Is formed.

Next, as shown in FIG. 3B, the bonding pad 14 is coated with the protective resist 18 to protect the bonding pad 14 and secure the tolerance during the cavity processing to expose the bonding pad 14. In order to coat the protective resist 18, the resist may be exposed and developed.

Next, in order to produce a circuit pattern 22 to be used as an outer layer as shown in FIG. 3C, the dry film 23 is laminated on the seed layer 20 laminated on the carrier film 24, and the exposure and development are performed. And the like, and the circuit pattern 22 is formed by pattern plating as shown in FIG. 3 (d), the dry film is peeled off to form the buried pattern substrate 21.

Next, as shown in FIG. 3E, the buried pattern substrate 21 is laminated on the core substrate 11 with the insulating material 30 interposed therebetween. In the lamination process, guide holes and rivets may be used to match the inner and outer layers.

Next, as shown in (f) of FIG. 3, the via hole 32 is processed for electrical conduction between the circuit pattern layers, and as shown in (g) of FIG. 3, conductivity is applied to the insulating material 30 which is the surface of the via hole 32. In order to do so, electroless copper plating is performed to form the electroless plating layer 34.

Next, in order to peel the via hole 32 as shown in FIG. 3H, the plating resist 40 is laminated, and only the portion of the via hole 32 is exposed through the exposure and development processes, and the remaining portion is the plating resist 40. After coating, the inside of the via hole 32 is peeled to form a fill plating layer 36, and the plating resist 40 is peeled off as shown in FIG.

Next, the cavity is processed to expose the bonding pads 14 formed on the inside of the package substrate, that is, the surface of the core substrate 11, as shown in FIG. In the case where the protective resist 18 for protecting the bonding pad 14 is coated as shown in FIG. 3 (b), the cavity processing process is performed only until the protective resist 18 is exposed. The exposed protective resist 18 is then peeled off. As a result, the bonding pad 14 is exposed.

Next, as shown in FIG. 3 (l), the plating resist 42 is laminated, and the plating resist 42 is coated on portions other than the portion where the gold plating is applied, such as the bonding pad 14, through exposure and development processes. In this process, other surface treatments may be applied to areas not covered by gold plating.

Finally, as shown in (m) of FIG. 3, the plating layer 42 is formed on the surface of the bonding pad 14 by applying power for plating to the seed layer 20, and then the plating resist 42 is peeled off and etched. The seed layer 20 is removed.

Thereafter, a general package substrate manufacturing process such as applying a solder resist 50 to the surface of the package substrate and mounting an electronic device is performed.

In order to apply such a package substrate manufacturing process, a cross section of the substrate immediately after the gold plating process is performed is shown in FIG. 4, and a final product cross section of the package substrate is shown in FIG. 5. As described above, the seed layer 20 of the buried circuit pattern 22 of the outermost layer is used as the plating lead line to form the gold plating layer 15 on the bonding pad 14 as shown in FIG. 4 without a separate plating lead line. It is preferable to manufacture the substrate with a structure.

First, the bonding pad 14 existing in the inner circuit 12 and the buried circuit pattern 22 of the outermost layer, that is, the seed layer 20 may be electrically connected. Second, when the bonding pads 14 are formed in the inner layer circuit 12, a cavity, which is a kind of groove, may be formed. Third, via holes such as BVH, IVH 16, and plated through holes (PTH) are used to realize electrical connection between circuit pattern layers.

In the present embodiment, a package substrate having a multi-layered circuit pattern and a bonding pad 14 formed on the inner layer circuit 12 has been described as an example. In addition, when the single-layered circuit pattern is formed or the bonding pad 14 is formed on the surface of the substrate. Of course, the technical spirit of the present invention can be applied to the case where) is formed.

Many embodiments other than the above-described embodiments are within the scope of the claims of the present invention.

As described above, according to the preferred embodiment of the present invention, since a separate plating lead wire for gold plating such as a bonding pad is unnecessary, circuit design freedom is improved, and an additional circuit design is possible at a portion where the plating lead wire is to be formed. It is advantageous to manufacture, and it is possible to improve the electrical characteristics of the package substrate by preventing signal noise that may occur due to the remaining plating lead wire.

In addition, the surface treatment of the solder ball pad can be different from that of the wire bonding pad by controlling the application of the plating resist, thereby improving the bonding reliability between the solder ball pad and the solder ball.

Claims (7)

In the manufacturing method of the package substrate in which the electronic device is mounted by connecting the electrode of the electronic device to the bonding pad, (a) A buried pattern substrate in which a circuit pattern is formed on a surface of a seed layer via an insulating material on a core substrate on which an inner layer circuit including a bonding pad is formed on the surface of the insulating layer. Stacking circuit patterns so as to face the core substrate; (b) perforating the insulating material to form a via hole, and plating the via hole to electrically conduct the inner circuit and the seed layer; (c) exposing the bonding pads by removing a portion of the buried pattern substrate and the insulating material; And (d) applying a power to the seed layer to coat the plating layer on the bonding pads. The method of claim 1, Before step (a) above, (e) forming an inner layer circuit on the surface of the insulating layer, and forming an interstitial via hole (IVH) penetrating the insulating layer. The method of claim 2, Between the step (e) and the step (a), Covering the area where the bonding pad is formed in the inner layer circuit with a protective resist; Step (c) is, And removing the buried pattern substrate and the insulating material and peeling the protective resist in correspondence to the area covered with the protective resist. The method of claim 1, The method may further include forming a circuit pattern by applying a modified semi additive process (MSAP) method on a carrier film on which the seed layer is stacked before the step (a). The step (a) is a method of manufacturing a package substrate comprising the step of laminating the buried pattern substrate on the core substrate, the carrier film. The method of claim 1, Step (b) is, (b1) electroless copper plating on the surface of the via hole; (b2) applying a first plating resist to the surface of the seed layer except for the portion where the via hole is formed; And (b3) filling the via hole and peeling the first plating resist. The method of claim 1, Between the step (c) and the step (d), Applying a second plating resist to a surface of the seed layer except for a region where the bonding pad is formed; After step (d) above, Peeling the second plating resist further comprises a package substrate manufacturing method. The method of claim 1, And removing said seed layer by etching after said step (d).

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