KR20030075824A - The fabrication method of printed circuit board for semiconductor package having tailless pattern - Google Patents

The fabrication method of printed circuit board for semiconductor package having tailless pattern Download PDF

Info

Publication number
KR20030075824A
KR20030075824A KR1020020015286A KR20020015286A KR20030075824A KR 20030075824 A KR20030075824 A KR 20030075824A KR 1020020015286 A KR1020020015286 A KR 1020020015286A KR 20020015286 A KR20020015286 A KR 20020015286A KR 20030075824 A KR20030075824 A KR 20030075824A
Authority
KR
South Korea
Prior art keywords
solder
nickel
copper
dry film
plating
Prior art date
Application number
KR1020020015286A
Other languages
Korean (ko)
Inventor
유문상
이승헌
차상석
Original Assignee
주식회사 심텍
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 주식회사 심텍 filed Critical 주식회사 심텍
Priority to KR1020020015286A priority Critical patent/KR20030075824A/en
Publication of KR20030075824A publication Critical patent/KR20030075824A/en

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0011—Working of insulating substrates or insulating layers
    • H05K3/0017—Etching of the substrate by chemical or physical means
    • H05K3/002—Etching of the substrate by chemical or physical means by liquid chemical etching
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0011—Working of insulating substrates or insulating layers
    • H05K3/0017—Etching of the substrate by chemical or physical means
    • H05K3/0023—Etching of the substrate by chemical or physical means by exposure and development of a photosensitive insulating layer
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3431—Leadless components
    • H05K3/3436—Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3452—Solder masks
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/07—Treatments involving liquids, e.g. plating, rinsing
    • H05K2203/0779—Treatments involving liquids, e.g. plating, rinsing characterised by the specific liquids involved
    • H05K2203/0786—Using an aqueous solution, e.g. for cleaning or during drilling of holes
    • H05K2203/0793—Aqueous alkaline solution, e.g. for cleaning or etching

Abstract

PURPOSE: A method of fabricating a PCB(Printed Circuit Board) for semiconductor package having a tailless pattern is provided to perform an electric nickel/gold plating process regardless of a design for a circuit pattern and reduce the electric noise due to a tail of a finger by forming necessary patterns without using a plating lead line. CONSTITUTION: A dry film is coated on both sides of a substrate including a copper layer. The first imaging process is performed to expose partially the copper layer corresponding to a bonding finger forming part and a solder ball land forming part. A nickel/gold plating process is performed to form a nickel/gold plating layer on the exposed copper layer. The first strip process is performed to remove the dry film. The second imaging process is performed to expose a part of the copper layer corresponding to a circuit pattern by coating, exposing, and developing the dry film. A solder plating process is performed to form a solder plating layer. The second strip process is performed to remove the dry film. An etching process is performed to remove the copper layer without the nickel/gold plating layer and the solder plating layer. The third strip process is performed to remove the solder plating layer. A solder masking process is performed to form a plastic layer on the remaining region except a soldering region.

Description

테일리스 패턴을 갖는 반도체 패키지용 인쇄회로기판의 제조방법{The fabrication method of printed circuit board for semiconductor package having tailless pattern}The fabrication method of printed circuit board for semiconductor package having tailless pattern}

본 발명은 반도체 패키지용 인쇄회로기판의 제조방법에 관한 것으로서, 특히, 양면 전체에 동이 덮혀진 기판상에 제1이미징 및 니켈/금도금에 의해 핑거 및 솔더볼랜드를 먼저 형성하고 제2이미징 및 솔더도금에 의해 회로 패턴을 형성한 후, 니켈/금도금 및 솔더도금되지 않은 동부분을 에칭으로 제거하고 회로패턴상의 솔더도금층을 제거하여, 핑거의 니켈/금 도금을 위한 도금용 리드선을 별도로 형성하지 않고 필요한 패턴만을 형성하도록 함으로써, 회로패턴의 디자인에 관계없이 전기 니켈/금 도금을 할 수 있고, 핑거의 테일로 인한 전기적 노이즈를 감소시킬 수 있는 테일리스 패턴을 갖는 반도체 패키지용 인쇄회로기판의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a printed circuit board for a semiconductor package. In particular, a finger and solder bores are first formed by first imaging and nickel / gold plating on a copper-covered substrate on both sides, and second imaging and solder plating. After the circuit pattern is formed, the nickel / gold plated and unsoldered copper powder is removed by etching and the solder plated layer on the circuit pattern is removed, so that the plating lead wire for nickel / gold plating of the finger is not formed separately. By forming only the pattern, the method of manufacturing a printed circuit board for a semiconductor package having a tailless pattern that can be electro-nickel / gold plating regardless of the design of the circuit pattern, and can reduce the electrical noise due to the tail of the finger. It is about.

일반적으로 반도체 패키지는 회로패턴이 형성된 인쇄회로기판 상에 반도체 칩을 부착시키고, 반도체 칩상의 입출력 패드인 본딩패드와 인쇄회로기판상에 형성된 본딩핑거를 도전성 와이어로 연결하고, 상기 인쇄회로기판상의 반도체 칩, 도전성 와이어, 회로패턴 등을 외부의 환경으로부터 보호하기 위해 상부면을 몰딩수지로 몰딩하여 형성된다. 여기에서, 상기 반도체 칩의 본딩패드와 와이어로 연결되는 인쇄회로기판상의 본딩핑거는 그 전기적 신뢰성을 높이기 위해 니켈/금 도금 처리를 하고 있다. 이러한 본딩핑거의 니켈/금 도금 및 회로패턴을 형성하는 종래의 인쇄회로기판 제조방법이 도 1 및 도 2a 내지 도 2f에 도시되어 있다.In general, a semiconductor package attaches a semiconductor chip on a printed circuit board on which a circuit pattern is formed, connects a bonding pad, which is an input / output pad on the semiconductor chip, and a bonding finger formed on the printed circuit board, with a conductive wire, and the semiconductor on the printed circuit board. In order to protect the chip, the conductive wire, the circuit pattern, and the like from the external environment, the upper surface is formed by molding the molding resin. Here, the bonding finger on the printed circuit board connected to the bonding pad and wire of the semiconductor chip is subjected to nickel / gold plating to increase its electrical reliability. Conventional printed circuit board manufacturing methods for forming the nickel / gold plating and the circuit pattern of the bonding finger is shown in Figures 1 and 2a to 2f.

도면을 참고하면, 먼저, 이미징 단계에서 도 2a에 도시된 것과 같이 양면에 동(12)이 입혀진 기판(11) 양면상에 드라이필름(13)을 도포하고, 본딩핑거, 회로패턴 및 도금용 리드선 부분을 노광 및 현상하여, 도 2b와 같이 본딩핑거, 회로패턴 및 도금용 리드선이 형성될 부분을 제외한 부분의 동박(12)을 외부로 노출시킨다.Referring to the drawings, first, in the imaging step, as shown in FIG. 2A, the dry film 13 is coated on both surfaces of the substrate 11 coated with copper 12 on both sides, and bonding fingers, circuit patterns, and plating leads are used. The portion is exposed and developed to expose the copper foil 12 of the portion except for the portion where the bonding finger, the circuit pattern and the plating lead wire are to be formed as shown in FIG. 2B.

그 후, 에칭단계에서는 도 2c와 같이 상기 외부로 노출된 동박(12)을 제거하고, 스트립 단계에서는 도 2d와 같이 상기 본딩핑거, 회로패턴 및 도금용 리드선을 덮고 있는 드라이필름(13)을 제거하여 원하는 패턴을 얻는다.Thereafter, in the etching step, the copper foil 12 exposed to the outside is removed as shown in FIG. 2C, and in the stripping step, the dry film 13 covering the bonding finger, the circuit pattern, and the plating lead wire is removed as shown in FIG. 2D. To get the desired pattern.

또, 솔더 마스킹 단계에서는 도 2e에서와 같이 니켈/금 도금을 위한 본딩핑거 부분을 제외한 회로패턴(14) 상부에 얇은 플라스틱의 막을 덮어씌워 절연시킨다.In addition, in the solder masking step, as shown in FIG. 2E, a thin plastic film is covered and insulated on the circuit pattern 14 except for the bonding finger for nickel / gold plating.

다음으로, 니켈/금 도금단계에서는 도 2f와 같이 솔더 마스크(15)가 덮혀지지 않은 본딩핑거(16) 및 솔더볼랜드(17)상에 전기 도금을 수행하여 니켈/금(18)을 형성시킨다.Next, in the nickel / gold plating step, as shown in FIG. 2F, electroplating is performed on the bonding finger 16 and the solder borland 17 on which the solder mask 15 is not covered to form nickel / gold 18.

상기와 같이 종래에는 인쇄회로기판상에 회로패턴과 본딩핑거를 단일 이미징 공정에 의해 함께 형성시키고, 본딩핑거상에 니켈/금 도금을 하기 위한 도금용 리드선을 별도로 형성하였다.As described above, in the related art, a circuit pattern and a bonding finger are formed together by a single imaging process on a printed circuit board, and a plating lead wire for nickel / gold plating is separately formed on the bonding finger.

도 3은 종래의 반도체 패키지용 인쇄회로기판의 제조과정에 의해 회로 패턴이 형성된 상태를 나타내는 인쇄회로기판의 평면도이다.3 is a plan view of a printed circuit board showing a state in which a circuit pattern is formed by a manufacturing process of a conventional printed circuit board for semiconductor packages.

도면에서 알 수 있는 것과 같이, 종래의 제조과정에서는 회로패턴, 본딩핑거 및 도금용 리드선을 단일 이미징으로 함께 형성시킨 후, 본딩핑거를 니켈/금 도금 처리하기 때문에, 비아홀(20) 등에 의해 하부 패턴과 연결되어 중간에 회로패턴과 연결이 끊기는 본딩핑거(16)인 경우 전기도금을 위한 별도의 리드선(19)을 형성시켜야 한다. 이러한 리드선(19)은 본딩핑거(16)에 테일(tail)을 형성시키게 되고 고주파신호의 처리를 필요로 하는 반도체 소자인 경우 노이즈를 발생시키게 되는 문제점이 있었다.As can be seen in the drawing, in the conventional manufacturing process, the circuit pattern, the bonding finger and the plating lead are formed together in a single imaging, and then the bonding finger is nickel / gold plated, so that the lower pattern is formed by the via hole 20 or the like. In the case of a bonding finger 16 connected to the circuit pattern and disconnected in the middle, a separate lead wire 19 for electroplating should be formed. Such a lead wire 19 has a problem in that a tail is formed in the bonding finger 16 and noise is generated in the case of a semiconductor device requiring high frequency signal processing.

상기의 문제점을 해결하기 위한 본 발명의 목적은 양면 전체에 동이 덮혀진 기판상에 제1이미징 및 니켈/금도금에 의해 핑거 및 솔더볼랜드를 먼저 형성하고 제2이미징 및 솔더도금에 의해 회로 패턴을 형성한 후, 니켈/금도금 및 솔더도금되지 않은 동부분을 에칭으로 제거하고 회로패턴상의 솔더도금층을 제거하여, 핑거의 니켈/금 도금을 위한 도금용 리드선을 별도로 형성하지 않고 필요한 패턴만을 형성하도록 함으로써, 회로패턴의 디자인에 관계없이 전기 니켈/금 도금을 할 수 있고, 핑거의 테일로 인한 전기적 노이즈를 감소시킬 수 있는 테일리스 패턴을 갖는 반도체 패키지용 인쇄회로기판의 제조방법을 제공하는데 있다.An object of the present invention for solving the above problems is to first form a finger and solder bores by first imaging and nickel / gold plating on a copper-covered substrate on both sides and a circuit pattern by second imaging and solder plating After that, the nickel / gold plated and unplated copper powder is removed by etching and the solder plated layer on the circuit pattern is removed so that only necessary patterns are formed without forming a plating lead wire for nickel / gold plating of the finger. The present invention provides a method of manufacturing a printed circuit board for a semiconductor package having a tailless pattern capable of electro-nickel / gold plating and reducing electrical noise due to a tail of a finger, regardless of the design of the circuit pattern.

도 1은 종래의 반도체 패키지용 인쇄회로기판의 제조과정을 나타내는 흐름도,1 is a flowchart illustrating a manufacturing process of a conventional printed circuit board for a semiconductor package;

도 2a 내지 도 2f는 종래의 반도체 패키지용 인쇄회로기판의 제조과정을 나타내는 단면도,2A through 2F are cross-sectional views illustrating a manufacturing process of a conventional printed circuit board for semiconductor packages;

도 3은 종래의 반도체 패키지용 인쇄회로기판의 제조과정에 의해 회로 패턴이 형성된 상태를 나타내는 인쇄회로기판의 평면도,3 is a plan view of a printed circuit board showing a state in which a circuit pattern is formed by a manufacturing process of a conventional printed circuit board for semiconductor packages;

도 4는 본 발명에 의한 반도체 패키지용 인쇄회로기판의 제조과정을 나타내는 흐름도,4 is a flowchart illustrating a manufacturing process of a printed circuit board for a semiconductor package according to the present invention;

도 5a 내지 도 5f는 본 발명에 의한 반도체 패키지용 인쇄회로기판의 핑거와 솔더볼랜드 형성과정을 나타내는 도면,5A to 5F are views illustrating a process of forming a finger and a solder ball land of a printed circuit board for a semiconductor package according to the present invention;

도 6a 내지 도 6f는 본 발명에 의한 반도체 패키지용 인쇄회로기판의 회로 패턴 형성과정을 나타내는 도면.6a to 6f are views illustrating a circuit pattern forming process of a printed circuit board for a semiconductor package according to the present invention.

<도면의 주요부분에 대한 부호의 설명><Description of Symbols for Main Parts of Drawings>

1, 25 : 반도체칩 접착부20 : 비아홀1, 25: semiconductor chip bonding portion 20: via hole

11, 21 : 기판12, 22 : 동11, 21: substrate 12, 22: copper

13, 23 : 드라이필름14, 29 : 회로패턴13, 23: dry film 14, 29: circuit pattern

15 : 솔더마스크16, 27 : 본딩핑거15: solder mask 16, 27: bonding finger

17, 28 : 솔더볼랜드18, 24 : 니켈/금도금층17, 28: solder bores 18, 24: nickel / gold plated layer

19 : 도금용 리드선26 : 솔더도금층19: plating lead wire 26: solder plating layer

상기 목적을 해결하기 위해, 본 발명은 양면에 동이 입혀진 기판 양면에 드라이필름을 도포하고, 노광 및 현상하여 반도체 칩 접착부 둘레의 본딩핑거 형성부분과 솔더볼랜드 형성부분의 동만을 외부로 노출시키는 제1이미징단계; 상기 외부로 노출된 동에 전기도금을 수행하여 니켈/금도금층을 형성시키는 니켈/금도금단계; 상기 드라이필름을 제거하는 제1스트립단계; 상기 본딩핑거 및 솔더볼랜드가 도금된 기판의 양면에 드라이필름을 도포하고, 노광 및 현상하여 회로패턴이 형성될 부분의 동을 외부로 노출시키는 제2이미징단계; 상기 외부로 노출된 동에 전기도금을 수행하여 솔더도금층을 형성하는 솔더도금단계; 상기 드라이필름을 제거하는 제2스트립단계; 상기 니켈/금도금 및 솔더도금이 되지 않은 부분의 동을 알칼리 에칭에 의해 제거하는 에칭단계; 회로패턴상의 솔더도금층을 제거하는 제3스트립단계; 솔더 레지스트를 인쇄하여 부품을 납땜할 자리를 제외한 모든 영역에 얇은 플라스틱의 막을 덮어씌워 절연시키는 솔더마스킹단계를 포함하여 이루어진 것을 특징으로 한다.In order to solve the above object, the present invention is to apply a dry film on both sides of the substrate coated with copper on both sides, exposure and development to expose only the copper of the bonding finger forming portion and the solder ballland forming portion around the semiconductor chip adhesive portion to the outside Imaging step; A nickel / gold plating step of electroplating the exposed copper to form a nickel / gold plating layer; A first stripping step of removing the dry film; A second imaging step of applying a dry film to both surfaces of the bonding finger and the solder borland plated substrate, and exposing and developing the copper of the portion where the circuit pattern is to be formed; A solder plating step of forming a solder plating layer by performing electroplating on the copper exposed to the outside; A second strip step of removing the dry film; An etching step of removing copper of the portions which are not nickel / gold plated and solder plated by alkali etching; A third stripping step of removing the solder plating layer on the circuit pattern; And a solder masking step of covering and insulating a thin film of plastic over all areas except the place where the parts are to be soldered by printing a solder resist.

이하, 첨부된 도면을 참고하여 본 발명을 좀더 상세히 설명한다.Hereinafter, with reference to the accompanying drawings will be described the present invention in more detail.

도 4는 본 발명에 의한 반도체 패키지용 인쇄회로기판의 제조과정을 나타내는 흐름도이고, 도 5a 내지 도 5f는 본 발명에 의한 반도체 패키지용 인쇄회로기판의 핑거와 솔더볼랜드 형성과정을 나타내는 도면이고, 도 6a 내지 도 6f는 본 발명에 의한 반도체 패키지용 인쇄회로기판의 회로 패턴 형성과정을 나타내는 도면이다.4 is a flowchart illustrating a process of manufacturing a printed circuit board for a semiconductor package according to the present invention, and FIGS. 5A to 5F are views illustrating a process of forming a finger and solder borland of the printed circuit board for a semiconductor package according to the present invention. 6a to 6f are views illustrating a circuit pattern forming process of a printed circuit board for a semiconductor package according to the present invention.

먼저, 제1이미징단계에서는 도 5a 및 도 5b와 같이, 양면에 동(22)이 입혀진기판(21) 양면에 드라이필름(23)을 도포하고, 노광 및 현상하여 반도체 칩 접착부 둘레의 본딩핑거 형성부분과 솔더볼랜드 형성부분의 동(22)만을 외부로 노출시킨다. 또, 니켈/금도금단계에서는 도 5c와 같이, 상기 외부로 노출된 동(22)에 전기 니켈/금도금을 수행하여 니켈/금도금층(24)을 형성시키고, 제1스트립단계에서는 도 5d와 같이 드라이필름(23)을 제거한다.First, in the first imaging step, as shown in FIGS. 5A and 5B, the dry film 23 is coated on both surfaces of the substrate 21 coated with copper 22 on both surfaces, and exposed and developed to form a bonding finger around the semiconductor chip bonding portion. Only the copper 22 of the portion and the solder ball land forming portion is exposed to the outside. In addition, in the nickel / gold plating step, as shown in FIG. 5C, the nickel / gold plating layer 24 is formed by performing electric nickel / gold plating on the copper 22 exposed to the outside, and in the first stripping step, as shown in FIG. 5D. The film 23 is removed.

상기의 공정에 의해, 기판(21)의 반도체 칩 접착면에는 도 5e와 같이 반도체 칩 접착부(25) 둘레의 본딩핑거 형성부분에 니켈/금도금층(24)이 형성되고, 기판(21)의 솔더볼 접착면에는 도 5f와 같이 솔더볼랜드 형성부분에 니켈/금도금층(24)이 형성된다.By the above process, the nickel / gold plated layer 24 is formed on the bonding chip formation part around the semiconductor chip bonding part 25 on the semiconductor chip bonding surface of the board | substrate 21 like FIG. 5E, and the solder ball of the board | substrate 21 is carried out. On the adhesive surface, a nickel / gold plated layer 24 is formed on the solder ball land forming portion as shown in FIG. 5F.

그 후, 제2이미징단계에서는 도 6a와 같이 상기 본딩핑거 및 솔더볼랜드가 도금된 기판(21)의 양면에 드라이필름(23)을 도포하고, 도 6b 및 도 6c와 같이 노광 및 현상하여 회로패턴이 형성될 부분(P)의 동(22)을 외부로 노출시킨다.Subsequently, in the second imaging step, the dry film 23 is coated on both surfaces of the bonding finger and the solder ballland-plated substrate 21 as shown in FIG. 6A, and the circuit pattern is exposed and developed as shown in FIGS. 6B and 6C. The copper 22 of the portion P to be formed is exposed to the outside.

또, 솔더도금단계에서는 도 6d와 같이 상기 외부로 노출된 동(22)에 전기도금을 수행하여 솔더도금층(26)을 형성하고, 제2스트립단계에서는 상기 드라이필름(23)을 제거하며, 에칭단계에서는 도 6e와 같이 상기 니켈/금도금 및 솔더도금이 되지 않은 부분의 동(22)을 알칼리 에칭에 의해 제거한다.In addition, in the solder plating step, as shown in FIG. 6D, electroplating is performed on the externally exposed copper 22 to form the solder plating layer 26. In the second strip step, the dry film 23 is removed and etched. In the step, as shown in FIG. 6E, the copper 22 of the nickel / gold plating and the non-solder plating portions is removed by alkali etching.

상기의 공정에 의해 기판(21)의 양면 각각에는 니켈/금도금된 본딩핑거(27) 및 솔더볼랜드(28)와 솔더도금된 회로패턴(29)이 형성된다.By the above process, nickel / gold plated bonding fingers 27, solder bores 28, and solder plated circuit patterns 29 are formed on both surfaces of the substrate 21.

그 후, 제3스트립단계에서는 도 6f와 같이 회로패턴(29)상의 솔더도금층(26)을 제거하고, 솔더마스킹 단계에서는 솔더 레지스트를 인쇄하여 부품을 납땜할 자리를 제외한 모든 영역에 얇은 플라스틱의 막을 덮어씌워 절연시킨다.Subsequently, in the third stripping step, as shown in FIG. 6F, the solder plating layer 26 on the circuit pattern 29 is removed. In the soldermasking step, a thin film of plastic is applied to all areas except for the place where the parts are to be soldered by printing a solder resist. Cover and insulate.

상기와 같이, 본 발명은 본딩핑거 및 솔더볼랜드를 니켈/금도금에 의해 먼저 형성시키고, 솔더도금에 의해 회로패턴을 형성시킨 후, 니켈/금도금 및 솔더도금되지 않은 동을 알칼리 에칭으로 제거하므로 본딩핑거의 니켈/금 도금을 위한 리드선을 별도로 형성시킬 필요가 없다.As described above, in the present invention, the bonding finger and the solder borland are first formed by nickel / gold plating, the circuit pattern is formed by solder plating, and then the nickel / gold plating and the non-soldered copper are removed by alkali etching. It is not necessary to separately form a lead wire for nickel / gold plating.

상기한 바와 같이 본 발명에 의하면, 양면 전체에 동이 덮혀진 기판상에 제1이미징 및 니켈/금도금에 의해 핑거 및 솔더볼랜드를 먼저 형성하고 제2이미징 및 솔더도금에 의해 회로 패턴을 형성한 후, 니켈/금도금 및 솔더도금되지 않은 동부분을 에칭으로 제거하고 회로패턴상의 솔더도금층을 제거하여, 핑거의 니켈/금 도금을 위한 도금용 리드선을 별도로 형성하지 않고 필요한 패턴만을 형성하도록 함으로써, 회로패턴의 디자인에 관계없이 전기 니켈/금 도금을 할 수 있고, 핑거의 테일로 인한 전기적 노이즈를 감소시킬 수 있는 효과가 있다.As described above, according to the present invention, a finger and solder bores are first formed by first imaging and nickel / gold plating on a substrate covered with copper on both sides, and a circuit pattern is formed by second imaging and solder plating. By removing the nickel / gold plated and unplated copper powder by etching and removing the solder plated layer on the circuit pattern, only the necessary pattern is formed without forming a plating lead wire for nickel / gold plating of the finger. Regardless of the design, electro-nickel / gold plating can be performed, and electrical noise due to the tail of the finger can be reduced.

Claims (1)

반도체 패키지용 인쇄회로기판의 제조방법에 있어서, 양면에 동(22)이 입혀진 기판(21) 양면에 드라이필름(23)을 도포하고, 노광 및 현상하여 반도체 칩 접착부 둘레의 본딩핑거 형성부분과 솔더볼랜드 형성부분의 동(22)만을 외부로 노출시키는 제1이미징단계; 상기 외부로 노출된 동(22)에 전기도금을 수행하여 니켈/금도금층(24)을 형성시키는 니켈/금도금단계; 상기 드라이필름(23)을 제거하는 제1스트립단계; 상기 본딩핑거 및 솔더볼랜드가 도금된 기판(21)의 양면에 드라이필름(23)을 도포하고, 노광 및 현상하여 회로패턴이 형성될 부분의 동(22)을 외부로 노출시키는 제2이미징단계; 상기 외부로 노출된 동(22)에 전기도금을 수행하여 솔더도금층(26)을 형성하는 솔더도금단계; 상기 드라이필름(23)을 제거하는 제2스트립단계; 상기 니켈/금도금 및 솔더도금이 되지 않은 부분의 동(22)을 알칼리 에칭에 의해 제거하는 에칭단계; 회로패턴(29)상의 솔더도금층(26)을 제거하는 제3스트립단계; 솔더 레지스트를 인쇄하여 부품을 납땜할 자리를 제외한 모든 영역에 얇은 플라스틱의 막을 덮어씌워 절연시키는 솔더마스킹단계를 포함하는 것을 특징으로 하는 테일리스 패턴을 갖는 반도체 패키지용 인쇄회로기판의 제조방법.In the method of manufacturing a printed circuit board for a semiconductor package, a dry film 23 is coated on both surfaces of a substrate 21 coated with copper 22 on both surfaces, and exposed and developed to bond bonding portions and solder balls around the semiconductor chip bonding portion. A first imaging step of exposing only the copper 22 of the land forming portion to the outside; A nickel / gold plating step of forming the nickel / gold plating layer 24 by performing electroplating on the copper 22 exposed to the outside; A first stripping step of removing the dry film 23; A second imaging step of applying a dry film 23 to both surfaces of the bonding finger and the solder borland plated substrate 21 and exposing and developing the copper 22 of a portion where a circuit pattern is to be formed to the outside; A solder plating step of forming a solder plating layer 26 by electroplating the copper 22 exposed to the outside; A second stripping step of removing the dry film 23; An etching step of removing the copper 22 of the nickel / gold plating and the solder plating portion by alkali etching; A third stripping step of removing the solder plating layer 26 on the circuit pattern 29; A method of manufacturing a printed circuit board for a semiconductor package having a tailless pattern, comprising: a solder masking step of printing a solder resist to cover and insulate a thin plastic film in all areas except a place to solder a component.
KR1020020015286A 2002-03-21 2002-03-21 The fabrication method of printed circuit board for semiconductor package having tailless pattern KR20030075824A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020020015286A KR20030075824A (en) 2002-03-21 2002-03-21 The fabrication method of printed circuit board for semiconductor package having tailless pattern

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020020015286A KR20030075824A (en) 2002-03-21 2002-03-21 The fabrication method of printed circuit board for semiconductor package having tailless pattern

Publications (1)

Publication Number Publication Date
KR20030075824A true KR20030075824A (en) 2003-09-26

Family

ID=32225640

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020020015286A KR20030075824A (en) 2002-03-21 2002-03-21 The fabrication method of printed circuit board for semiconductor package having tailless pattern

Country Status (1)

Country Link
KR (1) KR20030075824A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100499003B1 (en) * 2002-12-12 2005-07-01 삼성전기주식회사 A package substrate for electrolytic leadless plating, and its manufacturing method
KR100548612B1 (en) * 2003-09-29 2006-01-31 삼성전기주식회사 Printed circuit board without plating lead wire and manufacturing method thereof
KR100694668B1 (en) * 2006-03-27 2007-03-14 삼성전기주식회사 Manufacturing method of package substrate without lead line for plating
CN111246669A (en) * 2020-01-17 2020-06-05 深圳市德名利电子有限公司 Design method of LPDDR substrate, LPDDR substrate and electronic equipment

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5302492A (en) * 1989-06-16 1994-04-12 Hewlett-Packard Company Method of manufacturing printing circuit boards
JPH10224014A (en) * 1996-12-20 1998-08-21 Alcatel Alsthom Co General Electricite Method for creating metallic stand-off on electronic circuit
JP2001210932A (en) * 2000-01-26 2001-08-03 Matsushita Electric Works Ltd Method of manufacturing printed wiring board

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5302492A (en) * 1989-06-16 1994-04-12 Hewlett-Packard Company Method of manufacturing printing circuit boards
JPH10224014A (en) * 1996-12-20 1998-08-21 Alcatel Alsthom Co General Electricite Method for creating metallic stand-off on electronic circuit
JP2001210932A (en) * 2000-01-26 2001-08-03 Matsushita Electric Works Ltd Method of manufacturing printed wiring board

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100499003B1 (en) * 2002-12-12 2005-07-01 삼성전기주식회사 A package substrate for electrolytic leadless plating, and its manufacturing method
KR100548612B1 (en) * 2003-09-29 2006-01-31 삼성전기주식회사 Printed circuit board without plating lead wire and manufacturing method thereof
KR100694668B1 (en) * 2006-03-27 2007-03-14 삼성전기주식회사 Manufacturing method of package substrate without lead line for plating
CN111246669A (en) * 2020-01-17 2020-06-05 深圳市德名利电子有限公司 Design method of LPDDR substrate, LPDDR substrate and electronic equipment
CN111246669B (en) * 2020-01-17 2021-07-30 深圳市德明利技术股份有限公司 Design method of LPDDR substrate, LPDDR substrate and electronic equipment

Similar Documents

Publication Publication Date Title
US8115104B2 (en) Circuit board with buried conductive trace formed thereon and method for manufacturing the same
US7506437B2 (en) Printed circuit board having chip package mounted thereon and method of fabricating same
JP3895303B2 (en) Method for manufacturing package substrate without using plated lead
US7256495B2 (en) Package substrate manufactured using electrolytic leadless plating process, and method for manufacturing the same
US6852625B2 (en) Package substrate manufactured using electrolytic leadless plating process, and method for manufacturing the same
KR100389314B1 (en) Making method of PCB
US6472609B2 (en) Printed-wiring substrate and method for fabricating the printed-wiring substrate
KR100780092B1 (en) Manufacturing method for printed circuit board having non-plate pattern
JP2014504034A (en) Electronic device tape with enhanced lead cracks
US6896173B2 (en) Method of fabricating circuit substrate
KR100780093B1 (en) Manufacturing method for printed circuit board having non-plate pattern
KR20030075824A (en) The fabrication method of printed circuit board for semiconductor package having tailless pattern
KR20030075823A (en) The fabrication method of printed circuit board for semiconductor package having tailless pattern
KR20030075825A (en) The fabrication method of printed circuit board for semiconductor package having tailless pattern
KR20030011433A (en) Manufacturing method for hidden laser via hole of multi-layered printed circuit board
KR100614437B1 (en) The fabrication method of printed circuit board for BOC semiconductor package substrate having non-plate pattern to semi-additive process
KR101351188B1 (en) Ball grid array package printed-circuit board and manufacturing method thereof
KR20060035854A (en) The fabrication method of printed circuit board for semiconductor package having non-lead pattern by solder plating method
KR100599636B1 (en) The fabrication method of printed circuit board for BOC semiconductor package substrate having non-plate pattern
KR100694668B1 (en) Manufacturing method of package substrate without lead line for plating
KR20030072855A (en) The method for plating bump pads of printed circuit board for flip chip BGA semiconductor package
JP2004014568A (en) Semiconductor device
KR20020095497A (en) Printed circuit board having connection pad on via hole land and manufacturing method thereof
KR100763963B1 (en) TBGA Semiconductor Package and the fabrication method thereof
KR20010005136A (en) Method of manufacturing package substrate

Legal Events

Date Code Title Description
A201 Request for examination
E701 Decision to grant or registration of patent right
NORF Unpaid initial registration fee