CN111246669B

CN111246669B - Design method of LPDDR substrate, LPDDR substrate and electronic equipment

Info

Publication number: CN111246669B
Application number: CN202010056038.6A
Authority: CN
Inventors: 李虎; 谭少鹏
Original assignee: Shenzhen Demingli Electronics Co Ltd
Current assignee: Shenzhen Demingli Electronics Co Ltd
Priority date: 2020-01-17
Filing date: 2020-01-17
Publication date: 2021-07-30
Anticipated expiration: 2040-01-17
Also published as: CN111246669A

Abstract

The invention discloses a design method of an LPDDR substrate, the LPDDR substrate and an electronic device, wherein the design method of the LPDDR substrate comprises the following steps: determining a chip packaging area on the LPDDR substrate; and adjacent areas at two ends of the chip packaging area are respectively provided with a first etching area and a second etching area, wherein the first etching area and the second etching area are both used for arranging a first electroplating lead, and the first electroplating lead is electrically connected with a circuit network to be electroplated on the LPDDR substrate. The design method has the advantages that the etching area of the electroplated lead is concentrated, the later inspection is convenient, and the tail of the lead is hardly remained, so that the defects caused by the design of the traditional substrate are well overcome, and the performance requirement and the aesthetic requirement of the LPDDR substrate are met.

Description

Design method of LPDDR substrate, LPDDR substrate and electronic equipment

Technical Field

The present invention relates to the field of storage devices, and more particularly, to a method for designing an LPDDR substrate, and an electronic device.

Background

On a PCB board, copper is used to interconnect components on the board, and although it is a good conductor material to form a pattern of the conductive path surface of the PCB, it is also prone to tarnishing by oxidation and solderability by corrosion if exposed to air for a long period of time. Therefore, electroplating techniques are used to protect the copper tracks, vias and plated through holes.

Copper tracks need to be electroplated through leads, the traditional leads are designed on the bottom surface of the substrate, and as etching needs to be carried out outside a wafer chip as far as possible, a large number of circuits need to lead to the outside of a product, and wiring is complex. As shown in fig. 1 and 2, the portions of the dashed frame portion in fig. 2 are both etched lead wire tails. The wire tails of the copper tracks all form antennas, causing signal reflections, affecting signal transmission, and simultaneously causing appearance problems and electromagnetic interference problems. Meanwhile, the residual length of the copper printed wire tail is different, the quality of wiring is directly influenced, the effective difference equidistance requirement cannot be met, and the problem of signal sampling delay is caused. In addition, as shown in fig. 3 and 4, the conventional lead design causes the substrate chip package area to be etched. If the front area of the substrate of the packaged wafer chip is etched, the etching can form a closed air cavity, and the air cavity expands after being heated, so that the wafer chip is broken, or the substrate deforms and bulges, and the substrate partially falls off or is recessed. If there is etching on the bottom surface of the substrate, the pressure under the plastic package will cause local deformation of the substrate, and may cause the wafer chip to crack seriously, and the circuit of the substrate will be damaged. Therefore, it is necessary to solve the problem of wire residue after the LPDDR substrate is etched.

Disclosure of Invention

The invention mainly aims to provide a design method of an LPDDR substrate, aiming at solving the problem of lead wire residue after the LPDDR substrate is etched.

The invention provides a design method of an LPDDR substrate, which comprises the following steps:

determining a chip packaging area on the LPDDR substrate;

and adjacent areas at two ends of the chip packaging area are respectively provided with a first etching area and a second etching area, wherein the first etching area and the second etching area are both used for arranging a first electroplating lead, and the first electroplating lead is electrically connected with a circuit network to be electroplated on the LPDDR substrate.

Preferably, the first etched region and the second etched region each have a width of at least 0.26 mm.

Preferably, the width of each of the first etching region and the second etching region is 0.26 mm.

Preferably, after the electroplated wires of the first etching area and the second etching area are etched, the first etching area and the second etching area are both used for gold wire bonding.

Preferably, the chip package region is located in a central region of the LPDDR substrate.

Preferably, the circuit network to be plated comprises differential traces.

Preferably, the invention also provides an LPDDR substrate, which comprises the above chip package region, a first etched region and a second etched region.

Preferably, the invention also provides an electronic device comprising the LPDDR substrate.

The invention has the beneficial effects that: the design method has the advantages that the etching area of the electroplated lead is concentrated, the later inspection is convenient, and the tail of the lead is hardly remained, so that the defects caused by the design of the traditional substrate are well overcome, and the performance requirement and the aesthetic requirement of the LPDDR substrate are met.

Drawings

FIG. 1 is a schematic diagram of a prior art plating lead design for an LPDDR substrate;

FIG. 2 is a schematic diagram of the structure of the residual plated leads after etching of a LPDDR substrate in the prior art;

FIG. 3 is a schematic diagram of an LPDDR package in the prior art;

FIG. 4 is an enlarged view of a portion of FIG. 3;

FIG. 5 is a schematic diagram of a first process flow of a LPDDR substrate design method of the present invention;

FIG. 6 is a schematic view of an LPDDR substrate design using the design method of the present invention;

FIG. 7 is a schematic diagram of a structure of a plating lead on the front surface of an LPDDR substrate designed by the method of the invention;

FIG. 8 is a schematic view of a plating lead on the reverse side of an LPDDR substrate designed by the method of the invention;

FIG. 9 is a schematic front view of an LPDDR substrate designed by the method of the present invention after lead lines are etched;

FIG. 10 is a schematic diagram of the backside structure of an LPDDR substrate designed by the method of the present invention after etching the plated leads;

FIG. 11 is a schematic diagram of the front side of an etch-inhibited area of an LPDDR substrate designed by the method of the invention;

FIG. 12 is a schematic backside view of an etch-inhibited area of an LPDDR substrate designed by the method of the present invention.

Description of reference numerals:

1. a first etching region; 2. a second etching region; 3. a first plated lead; 4. a chip packaging region; 5. and a second plated lead.

The implementation, functional features and advantages of the objects of the present invention will be further explained with reference to the accompanying drawings.

Detailed Description

It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

Referring to FIG. 5, the present invention provides a method for designing an LPDDR substrate, comprising:

s1: determining a chip packaging area 4 on the LPDDR substrate;

s2: the adjacent areas at two ends of the chip packaging area 4 are respectively provided with a first etching area 1 and a second etching area 2, wherein the first etching area 1 and the second etching area 2 are both used for arranging a first electroplating lead 3, and the first electroplating lead 3 is electrically connected with a circuit network to be electroplated on the LPDDR substrate.

In the embodiment of the invention, the basic design flow of the PCB is as follows: the first step is early preparation, which comprises the steps of preparing a component library and a schematic diagram; secondly, designing a PCB structure, drawing a PCB layout under a PCB design environment according to the determined circuit board size and various mechanical positioning, and placing a required connector according to the positioning requirement; thirdly, the PCB is laid out, a network table is generated on the schematic diagram, and then the network table is led in the PCB; and the fourth step is wiring, which is required to meet the performance of the electric appliance and to be beautiful. The innovation point of the invention is wiring. Referring to fig. 6 and 7, when designing the LPDDR substrate, a chip package region 4 is first defined on the LPDDR substrate for packaging a wafer chip, so as to prevent the substrate of the chip package region 4 from being etched to cause substrate damage or wafer chip damage. The adjacent areas at the two ends of the chip packaging area 4 are respectively provided with a first etching area 1 and a second etching area 2, wherein the first etching area 1 and the second etching area 2 are both used for arranging electroplating leads which are electrically connected with a circuit network to be electroplated on the LPDDR substrate, the purpose is to connect one end of each copper printed wire on the LPDDR with a tin ball pad with a circuit function, and the other end is concentrated on the first etching area 1 or the second etching area 2, so that a substrate manufacturer respectively arranges a first electroplating lead 3 in the first etching area 1 and the second etching area 2, and then the first electroplating lead 3 can be electrically connected with the circuit network to be electroplated on the LPDDR substrate. By the above design method, not only can the circuit network to be plated on the LPDDR substrate be connected together through the shortest plating lead, but also the plating lead is designed on the front surface of the LPDDR substrate, which is simple and intuitive, and perfectly avoids the etching forbidden region (such as the chip packaging region 4) on all LPDDR substrates, as shown in fig. 11 and 12. In conclusion, the design method has the advantages that the etching area of the electroplated lead is concentrated, the later inspection is convenient, and the tail of the lead is hardly remained, so that the defects caused by the traditional substrate design are well overcome, and the performance requirement and the aesthetic requirement of the LPDDR substrate are met.

In order to more intuitively show the superiority of this embodiment, the process of manufacturing the LPDDR substrate is described in the present specification by the characters and drawings.

First, a circuit pattern is printed on the LPDDR substrate, and copper tracks (i.e., a circuit network), a first etched area 1 and a second etched area 2 are formed on the circuit board through one etching, as shown in fig. 6. Next, a first plating lead 3 is formed on each of the first etched area 1 and the second etched area 2 of the LPDDR substrate, and the other end of each copper trace is concentrated on each of the first etched area 1 and the second etched area 2 and is connected to the plating lead of each of the first etched area 1 and the second etched area 2, as shown in FIG. 7. On the back edge of the LPDDR substrate, the second plating lead 5 is provided to connect the isolated solder ball site pads without circuit function on the back of the LPDDR substrate, and the plating of the copper tracks on the LPDDR substrate and the isolated solder ball site pads without circuit function is realized by the plating lead on the back edge of the LPDDR substrate, as shown in FIG. 8. The electroplating method of the present invention is various, and the example is only one of the electroplating methods, and the present invention is not limited thereto. After the plating is completed, the non-etched region on the LPDDR substrate is coated and a second etching is performed to remove the excess plated leads on the first etched region 1, the second etched region 2 and the edge of the back surface of the LPDDR substrate, as shown in FIGS. 9 and 10. Because the isolated solder ball position pad is mainly used for welding and fixing and has no circuit function, the signal transmission cannot be influenced by the residual lead wire tail.

In other embodiments of the invention, the first etched area 1 and the second etched area 2 on the LPDDR substrate each have a width of at least 0.26 mm. Preferably, the width of each of the first etching region 1 and the second etching region 2 is 0.26 mm. The width meets the minimum requirement of the LPDDR substrate on the etching distance, and the circuit density on the LPDDR substrate is improved on the premise of not influencing the performance of the LPDDR substrate.

In other embodiments of the present invention, after the plated wires of the first etching region 1 and the second etching region 2 are etched, both the first etching region 1 and the second etching region 2 are used for gold wire bonding, i.e. the interface of the wafer chip and the interface of the substrate are bonded by using high-purity gold wires.

Furthermore, the chip package region 4 is located in the central region of the LPDDR substrate, so as to make the wiring distribution on the LPDDR substrate more uniform, thereby achieving better performance and more beautiful appearance of the circuit substrate.

Further, the circuit network to be plated includes differential traces.

Differential Signal (Differential Signal) is more and more widely applied to high-speed circuit design, and the most critical signals in the circuit are often designed by adopting a Differential structure. In general, the driving end sends two signals with equal value and opposite phase, and the receiving end judges whether the logic state is '0' or '1' by comparing the difference value of the two voltages. And the pair of traces carrying the differential signals is referred to as differential traces. Compared with a common single-ended signal wire, the most obvious advantages of differential signals are represented by the following three aspects: firstly, the anti-interference capability is strong, because the coupling between the two differential wirings is good, when noise interference exists outside, the two differential wirings are almost simultaneously coupled to the two wirings, and the receiving end only concerns the difference value of the two signals, so that the outside common mode noise can be completely offset; secondly, the EMI can be effectively inhibited, and on the same reason, because the polarities of the two signals are opposite, the electromagnetic fields radiated by the two signals can be mutually offset, and the tighter the coupling is, the less electromagnetic energy is released to the outside; and thirdly, the time sequence is accurately positioned, and because the switching change of the differential signal is positioned at the intersection point of the two signals, the common single-ended signal is not judged by depending on high and low threshold voltages, the influence of the process and the temperature is small, the error on the time sequence can be reduced, and the circuit is more suitable for a circuit with low-amplitude signals.

Furthermore, the invention also provides an LPDDR substrate, which adopts the design method of the LPDDR substrate and comprises a chip packaging area 4, a first etching area 1 and a second etching area 2. The line tail does not exist in the positive copper printed line of LPDDR base plate of this scheme, and the partial line tail at the LPDDR base plate back does not form the antenna, consequently can not cause signal reflection, influences signal transmission, has solved outward appearance problem and electromagnetic interference problem simultaneously, has satisfied effectual difference equidistance requirement, has solved the problem that signal sampling delays.

Furthermore, the invention also provides an electronic device which comprises the LPDDR substrate.

In the embodiment of the invention, the electronic equipment comprises but is not limited to a smart phone and a tablet computer, and the LPDDR substrate is adopted, so that the electronic equipment can operate efficiently.

The above description is only a preferred embodiment of the present invention, and not intended to limit the scope of the present invention, and all modifications of equivalent structures and equivalent processes, which are made by using the contents of the present specification and the accompanying drawings, or directly or indirectly applied to other related technical fields, are included in the scope of the present invention.

Claims

1. A method of designing an LPDDR substrate, comprising:

determining a chip packaging area on the front surface of the LPDDR substrate;

a first etching area and a second etching area are respectively arranged on adjacent areas at two ends of the chip packaging area, wherein electroplating leads on the front surface of the LPDDR substrate are only arranged on the first etching area and the second etching area, and the electroplating leads are electrically connected with a circuit network to be electroplated on the LPDDR substrate;

and the electroplated lead is etched after electroplating, and the electroplated lead in the first etching area and the second etching area is completely removed.

2. The method of claim 1, wherein the first etched area and the second etched area are each at least 0.26 mm wide.

3. The method of claim 2, wherein the first etched area and the second etched area are each 0.26 mm wide.

4. The LPDDR substrate design method of any one of claims 1 to 3, wherein the first etched region and the second etched region are used for gold wire bonding after the plated wires of the first etched region and the second etched region are etched.

5. The method of claim 1, wherein the chip area is located in a center region of the LPDDR substrate.

6. The method of claim 1 wherein the circuit network to be plated includes differential routing.

7. An LPDDR substrate, wherein the LPDDR substrate is designed by the method of any one of claims 1 to 6, comprising the chip packaging region, the first etching region and the second etching region.

8. An electronic device comprising the LPDDR substrate of claim 7.